Maxim Integrated
Driver for MAX31331 and MAX31334 Real Time Clock ICs.
max3133x.hpp@0:4a2754e462db, 2022-08-02 (annotated)
- Committer:
- Sinan Divarci
- Date:
- Tue Aug 02 18:20:54 2022 +0300
- Revision:
- 0:4a2754e462db
Initial Commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Sinan Divarci |
0:4a2754e462db | 1 | /******************************************************************************* |
| Sinan Divarci |
0:4a2754e462db | 2 | * Copyright(C) Analog Devices Inc., All Rights Reserved. |
| Sinan Divarci |
0:4a2754e462db | 3 | * |
| Sinan Divarci |
0:4a2754e462db | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Sinan Divarci |
0:4a2754e462db | 5 | * copy of this software and associated documentation files(the "Software"), |
| Sinan Divarci |
0:4a2754e462db | 6 | * to deal in the Software without restriction, including without limitation |
| Sinan Divarci |
0:4a2754e462db | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Sinan Divarci |
0:4a2754e462db | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Sinan Divarci |
0:4a2754e462db | 9 | * Software is furnished to do so, subject to the following conditions: |
| Sinan Divarci |
0:4a2754e462db | 10 | * |
| Sinan Divarci |
0:4a2754e462db | 11 | * The above copyright notice and this permission notice shall be included |
| Sinan Divarci |
0:4a2754e462db | 12 | * in all copies or substantial portions of the Software. |
| Sinan Divarci |
0:4a2754e462db | 13 | * |
| Sinan Divarci |
0:4a2754e462db | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Sinan Divarci |
0:4a2754e462db | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Sinan Divarci |
0:4a2754e462db | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Sinan Divarci |
0:4a2754e462db | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Sinan Divarci |
0:4a2754e462db | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Sinan Divarci |
0:4a2754e462db | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Sinan Divarci |
0:4a2754e462db | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Sinan Divarci |
0:4a2754e462db | 21 | * |
| Sinan Divarci |
0:4a2754e462db | 22 | * Except as contained in this notice, the name of Analog Devices Inc. |
| Sinan Divarci |
0:4a2754e462db | 23 | * shall not be used except as stated in the Analog Devices Inc. |
| Sinan Divarci |
0:4a2754e462db | 24 | * Branding Policy. |
| Sinan Divarci |
0:4a2754e462db | 25 | * |
| Sinan Divarci |
0:4a2754e462db | 26 | * The mere transfer of this software does not imply any licenses |
| Sinan Divarci |
0:4a2754e462db | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Sinan Divarci |
0:4a2754e462db | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Sinan Divarci |
0:4a2754e462db | 29 | * property whatsoever. Analog Devices Inc.retains all ownership rights. |
| Sinan Divarci |
0:4a2754e462db | 30 | ******************************************************************************* |
| Sinan Divarci |
0:4a2754e462db | 31 | */ |
| Sinan Divarci |
0:4a2754e462db | 32 | |
| Sinan Divarci |
0:4a2754e462db | 33 | #ifndef MAX3133X_HPP_ |
| Sinan Divarci |
0:4a2754e462db | 34 | #define MAX3133X_HPP_ |
| Sinan Divarci |
0:4a2754e462db | 35 | |
| Sinan Divarci |
0:4a2754e462db | 36 | #include "mbed.h" |
| Sinan Divarci |
0:4a2754e462db | 37 | #include "rtos.h" |
| Sinan Divarci |
0:4a2754e462db | 38 | #include "max3133x_regs.hpp" |
| Sinan Divarci |
0:4a2754e462db | 39 | |
| Sinan Divarci |
0:4a2754e462db | 40 | #define MAX3133X_I2C_ADDRESS 0x68 |
| Sinan Divarci |
0:4a2754e462db | 41 | #define MAX3133X_I2C_W (MAX3133X_I2C_ADDRESS << 1) |
| Sinan Divarci |
0:4a2754e462db | 42 | #define MAX3133X_I2C_R ((MAX3133X_I2C_ADDRESS << 1) | 1) |
| Sinan Divarci |
0:4a2754e462db | 43 | |
| Sinan Divarci |
0:4a2754e462db | 44 | enum max3133x_error_codes { |
| Sinan Divarci |
0:4a2754e462db | 45 | MAX3133X_NO_ERR, |
| Sinan Divarci |
0:4a2754e462db | 46 | MAX3133X_NULL_VALUE_ERR = -1, |
| Sinan Divarci |
0:4a2754e462db | 47 | MAX3133X_READ_REG_ERR = -2, |
| Sinan Divarci |
0:4a2754e462db | 48 | MAX3133X_WRITE_REG_ERR = -3, |
| Sinan Divarci |
0:4a2754e462db | 49 | MAX3133X_INVALID_TIME_ERR = -4, |
| Sinan Divarci |
0:4a2754e462db | 50 | MAX3133X_INVALID_DATE_ERR = -5, |
| Sinan Divarci |
0:4a2754e462db | 51 | MAX3133X_INVALID_MASK_ERR = -6, |
| Sinan Divarci |
0:4a2754e462db | 52 | MAX3133X_INVALID_ALARM_PERIOD_ERR = -7, |
| Sinan Divarci |
0:4a2754e462db | 53 | MAX3133X_ALARM_ONETIME_NOT_SUPP_ERR = -8, |
| Sinan Divarci |
0:4a2754e462db | 54 | MAX3133X_ALARM_YEARLY_NOT_SUPP_ERR = -9, |
| Sinan Divarci |
0:4a2754e462db | 55 | MAX3133X_ALARM_EVERYMINUTE_NOT_SUPP_ERR = -10, |
| Sinan Divarci |
0:4a2754e462db | 56 | MAX3133X_ALARM_EVERYSECOND_NOT_SUPP_ERR = -11 |
| Sinan Divarci |
0:4a2754e462db | 57 | }; |
| Sinan Divarci |
0:4a2754e462db | 58 | |
| Sinan Divarci |
0:4a2754e462db | 59 | class MAX3133X |
| Sinan Divarci |
0:4a2754e462db | 60 | { |
| Sinan Divarci |
0:4a2754e462db | 61 | public: |
| Sinan Divarci |
0:4a2754e462db | 62 | /* PUBLIC FUNCTION DECLARATIONS */ |
| Sinan Divarci |
0:4a2754e462db | 63 | |
| Sinan Divarci |
0:4a2754e462db | 64 | /** |
| Sinan Divarci |
0:4a2754e462db | 65 | * @brief Read from a register. |
| Sinan Divarci |
0:4a2754e462db | 66 | * |
| Sinan Divarci |
0:4a2754e462db | 67 | * @param[in] reg Address of a register to be read. |
| Sinan Divarci |
0:4a2754e462db | 68 | * @param[out] value Pointer to save result value. |
| Sinan Divarci |
0:4a2754e462db | 69 | * @param[in] len Size of result to be read. |
| Sinan Divarci |
0:4a2754e462db | 70 | * |
| Sinan Divarci |
0:4a2754e462db | 71 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 72 | */ |
| Sinan Divarci |
0:4a2754e462db | 73 | int read_register(uint8_t reg, uint8_t *value, uint8_t len); |
| Sinan Divarci |
0:4a2754e462db | 74 | |
| Sinan Divarci |
0:4a2754e462db | 75 | /** |
| Sinan Divarci |
0:4a2754e462db | 76 | * @brief Write to a register. |
| Sinan Divarci |
0:4a2754e462db | 77 | * |
| Sinan Divarci |
0:4a2754e462db | 78 | * @param[in] reg Address of a register to be written. |
| Sinan Divarci |
0:4a2754e462db | 79 | * @param[out] value Pointer of value to be written to register. |
| Sinan Divarci |
0:4a2754e462db | 80 | * @param[in] len Size of result to be written. |
| Sinan Divarci |
0:4a2754e462db | 81 | * |
| Sinan Divarci |
0:4a2754e462db | 82 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 83 | */ |
| Sinan Divarci |
0:4a2754e462db | 84 | int write_register(uint8_t reg, const uint8_t *value, uint8_t len); |
| Sinan Divarci |
0:4a2754e462db | 85 | |
| Sinan Divarci |
0:4a2754e462db | 86 | /** |
| Sinan Divarci |
0:4a2754e462db | 87 | * @brief Read time info from RTC. |
| Sinan Divarci |
0:4a2754e462db | 88 | * |
| Sinan Divarci |
0:4a2754e462db | 89 | * @param[out] rtc_ctime Time info from RTC. |
| Sinan Divarci |
0:4a2754e462db | 90 | * |
| Sinan Divarci |
0:4a2754e462db | 91 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 92 | */ |
| Sinan Divarci |
0:4a2754e462db | 93 | int get_time(struct tm *rtc_ctime, uint16_t *sub_sec = NULL); |
| Sinan Divarci |
0:4a2754e462db | 94 | |
| Sinan Divarci |
0:4a2754e462db | 95 | /** |
| Sinan Divarci |
0:4a2754e462db | 96 | * @brief Selection of 24hr-12hr hour format |
| Sinan Divarci |
0:4a2754e462db | 97 | */ |
| Sinan Divarci |
0:4a2754e462db | 98 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 99 | HOUR24 = 0, /**< 24-Hour format */ |
| Sinan Divarci |
0:4a2754e462db | 100 | HOUR12 = 1, /**< 12-Hour format */ |
| Sinan Divarci |
0:4a2754e462db | 101 | }hour_format_t; |
| Sinan Divarci |
0:4a2754e462db | 102 | |
| Sinan Divarci |
0:4a2754e462db | 103 | /** |
| Sinan Divarci |
0:4a2754e462db | 104 | * @brief Set time info to RTC. |
| Sinan Divarci |
0:4a2754e462db | 105 | * |
| Sinan Divarci |
0:4a2754e462db | 106 | * @param[in] rtc_ctime Time info to be written to RTC. |
| Sinan Divarci |
0:4a2754e462db | 107 | * |
| Sinan Divarci |
0:4a2754e462db | 108 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 109 | */ |
| Sinan Divarci |
0:4a2754e462db | 110 | int set_time(const struct tm *rtc_ctime, hour_format_t format = HOUR24); |
| Sinan Divarci |
0:4a2754e462db | 111 | |
| Sinan Divarci |
0:4a2754e462db | 112 | /** |
| Sinan Divarci |
0:4a2754e462db | 113 | * @brief Alarm periodicity selection |
| Sinan Divarci |
0:4a2754e462db | 114 | */ |
| Sinan Divarci |
0:4a2754e462db | 115 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 116 | ALARM_PERIOD_EVERYSECOND, /**< Once a second */ |
| Sinan Divarci |
0:4a2754e462db | 117 | ALARM_PERIOD_EVERYMINUTE, /**< Seconds match */ |
| Sinan Divarci |
0:4a2754e462db | 118 | ALARM_PERIOD_HOURLY, /**< Seconds and Minutes match */ |
| Sinan Divarci |
0:4a2754e462db | 119 | ALARM_PERIOD_DAILY, /**< Hours, Minutes and Seconds match*/ |
| Sinan Divarci |
0:4a2754e462db | 120 | ALARM_PERIOD_WEEKLY, /**< Day and Time match */ |
| Sinan Divarci |
0:4a2754e462db | 121 | ALARM_PERIOD_MONTHLY, /**< Date and Time match */ |
| Sinan Divarci |
0:4a2754e462db | 122 | ALARM_PERIOD_YEARLY, /**< Month, Date and Time match */ |
| Sinan Divarci |
0:4a2754e462db | 123 | ALARM_PERIOD_ONETIME, /**< Year, Month, Date and Time match */ |
| Sinan Divarci |
0:4a2754e462db | 124 | }alarm_period_t; |
| Sinan Divarci |
0:4a2754e462db | 125 | |
| Sinan Divarci |
0:4a2754e462db | 126 | /** |
| Sinan Divarci |
0:4a2754e462db | 127 | * @brief Alarm number selection |
| Sinan Divarci |
0:4a2754e462db | 128 | */ |
| Sinan Divarci |
0:4a2754e462db | 129 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 130 | ALARM1, /**< Alarm number 1 */ |
| Sinan Divarci |
0:4a2754e462db | 131 | ALARM2, /**< Alarm number 2 */ |
| Sinan Divarci |
0:4a2754e462db | 132 | }alarm_no_t; |
| Sinan Divarci |
0:4a2754e462db | 133 | |
| Sinan Divarci |
0:4a2754e462db | 134 | /** |
| Sinan Divarci |
0:4a2754e462db | 135 | * @brief Set an alarm condition |
| Sinan Divarci |
0:4a2754e462db | 136 | * |
| Sinan Divarci |
0:4a2754e462db | 137 | * @param[in] alarm_no Alarm number, ALARM1 or ALARM2 |
| Sinan Divarci |
0:4a2754e462db | 138 | * @param[in] alarm_time Pointer to alarm time to be set |
| Sinan Divarci |
0:4a2754e462db | 139 | * @param[in] period Alarm periodicity, one of ALARM_PERIOD_* |
| Sinan Divarci |
0:4a2754e462db | 140 | * |
| Sinan Divarci |
0:4a2754e462db | 141 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 142 | */ |
| Sinan Divarci |
0:4a2754e462db | 143 | int set_alarm(alarm_no_t alarm_no, const struct tm *alarm_time, alarm_period_t period); |
| Sinan Divarci |
0:4a2754e462db | 144 | |
| Sinan Divarci |
0:4a2754e462db | 145 | /** |
| Sinan Divarci |
0:4a2754e462db | 146 | * @brief Get alarm data & time |
| Sinan Divarci |
0:4a2754e462db | 147 | * |
| Sinan Divarci |
0:4a2754e462db | 148 | * @param[in] alarm_no Alarm number, ALARM1 or ALARM2 |
| Sinan Divarci |
0:4a2754e462db | 149 | * @param[out] alarm_time Pointer to alarm time to be filled in |
| Sinan Divarci |
0:4a2754e462db | 150 | * @param[out] period Pointer to the period of alarm, one of ALARM_PERIOD_* |
| Sinan Divarci |
0:4a2754e462db | 151 | * @param[out] is_enabled Pointer to the state of alarm |
| Sinan Divarci |
0:4a2754e462db | 152 | * |
| Sinan Divarci |
0:4a2754e462db | 153 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 154 | */ |
| Sinan Divarci |
0:4a2754e462db | 155 | int get_alarm(alarm_no_t alarm_no, struct tm *alarm_time, alarm_period_t *period, bool *is_enabled); |
| Sinan Divarci |
0:4a2754e462db | 156 | |
| Sinan Divarci |
0:4a2754e462db | 157 | /** |
| Sinan Divarci |
0:4a2754e462db | 158 | * @brief Gets Status Register Value |
| Sinan Divarci |
0:4a2754e462db | 159 | * |
| Sinan Divarci |
0:4a2754e462db | 160 | * @param[in] status_reg |
| Sinan Divarci |
0:4a2754e462db | 161 | * |
| Sinan Divarci |
0:4a2754e462db | 162 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 163 | */ |
| Sinan Divarci |
0:4a2754e462db | 164 | int get_status_reg(max3133x_status_reg_t * status_reg); |
| Sinan Divarci |
0:4a2754e462db | 165 | |
| Sinan Divarci |
0:4a2754e462db | 166 | /** |
| Sinan Divarci |
0:4a2754e462db | 167 | * @brief Gets Interrupt Enable Register Value |
| Sinan Divarci |
0:4a2754e462db | 168 | * |
| Sinan Divarci |
0:4a2754e462db | 169 | * @param[in] int_en_reg |
| Sinan Divarci |
0:4a2754e462db | 170 | * |
| Sinan Divarci |
0:4a2754e462db | 171 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 172 | */ |
| Sinan Divarci |
0:4a2754e462db | 173 | int get_interrupt_reg(max3133x_int_en_reg_t * int_en_reg); |
| Sinan Divarci |
0:4a2754e462db | 174 | |
| Sinan Divarci |
0:4a2754e462db | 175 | /** |
| Sinan Divarci |
0:4a2754e462db | 176 | * @brief Selection of interrupt ids |
| Sinan Divarci |
0:4a2754e462db | 177 | */ |
| Sinan Divarci |
0:4a2754e462db | 178 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 179 | INTR_ID_A1IE, /**< Alarm1 interrupt flag */ |
| Sinan Divarci |
0:4a2754e462db | 180 | INTR_ID_A2IE, /**< Alarm2 interrupt flag */ |
| Sinan Divarci |
0:4a2754e462db | 181 | INTR_ID_TIE, /**< Timer interrupt flag */ |
| Sinan Divarci |
0:4a2754e462db | 182 | INTR_ID_DIE, /**< Digital (DIN) interrupt flag */ |
| Sinan Divarci |
0:4a2754e462db | 183 | INTR_ID_VBATLOWIE, /**< VBAT Low Interrupt enable */ |
| Sinan Divarci |
0:4a2754e462db | 184 | INTR_ID_PFAILE /**< Power fail Interrupt flag */ |
| Sinan Divarci |
0:4a2754e462db | 185 | }intr_id_t; |
| Sinan Divarci |
0:4a2754e462db | 186 | |
| Sinan Divarci |
0:4a2754e462db | 187 | /*Interrupt Enable Register Masks*/ |
| Sinan Divarci |
0:4a2754e462db | 188 | #define A1IE 0b00000001 /*Alarm1 interrupt mask*/ |
| Sinan Divarci |
0:4a2754e462db | 189 | #define A2IE 0b00000010 /*Alarm2 interrupt mask*/ |
| Sinan Divarci |
0:4a2754e462db | 190 | #define TIE 0b00000100 /*Timer interrupt mask*/ |
| Sinan Divarci |
0:4a2754e462db | 191 | #define DIE 0b00001000 /*Digital (DIN) interrupt mask*/ |
| Sinan Divarci |
0:4a2754e462db | 192 | #define VBATLOWIE 0b00010000 /*VBAT Low Interrupt mask*/ |
| Sinan Divarci |
0:4a2754e462db | 193 | #define PFAILE 0b00100000 /*Power fail Interrupt mask*/ |
| Sinan Divarci |
0:4a2754e462db | 194 | #define DOSF 0b01000000 /*Disable oscillator flag*/ |
| Sinan Divarci |
0:4a2754e462db | 195 | #define INT_ALL 0b00111111 /*All Interrupts*/ |
| Sinan Divarci |
0:4a2754e462db | 196 | #define NUM_OF_INTR_ID 6 /*Number of Interrupt IDs*/ |
| Sinan Divarci |
0:4a2754e462db | 197 | |
| Sinan Divarci |
0:4a2754e462db | 198 | /** |
| Sinan Divarci |
0:4a2754e462db | 199 | * @brief Enables Interrupts |
| Sinan Divarci |
0:4a2754e462db | 200 | * |
| Sinan Divarci |
0:4a2754e462db | 201 | * @param[in] mask |
| Sinan Divarci |
0:4a2754e462db | 202 | * |
| Sinan Divarci |
0:4a2754e462db | 203 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 204 | */ |
| Sinan Divarci |
0:4a2754e462db | 205 | int interrupt_enable(uint8_t mask); |
| Sinan Divarci |
0:4a2754e462db | 206 | |
| Sinan Divarci |
0:4a2754e462db | 207 | /** |
| Sinan Divarci |
0:4a2754e462db | 208 | * @brief Disables Interrupts |
| Sinan Divarci |
0:4a2754e462db | 209 | * |
| Sinan Divarci |
0:4a2754e462db | 210 | * @param[in] mask |
| Sinan Divarci |
0:4a2754e462db | 211 | * |
| Sinan Divarci |
0:4a2754e462db | 212 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 213 | */ |
| Sinan Divarci |
0:4a2754e462db | 214 | int interrupt_disable(uint8_t mask); |
| Sinan Divarci |
0:4a2754e462db | 215 | |
| Sinan Divarci |
0:4a2754e462db | 216 | /** |
| Sinan Divarci |
0:4a2754e462db | 217 | * @brief Put device into reset state |
| Sinan Divarci |
0:4a2754e462db | 218 | * |
| Sinan Divarci |
0:4a2754e462db | 219 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 220 | */ |
| Sinan Divarci |
0:4a2754e462db | 221 | int sw_reset_assert(); |
| Sinan Divarci |
0:4a2754e462db | 222 | |
| Sinan Divarci |
0:4a2754e462db | 223 | /** |
| Sinan Divarci |
0:4a2754e462db | 224 | * @brief Release device from state state |
| Sinan Divarci |
0:4a2754e462db | 225 | * |
| Sinan Divarci |
0:4a2754e462db | 226 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 227 | */ |
| Sinan Divarci |
0:4a2754e462db | 228 | int sw_reset_release(); |
| Sinan Divarci |
0:4a2754e462db | 229 | |
| Sinan Divarci |
0:4a2754e462db | 230 | /** |
| Sinan Divarci |
0:4a2754e462db | 231 | * @brief Resets the digital block and the I2C programmable registers except for RAM registers and RTC_reset. |
| Sinan Divarci |
0:4a2754e462db | 232 | * |
| Sinan Divarci |
0:4a2754e462db | 233 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 234 | */ |
| Sinan Divarci |
0:4a2754e462db | 235 | int sw_reset(); |
| Sinan Divarci |
0:4a2754e462db | 236 | |
| Sinan Divarci |
0:4a2754e462db | 237 | /** |
| Sinan Divarci |
0:4a2754e462db | 238 | * @brief Data retention mode enable/disable Configuration |
| Sinan Divarci |
0:4a2754e462db | 239 | * |
| Sinan Divarci |
0:4a2754e462db | 240 | * @details |
| Sinan Divarci |
0:4a2754e462db | 241 | * - Register : RTC_CONFIG1 |
| Sinan Divarci |
0:4a2754e462db | 242 | * - Bit Fields : [2] |
| Sinan Divarci |
0:4a2754e462db | 243 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 244 | * - Description : Data retention mode enable/disable. |
| Sinan Divarci |
0:4a2754e462db | 245 | */ |
| Sinan Divarci |
0:4a2754e462db | 246 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 247 | NORMAL_OP_MODE, |
| Sinan Divarci |
0:4a2754e462db | 248 | DATA_RETENTION_MODE |
| Sinan Divarci |
0:4a2754e462db | 249 | }data_ret_t; |
| Sinan Divarci |
0:4a2754e462db | 250 | |
| Sinan Divarci |
0:4a2754e462db | 251 | /** |
| Sinan Divarci |
0:4a2754e462db | 252 | * @brief I2C timeout enable Configuration |
| Sinan Divarci |
0:4a2754e462db | 253 | * |
| Sinan Divarci |
0:4a2754e462db | 254 | * @details |
| Sinan Divarci |
0:4a2754e462db | 255 | * - Register : RTC_CONFIG1 |
| Sinan Divarci |
0:4a2754e462db | 256 | * - Bit Fields : [1] |
| Sinan Divarci |
0:4a2754e462db | 257 | * - Default : 0x1 |
| Sinan Divarci |
0:4a2754e462db | 258 | * - Description : I2C timeout enable |
| Sinan Divarci |
0:4a2754e462db | 259 | */ |
| Sinan Divarci |
0:4a2754e462db | 260 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 261 | DISABLE_I2C_TIMEOUT, |
| Sinan Divarci |
0:4a2754e462db | 262 | ENABLE_I2C_TIMEOUT |
| Sinan Divarci |
0:4a2754e462db | 263 | }i2c_timeout_t; |
| Sinan Divarci |
0:4a2754e462db | 264 | |
| Sinan Divarci |
0:4a2754e462db | 265 | /** |
| Sinan Divarci |
0:4a2754e462db | 266 | * @brief Active-high enable for the crystal oscillator Configuration |
| Sinan Divarci |
0:4a2754e462db | 267 | * |
| Sinan Divarci |
0:4a2754e462db | 268 | * @details |
| Sinan Divarci |
0:4a2754e462db | 269 | * - Register : RTC_CONFIG1 |
| Sinan Divarci |
0:4a2754e462db | 270 | * - Bit Fields : [0] |
| Sinan Divarci |
0:4a2754e462db | 271 | * - Default : 0x1 |
| Sinan Divarci |
0:4a2754e462db | 272 | * - Description : Active-high enable for the crystal oscillator |
| Sinan Divarci |
0:4a2754e462db | 273 | */ |
| Sinan Divarci |
0:4a2754e462db | 274 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 275 | DISABLE_OSCILLATOR, |
| Sinan Divarci |
0:4a2754e462db | 276 | ENABLE_OSCILLATOR |
| Sinan Divarci |
0:4a2754e462db | 277 | }en_osc_t; |
| Sinan Divarci |
0:4a2754e462db | 278 | |
| Sinan Divarci |
0:4a2754e462db | 279 | /** |
| Sinan Divarci |
0:4a2754e462db | 280 | * @brief Digital (DIN) pin Sleep Entry Enable Configuration |
| Sinan Divarci |
0:4a2754e462db | 281 | * |
| Sinan Divarci |
0:4a2754e462db | 282 | * @details |
| Sinan Divarci |
0:4a2754e462db | 283 | * - Register : RTC_CONFIG2 |
| Sinan Divarci |
0:4a2754e462db | 284 | * - Bit Fields : [4] |
| Sinan Divarci |
0:4a2754e462db | 285 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 286 | * - Description : Digital (DIN) pin Sleep Entry Enable |
| Sinan Divarci |
0:4a2754e462db | 287 | */ |
| Sinan Divarci |
0:4a2754e462db | 288 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 289 | DIN_SLEEP_ENTRY_DISABLE, |
| Sinan Divarci |
0:4a2754e462db | 290 | DIN_SLEEP_ENTRY_ENABLE |
| Sinan Divarci |
0:4a2754e462db | 291 | }dse_t; |
| Sinan Divarci |
0:4a2754e462db | 292 | |
| Sinan Divarci |
0:4a2754e462db | 293 | /** |
| Sinan Divarci |
0:4a2754e462db | 294 | * @brief Digital (DIN) pin Debounce Enable Configuration |
| Sinan Divarci |
0:4a2754e462db | 295 | * |
| Sinan Divarci |
0:4a2754e462db | 296 | * @details |
| Sinan Divarci |
0:4a2754e462db | 297 | * - Register : RTC_CONFIG2 |
| Sinan Divarci |
0:4a2754e462db | 298 | * - Bit Fields : [3] |
| Sinan Divarci |
0:4a2754e462db | 299 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 300 | * - Description : Digital (DIN) pin Debounce Enable |
| Sinan Divarci |
0:4a2754e462db | 301 | */ |
| Sinan Divarci |
0:4a2754e462db | 302 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 303 | DIN_DEBOUNCE_DISABLE, |
| Sinan Divarci |
0:4a2754e462db | 304 | DIN_DEBOUNCE_ENABLE |
| Sinan Divarci |
0:4a2754e462db | 305 | }ddb_t; |
| Sinan Divarci |
0:4a2754e462db | 306 | |
| Sinan Divarci |
0:4a2754e462db | 307 | /** |
| Sinan Divarci |
0:4a2754e462db | 308 | * @brief CLKOUT enable Configuration |
| Sinan Divarci |
0:4a2754e462db | 309 | * |
| Sinan Divarci |
0:4a2754e462db | 310 | * @details |
| Sinan Divarci |
0:4a2754e462db | 311 | * - Register : RTC_CONFIG2 |
| Sinan Divarci |
0:4a2754e462db | 312 | * - Bit Fields : [2] |
| Sinan Divarci |
0:4a2754e462db | 313 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 314 | * - Description : CLKOUT enable |
| Sinan Divarci |
0:4a2754e462db | 315 | */ |
| Sinan Divarci |
0:4a2754e462db | 316 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 317 | INTERRUPT, |
| Sinan Divarci |
0:4a2754e462db | 318 | CLOCK_OUTPUT |
| Sinan Divarci |
0:4a2754e462db | 319 | }enclko_t; |
| Sinan Divarci |
0:4a2754e462db | 320 | |
| Sinan Divarci |
0:4a2754e462db | 321 | /** |
| Sinan Divarci |
0:4a2754e462db | 322 | * @brief Register Configuration |
| Sinan Divarci |
0:4a2754e462db | 323 | * |
| Sinan Divarci |
0:4a2754e462db | 324 | * @details |
| Sinan Divarci |
0:4a2754e462db | 325 | * - Register : RTC_CONFIG1 |
| Sinan Divarci |
0:4a2754e462db | 326 | * - Bit Fields : [5:4] |
| Sinan Divarci |
0:4a2754e462db | 327 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 328 | * - Description : Alarm1 Auto Clear |
| Sinan Divarci |
0:4a2754e462db | 329 | */ |
| Sinan Divarci |
0:4a2754e462db | 330 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 331 | BY_READING, /**< 0x0: Alarm1 flag and interrupt can only be cleared by reading Status register via I2C */ |
| Sinan Divarci |
0:4a2754e462db | 332 | AFTER_10MS, /**< 0x1: Alarm1 flag and interrupt are cleared ~10ms after assertion */ |
| Sinan Divarci |
0:4a2754e462db | 333 | AFTER_500MS, /**< 0x2: Alarm1 flag and interrupt are cleared ~500ms after assertion */ |
| Sinan Divarci |
0:4a2754e462db | 334 | AFTER_5s /**< 0x3: Alarm1 flag and interrupt are cleared ~5s after assertion. This option should not be used when Alarm1 is set to OncePerSec. */ |
| Sinan Divarci |
0:4a2754e462db | 335 | }a1ac_t; |
| Sinan Divarci |
0:4a2754e462db | 336 | |
| Sinan Divarci |
0:4a2754e462db | 337 | /** |
| Sinan Divarci |
0:4a2754e462db | 338 | * @brief Sets Alarm1 Auto Clear Mode |
| Sinan Divarci |
0:4a2754e462db | 339 | * |
| Sinan Divarci |
0:4a2754e462db | 340 | * @param[in] a1ac A1AC bits. |
| Sinan Divarci |
0:4a2754e462db | 341 | * |
| Sinan Divarci |
0:4a2754e462db | 342 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 343 | */ |
| Sinan Divarci |
0:4a2754e462db | 344 | int set_alarm1_auto_clear(a1ac_t a1ac); |
| Sinan Divarci |
0:4a2754e462db | 345 | |
| Sinan Divarci |
0:4a2754e462db | 346 | /** |
| Sinan Divarci |
0:4a2754e462db | 347 | * @brief Digital (DIN) interrupt polarity configuration |
| Sinan Divarci |
0:4a2754e462db | 348 | * |
| Sinan Divarci |
0:4a2754e462db | 349 | * @details |
| Sinan Divarci |
0:4a2754e462db | 350 | * - Register : RTC_CONFIG1 |
| Sinan Divarci |
0:4a2754e462db | 351 | * - Bit Fields : [3] |
| Sinan Divarci |
0:4a2754e462db | 352 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 353 | * - Description : Digital (DIN) interrupt polarity |
| Sinan Divarci |
0:4a2754e462db | 354 | */ |
| Sinan Divarci |
0:4a2754e462db | 355 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 356 | FALLING_EDGE, /**< 0x0: Interrupt triggers on falling edge of DIN input. */ |
| Sinan Divarci |
0:4a2754e462db | 357 | RISING_EDGE /**< 0x1: Interrupt triggers on rising edge of DIN input. */ |
| Sinan Divarci |
0:4a2754e462db | 358 | }dip_t; |
| Sinan Divarci |
0:4a2754e462db | 359 | |
| Sinan Divarci |
0:4a2754e462db | 360 | /** |
| Sinan Divarci |
0:4a2754e462db | 361 | * @brief Digital (DIN) interrupt polarity |
| Sinan Divarci |
0:4a2754e462db | 362 | * |
| Sinan Divarci |
0:4a2754e462db | 363 | * @param[in] dip |
| Sinan Divarci |
0:4a2754e462db | 364 | * |
| Sinan Divarci |
0:4a2754e462db | 365 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 366 | */ |
| Sinan Divarci |
0:4a2754e462db | 367 | int set_din_polarity(dip_t dip); |
| Sinan Divarci |
0:4a2754e462db | 368 | |
| Sinan Divarci |
0:4a2754e462db | 369 | /** |
| Sinan Divarci |
0:4a2754e462db | 370 | * @brief Put device into data retention mode |
| Sinan Divarci |
0:4a2754e462db | 371 | * |
| Sinan Divarci |
0:4a2754e462db | 372 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 373 | */ |
| Sinan Divarci |
0:4a2754e462db | 374 | int data_retention_mode_enter(); |
| Sinan Divarci |
0:4a2754e462db | 375 | |
| Sinan Divarci |
0:4a2754e462db | 376 | /** |
| Sinan Divarci |
0:4a2754e462db | 377 | * @brief Remove device from data retention mode |
| Sinan Divarci |
0:4a2754e462db | 378 | * |
| Sinan Divarci |
0:4a2754e462db | 379 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 380 | */ |
| Sinan Divarci |
0:4a2754e462db | 381 | int data_retention_mode_exit(); |
| Sinan Divarci |
0:4a2754e462db | 382 | |
| Sinan Divarci |
0:4a2754e462db | 383 | /** |
| Sinan Divarci |
0:4a2754e462db | 384 | * @brief Enable I2C timeout |
| Sinan Divarci |
0:4a2754e462db | 385 | * |
| Sinan Divarci |
0:4a2754e462db | 386 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 387 | */ |
| Sinan Divarci |
0:4a2754e462db | 388 | int i2c_timeout_enable(); |
| Sinan Divarci |
0:4a2754e462db | 389 | |
| Sinan Divarci |
0:4a2754e462db | 390 | /** |
| Sinan Divarci |
0:4a2754e462db | 391 | * @brief Disable I2C timeout |
| Sinan Divarci |
0:4a2754e462db | 392 | * |
| Sinan Divarci |
0:4a2754e462db | 393 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 394 | */ |
| Sinan Divarci |
0:4a2754e462db | 395 | int i2c_timeout_disable(); |
| Sinan Divarci |
0:4a2754e462db | 396 | |
| Sinan Divarci |
0:4a2754e462db | 397 | /** |
| Sinan Divarci |
0:4a2754e462db | 398 | * @brief Enable the crystal oscillator. |
| Sinan Divarci |
0:4a2754e462db | 399 | * |
| Sinan Divarci |
0:4a2754e462db | 400 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 401 | */ |
| Sinan Divarci |
0:4a2754e462db | 402 | int oscillator_enable(); |
| Sinan Divarci |
0:4a2754e462db | 403 | |
| Sinan Divarci |
0:4a2754e462db | 404 | /** |
| Sinan Divarci |
0:4a2754e462db | 405 | * @brief Disable the crystal oscillator. |
| Sinan Divarci |
0:4a2754e462db | 406 | * |
| Sinan Divarci |
0:4a2754e462db | 407 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 408 | */ |
| Sinan Divarci |
0:4a2754e462db | 409 | int oscillator_disable(); |
| Sinan Divarci |
0:4a2754e462db | 410 | |
| Sinan Divarci |
0:4a2754e462db | 411 | /** |
| Sinan Divarci |
0:4a2754e462db | 412 | * @brief Enable the CLKOUT. Sets INTBb/CLKOUT pin as CLKO (clock output). |
| Sinan Divarci |
0:4a2754e462db | 413 | * |
| Sinan Divarci |
0:4a2754e462db | 414 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 415 | */ |
| Sinan Divarci |
0:4a2754e462db | 416 | int clkout_enable(); |
| Sinan Divarci |
0:4a2754e462db | 417 | |
| Sinan Divarci |
0:4a2754e462db | 418 | /** |
| Sinan Divarci |
0:4a2754e462db | 419 | * @brief Disable the CLKOUT. Sets INTBb/CLKOUT pin as INTBb (interrupt). |
| Sinan Divarci |
0:4a2754e462db | 420 | * |
| Sinan Divarci |
0:4a2754e462db | 421 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 422 | */ |
| Sinan Divarci |
0:4a2754e462db | 423 | int clkout_disable(); |
| Sinan Divarci |
0:4a2754e462db | 424 | |
| Sinan Divarci |
0:4a2754e462db | 425 | /** |
| Sinan Divarci |
0:4a2754e462db | 426 | * @brief Set output clock frequency on INTBb/CLKOUT pin Configuration |
| Sinan Divarci |
0:4a2754e462db | 427 | * |
| Sinan Divarci |
0:4a2754e462db | 428 | * @details |
| Sinan Divarci |
0:4a2754e462db | 429 | * - Register : RTC_CONFIG2 |
| Sinan Divarci |
0:4a2754e462db | 430 | * - Bit Fields : [1:0] |
| Sinan Divarci |
0:4a2754e462db | 431 | * - Default : 0x3 |
| Sinan Divarci |
0:4a2754e462db | 432 | * - Description : Output clock frequency on INTBb/CLKOUT pin |
| Sinan Divarci |
0:4a2754e462db | 433 | */ |
| Sinan Divarci |
0:4a2754e462db | 434 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 435 | CLKOUT_1HZ, |
| Sinan Divarci |
0:4a2754e462db | 436 | CLKOUT_64HZ, |
| Sinan Divarci |
0:4a2754e462db | 437 | CLKOUT_1024KHZ, |
| Sinan Divarci |
0:4a2754e462db | 438 | CLKOUT_32KHZ_UNCOMP |
| Sinan Divarci |
0:4a2754e462db | 439 | }clko_hz_t; |
| Sinan Divarci |
0:4a2754e462db | 440 | |
| Sinan Divarci |
0:4a2754e462db | 441 | /** |
| Sinan Divarci |
0:4a2754e462db | 442 | * @brief Set output clock frequency on INTBb/CLKOUT pin |
| Sinan Divarci |
0:4a2754e462db | 443 | * |
| Sinan Divarci |
0:4a2754e462db | 444 | * @param[in] clko_hz |
| Sinan Divarci |
0:4a2754e462db | 445 | * |
| Sinan Divarci |
0:4a2754e462db | 446 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 447 | */ |
| Sinan Divarci |
0:4a2754e462db | 448 | int set_clko_freq(clko_hz_t clko_hz); |
| Sinan Divarci |
0:4a2754e462db | 449 | |
| Sinan Divarci |
0:4a2754e462db | 450 | /** |
| Sinan Divarci |
0:4a2754e462db | 451 | * @brief Get output clock frequency on INTBb/CLKOUT pin |
| Sinan Divarci |
0:4a2754e462db | 452 | * |
| Sinan Divarci |
0:4a2754e462db | 453 | * @param[out] clko_hz |
| Sinan Divarci |
0:4a2754e462db | 454 | * |
| Sinan Divarci |
0:4a2754e462db | 455 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 456 | */ |
| Sinan Divarci |
0:4a2754e462db | 457 | int get_clko_freq(clko_hz_t *clko_hz); |
| Sinan Divarci |
0:4a2754e462db | 458 | |
| Sinan Divarci |
0:4a2754e462db | 459 | /** |
| Sinan Divarci |
0:4a2754e462db | 460 | * @brief Enable the Timestamp Function |
| Sinan Divarci |
0:4a2754e462db | 461 | * |
| Sinan Divarci |
0:4a2754e462db | 462 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 463 | */ |
| Sinan Divarci |
0:4a2754e462db | 464 | int timestamp_function_enable(); |
| Sinan Divarci |
0:4a2754e462db | 465 | |
| Sinan Divarci |
0:4a2754e462db | 466 | /** |
| Sinan Divarci |
0:4a2754e462db | 467 | * @brief Disable the Timestamp Function |
| Sinan Divarci |
0:4a2754e462db | 468 | * |
| Sinan Divarci |
0:4a2754e462db | 469 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 470 | */ |
| Sinan Divarci |
0:4a2754e462db | 471 | int timestamp_function_disable(); |
| Sinan Divarci |
0:4a2754e462db | 472 | |
| Sinan Divarci |
0:4a2754e462db | 473 | /** |
| Sinan Divarci |
0:4a2754e462db | 474 | * @brief All Timestamp registers are reset to 0x00. If the Timestamp Function is Enabled, timestamp recording will start again. |
| Sinan Divarci |
0:4a2754e462db | 475 | * |
| Sinan Divarci |
0:4a2754e462db | 476 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 477 | */ |
| Sinan Divarci |
0:4a2754e462db | 478 | int timestamp_registers_reset(); |
| Sinan Divarci |
0:4a2754e462db | 479 | |
| Sinan Divarci |
0:4a2754e462db | 480 | /** |
| Sinan Divarci |
0:4a2754e462db | 481 | * @brief Enable Timestamp Overwrite mode |
| Sinan Divarci |
0:4a2754e462db | 482 | * |
| Sinan Divarci |
0:4a2754e462db | 483 | * @details More than 4 timestamps are recorded by overwriting oldest timestamp. Latest timestamp is always stored in the TS0 bank; earliest timestamp will be stored in the TS3 bank. |
| Sinan Divarci |
0:4a2754e462db | 484 | * |
| Sinan Divarci |
0:4a2754e462db | 485 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 486 | */ |
| Sinan Divarci |
0:4a2754e462db | 487 | int timestamp_overwrite_enable(); |
| Sinan Divarci |
0:4a2754e462db | 488 | |
| Sinan Divarci |
0:4a2754e462db | 489 | /** |
| Sinan Divarci |
0:4a2754e462db | 490 | * @brief Disable Timestamp Overwrite mode |
| Sinan Divarci |
0:4a2754e462db | 491 | * |
| Sinan Divarci |
0:4a2754e462db | 492 | * @details Timestamps are recorded (TS0 -> .. -> TS3). Latest timestamp is always stored in the TS0 bank. Further TS trigger events do not record timestamps. |
| Sinan Divarci |
0:4a2754e462db | 493 | * |
| Sinan Divarci |
0:4a2754e462db | 494 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 495 | */ |
| Sinan Divarci |
0:4a2754e462db | 496 | int timestamp_overwrite_disable(); |
| Sinan Divarci |
0:4a2754e462db | 497 | |
| Sinan Divarci |
0:4a2754e462db | 498 | /*Timestamp Config Register Masks*/ |
| Sinan Divarci |
0:4a2754e462db | 499 | #define TSVLOW 0b00100000 /*Record Timestamp on VBATLOW detection */ |
| Sinan Divarci |
0:4a2754e462db | 500 | #define TSPWM 0b00010000 /*Record Timestamp on power supply switch (VCC <-> VBAT)*/ |
| Sinan Divarci |
0:4a2754e462db | 501 | #define TSDIN 0b00001000 /*Record Timestamp on DIN transition. Polarity controlled by DIP bitfield in RTC_Config1 register.*/ |
| Sinan Divarci |
0:4a2754e462db | 502 | |
| Sinan Divarci |
0:4a2754e462db | 503 | /** |
| Sinan Divarci |
0:4a2754e462db | 504 | * @brief Enable Timestamp Records |
| Sinan Divarci |
0:4a2754e462db | 505 | * |
| Sinan Divarci |
0:4a2754e462db | 506 | * @param[in] record_enable_mask one or more of TS* |
| Sinan Divarci |
0:4a2754e462db | 507 | * |
| Sinan Divarci |
0:4a2754e462db | 508 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 509 | */ |
| Sinan Divarci |
0:4a2754e462db | 510 | int timestamp_record_enable(uint8_t record_enable_mask); |
| Sinan Divarci |
0:4a2754e462db | 511 | |
| Sinan Divarci |
0:4a2754e462db | 512 | /** |
| Sinan Divarci |
0:4a2754e462db | 513 | * @brief Disable Timestamp Records |
| Sinan Divarci |
0:4a2754e462db | 514 | * |
| Sinan Divarci |
0:4a2754e462db | 515 | * @param[in] record_disable_mask one or more of TS* |
| Sinan Divarci |
0:4a2754e462db | 516 | * |
| Sinan Divarci |
0:4a2754e462db | 517 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 518 | */ |
| Sinan Divarci |
0:4a2754e462db | 519 | int timestamp_record_disable(uint8_t record_disable_mask); |
| Sinan Divarci |
0:4a2754e462db | 520 | |
| Sinan Divarci |
0:4a2754e462db | 521 | /** |
| Sinan Divarci |
0:4a2754e462db | 522 | * @brief Timer frequency selection Configuration |
| Sinan Divarci |
0:4a2754e462db | 523 | * |
| Sinan Divarci |
0:4a2754e462db | 524 | * @details |
| Sinan Divarci |
0:4a2754e462db | 525 | * - Register : TIMER_CONFIG |
| Sinan Divarci |
0:4a2754e462db | 526 | * - Bit Fields : [1:0] |
| Sinan Divarci |
0:4a2754e462db | 527 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 528 | * - Description : Timer frequency selection |
| Sinan Divarci |
0:4a2754e462db | 529 | */ |
| Sinan Divarci |
0:4a2754e462db | 530 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 531 | TIMER_FREQ_1024HZ, /**< 1024Hz */ |
| Sinan Divarci |
0:4a2754e462db | 532 | TIMER_FREQ_256HZ, /**< 256Hz */ |
| Sinan Divarci |
0:4a2754e462db | 533 | TIMER_FREQ_64HZ, /**< 64Hz */ |
| Sinan Divarci |
0:4a2754e462db | 534 | TIMER_FREQ_16HZ, /**< 16Hz */ |
| Sinan Divarci |
0:4a2754e462db | 535 | }timer_freq_t; |
| Sinan Divarci |
0:4a2754e462db | 536 | |
| Sinan Divarci |
0:4a2754e462db | 537 | /** |
| Sinan Divarci |
0:4a2754e462db | 538 | * @brief Enable timer |
| Sinan Divarci |
0:4a2754e462db | 539 | * |
| Sinan Divarci |
0:4a2754e462db | 540 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 541 | */ |
| Sinan Divarci |
0:4a2754e462db | 542 | int timer_start(); |
| Sinan Divarci |
0:4a2754e462db | 543 | |
| Sinan Divarci |
0:4a2754e462db | 544 | /** |
| Sinan Divarci |
0:4a2754e462db | 545 | * @brief Pause timer, timer value is preserved |
| Sinan Divarci |
0:4a2754e462db | 546 | * |
| Sinan Divarci |
0:4a2754e462db | 547 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 548 | */ |
| Sinan Divarci |
0:4a2754e462db | 549 | int timer_pause(); |
| Sinan Divarci |
0:4a2754e462db | 550 | |
| Sinan Divarci |
0:4a2754e462db | 551 | /** |
| Sinan Divarci |
0:4a2754e462db | 552 | * @brief Start timer from the paused value |
| Sinan Divarci |
0:4a2754e462db | 553 | * |
| Sinan Divarci |
0:4a2754e462db | 554 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 555 | */ |
| Sinan Divarci |
0:4a2754e462db | 556 | int timer_continue(); |
| Sinan Divarci |
0:4a2754e462db | 557 | |
| Sinan Divarci |
0:4a2754e462db | 558 | /** |
| Sinan Divarci |
0:4a2754e462db | 559 | * @brief Disable timer |
| Sinan Divarci |
0:4a2754e462db | 560 | * |
| Sinan Divarci |
0:4a2754e462db | 561 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 562 | */ |
| Sinan Divarci |
0:4a2754e462db | 563 | int timer_stop(); |
| Sinan Divarci |
0:4a2754e462db | 564 | |
| Sinan Divarci |
0:4a2754e462db | 565 | /** |
| Sinan Divarci |
0:4a2754e462db | 566 | * @brief Turn-on the Battery Voltage Detector Function |
| Sinan Divarci |
0:4a2754e462db | 567 | * |
| Sinan Divarci |
0:4a2754e462db | 568 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 569 | */ |
| Sinan Divarci |
0:4a2754e462db | 570 | int battery_voltage_detector_enable(); |
| Sinan Divarci |
0:4a2754e462db | 571 | |
| Sinan Divarci |
0:4a2754e462db | 572 | /** |
| Sinan Divarci |
0:4a2754e462db | 573 | * @brief Turn-off the Battery Voltage Detector Function |
| Sinan Divarci |
0:4a2754e462db | 574 | * |
| Sinan Divarci |
0:4a2754e462db | 575 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 576 | */ |
| Sinan Divarci |
0:4a2754e462db | 577 | int battery_voltage_detector_disable(); |
| Sinan Divarci |
0:4a2754e462db | 578 | |
| Sinan Divarci |
0:4a2754e462db | 579 | /** |
| Sinan Divarci |
0:4a2754e462db | 580 | * @brief Supply voltage select. |
| Sinan Divarci |
0:4a2754e462db | 581 | */ |
| Sinan Divarci |
0:4a2754e462db | 582 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 583 | POW_MGMT_SUPPLY_SEL_AUTO, /**< Circuit decides whether to use VCC or VBACKUP */ |
| Sinan Divarci |
0:4a2754e462db | 584 | POW_MGMT_SUPPLY_SEL_VCC, /**< Use VCC as supply */ |
| Sinan Divarci |
0:4a2754e462db | 585 | POW_MGMT_SUPPLY_SEL_VBAT, /**< Use VBAT as supply */ |
| Sinan Divarci |
0:4a2754e462db | 586 | }power_mgmt_supply_t; |
| Sinan Divarci |
0:4a2754e462db | 587 | |
| Sinan Divarci |
0:4a2754e462db | 588 | /** |
| Sinan Divarci |
0:4a2754e462db | 589 | * @brief Select device power source |
| Sinan Divarci |
0:4a2754e462db | 590 | * |
| Sinan Divarci |
0:4a2754e462db | 591 | * @param[in] supply Supply selection, one of POW_MGMT_SUPPLY_SEL_* |
| Sinan Divarci |
0:4a2754e462db | 592 | * |
| Sinan Divarci |
0:4a2754e462db | 593 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 594 | */ |
| Sinan Divarci |
0:4a2754e462db | 595 | int supply_select(power_mgmt_supply_t supply); |
| Sinan Divarci |
0:4a2754e462db | 596 | |
| Sinan Divarci |
0:4a2754e462db | 597 | /** |
| Sinan Divarci |
0:4a2754e462db | 598 | * @brief Selection of charging path's resistor value |
| Sinan Divarci |
0:4a2754e462db | 599 | */ |
| Sinan Divarci |
0:4a2754e462db | 600 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 601 | TRICKLE_CHARGER_3K, /**< 3000 Ohm */ |
| Sinan Divarci |
0:4a2754e462db | 602 | TRICKLE_CHARGER_3K_2, /**< 3000 Ohm */ |
| Sinan Divarci |
0:4a2754e462db | 603 | TRICKLE_CHARGER_6K, /**< 6000 Ohm */ |
| Sinan Divarci |
0:4a2754e462db | 604 | TRICKLE_CHARGER_11K, /**< 11000 Ohm */ |
| Sinan Divarci |
0:4a2754e462db | 605 | }trickle_charger_ohm_t; |
| Sinan Divarci |
0:4a2754e462db | 606 | |
| Sinan Divarci |
0:4a2754e462db | 607 | /** |
| Sinan Divarci |
0:4a2754e462db | 608 | * @brief Configure trickle charger charging path, also enable it |
| Sinan Divarci |
0:4a2754e462db | 609 | * |
| Sinan Divarci |
0:4a2754e462db | 610 | * @param[in] res Value of resistor |
| Sinan Divarci |
0:4a2754e462db | 611 | * @param[in] diode Enable diode |
| Sinan Divarci |
0:4a2754e462db | 612 | * |
| Sinan Divarci |
0:4a2754e462db | 613 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 614 | */ |
| Sinan Divarci |
0:4a2754e462db | 615 | int trickle_charger_enable(trickle_charger_ohm_t res, bool diode); |
| Sinan Divarci |
0:4a2754e462db | 616 | |
| Sinan Divarci |
0:4a2754e462db | 617 | /** |
| Sinan Divarci |
0:4a2754e462db | 618 | * @brief Disable Trickle Charger |
| Sinan Divarci |
0:4a2754e462db | 619 | * |
| Sinan Divarci |
0:4a2754e462db | 620 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 621 | */ |
| Sinan Divarci |
0:4a2754e462db | 622 | int trickle_charger_disable(); |
| Sinan Divarci |
0:4a2754e462db | 623 | |
| Sinan Divarci |
0:4a2754e462db | 624 | /** |
| Sinan Divarci |
0:4a2754e462db | 625 | * @brief Selection of Timestamp |
| Sinan Divarci |
0:4a2754e462db | 626 | */ |
| Sinan Divarci |
0:4a2754e462db | 627 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 628 | TS0, /**< Timestamp 0 */ |
| Sinan Divarci |
0:4a2754e462db | 629 | TS1, /**< Timestamp 1 */ |
| Sinan Divarci |
0:4a2754e462db | 630 | TS2, /**< Timestamp 2 */ |
| Sinan Divarci |
0:4a2754e462db | 631 | TS3, /**< Timestamp 3 */ |
| Sinan Divarci |
0:4a2754e462db | 632 | NUM_OF_TS /**< Number of Timestamps */ |
| Sinan Divarci |
0:4a2754e462db | 633 | }ts_num_t; |
| Sinan Divarci |
0:4a2754e462db | 634 | |
| Sinan Divarci |
0:4a2754e462db | 635 | /** |
| Sinan Divarci |
0:4a2754e462db | 636 | * @brief Timestamp Triggers |
| Sinan Divarci |
0:4a2754e462db | 637 | */ |
| Sinan Divarci |
0:4a2754e462db | 638 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 639 | NOT_TRIGGERED, /**< Not Triggered */ |
| Sinan Divarci |
0:4a2754e462db | 640 | DINF, /**< triggered by DIN transition */ |
| Sinan Divarci |
0:4a2754e462db | 641 | VCCF, /**< triggered by VBAT -> VCC switch */ |
| Sinan Divarci |
0:4a2754e462db | 642 | VBATF, /**< triggered by VCC -> VBAT switch */ |
| Sinan Divarci |
0:4a2754e462db | 643 | VLOWF, /**< triggered by VLOW detection */ |
| Sinan Divarci |
0:4a2754e462db | 644 | NUM_OF_TRIG /**< Number of Triggers */ |
| Sinan Divarci |
0:4a2754e462db | 645 | }ts_trigger_t; |
| Sinan Divarci |
0:4a2754e462db | 646 | |
| Sinan Divarci |
0:4a2754e462db | 647 | typedef struct { |
| Sinan Divarci |
0:4a2754e462db | 648 | ts_num_t ts_num; |
| Sinan Divarci |
0:4a2754e462db | 649 | ts_trigger_t ts_trigger; |
| Sinan Divarci |
0:4a2754e462db | 650 | uint16_t sub_sec; |
| Sinan Divarci |
0:4a2754e462db | 651 | struct tm ctime; |
| Sinan Divarci |
0:4a2754e462db | 652 | }timestamp_t; |
| Sinan Divarci |
0:4a2754e462db | 653 | |
| Sinan Divarci |
0:4a2754e462db | 654 | /** |
| Sinan Divarci |
0:4a2754e462db | 655 | * @brief Read Timestamp info. |
| Sinan Divarci |
0:4a2754e462db | 656 | * |
| Sinan Divarci |
0:4a2754e462db | 657 | * @param[in] ts_num Timestamp number. |
| Sinan Divarci |
0:4a2754e462db | 658 | * @param[out] timestamp Time info. |
| Sinan Divarci |
0:4a2754e462db | 659 | * |
| Sinan Divarci |
0:4a2754e462db | 660 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 661 | */ |
| Sinan Divarci |
0:4a2754e462db | 662 | int get_timestamp(int ts_num, timestamp_t *timestamp); |
| Sinan Divarci |
0:4a2754e462db | 663 | |
| Sinan Divarci |
0:4a2754e462db | 664 | /** |
| Sinan Divarci |
0:4a2754e462db | 665 | * @brief correct the clock accuracy on your board. refer the datasheet for additional informations |
| Sinan Divarci |
0:4a2754e462db | 666 | * |
| Sinan Divarci |
0:4a2754e462db | 667 | * @param[in] meas Timestamp number. |
| Sinan Divarci |
0:4a2754e462db | 668 | * |
| Sinan Divarci |
0:4a2754e462db | 669 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 670 | */ |
| Sinan Divarci |
0:4a2754e462db | 671 | int offset_configuration(int meas); |
| Sinan Divarci |
0:4a2754e462db | 672 | |
| Sinan Divarci |
0:4a2754e462db | 673 | /** |
| Sinan Divarci |
0:4a2754e462db | 674 | * @brief Allow the OSF to indicate the oscillator status. |
| Sinan Divarci |
0:4a2754e462db | 675 | * |
| Sinan Divarci |
0:4a2754e462db | 676 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 677 | */ |
| Sinan Divarci |
0:4a2754e462db | 678 | int oscillator_flag_enable(); |
| Sinan Divarci |
0:4a2754e462db | 679 | |
| Sinan Divarci |
0:4a2754e462db | 680 | /** |
| Sinan Divarci |
0:4a2754e462db | 681 | * @brief Disable the oscillator flag, irrespective of the oscillator status |
| Sinan Divarci |
0:4a2754e462db | 682 | * |
| Sinan Divarci |
0:4a2754e462db | 683 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 684 | */ |
| Sinan Divarci |
0:4a2754e462db | 685 | int oscillator_flag_disable(); |
| Sinan Divarci |
0:4a2754e462db | 686 | |
| Sinan Divarci |
0:4a2754e462db | 687 | /** |
| Sinan Divarci |
0:4a2754e462db | 688 | * @brief Function pointer type to interrupt handler function |
| Sinan Divarci |
0:4a2754e462db | 689 | */ |
| Sinan Divarci |
0:4a2754e462db | 690 | typedef void (*interrupt_handler_function)(void *); |
| Sinan Divarci |
0:4a2754e462db | 691 | |
| Sinan Divarci |
0:4a2754e462db | 692 | /** |
| Sinan Divarci |
0:4a2754e462db | 693 | * @brief Set interrupt handler for a specific interrupt id |
| Sinan Divarci |
0:4a2754e462db | 694 | * |
| Sinan Divarci |
0:4a2754e462db | 695 | * @param[in] id Interrupt id, one of INTR_ID_* |
| Sinan Divarci |
0:4a2754e462db | 696 | * @param[in] func Interrupt handler function |
| Sinan Divarci |
0:4a2754e462db | 697 | * @param[in] cb Interrupt handler data |
| Sinan Divarci |
0:4a2754e462db | 698 | */ |
| Sinan Divarci |
0:4a2754e462db | 699 | void set_intr_handler(intr_id_t id, interrupt_handler_function func, void *cb); |
| Sinan Divarci |
0:4a2754e462db | 700 | |
| Sinan Divarci |
0:4a2754e462db | 701 | protected: |
| Sinan Divarci |
0:4a2754e462db | 702 | |
| Sinan Divarci |
0:4a2754e462db | 703 | typedef struct { |
| Sinan Divarci |
0:4a2754e462db | 704 | uint8_t status_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 705 | uint8_t int_en_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 706 | uint8_t rtc_reset_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 707 | uint8_t rtc_config1_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 708 | uint8_t rtc_config2_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 709 | uint8_t timestamp_config_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 710 | uint8_t timer_config_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 711 | uint8_t sleep_config_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 712 | uint8_t seconds_1_128_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 713 | uint8_t seconds_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 714 | uint8_t minutes_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 715 | uint8_t hours_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 716 | uint8_t day_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 717 | uint8_t date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 718 | uint8_t month_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 719 | uint8_t year_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 720 | uint8_t alm1_sec_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 721 | uint8_t alm1_min_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 722 | uint8_t alm1_hrs_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 723 | uint8_t alm1_day_date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 724 | uint8_t alm1_mon_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 725 | uint8_t alm1_year_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 726 | uint8_t alm2_min_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 727 | uint8_t alm2_hrs_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 728 | uint8_t alm2_day_date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 729 | uint8_t timer_count_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 730 | uint8_t timer_count2_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 731 | uint8_t timer_count1_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 732 | uint8_t timer_init_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 733 | uint8_t timer_init2_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 734 | uint8_t timer_init1_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 735 | uint8_t pwr_mgmt_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 736 | uint8_t trickle_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 737 | uint8_t offset_high_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 738 | uint8_t offset_low_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 739 | uint8_t ts0_sec_1_128_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 740 | uint8_t ts0_sec_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 741 | uint8_t ts0_min_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 742 | uint8_t ts0_hour_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 743 | uint8_t ts0_date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 744 | uint8_t ts0_month_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 745 | uint8_t ts0_year_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 746 | uint8_t ts0_flags_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 747 | uint8_t ts1_sec_1_128_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 748 | uint8_t ts1_sec_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 749 | uint8_t ts1_min_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 750 | uint8_t ts1_hour_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 751 | uint8_t ts1_date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 752 | uint8_t ts1_month_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 753 | uint8_t ts1_year_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 754 | uint8_t ts1_flags_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 755 | uint8_t ts2_sec_1_128_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 756 | uint8_t ts2_sec_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 757 | uint8_t ts2_min_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 758 | uint8_t ts2_hour_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 759 | uint8_t ts2_date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 760 | uint8_t ts2_month_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 761 | uint8_t ts2_year_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 762 | uint8_t ts2_flags_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 763 | uint8_t ts3_sec_1_128_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 764 | uint8_t ts3_sec_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 765 | uint8_t ts3_min_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 766 | uint8_t ts3_hour_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 767 | uint8_t ts3_date_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 768 | uint8_t ts3_month_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 769 | uint8_t ts3_year_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 770 | uint8_t ts3_flags_reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 771 | }reg_addr_t; |
| Sinan Divarci |
0:4a2754e462db | 772 | |
| Sinan Divarci |
0:4a2754e462db | 773 | /* Constructors */ |
| Sinan Divarci |
0:4a2754e462db | 774 | MAX3133X(const reg_addr_t *reg_addr, I2C *i2c, PinName inta_pin = NC, PinName intb_pin = NC); |
| Sinan Divarci |
0:4a2754e462db | 775 | |
| Sinan Divarci |
0:4a2754e462db | 776 | private: |
| Sinan Divarci |
0:4a2754e462db | 777 | /* PRIVATE TYPE DECLARATIONS */ |
| Sinan Divarci |
0:4a2754e462db | 778 | |
| Sinan Divarci |
0:4a2754e462db | 779 | /* PRIVATE VARIABLE DECLARATIONS */ |
| Sinan Divarci |
0:4a2754e462db | 780 | I2C *i2c_handler; |
| Sinan Divarci |
0:4a2754e462db | 781 | InterruptIn *inta_pin; |
| Sinan Divarci |
0:4a2754e462db | 782 | InterruptIn *intb_pin; |
| Sinan Divarci |
0:4a2754e462db | 783 | |
| Sinan Divarci |
0:4a2754e462db | 784 | /* PRIVATE CONSTANT VARIABLE DECLARATIONS */ |
| Sinan Divarci |
0:4a2754e462db | 785 | const reg_addr_t *reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 786 | |
| Sinan Divarci |
0:4a2754e462db | 787 | /* PRIVATE FUNCTION DECLARATIONS */ |
| Sinan Divarci |
0:4a2754e462db | 788 | void rtc_regs_to_time(struct tm *time, const max3133x_rtc_time_regs_t *regs, uint16_t *sub_sec); |
| Sinan Divarci |
0:4a2754e462db | 789 | |
| Sinan Divarci |
0:4a2754e462db | 790 | int time_to_rtc_regs(max3133x_rtc_time_regs_t *regs, const struct tm *time, hour_format_t format); |
| Sinan Divarci |
0:4a2754e462db | 791 | |
| Sinan Divarci |
0:4a2754e462db | 792 | void timestamp_regs_to_time(timestamp_t *timestamp, const max3133x_ts_regs_t *timestamp_reg); |
| Sinan Divarci |
0:4a2754e462db | 793 | |
| Sinan Divarci |
0:4a2754e462db | 794 | int time_to_alarm_regs(max3133x_alarm_regs_t ®s, const struct tm *alarm_time, hour_format_t format); |
| Sinan Divarci |
0:4a2754e462db | 795 | |
| Sinan Divarci |
0:4a2754e462db | 796 | void alarm_regs_to_time(alarm_no_t alarm_no, struct tm *alarm_time, const max3133x_alarm_regs_t *regs, hour_format_t format); |
| Sinan Divarci |
0:4a2754e462db | 797 | |
| Sinan Divarci |
0:4a2754e462db | 798 | int set_alarm_period(alarm_no_t alarm_no, max3133x_alarm_regs_t ®s, alarm_period_t period); |
| Sinan Divarci |
0:4a2754e462db | 799 | |
| Sinan Divarci |
0:4a2754e462db | 800 | int set_alarm_regs(alarm_no_t alarm_no, const max3133x_alarm_regs_t *regs); |
| Sinan Divarci |
0:4a2754e462db | 801 | |
| Sinan Divarci |
0:4a2754e462db | 802 | uint8_t to_24hr(uint8_t hr, uint8_t pm); |
| Sinan Divarci |
0:4a2754e462db | 803 | |
| Sinan Divarci |
0:4a2754e462db | 804 | void to_12hr(uint8_t hr, uint8_t *hr_12, uint8_t *pm); |
| Sinan Divarci |
0:4a2754e462db | 805 | |
| Sinan Divarci |
0:4a2754e462db | 806 | int get_rtc_time_format(hour_format_t *format); |
| Sinan Divarci |
0:4a2754e462db | 807 | |
| Sinan Divarci |
0:4a2754e462db | 808 | int data_retention_mode_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 809 | |
| Sinan Divarci |
0:4a2754e462db | 810 | int battery_voltage_detector_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 811 | |
| Sinan Divarci |
0:4a2754e462db | 812 | int clkout_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 813 | |
| Sinan Divarci |
0:4a2754e462db | 814 | int i2c_timeout_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 815 | |
| Sinan Divarci |
0:4a2754e462db | 816 | int oscillator_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 817 | |
| Sinan Divarci |
0:4a2754e462db | 818 | int timestamp_overwrite_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 819 | |
| Sinan Divarci |
0:4a2754e462db | 820 | int oscillator_flag_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 821 | |
| Sinan Divarci |
0:4a2754e462db | 822 | /** |
| Sinan Divarci |
0:4a2754e462db | 823 | * @brief Interrupt handler function |
| Sinan Divarci |
0:4a2754e462db | 824 | */ |
| Sinan Divarci |
0:4a2754e462db | 825 | void interrupt_handler(); |
| Sinan Divarci |
0:4a2754e462db | 826 | |
| Sinan Divarci |
0:4a2754e462db | 827 | /** |
| Sinan Divarci |
0:4a2754e462db | 828 | * @brief Post interrupt jobs after interrupt is detected. |
| Sinan Divarci |
0:4a2754e462db | 829 | */ |
| Sinan Divarci |
0:4a2754e462db | 830 | void post_interrupt_work(); |
| Sinan Divarci |
0:4a2754e462db | 831 | |
| Sinan Divarci |
0:4a2754e462db | 832 | Thread *post_intr_work_thread; |
| Sinan Divarci |
0:4a2754e462db | 833 | |
| Sinan Divarci |
0:4a2754e462db | 834 | struct handler { |
| Sinan Divarci |
0:4a2754e462db | 835 | void (*func)(void *); |
| Sinan Divarci |
0:4a2754e462db | 836 | void *cb; |
| Sinan Divarci |
0:4a2754e462db | 837 | }; |
| Sinan Divarci |
0:4a2754e462db | 838 | |
| Sinan Divarci |
0:4a2754e462db | 839 | handler interrupt_handler_list[NUM_OF_INTR_ID]; |
| Sinan Divarci |
0:4a2754e462db | 840 | }; |
| Sinan Divarci |
0:4a2754e462db | 841 | |
| Sinan Divarci |
0:4a2754e462db | 842 | /** MAX31334 Device Class |
| Sinan Divarci |
0:4a2754e462db | 843 | * |
| Sinan Divarci |
0:4a2754e462db | 844 | * Hold configurations for the MAX31334 |
| Sinan Divarci |
0:4a2754e462db | 845 | */ |
| Sinan Divarci |
0:4a2754e462db | 846 | class MAX31334 : public MAX3133X |
| Sinan Divarci |
0:4a2754e462db | 847 | { |
| Sinan Divarci |
0:4a2754e462db | 848 | private: |
| Sinan Divarci |
0:4a2754e462db | 849 | static const reg_addr_t reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 850 | |
| Sinan Divarci |
0:4a2754e462db | 851 | int din_sleep_entry_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 852 | |
| Sinan Divarci |
0:4a2754e462db | 853 | int din_pin_debounce_config(bool enable); |
| Sinan Divarci |
0:4a2754e462db | 854 | |
| Sinan Divarci |
0:4a2754e462db | 855 | public: |
| Sinan Divarci |
0:4a2754e462db | 856 | typedef struct { |
| Sinan Divarci |
0:4a2754e462db | 857 | a1ac_t a1ac; /*RTC_CONFIG1 - Alarm1 Auto Clear */ |
| Sinan Divarci |
0:4a2754e462db | 858 | dip_t dip; /*RTC_CONFIG1 - Digital (DIN) interrupt polarity */ |
| Sinan Divarci |
0:4a2754e462db | 859 | data_ret_t data_ret; /*RTC_CONFIG1 - Data retention mode enable/disable. */ |
| Sinan Divarci |
0:4a2754e462db | 860 | i2c_timeout_t i2c_timeout;/*RTC_CONFIG1 - I2C timeout enable */ |
| Sinan Divarci |
0:4a2754e462db | 861 | en_osc_t en_osc; /*RTC_CONFIG1 - Active-high enable for the crystal oscillator */ |
| Sinan Divarci |
0:4a2754e462db | 862 | dse_t dse; /*RTC_CONFIG2 - Digital (DIN) pin Sleep Entry Enable */ |
| Sinan Divarci |
0:4a2754e462db | 863 | ddb_t ddb; /*RTC_CONFIG2 - Digital (DIN) pin Debounce Enable */ |
| Sinan Divarci |
0:4a2754e462db | 864 | enclko_t enclko; /*RTC_CONFIG2 - CLKOUT enable */ |
| Sinan Divarci |
0:4a2754e462db | 865 | clko_hz_t clko_hz; /*RTC_CONFIG2 - Set output clock frequency on INTBb/CLKOUT pin */ |
| Sinan Divarci |
0:4a2754e462db | 866 | }rtc_config_t; |
| Sinan Divarci |
0:4a2754e462db | 867 | |
| Sinan Divarci |
0:4a2754e462db | 868 | /** |
| Sinan Divarci |
0:4a2754e462db | 869 | * @brief Configure the device |
| Sinan Divarci |
0:4a2754e462db | 870 | * |
| Sinan Divarci |
0:4a2754e462db | 871 | * @param[in] max31334_config Device configuration |
| Sinan Divarci |
0:4a2754e462db | 872 | * |
| Sinan Divarci |
0:4a2754e462db | 873 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 874 | * |
| Sinan Divarci |
0:4a2754e462db | 875 | * @note RTC_CONFIG1 and RTC_CONFIG2 registers are set. |
| Sinan Divarci |
0:4a2754e462db | 876 | */ |
| Sinan Divarci |
0:4a2754e462db | 877 | int rtc_config(rtc_config_t *max31334_config); |
| Sinan Divarci |
0:4a2754e462db | 878 | |
| Sinan Divarci |
0:4a2754e462db | 879 | /** |
| Sinan Divarci |
0:4a2754e462db | 880 | * @brief Get device configuration |
| Sinan Divarci |
0:4a2754e462db | 881 | * |
| Sinan Divarci |
0:4a2754e462db | 882 | * @param[out] max31334_config Device configuration |
| Sinan Divarci |
0:4a2754e462db | 883 | * |
| Sinan Divarci |
0:4a2754e462db | 884 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 885 | * |
| Sinan Divarci |
0:4a2754e462db | 886 | * @note RTC_CONFIG1 and RTC_CONFIG2 register values are read. |
| Sinan Divarci |
0:4a2754e462db | 887 | */ |
| Sinan Divarci |
0:4a2754e462db | 888 | int get_rtc_config(rtc_config_t *max31334_config); |
| Sinan Divarci |
0:4a2754e462db | 889 | |
| Sinan Divarci |
0:4a2754e462db | 890 | /** |
| Sinan Divarci |
0:4a2754e462db | 891 | * @brief Initialize timer |
| Sinan Divarci |
0:4a2754e462db | 892 | * |
| Sinan Divarci |
0:4a2754e462db | 893 | * @param[in] init_val Timer initial value |
| Sinan Divarci |
0:4a2754e462db | 894 | * @param[in] repeat Timer repeat mode enable/disable |
| Sinan Divarci |
0:4a2754e462db | 895 | * @param[in] freq Timer frequency, one of TIMER_FREQ_* |
| Sinan Divarci |
0:4a2754e462db | 896 | * |
| Sinan Divarci |
0:4a2754e462db | 897 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 898 | */ |
| Sinan Divarci |
0:4a2754e462db | 899 | int timer_init(uint16_t init_val, bool repeat, timer_freq_t freq); |
| Sinan Divarci |
0:4a2754e462db | 900 | |
| Sinan Divarci |
0:4a2754e462db | 901 | /** |
| Sinan Divarci |
0:4a2754e462db | 902 | * @brief Read timer value |
| Sinan Divarci |
0:4a2754e462db | 903 | * |
| Sinan Divarci |
0:4a2754e462db | 904 | * @return timer value on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 905 | */ |
| Sinan Divarci |
0:4a2754e462db | 906 | int timer_get(); |
| Sinan Divarci |
0:4a2754e462db | 907 | |
| Sinan Divarci |
0:4a2754e462db | 908 | /** |
| Sinan Divarci |
0:4a2754e462db | 909 | * @brief Get Sleep State |
| Sinan Divarci |
0:4a2754e462db | 910 | * |
| Sinan Divarci |
0:4a2754e462db | 911 | * @return Sleep State. 0: SLST=0 indicates the PSW SM is not in Sleep state, |
| Sinan Divarci |
0:4a2754e462db | 912 | * 1: SLST=1 indicates the PSW SM is in Sleep state. |
| Sinan Divarci |
0:4a2754e462db | 913 | * negative: on failure |
| Sinan Divarci |
0:4a2754e462db | 914 | */ |
| Sinan Divarci |
0:4a2754e462db | 915 | int get_sleep_state(); |
| Sinan Divarci |
0:4a2754e462db | 916 | |
| Sinan Divarci |
0:4a2754e462db | 917 | /** |
| Sinan Divarci |
0:4a2754e462db | 918 | * @brief Enable the Digital (DIN) pin Sleep Entry |
| Sinan Divarci |
0:4a2754e462db | 919 | * |
| Sinan Divarci |
0:4a2754e462db | 920 | * @details DIN pin can be used to enter sleep state. |
| Sinan Divarci |
0:4a2754e462db | 921 | * |
| Sinan Divarci |
0:4a2754e462db | 922 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 923 | */ |
| Sinan Divarci |
0:4a2754e462db | 924 | int din_sleep_entry_enable(); |
| Sinan Divarci |
0:4a2754e462db | 925 | |
| Sinan Divarci |
0:4a2754e462db | 926 | /** |
| Sinan Divarci |
0:4a2754e462db | 927 | * @brief Disable the Digital (DIN) pin Sleep Entry |
| Sinan Divarci |
0:4a2754e462db | 928 | * |
| Sinan Divarci |
0:4a2754e462db | 929 | * @details DIN pin cannot be used to enter sleep state (Sleep state entry is only possible by writing SLP=1 over I2C). |
| Sinan Divarci |
0:4a2754e462db | 930 | * |
| Sinan Divarci |
0:4a2754e462db | 931 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 932 | */ |
| Sinan Divarci |
0:4a2754e462db | 933 | int din_sleep_entry_disable(); |
| Sinan Divarci |
0:4a2754e462db | 934 | |
| Sinan Divarci |
0:4a2754e462db | 935 | /** |
| Sinan Divarci |
0:4a2754e462db | 936 | * @brief Enable the Digital (DIN) pin Debounce function |
| Sinan Divarci |
0:4a2754e462db | 937 | * |
| Sinan Divarci |
0:4a2754e462db | 938 | * @details 50ms debounce on DIN pin enabled. |
| Sinan Divarci |
0:4a2754e462db | 939 | * |
| Sinan Divarci |
0:4a2754e462db | 940 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 941 | */ |
| Sinan Divarci |
0:4a2754e462db | 942 | int din_pin_debounce_enable(); |
| Sinan Divarci |
0:4a2754e462db | 943 | |
| Sinan Divarci |
0:4a2754e462db | 944 | /** |
| Sinan Divarci |
0:4a2754e462db | 945 | * @brief Disable the Digital (DIN) pin Debounce function |
| Sinan Divarci |
0:4a2754e462db | 946 | * |
| Sinan Divarci |
0:4a2754e462db | 947 | * @details No debounce on DIN pin. |
| Sinan Divarci |
0:4a2754e462db | 948 | * |
| Sinan Divarci |
0:4a2754e462db | 949 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 950 | */ |
| Sinan Divarci |
0:4a2754e462db | 951 | int din_pin_debounce_disable(); |
| Sinan Divarci |
0:4a2754e462db | 952 | |
| Sinan Divarci |
0:4a2754e462db | 953 | /** |
| Sinan Divarci |
0:4a2754e462db | 954 | * @brief Put PSW SM into Active state. |
| Sinan Divarci |
0:4a2754e462db | 955 | * |
| Sinan Divarci |
0:4a2754e462db | 956 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 957 | */ |
| Sinan Divarci |
0:4a2754e462db | 958 | int sleep_enter(); |
| Sinan Divarci |
0:4a2754e462db | 959 | |
| Sinan Divarci |
0:4a2754e462db | 960 | /** |
| Sinan Divarci |
0:4a2754e462db | 961 | * @brief Put PSW SM into Sleep state. |
| Sinan Divarci |
0:4a2754e462db | 962 | * |
| Sinan Divarci |
0:4a2754e462db | 963 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 964 | */ |
| Sinan Divarci |
0:4a2754e462db | 965 | int sleep_exit(); |
| Sinan Divarci |
0:4a2754e462db | 966 | |
| Sinan Divarci |
0:4a2754e462db | 967 | /** |
| Sinan Divarci |
0:4a2754e462db | 968 | * @brief Register Configuration |
| Sinan Divarci |
0:4a2754e462db | 969 | * |
| Sinan Divarci |
0:4a2754e462db | 970 | * @details |
| Sinan Divarci |
0:4a2754e462db | 971 | * - Register : SLEEP_CONFIG |
| Sinan Divarci |
0:4a2754e462db | 972 | * - Bit Fields : [6:4] |
| Sinan Divarci |
0:4a2754e462db | 973 | * - Default : 0x0 |
| Sinan Divarci |
0:4a2754e462db | 974 | * - Description : Wait State Timeout. This bitfield must be set before writing SLP=1 if a finite wait state duration is |
| Sinan Divarci |
0:4a2754e462db | 975 | * desired before entering the sleep state. |
| Sinan Divarci |
0:4a2754e462db | 976 | */ |
| Sinan Divarci |
0:4a2754e462db | 977 | typedef enum { |
| Sinan Divarci |
0:4a2754e462db | 978 | WSTO_0MS, /**< 0ms */ |
| Sinan Divarci |
0:4a2754e462db | 979 | WSTO_8MS, /**< 8ms */ |
| Sinan Divarci |
0:4a2754e462db | 980 | WSTO_16MS, /**< 16ms */ |
| Sinan Divarci |
0:4a2754e462db | 981 | WSTO_24MS, /**< 24ms */ |
| Sinan Divarci |
0:4a2754e462db | 982 | WSTO_32MS, /**< 32ms */ |
| Sinan Divarci |
0:4a2754e462db | 983 | WSTO_40MS, /**< 40ms */ |
| Sinan Divarci |
0:4a2754e462db | 984 | WSTO_48MS, /**< 48ms */ |
| Sinan Divarci |
0:4a2754e462db | 985 | WSTO_56MS /**< 56ms */ |
| Sinan Divarci |
0:4a2754e462db | 986 | }wsto_t; |
| Sinan Divarci |
0:4a2754e462db | 987 | |
| Sinan Divarci |
0:4a2754e462db | 988 | /** |
| Sinan Divarci |
0:4a2754e462db | 989 | * @brief Set Wait State Timeout |
| Sinan Divarci |
0:4a2754e462db | 990 | * |
| Sinan Divarci |
0:4a2754e462db | 991 | * @param[in] wsto Wait State Timeout |
| Sinan Divarci |
0:4a2754e462db | 992 | * |
| Sinan Divarci |
0:4a2754e462db | 993 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 994 | */ |
| Sinan Divarci |
0:4a2754e462db | 995 | int set_wait_state_timeout(wsto_t wsto); |
| Sinan Divarci |
0:4a2754e462db | 996 | |
| Sinan Divarci |
0:4a2754e462db | 997 | /** |
| Sinan Divarci |
0:4a2754e462db | 998 | * @brief Get Wait State Timeout |
| Sinan Divarci |
0:4a2754e462db | 999 | * |
| Sinan Divarci |
0:4a2754e462db | 1000 | * @param[out] wsto Wait State Timeout |
| Sinan Divarci |
0:4a2754e462db | 1001 | * |
| Sinan Divarci |
0:4a2754e462db | 1002 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 1003 | */ |
| Sinan Divarci |
0:4a2754e462db | 1004 | int get_wait_state_timeout(wsto_t* wsto); |
| Sinan Divarci |
0:4a2754e462db | 1005 | |
| Sinan Divarci |
0:4a2754e462db | 1006 | /*Sleep Config Register Masks*/ |
| Sinan Divarci |
0:4a2754e462db | 1007 | #define A1WE 0b00000001 /*Alarm1 Wakeup Enable */ |
| Sinan Divarci |
0:4a2754e462db | 1008 | #define A2WE 0b00000010 /*Alarm2 Wakeup Enable */ |
| Sinan Divarci |
0:4a2754e462db | 1009 | #define TWE 0b00000100 /*Timer Wakeup Enable */ |
| Sinan Divarci |
0:4a2754e462db | 1010 | #define DWE 0b00001000 /*DIN Wakeup Enable */ |
| Sinan Divarci |
0:4a2754e462db | 1011 | |
| Sinan Divarci |
0:4a2754e462db | 1012 | /** |
| Sinan Divarci |
0:4a2754e462db | 1013 | * @brief Enable Wakeup |
| Sinan Divarci |
0:4a2754e462db | 1014 | * |
| Sinan Divarci |
0:4a2754e462db | 1015 | * @param[in] wakeup_enable_mask one or more of Sleep Config Register Masks |
| Sinan Divarci |
0:4a2754e462db | 1016 | * |
| Sinan Divarci |
0:4a2754e462db | 1017 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 1018 | */ |
| Sinan Divarci |
0:4a2754e462db | 1019 | int wakeup_enable(uint8_t wakeup_enable_mask); |
| Sinan Divarci |
0:4a2754e462db | 1020 | |
| Sinan Divarci |
0:4a2754e462db | 1021 | /** |
| Sinan Divarci |
0:4a2754e462db | 1022 | * @brief Disable Wakeup |
| Sinan Divarci |
0:4a2754e462db | 1023 | * |
| Sinan Divarci |
0:4a2754e462db | 1024 | * @param[in] wakeup_disable_mask one or more of Sleep Config Register Masks |
| Sinan Divarci |
0:4a2754e462db | 1025 | * |
| Sinan Divarci |
0:4a2754e462db | 1026 | * @returns MAX3133X_NO_ERR on success, error code on failure. |
| Sinan Divarci |
0:4a2754e462db | 1027 | */ |
| Sinan Divarci |
0:4a2754e462db | 1028 | int wakeup_disable(uint8_t wakeup_disable_mask); |
| Sinan Divarci |
0:4a2754e462db | 1029 | |
| Sinan Divarci |
0:4a2754e462db | 1030 | MAX31334(I2C *i2c, PinName inta_pin = NC, PinName intb_pin = NC) : MAX3133X(®_addr, i2c, inta_pin, intb_pin) {} |
| Sinan Divarci |
0:4a2754e462db | 1031 | }; |
| Sinan Divarci |
0:4a2754e462db | 1032 | |
| Sinan Divarci |
0:4a2754e462db | 1033 | /** MAX31331 Device Class |
| Sinan Divarci |
0:4a2754e462db | 1034 | * |
| Sinan Divarci |
0:4a2754e462db | 1035 | * Hold configurations for the MAX31331 |
| Sinan Divarci |
0:4a2754e462db | 1036 | */ |
| Sinan Divarci |
0:4a2754e462db | 1037 | class MAX31331 : public MAX3133X |
| Sinan Divarci |
0:4a2754e462db | 1038 | { |
| Sinan Divarci |
0:4a2754e462db | 1039 | private: |
| Sinan Divarci |
0:4a2754e462db | 1040 | static const reg_addr_t reg_addr; |
| Sinan Divarci |
0:4a2754e462db | 1041 | |
| Sinan Divarci |
0:4a2754e462db | 1042 | public: |
| Sinan Divarci |
0:4a2754e462db | 1043 | typedef struct { |
| Sinan Divarci |
0:4a2754e462db | 1044 | a1ac_t a1ac; /*RTC_CONFIG1 - Alarm1 Auto Clear */ |
| Sinan Divarci |
0:4a2754e462db | 1045 | dip_t dip; /*RTC_CONFIG1 - Digital (DIN) interrupt polarity */ |
| Sinan Divarci |
0:4a2754e462db | 1046 | data_ret_t data_ret; /*RTC_CONFIG1 - Data retention mode enable/disable. */ |
| Sinan Divarci |
0:4a2754e462db | 1047 | i2c_timeout_t i2c_timeout;/*RTC_CONFIG1 - I2C timeout enable */ |
| Sinan Divarci |
0:4a2754e462db | 1048 | en_osc_t en_osc; /*RTC_CONFIG1 - Active-high enable for the crystal oscillator */ |
| Sinan Divarci |
0:4a2754e462db | 1049 | enclko_t enclko; /*RTC_CONFIG2 - CLKOUT enable */ |
| Sinan Divarci |
0:4a2754e462db | 1050 | clko_hz_t clko_hz; /*RTC_CONFIG2 - Set output clock frequency on INTBb/CLKOUT pin */ |
| Sinan Divarci |
0:4a2754e462db | 1051 | }rtc_config_t; |
| Sinan Divarci |
0:4a2754e462db | 1052 | |
| Sinan Divarci |
0:4a2754e462db | 1053 | /** |
| Sinan Divarci |
0:4a2754e462db | 1054 | * @brief Configure the device |
| Sinan Divarci |
0:4a2754e462db | 1055 | * |
| Sinan Divarci |
0:4a2754e462db | 1056 | * @param[in] max31331_config Device configuration |
| Sinan Divarci |
0:4a2754e462db | 1057 | * |
| Sinan Divarci |
0:4a2754e462db | 1058 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 1059 | * |
| Sinan Divarci |
0:4a2754e462db | 1060 | * @note RTC_CONFIG1 and RTC_CONFIG2 registers are set. |
| Sinan Divarci |
0:4a2754e462db | 1061 | */ |
| Sinan Divarci |
0:4a2754e462db | 1062 | int rtc_config(rtc_config_t *max31331_config); |
| Sinan Divarci |
0:4a2754e462db | 1063 | |
| Sinan Divarci |
0:4a2754e462db | 1064 | /** |
| Sinan Divarci |
0:4a2754e462db | 1065 | * @brief Get device configuration |
| Sinan Divarci |
0:4a2754e462db | 1066 | * |
| Sinan Divarci |
0:4a2754e462db | 1067 | * @param[out] max31331_config Device configuration |
| Sinan Divarci |
0:4a2754e462db | 1068 | * |
| Sinan Divarci |
0:4a2754e462db | 1069 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 1070 | * |
| Sinan Divarci |
0:4a2754e462db | 1071 | * @note RTC_CONFIG1 and RTC_CONFIG2 register values are read. |
| Sinan Divarci |
0:4a2754e462db | 1072 | */ |
| Sinan Divarci |
0:4a2754e462db | 1073 | int get_rtc_config(rtc_config_t *max31331_config); |
| Sinan Divarci |
0:4a2754e462db | 1074 | |
| Sinan Divarci |
0:4a2754e462db | 1075 | /** |
| Sinan Divarci |
0:4a2754e462db | 1076 | * @brief Initialize timer |
| Sinan Divarci |
0:4a2754e462db | 1077 | * |
| Sinan Divarci |
0:4a2754e462db | 1078 | * @param[in] init_val Timer initial value |
| Sinan Divarci |
0:4a2754e462db | 1079 | * @param[in] repeat Timer repeat mode enable/disable |
| Sinan Divarci |
0:4a2754e462db | 1080 | * @param[in] freq Timer frequency, one of TIMER_FREQ_* |
| Sinan Divarci |
0:4a2754e462db | 1081 | * |
| Sinan Divarci |
0:4a2754e462db | 1082 | * @return MAX3133X_NO_ERR on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 1083 | */ |
| Sinan Divarci |
0:4a2754e462db | 1084 | int timer_init(uint8_t init_val, bool repeat, timer_freq_t freq); |
| Sinan Divarci |
0:4a2754e462db | 1085 | |
| Sinan Divarci |
0:4a2754e462db | 1086 | /** |
| Sinan Divarci |
0:4a2754e462db | 1087 | * @brief Read timer value |
| Sinan Divarci |
0:4a2754e462db | 1088 | * |
| Sinan Divarci |
0:4a2754e462db | 1089 | * @return timer value on success, error code on failure |
| Sinan Divarci |
0:4a2754e462db | 1090 | */ |
| Sinan Divarci |
0:4a2754e462db | 1091 | int timer_get(); |
| Sinan Divarci |
0:4a2754e462db | 1092 | |
| Sinan Divarci |
0:4a2754e462db | 1093 | MAX31331(I2C *i2c, PinName inta_pin = NC, PinName intb_pin = NC) : MAX3133X(®_addr, i2c, inta_pin, intb_pin) {} |
| Sinan Divarci |
0:4a2754e462db | 1094 | }; |
| Sinan Divarci |
0:4a2754e462db | 1095 | |
| Sinan Divarci |
0:4a2754e462db | 1096 | #endif /* MAX3133X_HPP_ */ |