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SIMO PMIC with 300mA Switching Charger
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MAX77659_regs.h
00001 /******************************************************************************* 00002 * Copyright (C) 2022 Analog Devices, Inc., All rights Reserved. 00003 * 00004 * This software is protected by copyright laws of the United States and 00005 * of foreign countries. This material may also be protected by patent laws 00006 * and technology transfer regulations of the United States and of foreign 00007 * countries. This software is furnished under a license agreement and/or a 00008 * nondisclosure agreement and may only be used or reproduced in accordance 00009 * with the terms of those agreements. Dissemination of this information to 00010 * any party or parties not specified in the license agreement and/or 00011 * nondisclosure agreement is expressly prohibited. 00012 * 00013 * The above copyright notice and this permission notice shall be included 00014 * in all copies or substantial portions of the Software. 00015 * 00016 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00017 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00018 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00019 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES 00020 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00021 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00022 * OTHER DEALINGS IN THE SOFTWARE. 00023 * 00024 * Except as contained in this notice, the name of Maxim Integrated 00025 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00026 * Products, Inc. Branding Policy. 00027 * 00028 * The mere transfer of this software does not imply any licenses 00029 * of trade secrets, proprietary technology, copyrights, patents, 00030 * trademarks, maskwork rights, or any other form of intellectual 00031 * property whatsoever. Analog Devices, Inc. retains all 00032 * ownership rights. 00033 ******************************************************************************* 00034 */ 00035 00036 #ifndef MAX77659_REGS_H_ 00037 #define MAX77659_REGS_H_ 00038 00039 /** 00040 * @brief INT_GLBL0 Register 00041 * 00042 * Address : 0x00 00043 */ 00044 typedef union { 00045 unsigned char raw; 00046 struct { 00047 unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0. 00048 Note that "GPI" refers to the GPIO programmed to be an input. 00049 0 = No GPI falling edges have occurred since the last time this bit was read. 00050 1 = A GPI falling edge has occurred since the last time this bit was read. */ 00051 unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1. 00052 Note that "GPI" refers to the GPIO programmed to be an input. 00053 0 = No GPI rising edges have occurred since the last time this bit was read. 00054 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00055 unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2. 00056 0 = No nEN falling edges have occurred since the last time this bit was read. 00057 1 = A nEN falling edge as occurred since the last time this bit was read. */ 00058 unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3. 00059 0 = No nEN rising edges have occurred since the last time this bit was read. 00060 1 = A nEN rising edge as occurred since the last time this bit was read. */ 00061 unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4. 00062 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. 00063 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */ 00064 unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5. 00065 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. 00066 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */ 00067 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 6. */ 00068 unsigned char dod_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 7. 00069 0 = The LDO has not detected dropout since the last time this bit was read. 00070 1 = The LDO has detected dropout since the last time this bit was read. */ 00071 } bits; 00072 } reg_int_glbl0_t; 00073 00074 /** 00075 * @brief INT_GLBL1 Register 00076 * 00077 * Address : 0x04 00078 */ 00079 typedef union { 00080 unsigned char raw; 00081 struct { 00082 unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0. 00083 Note that "GPI" refers to the GPIO programmed to be an input. 00084 0 = No GPI falling edges have occurred since the last time this bit was read. 00085 1 = A GPI falling edge has occurred since the last time this bit was read. */ 00086 unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1. 00087 Note that "GPI" refers to the GPIO programmed to be an input. 00088 0 = No GPI rising edges have occurred since the last time this bit was read. 00089 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00090 unsigned char rsvd1 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3:2. */ 00091 unsigned char sbb_to : 1; /**< SBB Timeout. Bit 4. 00092 0 = NO SBB timeout occurred since the last time this bit was read 00093 1 = SBB timeout occurred since the last time this bit was read */ 00094 unsigned char ldo_f : 1; /**< LDO Fault Interrupt. Bit 5. 00095 0 = No fault has occurred on LDO since the last time this bit was read. 00096 1 = LDO has fallen out of regulation since the last time this bit was read. */ 00097 unsigned char ldo1_f : 1; /**< LDO1 Fault Interrupt. Bit 6. 00098 0 = No fault has occurred on LDO1 since the last time this bit was read. 00099 1 = LDO1 has fallen out of regulation since the last time this bit was read. */ 00100 unsigned char rsvd2 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */ 00101 } bits; 00102 } reg_int_glbl1_t; 00103 00104 /** 00105 * @brief ERCFLAG Register 00106 * 00107 * Address : 0x05 00108 */ 00109 typedef union { 00110 unsigned char raw; 00111 struct { 00112 unsigned char tovld : 1; /**< Thermal Overload. Bit 0. 00113 0 = Thermal overload has not occurred since the last read of this register. 00114 1 = Thermal overload has occurred since the list read of this register. 00115 This indicates that the junction temperature has exceeded 165ºC. */ 00116 unsigned char sysovlo : 1; /**< SYS Domain Overvoltage Lockout. Bit 1. 00117 0 = The SYS domain overvoltage lockout has not occurred since this last read of this register. 00118 1 = The SYS domain overvoltage lockout has occurred since the last read of this register. */ 00119 unsigned char avluvlo : 1; /**< AVL Domain Undervoltage Lockout. Bit 2. 00120 0 = The AVL domain undervoltage lockout has not occurred since this last read of this register. 00121 1 = The AVL domain undervoltage lockout has occurred since the last read of this register. */ 00122 unsigned char mrst : 1; /**< Manual Reset Timer. Bit 3. 00123 0 = A Manual Reset has not occurred since this last read of this register. 00124 1 = A Manual Reset has occurred since this last read of this register. */ 00125 unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4. 00126 0 = The SFT_OFF function has not occurred since the last read of this register. 00127 1 = The SFT_OFF function has occurred since the last read of this register. */ 00128 unsigned char sft_crst_f: 1; /**< Software Cold Reset Flag. Bit 5. 00129 0 = The software cold reset has not occurred since the last read of this register. 00130 1 = The software cold reset has occurred since the last read of this register. */ 00131 unsigned char wdt_off : 1; /**< Watchdog Timer OFF Flag. Bit 6. 00132 This bit sets when the watchdog timer expires and causes a power-off. 00133 0 = Watchdog timer has not caused a power-off since the last time this bit was read. 00134 1 = Watchdog timer has expired and caused a power-off since the last time this bit was read. */ 00135 unsigned char wdt_rst : 1; /**< Watchdog Timer Reset Flag. Bit 7. 00136 This bit sets when the watchdog timer expires and causes a power-reset. 00137 0 = Watchdog timer has not caused a power-reset since the last time this bit was read. 00138 1 = Watchdog timer has expired and caused a power-reset since the last time this bit was read.*/ 00139 } bits; 00140 } reg_ercflag_t; 00141 00142 /** 00143 * @brief STAT_GLBL Register 00144 * 00145 * Address : 0x06 00146 */ 00147 typedef union { 00148 unsigned char raw; 00149 struct { 00150 unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0. 00151 0 = unmasked gate drive is logic low 00152 1 = unmasked gate drive is logic high */ 00153 unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1. 00154 0 = nEN is not active (logic high) 00155 1 = nEN is active (logic low) */ 00156 unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2. 00157 0 = The junction temperature is less than TJAL1 00158 1 = The junction temperature is greater than TJAL1 */ 00159 unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3. 00160 0 = The junction temperature is less than TJAL2 00161 1 = The junction temperature is greater than TJAL2 */ 00162 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. */ 00163 unsigned char dod_s : 1; /**< LDO0 Dropout Detector Rising Status. Bit 5. 00164 0 = LDO0 is not in dropout 00165 1 = LDO0 is in dropout */ 00166 unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6. 00167 0 = Main Bias is not ready. 00168 1 = Main Bias enabled and ready. */ 00169 unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7. 00170 0 = MAX77659 00171 1 = Reserved */ 00172 } bits; 00173 } reg_stat_glbl_t; 00174 00175 /** 00176 * @brief INTM_GLBL1 Register 00177 * 00178 * Address : 0x08 00179 */ 00180 typedef union { 00181 unsigned char raw; 00182 struct { 00183 unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. 00184 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00185 nIRQ goes high when all interrupt bits are cleared. 00186 1 = Masked. nIRQ does not go low due to GPI_F. */ 00187 unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. 00188 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00189 nIRQ goes high when all interrupt bits are cleared. 00190 1 = Masked. nIRQ does not go low due to GPI_R. */ 00191 unsigned char rsvd1 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3:2. */ 00192 unsigned char sbb_to_m : 1; /**< SBB Timeout Mask. Bit 4. 00193 0 = Unmasked. If SBB_TO goes from 0 to 1, then nIRQ goes low. 00194 nIRQ goes high when all interrupt bits are cleared. 00195 1 = Masked. nIRQ does not go low due to SBB_TO */ 00196 unsigned char ldo_m : 1; /**< LDO0 Fault Interrupt. Bit 5. 00197 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. 00198 nIRQ goes high when all interrupt bits are cleared. 00199 1 = Masked. nIRQ does not go low due to LDO0_F. */ 00200 unsigned char rsvd2 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */ 00201 } bits; 00202 } reg_intm_glbl1_t; 00203 00204 /** 00205 * @brief INTM_GLBL0 Register 00206 * 00207 * Address : 0x09 00208 */ 00209 typedef union { 00210 unsigned char raw; 00211 struct { 00212 unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. 00213 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00214 nIRQ goes high when all interrupt bits are cleared. 00215 1 = Masked. nIRQ does not go low due to GPI_F. */ 00216 unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. 00217 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00218 nIRQ goes high when all interrupt bits are cleared. 00219 1 = Masked. nIRQ does not go low due to GPI_R. */ 00220 unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2. 00221 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. 00222 nIRQ goes high when all interrupt bits are cleared. 00223 1 = Masked. nIRQ does not go low due to nEN_F. */ 00224 unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3. 00225 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. 00226 nIRQ goes high when all interrupt bits are cleared. 00227 1 = Masked. nIRQ does not go low due to nEN_R. */ 00228 unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4. 00229 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. 00230 nIRQ goes high when all interrupt bits are cleared. 00231 1 = Masked. nIRQ does not go low due to TJAL1_R. */ 00232 unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5. 00233 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. 00234 nIRQ goes high when all interrupt bits are cleared. 00235 1 = Masked. nIRQ does not go low due to TJAL2_R. */ 00236 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 6. */ 00237 unsigned char dod_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 7. 00238 0 = Unmasked. If DOD0_R goes from 0 to 1, then nIRQ goes low. 00239 nIRQ goes high when all interrupt bits are cleared. 00240 1 = Masked. nIRQ does not go low due to DOD0_R. */ 00241 } bits; 00242 } reg_intm_glbl0_t; 00243 00244 /** 00245 * @brief CNFG_GLBL Register 00246 * 00247 * Address : 0x10 00248 */ 00249 typedef union { 00250 unsigned char raw; 00251 struct { 00252 unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0. 00253 0b00 = No Action 00254 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again. 00255 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. 00256 0b11 = Factory-Ship Mode Enter (FSM). */ 00257 unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2. 00258 0 = 500μs Debounce 00259 1 = 30ms Debounce */ 00260 unsigned char nen_mode : 1; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 3. 00261 0 = Push-Button Mode 00262 1 = Slide-Switch Mode */ 00263 unsigned char sbia_en : 1; /**< Main Bias Enable Software Request. Bit 4. 00264 0 = Main Bias not enabled by software. 00265 Note that the main bias may be on via the on/off controller. 00266 1 = Main Bias force enabled by software. */ 00267 unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5. 00268 0 = Main Bias requested to be in Normal-Power Mode by software. 00269 1 = Main Bias request to be in Low-Power Mode by software. */ 00270 unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6. 00271 0 = 8s 00272 1 = 3.3s */ 00273 unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7. 00274 0 = Strong internal nEN pullup (200kΩ) 00275 1 = Weak internal nEN pullup (10MΩ) */ 00276 } bits; 00277 } reg_cnfg_glbl_t; 00278 00279 /** 00280 * @brief CNFG_GPIO0 Register 00281 * 00282 * Address : 0x11 00283 */ 00284 typedef union { 00285 unsigned char raw; 00286 struct { 00287 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00288 0 = General purpose output (GPO) 00289 1 = General purpose input (GPI) */ 00290 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00291 0 = Input logic low 00292 1 = Input logic high */ 00293 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00294 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00295 0 = Open-Drain 00296 1 = Push-Pull */ 00297 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00298 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00299 0 = GPIO is output is logic low 00300 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00301 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00302 0 = no debounce 00303 1 = 30ms debounce */ 00304 unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO0. Bit 5. 00305 0 = Standard GPIO. 00306 1 = Active-high input, enable control for low-power mode. */ 00307 unsigned char : 1; /**< Bit 6. */ 00308 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care. */ 00309 } bits; 00310 } reg_cnfg_gpio0_t; 00311 00312 /** 00313 * @brief CNFG_GPIO1 Register 00314 * 00315 * Address : 0x12 00316 */ 00317 typedef union { 00318 unsigned char raw; 00319 struct { 00320 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00321 0 = General purpose output (GPO) 00322 1 = General purpose input (GPI) */ 00323 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00324 0 = Input logic low 00325 1 = Input logic high */ 00326 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00327 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00328 0 = Open-Drain 00329 1 = Push-Pull */ 00330 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00331 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00332 0 = GPIO is output is logic low 00333 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00334 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00335 0 = no debounce 00336 1 = 30ms debounce */ 00337 unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO1. Bit 5. 00338 0 = Standard GPIO. 00339 1 = Active-high input, enable control for the DVS feature for SBB0. */ 00340 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */ 00341 } bits; 00342 } reg_cnfg_gpio1_t; 00343 00344 /** 00345 * @brief CID Register 00346 * 00347 * Address : 0x14 00348 */ 00349 typedef union { 00350 unsigned char raw; 00351 struct { 00352 unsigned char cid_3_0 : 4; /**< Bits 0 to 3 of the Chip Identification Code. Bit 3:0. 00353 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ 00354 unsigned char : 3; /**< Bit 6:4. */ 00355 unsigned char cid_7 : 1; /**< Bit 4 of the Chip Identification Code. Bit 7. 00356 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ 00357 } bits; 00358 } reg_cid_t; 00359 00360 /** 00361 * @brief CNFG_WDT Register 00362 * 00363 * Address : 0x17 00364 */ 00365 typedef union { 00366 unsigned char raw; 00367 struct { 00368 unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0. 00369 0 = Watchdog timer can be enabled and disabled with WDT_EN. 00370 1 = Watchdog timer can not be disabled with WDT_EN. 00371 However, WDT_EN can still be used to enable the watchdog timer. */ 00372 unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1. 00373 0 = Watchdog timer is not enabled. 00374 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */ 00375 unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2. 00376 0 = Watchdog timer period is not reset. 00377 1 = Watchdog timer is reset back to tWD. */ 00378 unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3. 00379 0 = Watchdog timer expire causes power-off. 00380 1 = Watchdog timer expire causes power-reset. */ 00381 unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4. 00382 0b00 = 16 seconds 0b01 = 32 seconds 00383 0b10 = 64 seconds 0b11 = 128 seconds. */ 00384 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. 00385 Unutilized bit. Write to 0. Reads are don't care. */ 00386 } bits; 00387 } reg_cnfg_wdt_t; 00388 00389 /** 00390 * @brief INT_CHG Register 00391 * 00392 * Address : 0x01 00393 */ 00394 typedef union { 00395 unsigned char raw; 00396 struct { 00397 unsigned char thm_i : 1; /**< Thermistor related interrupt. Bit 0. 00398 0 = The bits in THM_DTLS[2:0] have not changed since the last time this bit was read 00399 1 = The bits in THM_DTLS[2:0] have changed since the last time this bit was read */ 00400 unsigned char chg_i : 1; /**< Charger related interrupt. Bit 1. 00401 0 = The bits in CHG_DTLS[3:0] have not changed since the last time this bit was read 00402 1 = The bits in CHG_DTLS[3:0] have changed since the last time this bit was read */ 00403 unsigned char chgin_i : 1; /**< CHGIN related interrupt. Bit 2. 00404 0 = The bits in CHGIN_DTLS[1:0] have not changed since the last time this bit was read 00405 1 = The bits in CHGIN_DTLS[1:0] have changed since the last time this bit was read */ 00406 unsigned char tj_reg_i : 1; /**< Die junction temperature regulation interrupt. Bit 3. 00407 0 = The die temperature has not exceeded TJ-REG since the last time this bit was read 00408 1 = The die temperature has exceeded TJ-REG since the last time this bit was read */ 00409 unsigned char sys_ctrl_i : 1; /**< Minimum System Voltage Regulation-loop related interrupt. Bit 4. 00410 0 = The minimum system voltage regulation loop has not engaged since the last time this bit was read 00411 1 = The minimum system voltage regulation loop has engaged since the last time this bit was read */ 00412 unsigned char rsvd : 1; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */ 00413 } bits; 00414 } reg_int_chg_t; 00415 00416 /** 00417 * @brief STAT_CHG_A 00418 * 00419 * Address : 0x02 00420 */ 00421 typedef union { 00422 unsigned char raw; 00423 struct 00424 { 00425 unsigned char thm_dtls : 3; /**< Battery Temperature Details. Bit 2:0. 00426 0b000 = Thermistor is disabled (THM_EN = 0) 00427 0b001 = Battery is cold as programmed by THM_COLD[1:0] If thermistor and charger are enabled while the battery is cold, a battery temperature fault will occur. 00428 0b010 = Battery is cool as programmed by THM_COOL[1:0] 00429 0b011 = Battery is warm as programmed by THM_WARM[1:0] 00430 0b100 = Battery is hot as programmed by THM_HOT[1:0]. If thermistor and charger are enabled while the battery is hot, a battery temperature fault will occur. 00431 0b101 = Battery is in the normal temperature region 00432 0b110 - 0b111 = reserved */ 00433 unsigned char tj_reg_stat : 1; /**< Maximum Junction Temperature Regulation Loop Status. Bit 3. 00434 0 = The maximum junction temperature regulation loop is not engaged 00435 1 = The maximum junction temperature regulation loop has engaged to regulate the junction temperature to less than TJ-REG */ 00436 unsigned char vsys_min_stat : 1; /**< Minimum System Voltage Regulation Loop Status. Bit 4. 00437 0 = The minimum system voltage regulation loop is not enganged 00438 1 = The minimum system voltage regulation loop is engaged to regulate VSYS ≥ VSYS-MIN */ 00439 unsigned char rsvd : 3; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */ 00440 } bits; 00441 } reg_stat_chg_a_t; 00442 00443 /** 00444 * @brief STAT_CHG_B 00445 * 00446 * Address : 0x03 00447 */ 00448 typedef union { 00449 unsigned char raw; 00450 struct 00451 { 00452 unsigned char time_sus : 1; /**< Time Suspend Indicator. Bit 0. 00453 0 = The charger's timers are either not active, or not suspended 00454 1 = The charger's active timer is suspended due to one of three reasons: 00455 charge current dropped below 20% of IFAST-CHG while the charger state machine is in FAST CHARGE CC mode, 00456 the charger is in SUPPLEMENT mode, or the charger state machine is in BATTERY TEMPERATURE FAULT mode. */ 00457 unsigned char chg : 1; /**< Quick Charger Status. Bit 1. 00458 0 = Charging is not happening 00459 1 = Charging is happening */ 00460 unsigned char chgin_dtls : 2; /**< CHGIN Status Detail. Bit 3:2. 00461 0b00 = The CHGIN input voltage is below the UVLO threshold (VCHGIN < VUVLO) 00462 0b01 = The CHGIN input voltage is above the OVP threshold (VCHGIN > VOVP) 00463 0b10 = The CHGIN input is being debounced (no power accepted from CHGIN during debounce) 00464 0b11 = The CHGIN input is okay and debounced */ 00465 unsigned char chg_dtls : 4; /**< Charger Details. Bit 7:4. 00466 0b0000 = Off 00467 0b0001 = Prequalification mode 00468 0b0010 = Fast-charge constant-current (CC) mode 00469 0b0011 = JEITA modified fast-charge constant-current mode 00470 0b0100 = Fast-charge constant-voltage (CV) mode 00471 0b0101 = JEITA modified fast-charge constant-voltage mode 00472 0b0110 = Top-off mode 00473 0b0111 = JEITA modified top-off mode 00474 0b1000 = Done 00475 0b1001 = JEITA modified done (done was entered through the JEITA-modified fast-charge states) 00476 0b1010 = Prequalification timer fault 00477 0b1011 = Fast-charge timer fault 00478 0b1100 = Battery temperature fault 00479 0b1101 - 0b1111 = reserved */ 00480 } bits; 00481 } reg_stat_chg_b_t; 00482 00483 /** 00484 * @brief INT_M_CHG Register 00485 * 00486 * Address : 0x07 00487 */ 00488 typedef union { 00489 unsigned char raw; 00490 struct { 00491 unsigned char thm_m : 1; /**< Setting this bit prevents the THM_I bit from causing hardware IRQs. Bit 0. 00492 0 = THM_I is not masked 00493 1 = THM_I is masked */ 00494 unsigned char chg_m : 1; /**< Setting this bit prevents the CHG_I bit from causing hardware IRQs. Bit 1. 00495 0 = CHG_I is not masked 00496 1 = CHG_I is masked */ 00497 unsigned char chgin_m : 1; /**< Setting this bit prevents the CHGIN_I bit from causing hardware IRQs. Bit 2. 00498 0 = CHGIN_I is not masked 00499 1 = CHGIN_I is masked */ 00500 unsigned char tj_reg_m : 1; /**< Setting this bit prevents the TJREG_I bit from causing hardware IRQs. Bit 3. 00501 0 = TJREG_I is not masked 00502 1 = TJREG_I is masked */ 00503 unsigned char sys_ctrl_m : 1; /**< Setting this bit prevents the SYS_CTRL_I bit from causing hardware IRQs. Bit 4. 00504 0 = SYS_CTRL_I is not masked 00505 1 = SYS_CTRL_I is masked */ 00506 unsigned char rsvd : 3; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */ 00507 } bits; 00508 } reg_int_m_chg_t; 00509 00510 /** 00511 * @brief CNFG_CHG_A 00512 * 00513 * Address : 0x20 00514 */ 00515 typedef union { 00516 unsigned char raw; 00517 struct 00518 { 00519 unsigned char thm_cold : 2; /**< Sets the VCOLD JEITA Temperature Threshold. Bit 1:0. 00520 0b00 = VCOLD = 1.024V (-10ºC for β = 3380K) 00521 0b01 = VCOLD = 0.976V (-5ºC for β = 3380K) 00522 0b10 = VCOLD = 0.923V (0ºC for β = 3380K) 00523 0b11 = VCOLD = 0.867V (5ºC for β = 3380K) */ 00524 unsigned char thm_cool : 2; /**< Sets the VCOOL JEITA Temperature Threshold. Bit 3:2. 00525 0b00 = VCOOL = 0.923V (0ºC for β = 3380K) 00526 0b01 = VCOOL = 0.867V (5ºC for β = 3380K) 00527 0b10 = VCOOL = 0.807V (10ºC for β = 3380K) 00528 0b11 = VCOOL = 0.747V (15ºC for β = 3380K) */ 00529 unsigned char thm_warm : 2; /**< Sets the VWARM JEITA Temperature Threshold. Bit 5:4. 00530 0b00 = VWARM = 0.511V (35ºC for β = 3380K) 00531 0b01 = VWARM = 0.459V (40ºC for β = 3380K) 00532 0b10 = VWARM = 0.411V (45ºC for β = 3380K) 00533 0b11 = VWARM = 0.367V (50ºC for β = 3380K) */ 00534 unsigned char thm_hot : 2; /**< Sets the VHOT JEITA Temperature Threshold. Bit 7:6. 00535 0b00 = VHOT = 0.411V (45ºC for β = 3380K) 00536 0b01 = VHOT = 0.367V (50ºC for β = 3380K) 00537 0b10 = VHOT = 0.327V (55ºC for β = 3380K) 00538 0b11 = VHOT = 0.291V (60ºC for β = 3380K) */ 00539 } bits; 00540 } reg_cnfg_chg_a_t; 00541 00542 /** 00543 * @brief CNFG_CHG_B 00544 * 00545 * Address : 0x21 00546 */ 00547 typedef union { 00548 unsigned char raw; 00549 struct 00550 { 00551 unsigned char chg_en : 1; /**< Charger Enable. Bit 0. 00552 0 = the battery charger is disabled 00553 1 = the battery charger is enabled */ 00554 unsigned char i_pq : 1; /**< Sets the prequalification charge current (IPQ) as a percentage of IFAST-CHG. Bit 1. 00555 0 = 10% 1 = 20% */ 00556 unsigned char rsvd : 6; /**< Reserved. Bit 7:2. Unutilized bit. Write to 0. Reads are don't care. */ 00557 } bits; 00558 } reg_cnfg_chg_b_t; 00559 00560 /** 00561 * @brief CNFG_CHG_C 00562 * 00563 * Address : 0x22 00564 */ 00565 typedef union { 00566 unsigned char raw; 00567 struct 00568 { 00569 unsigned char t_topoff : 3; /**< Top-off timer value (tTO). Bit 2:0. 00570 0b000 = 0 minutes 0b001 = 5 minutes 00571 0b010 = 10 minutes 0b011 = 15 minutes 00572 0b100 = 20 minutes 0b101 = 25 minutes 00573 0b110 = 30 minutes 0b111 = 35 minutes */ 00574 unsigned char i_term : 2; /**< Charger Termination Current (ITERM). Bit 4:3. 00575 00 = 5% 01 = 7.5% 00576 10 = 10% 11 = 15% */ 00577 unsigned char chg_pq : 3; /**< Battery prequalification voltage threshold (VPQ). Bit 7:5. 00578 0b000 = 2.3V 0b001 = 2.4V 00579 0b010 = 2.5V 0b011 = 2.6V 00580 0b100 = 2.7V 0b101 = 2.8V 00581 0b110 = 2.9V 0b111 = 3.0V */ 00582 } bits; 00583 } reg_cnfg_chg_c_t; 00584 00585 /** 00586 * @brief CNFG_CHG_D 00587 * 00588 * Address : 0x23 00589 */ 00590 typedef union { 00591 unsigned char raw; 00592 struct 00593 { 00594 unsigned char vsys_min : 2; /**< Minimum SYS Voltage . Bit 1:0. 00595 0x0 = 3.2V 0x1 = 3.3V 00596 0x2 = 3.4V 0x3 = 3.5V */ 00597 unsigned char rsvd : 2; /**< Reserved. Bit 3:2. Unutilized bit. Write to 0. Reads are don't care. */ 00598 unsigned char vsys_hdrm : 1; /**< SYS Headroom Voltage Regulation. Bit 4. 00599 0b0 = 0.15V 0b1 = 0.20V */ 00600 unsigned char tj_reg : 3; /**< Sets the die junction temperature regulation point, TJ-REG. Bit 7:5. 00601 0b000 = 60ºC 0b001 = 70ºC 00602 0b010 = 80ºC 0b011 = 90ºC 00603 0b100 - 0b111 = 100ºC */ 00604 } bits; 00605 } reg_cnfg_chg_d_t; 00606 00607 /** 00608 * @brief CNFG_CHG_E 00609 * 00610 * Address : 0x25 00611 */ 00612 typedef union { 00613 unsigned char raw; 00614 struct 00615 { 00616 unsigned char t_fast_chg : 2; /**< System voltage regulation (VSYS-REG). Bit 1:0. 00617 0b00 = timer disabled 0b01 = 3 hours 00618 0b10 = 5 hours 0b11 = 7 hours */ 00619 unsigned char chg_cc : 6; /**< Sets the fast-charge constant current value, IFAST-CHG. Bit 7:2. 00620 0x0 = 7.5mA 0x1 = 15.0mA 00621 0x2 = 22.5mA ... 00622 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */ 00623 } bits; 00624 } reg_cnfg_chg_e_t; 00625 00626 /** 00627 * @brief CNFG_CHG_F 00628 * 00629 * Address : 0x25 00630 */ 00631 typedef union { 00632 unsigned char raw; 00633 struct 00634 { 00635 unsigned char : 1; /**< Bit 0*/ 00636 unsigned char thm_en : 1; /**< Thermistor enable bit. Bit 1. 00637 0 = Thermistor is disabled 00638 1 = Thermistor is enabled */ 00639 unsigned char chg_cc_jeita : 6; /**< Sets IFAST-CHG-JEITA for when the battery is either cool or warm as defined 00640 by the VCOOL and VWARM temperature thresholds. Bit 7:2. 00641 0x0 = 7.5mA 0x1 = 15.0mA 00642 0x2 = 22.5mA ... 00643 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */ 00644 } bits; 00645 } reg_cnfg_chg_f_t; 00646 00647 /** 00648 * @brief CNFG_CHG_G 00649 * 00650 * Address : 0x26 00651 */ 00652 typedef union { 00653 unsigned char raw; 00654 struct 00655 { 00656 unsigned char rsvd : 1; /**< Reserved. Bit 0. Unutilized bit. Write to 0. Reads are don't care.*/ 00657 unsigned char usbs : 1; /**< Setting this bit places CHGIN in USB suspend mode. Bit 1. 00658 0 = CHGIN is not suspended and may draw current from an adapter source 00659 1 = CHGIN is suspended and may draw no current from an adapter source */ 00660 unsigned char chg_cv : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2. 00661 0x0 = 3.600V 0x1 = 3.625V 00662 0x2 = 3.650V ... 00663 0x27 = 4.575V 0x28 - 0x3F = 4.600V */ 00664 } bits; 00665 } reg_cnfg_chg_g_t; 00666 00667 /** 00668 * @brief CNFG_CHG_H 00669 * 00670 * Address : 0x27 00671 */ 00672 typedef union { 00673 unsigned char raw; 00674 struct 00675 { 00676 unsigned char rsvd : 2; /**< Reserved. Bit 1:0. Unutilized bit. Write to 0. Reads are don't care.*/ 00677 unsigned char chg_cv_jeita : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2. 00678 0x0 = 3.600V 0x1 = 3.625V 00679 0x2 = 3.650V ... 00680 0x27 = 4.575V 0x28 - 0x3F = 4.600V */ 00681 } bits; 00682 } reg_cnfg_chg_h_t; 00683 00684 /** 00685 * @brief CNFG_CHG_I 00686 * 00687 * Address : 0x28 00688 */ 00689 typedef union { 00690 unsigned char raw; 00691 struct 00692 { 00693 unsigned char mux_sel : 4; /**< Selects the analog channel to connect to AMUX. Bit 3:0. 00694 0b0000 = Multiplexer is disabled and AMUX is high-impedance. 00695 0b0001 = CHGIN voltage monitor. 00696 0b0010 = CHGIN current monitor. 00697 0b0011 = BATT voltage monitor. 00698 0b0100 = BATT charge current monitor. Valid only while battery charging is happening (CHG = 1). 00699 0b0101 = BATT discharge current monitor normal measurement. 00700 0b0110 = BATT discharge current monitor nulling measurement. 00701 0b0111 = THM voltage monitor 0b1000 = TBIAS voltage monitor 00702 0b1001 = AGND voltage monitor (through 100Ω pull-down resistor) 00703 0b1010 - 0b1111 = SYS voltage monitor */ 00704 unsigned char imon_dischg_scale : 4; /**< Selects the battery discharge current full-scale current value. Bit 7:4. 00705 0x0 = 8.2mA 0x1 = 40.5mA 0x2 = 72.3mA 00706 0x3 = 103.4mA 0x4 = 134.1mA 00707 0x5 = 164.1mA 0x6 = 193.7mA 00708 0x7 = 222.7mA 0x8 = 251.2mA 00709 0x9 = 279.3mA 0xA - 0xF = 300.0mA */ 00710 } bits; 00711 } reg_cnfg_chg_i_t; 00712 00713 /** 00714 * @brief CNFG_SBB0_A 00715 * 00716 * Address : 0x29 00717 */ 00718 typedef union { 00719 unsigned char raw; 00720 struct 00721 { 00722 unsigned char tv_sbb0 : 7; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 6:0. 00723 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00724 0x03 = 0.575V 0x04 = 0.600V 00725 ... 00726 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V 00727 ... 00728 0x7B = 5.450V 0x7C = 5.500V 00729 0x7D to 0x7F = Reserved */ 00730 unsigned char : 1; /**< Bit 7. */ 00731 } bits; 00732 } reg_cnfg_sbb0_a_t; 00733 00734 /** 00735 * @brief CNFG_SBB0_B 00736 * 00737 * Address : 0x2A 00738 */ 00739 typedef union { 00740 unsigned char raw; 00741 struct 00742 { 00743 unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0, 00744 selecting either an FPS slot the channel powers-up and powers-down in 00745 or whether the channel is forced on or off. Bit 2:0. 00746 0b000 = FPS slot 0 0b001 = FPS slot 1 00747 0b010 = FPS slot 2 0b011 = FPS slot 3 00748 0b100 = Off irrespective of FPS 00749 0b101 = same as 0b100 0b110 = On irrespective of FPS 00750 0b111 = same as 0b110 */ 00751 unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3. 00752 0 = The active discharge function is disabled. 00753 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00754 1 = The active discharge function is enabled. 00755 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00756 unsigned char : 2; /**< Bit 5:4*/ 00757 unsigned char op_mode : 1; /**< Operation mode of SBB0. Bit 6. 00758 0 = Buck-Boost Mode 00759 1 = Buck Mode*/ 00760 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/ 00761 } bits; 00762 } reg_cnfg_sbb0_b_t; 00763 00764 /** 00765 * @brief CNFG_SBB1_A 00766 * 00767 * Address : 0x2B 00768 */ 00769 typedef union { 00770 unsigned char raw; 00771 struct 00772 { 00773 unsigned char tv_sbb1 : 7; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 6:0. 00774 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00775 0x03 = 0.575V 0x04 = 0.600V 00776 ... 00777 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V 00778 ... 00779 0x7B = 5.450V 0x7C = 5.500V 00780 0x7D to 0x7F = Reserved */ 00781 unsigned char : 1; /**< Bit 7. */ 00782 } bits; 00783 } reg_cnfg_sbb1_a_t; 00784 00785 /** 00786 * @brief CNFG_SBB1_B 00787 * 00788 * Address : 0x2C 00789 */ 00790 typedef union { 00791 unsigned char raw; 00792 struct 00793 { 00794 unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1, 00795 selecting either an FPS slot the channel powers-up and powers-down in 00796 or whether the channel is forced on or off. Bit 2:0. 00797 0b000 = FPS slot 0 0b001 = FPS slot 1 00798 0b010 = FPS slot 2 0b011 = FPS slot 3 00799 0b100 = Off irrespective of FPS 00800 0b101 = same as 0b100 0b110 = On irrespective of FPS 00801 0b111 = same as 0b110 */ 00802 unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3. 00803 0 = The active discharge function is disabled. 00804 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00805 1 = The active discharge function is enabled. 00806 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00807 unsigned char : 2; /**< Bit 5:4.*/ 00808 unsigned char op_mode : 1; /**< Operation mode of SBB1. Bit 6. 00809 0 = Buck-Boost Mode 00810 1 = Buck Mode*/ 00811 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/ 00812 } bits; 00813 } reg_cnfg_sbb1_b_t; 00814 00815 /** 00816 * @brief CNFG_SBB2_A 00817 * 00818 * Address : 0x2D 00819 */ 00820 typedef union { 00821 unsigned char raw; 00822 struct 00823 { 00824 unsigned char tv_sbb2 : 7; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 6:0. 00825 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00826 0x03 = 0.575V 0x04 = 0.600V 00827 ... 00828 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V 00829 ... 00830 0x7B = 5.450V 0x7C = 5.500V 00831 0x7D to 0x7F = Reserved */ 00832 unsigned char : 1; /**< Bit 7. */ 00833 } bits; 00834 } reg_cnfg_sbb2_a_t; 00835 00836 /** 00837 * @brief CNFG_SBB2_B 00838 * 00839 * Address : 0x2E 00840 */ 00841 typedef union { 00842 unsigned char raw; 00843 struct 00844 { 00845 unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2, 00846 selecting either an FPS slot the channel powers-up and powers-down in 00847 or whether the channel is forced on or off. Bit 2:0. 00848 0b000 = FPS slot 0 0b001 = FPS slot 1 00849 0b010 = FPS slot 2 0b011 = FPS slot 3 00850 0b100 = Off irrespective of FPS 00851 0b101 = same as 0b100 0b110 = On irrespective of FPS 00852 0b111 = same as 0b110 */ 00853 unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3. 00854 0 = The active discharge function is disabled. 00855 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00856 1 = The active discharge function is enabled. 00857 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00858 unsigned char : 2; /**< Bit 5:4. */ 00859 unsigned char op_mode : 1; /**< Operation mode of SBB2. Bit 6. 00860 0 = Buck-Boost Mode 00861 1 = Buck Mode*/ 00862 unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/ 00863 } bits; 00864 } reg_cnfg_sbb2_b_t; 00865 00866 /** 00867 * @brief CNFG_SBB_TOP 00868 * 00869 * Address : 0x2F 00870 */ 00871 typedef union { 00872 unsigned char raw; 00873 struct 00874 { 00875 unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0. 00876 0b00 = fastest transition time 00877 0b01 = a little slower than 0b00 00878 0b10 = a little slower than 0b01 00879 0b11 = a little slower than 0b10 */ 00880 unsigned char : 5; /**< Bit 6:2. */ 00881 unsigned char op_mode_chg : 1; /**< Operation mode of the charging channel of SIMO. Bit 7. 00882 0 = Buck-boost mode 00883 1 = Buck mode */ 00884 } bits; 00885 } reg_cnfg_sbb_top_t; 00886 00887 /** 00888 * @brief CNFG_SBB_TOP_B 00889 * 00890 * Address : 0x30 00891 */ 00892 typedef union { 00893 unsigned char raw; 00894 struct 00895 { 00896 unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 1:0. 00897 0b00 = 1.000A 00898 0b01 = 0.750A 00899 0b10 = 0.500A 00900 0b11 = 0.333A */ 00901 unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 3:2. 00902 0b00 = 1.000A 00903 0b01 = 0.750A 00904 0b10 = 0.500A 00905 0b11 = 0.333A */ 00906 unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4. 00907 0b00 = 1.000A 00908 0b01 = 0.750A 00909 0b10 = 0.500A 00910 0b11 = 0.333A */ 00911 unsigned char ip_chg : 2; /**< SIMO Buck-Boost Charging Channel Peak Current Limit. Bit 7:6. 00912 0b00 = 2.000A 00913 0b01 = 1.500A 00914 0b10 = 1.000A 00915 0b11 = 0.500A */ 00916 } bits; 00917 } reg_cnfg_sbb_top_b_t; 00918 00919 /** 00920 * @brief CNFG_LDO0_A 00921 * 00922 * Address : 0x38 00923 */ 00924 typedef union { 00925 unsigned char raw; 00926 struct 00927 { 00928 unsigned char tv_ldo_volt : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function 00929 that starts at 0.5V and ends at 3.675V, with 25mV increments. Bit 6:0. 00930 0x00 = 0.500V 0x01 = 0.525V 00931 0x02 = 0.550V 0x03 = 0.575V 00932 0x04 = 0.600V 0x05 = 0.625V 00933 0x06 = 0.650V ... 00934 0x7D = 3.625V 0x7E = 3.650V 00935 0x7F = 3.675V */ 00936 unsigned char tv_ldo_offset : 1; /**< LDO Output Voltage. This bit applies a 1.325V offset to the output voltage of the LDO. Bit 7. 00937 0b0 = No offset 0b1 = 1.325V offset*/ 00938 } bits; 00939 } reg_cnfg_ldo0_a_t; 00940 00941 /** 00942 * @brief CNFG_LDO0_B 00943 * 00944 * Address : 0x39 00945 */ 00946 typedef union { 00947 unsigned char raw; 00948 struct 00949 { 00950 unsigned char en_ldo : 3; /**< Enable Control for LDO0, selecting either an FPS slot the channel powers-up and 00951 powers-down in or whether the channel is forced on or off. Bit 2:0. 00952 0b000 = FPS slot 0 0b001 = FPS slot 1 00953 0b010 = FPS slot 2 0b011 = FPS slot 3 00954 0b100 = Off irrespective of FPS 00955 0b101 = same as 0b100 00956 0b110 = On irrespective of FPS 00957 0b111 = same as 0b110 */ 00958 unsigned char ade_ldo : 1; /**< LDO0 Active-Discharge Enable. Bit 3. 00959 0 = The active discharge function is disabled. 00960 1 = The active discharge function is enabled. */ 00961 unsigned char ldo_md : 1; /**< Operation mode of LDO0. Bit 4. 00962 0 = Low Dropout Linear Regulator (LDO) Mode 00963 1 = Load Switch (LSW) Mode */ 00964 unsigned char rsvd : 3; /**< Bit 7:5. Reserved. Unutilized bit. Write to 0. Reads are don't care. */ 00965 } bits; 00966 } reg_cnfg_ldo0_b_t; 00967 00968 #endif /* MAX77659_REGS_H_ */
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