Maxim Integrated
SIMO PMIC with 300mA Switching Charger
Revision 0:047a7089311e, committed 2022-08-22
- Comitter:
- Okan Sahin
- Date:
- Mon Aug 22 19:05:12 2022 +0300
- Commit message:
- Initial Commit
Changed in this revision
diff -r 000000000000 -r 047a7089311e MAX77659.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77659.cpp Mon Aug 22 19:05:12 2022 +0300
@@ -0,0 +1,1899 @@
+/*******************************************************************************
+* Copyright (C) 2022 Analog Devices, Inc., All rights Reserved.
+*
+* This software is protected by copyright laws of the United States and
+* of foreign countries. This material may also be protected by patent laws
+* and technology transfer regulations of the United States and of foreign
+* countries. This software is furnished under a license agreement and/or a
+* nondisclosure agreement and may only be used or reproduced in accordance
+* with the terms of those agreements. Dissemination of this information to
+* any party or parties not specified in the license agreement and/or
+* nondisclosure agreement is expressly prohibited.
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Analog Devices, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+#include <Thread.h>
+#include "MAX77659.h"
+#include <math.h>
+
+#define POST_INTR_WORK_SIGNAL_ID 0x1
+#define TO_UINT8 0xFF
+#define TO_UINT16 0xFFFF
+
+MAX77659::MAX77659(I2C *i2c, PinName IRQPin)
+{
+ if (i2c == NULL)
+ return;
+
+ i2c_handler = i2c;
+
+ interrupt_handler_list = new handler[INT_CHG_END] {};
+
+ if (IRQPin != NC) {
+ irq_disable_all();
+ post_intr_work_thread = new Thread();
+ post_intr_work_thread->start(Callback<void()>(this, &MAX77659::post_interrupt_work));
+
+ this->irq_pin = new InterruptIn(IRQPin);
+ this->irq_pin->fall(Callback<void()>(this, &MAX77659::interrupt_handler));
+ this->irq_pin->enable_irq();
+ } else {
+ this->irq_pin = NULL;
+ }
+}
+
+MAX77659::~MAX77659()
+{
+ if (post_intr_work_thread)
+ delete post_intr_work_thread;
+
+ if (irq_pin)
+ delete irq_pin;
+
+ if (interrupt_handler_list)
+ delete [] interrupt_handler_list;
+}
+
+int MAX77659::read_register(uint8_t reg, uint8_t *value)
+{
+ int rtn_val;
+
+ if (value == NULL)
+ return MAX77659_VALUE_NULL;
+
+ rtn_val = i2c_handler->write(MAX77659_I2C_ADDRESS, (const char *)®, 1, true);
+ if (rtn_val != MAX77659_NO_ERROR)
+ return MAX77659_WRITE_DATA_FAILED;
+
+ rtn_val = i2c_handler->read(MAX77659_I2C_ADDRESS, (char *) value, 1, false);
+ if (rtn_val != MAX77659_NO_ERROR)
+ return MAX77659_READ_DATA_FAILED;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::write_register(uint8_t reg, const uint8_t *value)
+{
+ int rtn_val;
+ unsigned char local_data[2] = {0};
+
+ if (value == NULL)
+ return MAX77659_VALUE_NULL;
+
+ local_data[0] = reg;
+
+ memcpy(&local_data[1], value, 1);
+
+ rtn_val = i2c_handler->write(MAX77659_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
+ if (rtn_val != MAX77659_NO_ERROR)
+ return MAX77659_WRITE_DATA_FAILED;
+
+ return MAX77659_NO_ERROR;
+}
+
+#define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
+ int ret_val; \
+ ret_val = read_register(address, (uint8_t *)&(reg_name)); \
+ if (ret_val) { \
+ return ret_val; \
+ } \
+ bit_field_name = value; \
+ ret_val = write_register(address, (uint8_t *)&(reg_name)); \
+ if (ret_val) { \
+ return ret_val; \
+ }
+
+int MAX77659::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag)
+{
+ int ret;
+ reg_ercflag_t reg_ercflag = {0};
+
+ ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case ERCFLAG_TOVLD:
+ *flag = (uint8_t)reg_ercflag.bits.tovld;
+ break;
+ case ERCFLAG_SYSOVLO:
+ *flag = (uint8_t)reg_ercflag.bits.sysovlo;
+ break;
+ case ERCFLAG_AVLUVLO:
+ *flag = (uint8_t)reg_ercflag.bits.avluvlo;
+ break;
+ case ERCFLAG_MRST:
+ *flag = (uint8_t)reg_ercflag.bits.mrst;
+ break;
+ case ERCFLAG_SFT_OFF_F:
+ *flag = (uint8_t)reg_ercflag.bits.sft_off_f;
+ break;
+ case ERCFLAG_SFT_CRST_F:
+ *flag = (uint8_t)reg_ercflag.bits.sft_crst_f;
+ break;
+ case ERCFLAG_WDT_OFF:
+ *flag = (uint8_t)reg_ercflag.bits.wdt_off;
+ break;
+ case ERCFLAG_WDT_RST:
+ *flag = (uint8_t)reg_ercflag.bits.wdt_rst;
+ break;
+ default:
+ ret = MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return ret;
+}
+
+int MAX77659::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status)
+{
+ int ret;
+ reg_stat_glbl_t reg_stat_glbl = {0};
+
+ ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case STAT_GLBL_STAT_IRQ:
+ *status = (uint8_t)reg_stat_glbl.bits.stat_irq;
+ break;
+ case STAT_GLBL_STAT_EN:
+ *status = (uint8_t)reg_stat_glbl.bits.stat_en;
+ break;
+ case STAT_GLBL_TJAL1_S:
+ *status = (uint8_t)reg_stat_glbl.bits.tjal1_s;
+ break;
+ case STAT_GLBL_TJAL2_S:
+ *status = (uint8_t)reg_stat_glbl.bits.tjal2_s;
+ break;
+ case STAT_GLBL_RSVD:
+ *status = (uint8_t)reg_stat_glbl.bits.rsvd;
+ break;
+ case STAT_GLBL_DOD_S:
+ *status = (uint8_t)reg_stat_glbl.bits.dod_s;
+ break;
+ case STAT_GLBL_BOK:
+ *status = (uint8_t)reg_stat_glbl.bits.bok;
+ break;
+ case STAT_GLBL_DIDM:
+ *status = (uint8_t)reg_stat_glbl.bits.didm;
+ break;
+ default:
+ ret = MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return ret;
+}
+
+int MAX77659::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit)
+{
+ int ret;
+ uint8_t reg_addr;
+ reg_int_m_chg_t reg_int_m_chg = {0};
+ reg_intm_glbl0_t reg_intm_glbl0 = {0};
+ reg_intm_glbl1_t reg_intm_glbl1 = {0};
+
+ //INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09)
+ reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x07;
+
+ if (reg_addr == INT_M_CHG)
+ ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
+ else if (reg_addr == INTM_GLBL0)
+ ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
+ else if (reg_addr == INTM_GLBL1)
+ ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
+ else
+ return MAX77659_INVALID_DATA;
+
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case INT_M_CHG_THM_M:
+ reg_int_m_chg.bits.thm_m = maskBit;
+ break;
+ case INT_M_CHG_CHG_M:
+ reg_int_m_chg.bits.chg_m = maskBit;
+ break;
+ case INT_M_CHG_CHGIN_M:
+ reg_int_m_chg.bits.chgin_m = maskBit;
+ break;
+ case INT_M_CHG_TJ_REG_M:
+ reg_int_m_chg.bits.tj_reg_m = maskBit;
+ break;
+ case INT_M_CHG_SYS_CTRL_M:
+ reg_int_m_chg.bits.sys_ctrl_m = maskBit;
+ break;
+ case INTM_GLBL0_GPI0_FM:
+ reg_intm_glbl0.bits.gpi0_fm = maskBit;
+ break;
+ case INTM_GLBL1_GPI1_FM:
+ reg_intm_glbl1.bits.gpi1_fm = maskBit;
+ break;
+ case INTM_GLBL1_GPI1_RM:
+ reg_intm_glbl1.bits.gpi1_rm = maskBit;
+ break;
+ case INTM_GLBL1_SBB_TO_M:
+ reg_intm_glbl1.bits.sbb_to_m = maskBit;
+ break;
+ case INTM_GLBL1_LDO_M:
+ reg_intm_glbl1.bits.ldo_m = maskBit;
+ break;
+ case INTM_GLBL0_GPI0_RM:
+ reg_intm_glbl0.bits.gpi0_rm = maskBit;
+ break;
+ case INTM_GLBL0_nEN_FM:
+ reg_intm_glbl0.bits.nen_fm = maskBit;
+ break;
+ case INTM_GLBL0_nEN_RM:
+ reg_intm_glbl0.bits.nen_rm = maskBit;
+ break;
+ case INTM_GLBL0_TJAL1_RM:
+ reg_intm_glbl0.bits.tjal1_rm = maskBit;
+ break;
+ case INTM_GLBL0_TJAL2_RM:
+ reg_intm_glbl0.bits.tjal2_rm = maskBit;
+ break;
+ case INTM_GLBL0_DOD_RM:
+ reg_intm_glbl0.bits.dod_rm = maskBit;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ if (reg_addr == INT_M_CHG)
+ return write_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
+ else if (reg_addr == INTM_GLBL0)
+ return write_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
+ else if (reg_addr == INTM_GLBL1)
+ return write_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
+ else
+ return MAX77659_INVALID_DATA;
+}
+
+int MAX77659::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit)
+{
+ int ret;
+ uint8_t reg_addr;
+ reg_int_m_chg_t reg_int_m_chg = {0};
+ reg_intm_glbl0_t reg_intm_glbl0 = {0};
+ reg_intm_glbl1_t reg_intm_glbl1 = {0};
+
+ //INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09)
+ reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x07;
+
+ if (reg_addr == INT_M_CHG)
+ ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg));
+ else if (reg_addr == INTM_GLBL0)
+ ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
+ else if (reg_addr == INTM_GLBL1)
+ ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
+ else
+ return MAX77659_INVALID_DATA;
+
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case INT_M_CHG_THM_M:
+ *maskBit = (uint8_t)reg_int_m_chg.bits.thm_m;
+ break;
+ case INT_M_CHG_CHG_M:
+ *maskBit = (uint8_t)reg_int_m_chg.bits.chg_m;
+ break;
+ case INT_M_CHG_CHGIN_M:
+ *maskBit = (uint8_t)reg_int_m_chg.bits.chgin_m;
+ break;
+ case INT_M_CHG_TJ_REG_M:
+ *maskBit = (uint8_t)reg_int_m_chg.bits.tj_reg_m;
+ break;
+ case INT_M_CHG_SYS_CTRL_M:
+ *maskBit = (uint8_t)reg_int_m_chg.bits.sys_ctrl_m;
+ break;
+ case INTM_GLBL1_GPI1_FM:
+ *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_fm;
+ break;
+ case INTM_GLBL1_GPI1_RM:
+ *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_rm;
+ break;
+ case INTM_GLBL1_SBB_TO_M:
+ *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb_to_m;
+ break;
+ case INTM_GLBL1_LDO_M:
+ *maskBit = (uint8_t)reg_intm_glbl1.bits.ldo_m;
+ break;
+ case INTM_GLBL0_GPI0_FM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_fm;
+ break;
+ case INTM_GLBL0_GPI0_RM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_rm;
+ break;
+ case INTM_GLBL0_nEN_FM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_fm;
+ break;
+ case INTM_GLBL0_nEN_RM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_rm;
+ break;
+ case INTM_GLBL0_TJAL1_RM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal1_rm;
+ break;
+ case INTM_GLBL0_TJAL2_RM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal2_rm;
+ break;
+ case INTM_GLBL0_DOD_RM:
+ *maskBit = (uint8_t)reg_intm_glbl0.bits.dod_rm;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t config)
+{
+ int ret;
+ reg_cnfg_glbl_t reg_cnfg_glbl = {0};
+
+ ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GLBL_SFT_CTRL:
+ reg_cnfg_glbl.bits.sft_ctrl = config;
+ break;
+ case CNFG_GLBL_DBEN_nEN:
+ reg_cnfg_glbl.bits.dben_nen = config;
+ break;
+ case CNFG_GLBL_nEN_MODE:
+ reg_cnfg_glbl.bits.nen_mode = config;
+ break;
+ case CNFG_GLBL_SBIA_EN:
+ reg_cnfg_glbl.bits.sbia_en = config;
+ break;
+ case CNFG_GLBL_SBIA_LPM:
+ reg_cnfg_glbl.bits.sbia_lpm = config;
+ break;
+ case CNFG_GLBL_T_MRST:
+ reg_cnfg_glbl.bits.t_mrst = config;
+ break;
+ case CNFG_GLBL_PU_DIS:
+ reg_cnfg_glbl.bits.pu_dis = config;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return write_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
+}
+
+int MAX77659::get_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t *config)
+{
+ int ret;
+ reg_cnfg_glbl_t reg_cnfg_glbl = {0};
+
+ ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GLBL_SFT_CTRL:
+ *config = (uint8_t)reg_cnfg_glbl.bits.sft_ctrl;
+ break;
+ case CNFG_GLBL_DBEN_nEN:
+ *config = (uint8_t)reg_cnfg_glbl.bits.dben_nen;
+ break;
+ case CNFG_GLBL_nEN_MODE:
+ *config = (uint8_t)reg_cnfg_glbl.bits.nen_mode;
+ break;
+ case CNFG_GLBL_SBIA_EN:
+ *config = (uint8_t)reg_cnfg_glbl.bits.sbia_en;
+ break;
+ case CNFG_GLBL_SBIA_LPM:
+ *config = (uint8_t)reg_cnfg_glbl.bits.sbia_lpm;
+ break;
+ case CNFG_GLBL_T_MRST:
+ *config = (uint8_t)reg_cnfg_glbl.bits.t_mrst;
+ break;
+ case CNFG_GLBL_PU_DIS:
+ *config = (uint8_t)reg_cnfg_glbl.bits.pu_dis;
+ break;
+ default:
+ ret = MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return ret;
+}
+
+int MAX77659::set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config)
+{
+ int ret;
+ reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
+ reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
+
+ if (channel == 0)
+ {
+ ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GPIO_DIR:
+ reg_cnfg_gpio0.bits.gpo_dir = config;
+ break;
+ case CNFG_GPIO_DI:
+ reg_cnfg_gpio0.bits.gpo_di = config;
+ break;
+ case CNFG_GPIO_DRV:
+ reg_cnfg_gpio0.bits.gpo_drv = config;
+ break;
+ case CNFG_GPIO_DO:
+ reg_cnfg_gpio0.bits.gpo_do = config;
+ break;
+ case CNFG_GPIO_DBEN_GPI:
+ reg_cnfg_gpio0.bits.dben_gpi = config;
+ break;
+ case CNFG_GPIO_ALT_GPIO:
+ reg_cnfg_gpio0.bits.alt_gpio = config;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return write_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
+ }
+ else if (channel == 1)
+ {
+ ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GPIO_DIR:
+ reg_cnfg_gpio1.bits.gpo_dir = config;
+ break;
+ case CNFG_GPIO_DI:
+ reg_cnfg_gpio1.bits.gpo_di = config;
+ break;
+ case CNFG_GPIO_DRV:
+ reg_cnfg_gpio1.bits.gpo_drv = config;
+ break;
+ case CNFG_GPIO_DO:
+ reg_cnfg_gpio1.bits.gpo_do = config;
+ break;
+ case CNFG_GPIO_DBEN_GPI:
+ reg_cnfg_gpio1.bits.dben_gpi = config;
+ break;
+ case CNFG_GPIO_ALT_GPIO:
+ reg_cnfg_gpio1.bits.alt_gpio = config;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return write_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+}
+
+int MAX77659::get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config)
+{
+ int ret;
+ reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
+ reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
+
+ if (channel == 0)
+ {
+ ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GPIO_DIR:
+ *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_dir;
+ break;
+ case CNFG_GPIO_DI:
+ *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_di;
+ break;
+ case CNFG_GPIO_DRV:
+ *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_drv;
+ break;
+ case CNFG_GPIO_DO:
+ *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_do;
+ break;
+ case CNFG_GPIO_DBEN_GPI:
+ *config = (uint8_t)reg_cnfg_gpio0.bits.dben_gpi;
+ break;
+ case CNFG_GPIO_ALT_GPIO:
+ *config = (uint8_t)reg_cnfg_gpio0.bits.alt_gpio;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+ }
+ else if (channel == 1)
+ {
+ ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GPIO_DIR:
+ *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_dir;
+ break;
+ case CNFG_GPIO_DI:
+ *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_di;
+ break;
+ case CNFG_GPIO_DRV:
+ *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_drv;
+ break;
+ case CNFG_GPIO_DO:
+ *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_do;
+ break;
+ case CNFG_GPIO_DBEN_GPI:
+ *config = (uint8_t)reg_cnfg_gpio1.bits.dben_gpi;
+ break;
+ case CNFG_GPIO_ALT_GPIO:
+ *config = (uint8_t)reg_cnfg_gpio1.bits.alt_gpio;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return ret;
+}
+
+int MAX77659::get_cid(void) {
+ char rbuf[1] = {0};
+ int ret;
+
+ ret = read_register(CID, (uint8_t *)&(rbuf));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ return *rbuf;
+}
+
+int MAX77659::set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config)
+{
+ int ret;
+ reg_cnfg_wdt_t reg_cnfg_wdt = {0};
+
+ ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_WDT_WDT_LOCK:
+ reg_cnfg_wdt.bits.wdt_lock = config;
+ break;
+ case CNFG_WDT_WDT_EN:
+ reg_cnfg_wdt.bits.wdt_en = config;
+ break;
+ case CNFG_WDT_WDT_CLR:
+ reg_cnfg_wdt.bits.wdt_clr = config;
+ break;
+ case CNFG_WDT_WDT_MODE:
+ reg_cnfg_wdt.bits.wdt_mode = config;
+ break;
+ case CNFG_WDT_WDT_PER:
+ reg_cnfg_wdt.bits.wdt_per = config;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return write_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
+}
+
+int MAX77659::get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config)
+{
+ int ret;
+ reg_cnfg_wdt_t reg_cnfg_wdt = {0};
+
+ ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_WDT_WDT_LOCK:
+ *config = (uint8_t)reg_cnfg_wdt.bits.wdt_lock;
+ break;
+ case CNFG_WDT_WDT_EN:
+ *config = (uint8_t)reg_cnfg_wdt.bits.wdt_en;
+ break;
+ case CNFG_WDT_WDT_CLR:
+ *config = (uint8_t)reg_cnfg_wdt.bits.wdt_clr;
+ break;
+ case CNFG_WDT_WDT_MODE:
+ *config = (uint8_t)reg_cnfg_wdt.bits.wdt_mode;
+ break;
+ case CNFG_WDT_WDT_PER:
+ *config = (uint8_t)reg_cnfg_wdt.bits.wdt_per;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_stat_chg_a(reg_bit_stat_chg_a_t bit_field, uint8_t *status)
+{
+ int ret;
+ reg_stat_chg_a_t reg_stat_chg_a = {0};
+
+ ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case STAT_CHG_A_THM_DTLS:
+ *status = (uint8_t)reg_stat_chg_a.bits.thm_dtls;
+ break;
+ case STAT_CHG_A_TJ_REG_STAT:
+ *status = (uint8_t)reg_stat_chg_a.bits.tj_reg_stat;
+ break;
+ case STAT_CHG_A_VSYS_MIN_STAT:
+ *status = (uint8_t)reg_stat_chg_a.bits.vsys_min_stat;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_thm_dtls(decode_thm_dtls_t *thm_dtls)
+{
+ int ret;
+ reg_stat_chg_a_t reg_stat_chg_a = {0};
+
+ ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *thm_dtls = (decode_thm_dtls_t)reg_stat_chg_a.bits.thm_dtls;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_stat_chg_b(reg_bit_stat_chg_b_t bit_field, uint8_t *status)
+{
+ int ret;
+ reg_stat_chg_b_t reg_stat_chg_b = {0};
+
+ ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case STAT_CHG_B_TIME_SUS:
+ *status = (uint8_t)reg_stat_chg_b.bits.time_sus;
+ break;
+ case STAT_CHG_B_CHG:
+ *status = (uint8_t)reg_stat_chg_b.bits.chg;
+ break;
+ case STAT_CHG_B_CHGIN_DTLS:
+ *status = (uint8_t)reg_stat_chg_b.bits.chgin_dtls;
+ break;
+ case STAT_CHG_B_CHG_DTLS:
+ *status = (uint8_t)reg_stat_chg_b.bits.chg_dtls;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_chg_dtls(decode_chg_dtls_t *chg_dtls)
+{
+ int ret;
+ reg_stat_chg_b_t reg_stat_chg_b = {0};
+
+ ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *chg_dtls = (decode_chg_dtls_t)reg_stat_chg_b.bits.chg_dtls;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_thm_hot(decode_thm_hot_t thm_hot)
+{
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_hot, thm_hot);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_thm_hot(decode_thm_hot_t *thm_hot)
+{
+ int ret;
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *thm_hot = (decode_thm_hot_t)reg_cnfg_chg_a.bits.thm_hot;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_thm_warm(decode_thm_warm_t thm_warm)
+{
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_warm, thm_warm);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_thm_warm(decode_thm_warm_t *thm_warm)
+{
+ int ret;
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *thm_warm = (decode_thm_warm_t)reg_cnfg_chg_a.bits.thm_warm;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_thm_cool(decode_thm_cool_t thm_cool)
+{
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cool, thm_cool);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_thm_cool(decode_thm_cool_t *thm_cool)
+{
+ int ret;
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *thm_cool = (decode_thm_cool_t)reg_cnfg_chg_a.bits.thm_cool;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_thm_cold(decode_thm_cold_t thm_cold)
+{
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cold, thm_cold);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659:: get_thm_cold(decode_thm_cold_t *thm_cold)
+{
+ int ret;
+ reg_cnfg_chg_a_t reg_cnfg_chg_a = {0};
+
+ ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *thm_cold = (decode_thm_cold_t)reg_cnfg_chg_a.bits.thm_cold;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t config)
+{
+ int ret;
+ reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
+
+ ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_CHG_B_CHG_EN:
+ reg_cnfg_chg_b.bits.chg_en = config;
+ break;
+ case CNFG_CHG_B_I_PQ:
+ reg_cnfg_chg_b.bits.i_pq = config;
+ break;
+ case CNFG_CHG_B_RSVD:
+ reg_cnfg_chg_b.bits.rsvd = config;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return write_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
+}
+
+int MAX77659::get_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t *config)
+{
+ int ret;
+ reg_cnfg_chg_b_t reg_cnfg_chg_b = {0};
+
+ ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_CHG_B_CHG_EN:
+ *config = (uint8_t)reg_cnfg_chg_b.bits.chg_en;
+ break;
+ case CNFG_CHG_B_I_PQ:
+ *config = (uint8_t)reg_cnfg_chg_b.bits.i_pq;
+ break;
+ case CNFG_CHG_B_RSVD:
+ *config = (uint8_t)reg_cnfg_chg_b.bits.rsvd;
+ break;
+ default:
+ return MAX77659_INVALID_DATA;
+ break;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_chg_pq(float voltV)
+{
+ uint8_t value;
+ reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
+ float voltmV = voltV * 1000;
+
+ if (voltmV < 2300) voltmV = 2300;
+ else if (voltmV > 3000) voltmV = 3000;
+
+ value = (voltmV - 2300) / 100;
+
+ SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.chg_pq, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_chg_pq(float *voltV)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
+
+ ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_c.bits.chg_pq;
+ *voltV = (bit_value * 0.1f) + 2.3f;
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_i_term(float percent)
+{
+ uint8_t value;
+ reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
+
+ if (percent < 7.5f) value = 0;
+ else if ((percent >= 7.5f) && (percent < 10)) value = 1;
+ else if ((percent >= 10) && (percent < 15)) value = 2;
+ else if (percent >= 15) value = 3;
+
+ SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.i_term, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_i_term(float *percent)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
+
+ ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_c.bits.i_term;
+
+ if (bit_value == 0) *percent = 5.0f;
+ else if (bit_value == 1) *percent = 7.5f;
+ else if (bit_value == 2) *percent = 10.0f;
+ else if (bit_value == 3) *percent = 15.0f;
+ else return MAX77659_INVALID_DATA;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_t_topoff(uint8_t minute)
+{
+ uint8_t value;
+ reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
+
+ if (minute > 35) minute = 35;
+
+ value = (uint8_t)(minute / 5);
+
+ SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.t_topoff, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_t_topoff(uint8_t *minute)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_c_t reg_cnfg_chg_c = {0};
+
+ ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_c.bits.t_topoff;
+ *minute = (bit_value * 5);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_tj_reg(uint8_t tempDegC)
+{
+ uint8_t value;
+ reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
+
+ if (tempDegC < 60) tempDegC = 60;
+ else if (tempDegC > 100) tempDegC = 100;
+
+ value = (tempDegC - 60) / 10;
+
+ SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.tj_reg, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_tj_reg(uint8_t *tempDegC)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
+
+ ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_d.bits.tj_reg;
+ *tempDegC = (bit_value * 10) + 60;
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_vsys_hdrm(decode_vsys_hdrm_t vsys_hdrm)
+{
+ reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_hdrm, vsys_hdrm);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_vsys_hdrm(decode_vsys_hdrm_t *vsys_hdrm)
+{
+ int ret;
+ reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
+
+ ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *vsys_hdrm = (decode_vsys_hdrm_t)reg_cnfg_chg_d.bits.vsys_hdrm;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_vsys_min(decode_vsys_min_t vsys_min)
+{
+ reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_min, vsys_min);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_vsys_min(decode_vsys_min_t *vsys_min)
+{
+ int ret;
+ reg_cnfg_chg_d_t reg_cnfg_chg_d = {0};
+
+ ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *vsys_min = (decode_vsys_min_t)reg_cnfg_chg_d.bits.vsys_min;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_chg_cc(float currentmA)
+{
+ uint8_t value;
+ reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
+ float currentuA = currentmA * 1000;
+
+ if (currentuA < 7500) currentuA = 7500;
+ if (currentuA > 300000) currentuA = 300000;
+
+ value = (currentuA - 7500) / 7500;
+
+ SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.chg_cc, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_chg_cc(float *currentmA)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
+
+ ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_e.bits.chg_cc;
+ if (bit_value >= 39) bit_value = 39; //0x27 to 0x3F = 300.0mA
+
+ *currentmA = (bit_value * 7.5f) + 7.5f;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_t_fast_chg(decode_t_fast_chg_t t_fast_chg)
+{
+ reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.t_fast_chg, t_fast_chg);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_t_fast_chg(decode_t_fast_chg_t *t_fast_chg)
+{
+ int ret;
+ reg_cnfg_chg_e_t reg_cnfg_chg_e = {0};
+
+ ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *t_fast_chg = (decode_t_fast_chg_t)reg_cnfg_chg_e.bits.t_fast_chg;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_chg_cc_jeita(float currentmA)
+{
+ uint8_t value;
+ reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
+ float currentuA = currentmA * 1000;
+
+ if (currentuA < 7500) currentuA = 7500;
+ else if (currentuA > 300000) currentuA = 300000;
+
+ value = round(currentuA - 7500) / 7500;
+
+ SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.chg_cc_jeita, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_chg_cc_jeita(float *currentmA)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
+
+ ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_f.bits.chg_cc_jeita;
+ if (bit_value >= 39) bit_value = 39; //0x27 to 0x3F = 300.0mA
+
+ *currentmA = (bit_value * 7.5f) + 7.5f;
+ return MAX77659_NO_ERROR;
+}
+
+
+
+int MAX77659::set_thm_en(decode_thm_en_t thm_en)
+{
+ reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.thm_en, thm_en);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_thm_en(decode_thm_en_t *thm_en)
+{
+ int ret;
+ reg_cnfg_chg_f_t reg_cnfg_chg_f = {0};
+
+ ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *thm_en = (decode_thm_en_t)reg_cnfg_chg_f.bits.thm_en;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_chg_cv(float voltV)
+{
+ uint8_t value;
+ reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
+ float voltmV = voltV * 1000;
+
+ if (voltmV < 3600) voltmV = 3600;
+ else if (voltmV > 4600) voltmV = 4600;
+
+ value = (voltmV - 3600) / 25;
+
+ SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.chg_cv, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_chg_cv(float *voltV)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
+
+ ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_g.bits.chg_cv;
+ *voltV = (bit_value * 0.025f) + 3.6f;
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_usbs(decode_usbs_t usbs)
+{
+ reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.usbs, usbs);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_usbs(decode_usbs_t *usbs)
+{
+ int ret;
+ reg_cnfg_chg_g_t reg_cnfg_chg_g = {0};
+
+ ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *usbs = (decode_usbs_t)reg_cnfg_chg_g.bits.usbs;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_chg_cv_jeita(float voltV)
+{
+ uint8_t value;
+ reg_cnfg_chg_h_t reg_cnfg_chg_h = {0};
+ float voltmV = voltV * 1000;
+
+ if (voltmV < 3600) voltmV = 3600;
+ else if (voltmV > 4600) voltmV = 4600;
+
+ value = round(voltmV - 3600) / 25;
+
+ SET_BIT_FIELD(CNFG_CHG_H, reg_cnfg_chg_h, reg_cnfg_chg_h.bits.chg_cv_jeita, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_chg_cv_jeita(float *voltV)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_h_t reg_cnfg_chg_h = {0};
+
+ ret = read_register(CNFG_CHG_H, (uint8_t *)&(reg_cnfg_chg_h));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_h.bits.chg_cv_jeita;
+ *voltV = (bit_value * 0.025f) + 3.6f;
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_imon_dischg_scale(float currentmA)
+{
+ uint8_t value;
+ reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
+
+ if (currentmA < 40.5f) value = 0;
+ else if ((currentmA >= 40.5f) && (currentmA < 72.3f)) value = 1;
+ else if ((currentmA >= 72.3f) && (currentmA < 103.4f)) value = 2;
+ else if ((currentmA >= 103.4f) && (currentmA < 134.1f)) value = 3;
+ else if ((currentmA >= 134.1f) && (currentmA < 164.1f)) value = 4;
+ else if ((currentmA >= 164.1f) && (currentmA < 193.7f)) value = 5;
+ else if ((currentmA >= 193.7f) && (currentmA < 222.7f)) value = 6;
+ else if ((currentmA >= 222.7f) && (currentmA < 251.2f)) value = 7;
+ else if ((currentmA >= 251.2f) && (currentmA < 279.3f)) value = 8;
+ else if ((currentmA >= 279.3f) && (currentmA < 300.0f)) value = 9;
+ else if (currentmA >= 300.0f) value = 10;
+
+ SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.imon_dischg_scale, value);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_imon_dischg_scale(float *currentmA)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
+
+ ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_chg_i.bits.imon_dischg_scale;
+
+ if (bit_value == 0) *currentmA = 8.2f;
+ else if (bit_value == 1) *currentmA = 40.5f;
+ else if (bit_value == 2) *currentmA = 72.3f;
+ else if (bit_value == 3) *currentmA = 103.4f;
+ else if (bit_value == 4) *currentmA = 134.1f;
+ else if (bit_value == 5) *currentmA = 164.1f;
+ else if (bit_value == 6) *currentmA = 193.7f;
+ else if (bit_value == 7) *currentmA = 222.7f;
+ else if (bit_value == 8) *currentmA = 251.2f;
+ else if (bit_value == 9) *currentmA = 279.3f;
+ else *currentmA = 300.0f; //0xA to 0xF = 300.0mA
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_mux_sel(decode_mux_sel_t selection)
+{
+ reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
+
+ SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.mux_sel, selection);
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_mux_sel(decode_mux_sel_t *selection)
+{
+ int ret;
+ reg_cnfg_chg_i_t reg_cnfg_chg_i = {0};
+
+ ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *selection = (decode_mux_sel_t)reg_cnfg_chg_i.bits.mux_sel;
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_tv_sbb(uint8_t channel, float voltV)
+{
+ uint8_t value;
+ reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
+ reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
+ reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
+ float voltmV = voltV * 1000;
+
+ if (voltmV < 500) voltmV = 500;
+ else if (voltmV > 5500) voltmV = 5500;
+
+ value = (voltmV - 500) / 25;
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value);
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_tv_sbb(uint8_t channel, float *voltV)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
+ reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
+ reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ if (bit_value > 200) bit_value = 200;
+ *voltV = (bit_value * 0.025f) + 0.5f;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_op_mode(uint8_t channel, decode_op_mode_t mode)
+{
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode, mode);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode, mode);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode, mode);
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_op_mode(uint8_t channel, decode_op_mode_t *mode)
+{
+ int ret;
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *mode = (decode_op_mode_t)reg_cnfg_sbb0_b.bits.op_mode;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *mode = (decode_op_mode_t)reg_cnfg_sbb1_b.bits.op_mode;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *mode = (decode_op_mode_t)reg_cnfg_sbb2_b.bits.op_mode;
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb)
+{
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb)
+{
+ int ret;
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb)
+{
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb)
+{
+ int ret;
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_op_mode_chg(decode_op_mode_chg_t op_mode_chg)
+{
+ reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
+
+ SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.op_mode_chg, op_mode_chg);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_op_mode_chg(decode_op_mode_chg_t *op_mode_chg)
+{
+ int ret;
+ reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
+
+ ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *op_mode_chg = (decode_op_mode_chg_t)reg_cnfg_sbb_top.bits.op_mode_chg;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_drv_sbb(decode_drv_sbb_t drv_sbb)
+{
+ reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
+
+ SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.drv_sbb, drv_sbb);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_drv_sbb(decode_drv_sbb_t *drv_sbb)
+{
+ int ret;
+ reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
+
+ ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *drv_sbb = (decode_drv_sbb_t)reg_cnfg_sbb_top.bits.drv_sbb;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_ip_chg(decode_ip_chg_t ip_chg)
+{
+ reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0};
+
+ SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_chg, ip_chg);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_ip_chg(decode_ip_chg_t *ip_chg)
+{
+ int ret;
+ reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0};
+
+ ret = read_register(CNFG_SBB_TOP_B, (uint8_t *)&(reg_cnfg_sbb_top_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *ip_chg = (decode_ip_chg_t)reg_cnfg_sbb_top_b.bits.ip_chg;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb)
+{
+ reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0};
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb0, ip_sbb);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb1, ip_sbb);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb2, ip_sbb);
+ }
+ else {
+ return MAX77659_INVALID_DATA;
+ }
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb)
+{
+ int ret;
+ reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0};
+
+ ret = read_register(CNFG_SBB_TOP_B, (uint8_t *)&(reg_cnfg_sbb_top_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ if (channel == 0)
+ *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb0;
+ else if (channel == 1)
+ *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb1;
+ else if (channel == 2)
+ *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb2;
+ else
+ return MAX77659_INVALID_DATA;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_tv_ldo_offset(decode_tv_ldo_offset_t offset)
+{
+ reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+
+ SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo_offset, offset);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_tv_ldo_offset(decode_tv_ldo_offset_t *offset)
+{
+ int ret;
+ reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+
+ ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *offset = (decode_tv_ldo_offset_t)reg_cnfg_ldo0_a.bits.tv_ldo_offset;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_tv_ldo_volt(float voltV)
+{
+ int ret;
+ uint8_t value;
+ reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+ float voltmV = voltV * 1000;
+
+ ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ if (reg_cnfg_ldo0_a.bits.tv_ldo_offset == 0) { //No Offset
+ if (voltmV < 500) voltmV = 500;
+ else if (voltmV > 3675) voltmV = 3675;
+
+ value = (voltmV - 500) / 25;
+ }
+ else { //1.325V Offset
+ if (voltmV < 1825) voltmV = 1825;
+ else if (voltmV > 5000) voltmV = 5000;
+
+ value = (voltmV - 1825) / 25;
+ }
+
+ SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo_volt, value);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_tv_ldo_volt(float *voltV)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
+
+ ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_ldo0_a.bits.tv_ldo_volt;
+ if (reg_cnfg_ldo0_a.bits.tv_ldo_offset == 0) //No Offset
+ *voltV = (bit_value * 0.025f) + 0.5f;
+ else //1.325V Offset
+ *voltV = (bit_value * 0.025f) + 1.825f;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_en_ldo(decode_en_ldo_t en_ldo)
+{
+ reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+ SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo, en_ldo);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_en_ldo( decode_en_ldo_t *en_ldo)
+{
+ int ret;
+ reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+ ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *en_ldo = (decode_en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_ade_ldo(decode_ade_ldo_t ade_ldo)
+{
+ reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+ SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo, ade_ldo);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_ade_ldo(decode_ade_ldo_t *ade_ldo)
+{
+ int ret;
+ reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+ ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *ade_ldo = (decode_ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::set_ldo_md(decode_ldo_md_t mode)
+{
+ reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+ SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo_md, mode);
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::get_ldo_md(decode_ldo_md_t *mode)
+{
+ int ret;
+ reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
+
+ ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ *mode = (decode_ldo_md_t)reg_cnfg_ldo0_b.bits.ldo_md;
+
+ return MAX77659_NO_ERROR;
+}
+
+int MAX77659::irq_disable_all()
+{
+ int ret;
+ uint8_t reg = 0;
+ uint8_t status = 0;
+
+ //Disable Masks in INTM_GLBL1
+ ret = write_register(INTM_GLBL1, ®);
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ //Disable Masks in INTM_GLBL0
+ ret = write_register(INTM_GLBL0, ®);
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ //Disable Masks in INT_M_CHG
+ ret = write_register(INT_M_CHG, ®);
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ // Clear Interrupt Flags in INT_GLBL1
+ ret = read_register(INT_GLBL1, &status);
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ // Clear Interrupt Flags in INT_GLBL0
+ ret = read_register(INT_GLBL0, &status);
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ // Clear Interrupt Flags in INT_CHG
+ ret = read_register(INT_CHG, &status);
+ if (ret != MAX77659_NO_ERROR) return ret;
+
+ return MAX77659_NO_ERROR;
+}
+
+void MAX77659::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb)
+{
+ interrupt_handler_list[id].func = func;
+ interrupt_handler_list[id].cb = cb;
+}
+
+void MAX77659::post_interrupt_work()
+{
+ int ret;
+ uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0;
+
+
+ while (true) {
+
+ ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
+
+ // Check Interrupt Flags in INT_GLBL0
+ ret = read_register(INT_GLBL0, ®);
+ if (ret != MAX77659_NO_ERROR) return;
+
+ ret = read_register(INTM_GLBL0, &inten);
+ if (ret != MAX77659_NO_ERROR) return;
+
+ not_inten = ~inten; // 0 means unmasked.
+
+ for (int i = 0; i < INT_GLBL1_GPI1_F; i++) {
+ mask = (1 << i);
+ if ((reg & mask) && (not_inten & mask)) {
+ if (interrupt_handler_list[i].func != NULL) {
+ interrupt_handler_list[i]
+ .func(interrupt_handler_list[i].cb);
+ }
+ }
+ }
+
+ // Check Interrupt Flags in INT_GLBL1
+ ret = read_register(INT_GLBL1, ®);
+ if (ret != MAX77659_NO_ERROR) return;
+
+ ret = read_register(INTM_GLBL1, &inten);
+ if (ret != MAX77659_NO_ERROR) return;
+
+ not_inten = ~inten; // 0 means unmasked.
+
+ for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_THM_I; i++) {
+ mask = (1 << (i - INT_GLBL1_GPI1_F));
+ if ((reg & mask) && (not_inten & mask)) {
+ if (interrupt_handler_list[i].func != NULL) {
+ interrupt_handler_list[i]
+ .func(interrupt_handler_list[i].cb);
+ }
+ }
+ }
+
+ // Check Interrupt Flags in INT_CHG
+ ret = read_register(INT_CHG, ®);
+ if (ret != MAX77659_NO_ERROR) return;
+
+ ret = read_register(INT_M_CHG, &inten);
+ if (ret != MAX77659_NO_ERROR) return;
+ not_inten = ~inten; // 0 means unmasked.
+
+ for (int i = INT_CHG_THM_I; i < INT_CHG_END; i++) {
+ mask = (1 << (i - INT_CHG_THM_I));
+ if ((reg & mask) && (not_inten & mask)) {
+ if (interrupt_handler_list[i].func != NULL) {
+ interrupt_handler_list[i]
+ .func(interrupt_handler_list[i].cb);
+ }
+ }
+ }
+ }
+}
+
+void MAX77659::interrupt_handler()
+{
+ post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
+}
diff -r 000000000000 -r 047a7089311e MAX77659.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77659.h Mon Aug 22 19:05:12 2022 +0300
@@ -0,0 +1,1636 @@
+/*******************************************************************************
+* Copyright (C) 2022 Analog Devices, Inc., All rights Reserved.
+*
+* This software is protected by copyright laws of the United States and
+* of foreign countries. This material may also be protected by patent laws
+* and technology transfer regulations of the United States and of foreign
+* countries. This software is furnished under a license agreement and/or a
+* nondisclosure agreement and may only be used or reproduced in accordance
+* with the terms of those agreements. Dissemination of this information to
+* any party or parties not specified in the license agreement and/or
+* nondisclosure agreement is expressly prohibited.
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Analog Devices, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+#ifndef _MAX77659_H_
+#define _MAX77659_H_
+
+#include "mbed.h"
+#include "MAX77659_regs.h"
+
+#define MAX77659_NO_ERROR 0
+#define MAX77659_VALUE_NULL -1
+#define MAX77659_WRITE_DATA_FAILED -2
+#define MAX77659_READ_DATA_FAILED -3
+#define MAX77659_INVALID_DATA -4
+
+#define MAX77659_I2C_ADDRESS 0x80
+
+/**
+ * @brief MAX77659 SIMO PMIC with 300mA Switching Charger.
+ *
+ * @details The MAX77659 provides highly-efficient integrated battery
+ * charging and power supply solutions for low-power applications where size and efficiency are critical.
+ * https://www.maximintegrated.com/en/products/power/power-management-ics/MAX77659.html
+ *
+ * @code
+ * @endcode
+ */
+
+class MAX77659
+{
+private:
+ I2C *i2c_handler;
+ InterruptIn *irq_pin; // interrupt pin
+
+ /**
+ * @brief Register Addresses
+ * @details Enumerated MAX77659 register addresses
+ */
+ typedef enum {
+ /*Global*/
+ INT_GLBL0 = 0x00, // Interrupt Status 0
+ INT_GLBL1 = 0x04, // Interrupt Status 1
+ ERCFLAG = 0x05, // Flags
+ STAT_GLBL = 0x06, // Global Status
+ INTM_GLBL1 = 0x08, // Interrupt Mask 1
+ INTM_GLBL0 = 0x09, // Interrupt Mask 0
+ CNFG_GLBL = 0x10, // Configuration Global
+ CNFG_GPIO0 = 0x11, // GPIO0 Configuration
+ CNFG_GPIO1 = 0x12, // GPIO1 Configuration
+ CID = 0x14, // Chip Identification Code
+ CNFG_WDT = 0x17, // Configuration WatchDog Timer
+ /*Charger*/
+ INT_CHG = 0x01, // Charger Interrupt Status
+ STAT_CHG_A = 0x02, // Charger Status A
+ STAT_CHG_B = 0x03, // Charger Status B
+ INT_M_CHG = 0x07, // Charger Interrupt Mask
+ CNFG_CHG_A = 0x20, // Charger Configuration A
+ CNFG_CHG_B = 0x21, // Charger Configuration B
+ CNFG_CHG_C = 0x22, // Charger Configuration C
+ CNFG_CHG_D = 0x23, // Charger Configuration D
+ CNFG_CHG_E = 0x24, // Charger Configuration E
+ CNFG_CHG_F = 0x25, // Charger Configuration F
+ CNFG_CHG_G = 0x26, // Charger Configuration G
+ CNFG_CHG_H = 0x27, // Charger Configuration H
+ CNFG_CHG_I = 0x28, // Charger Configuration I
+ /*SBB*/
+ CNFG_SBB0_A = 0x29, // SIMO Buck-Boost 0 Configuration A
+ CNFG_SBB0_B = 0x2A, // SIMO Buck-Boost 0 Configuration B
+ CNFG_SBB1_A = 0x2B, // SIMO Buck-Boost 1 Configuration A
+ CNFG_SBB1_B = 0x2C, // SIMO Buck-Boost 1 Configuration B
+ CNFG_SBB2_A = 0x2D, // SIMO Buck-Boost 2 Configuration A
+ CNFG_SBB2_B = 0x2E, // SIMO Buck-Boost 2 Configuration B
+ CNFG_SBB_TOP = 0x2F, // SIMO Buck-Boost Configuration
+ CNFG_SBB_TOP_B = 0x30, // SIMO Buck-Boost Configuration
+ /*LDO*/
+ CNFG_LDO0_A = 0x38, // LDO Configuration A
+ CNFG_LDO0_B = 0x39 // LDO Configuration B
+ } reg_t;
+
+ /**
+ * @brief Interrupt handler function
+ */
+ void interrupt_handler();
+
+ void (MAX77659::*funcptr)(void);
+
+ /**
+ * @brief Post interrupt jobs after interrupt is detected.
+ */
+ void post_interrupt_work();
+
+ Thread *post_intr_work_thread;
+
+ struct handler {
+ void (*func)(void *);
+ void *cb;
+ };
+
+ handler *interrupt_handler_list;
+
+public:
+ /**
+ * @brief Register Configuration
+ * All Interrupt Flags combined from INT_GLBL0, INT_GLBL1 and INT_CHG
+ *
+ * @details
+ * - Register : ERCFLAG (0x05)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Enumerated interrupt flags
+ */
+ typedef enum {
+ INT_GLBL0_GPI0_F,
+ INT_GLBL0_GPI0_R,
+ INT_GLBL0_NEN_F,
+ INT_GLBL0_NEN_R,
+ INT_GLBL0_TJAL1_R,
+ INT_GLBL0_TJAL2_R,
+ INT_GLBL0_DOD_R,
+ INT_GLBL1_GPI1_F,
+ INT_GLBL1_GPI1_R,
+ INT_GLBL1_SBB_TO,
+ INT_GLBL1_LDO_F,
+ INT_CHG_THM_I,
+ INT_CHG_CGH_I,
+ INT_CHG_CHGIN_I,
+ INT_CHG_TJ_REG_I,
+ INT_CHG_SYS_CTRL_I,
+ INT_CHG_END
+ } reg_bit_int_glbl_t;
+
+ /**
+ * MAX77659 constructor.
+ */
+ MAX77659(I2C *i2c, PinName IRQPin = NC);
+
+ /**
+ * MAX77659 destructor.
+ */
+ ~MAX77659();
+
+ /**
+ * @brief Function pointer type to interrupt handler function
+ */
+ typedef void (*interrupt_handler_function)(void *);
+
+ /**
+ * @brief Read from a register.
+ *
+ * @param[in] reg Address of a register to be read.
+ * @param[out] value Pointer to save result value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int read_register(uint8_t reg, uint8_t *value);
+
+ /**
+ * @brief Write to a register.
+ *
+ * @param[in] reg Address of a register to be written.
+ * @param[out] value Pointer of value to be written to register.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int write_register(uint8_t reg, const uint8_t *value);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : ERCFLAG (0x05)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Event Recorder Flags.
+ */
+ typedef enum {
+ ERCFLAG_TOVLD,
+ ERCFLAG_SYSOVLO,
+ ERCFLAG_AVLUVLO,
+ ERCFLAG_MRST,
+ ERCFLAG_SFT_OFF_F,
+ ERCFLAG_SFT_CRST_F,
+ ERCFLAG_WDT_OFF,
+ ERCFLAG_WDT_RST
+ }reg_bit_ercflag_t;
+
+ /**
+ * @brief Get bit field of ERCFLAG (0x05) register.
+ *
+ * @param[in] bit_field ERCFLAG register bit field to be written.
+ * @param[out] flag Pointer to save result of ercglag bit states.
+ * For individual bit
+ * 0x0: ERCFLAG has not occurred,
+ * 0x1: ERCFLAG has occurred.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : STAT_GLBL (0x06)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Event Recorder Flags.
+ */
+ typedef enum {
+ STAT_GLBL_STAT_IRQ,
+ STAT_GLBL_STAT_EN,
+ STAT_GLBL_TJAL1_S,
+ STAT_GLBL_TJAL2_S,
+ STAT_GLBL_RSVD,
+ STAT_GLBL_DOD_S,
+ STAT_GLBL_BOK,
+ STAT_GLBL_DIDM
+ }reg_bit_stat_glbl_t;
+
+ /**
+ * @brief Get bit field of STAT_GLBL (0x06) register.
+ *
+ * @param[in] bit_field STAT_GLBL register bit field to be written.
+ * @param[out] status Pointer to save result of Status Global bit state.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : All interrupt mask bits.
+ */
+ typedef enum {
+ INT_M_CHG_THM_M,
+ INT_M_CHG_CHG_M,
+ INT_M_CHG_CHGIN_M,
+ INT_M_CHG_TJ_REG_M,
+ INT_M_CHG_SYS_CTRL_M,
+ INTM_GLBL1_GPI1_FM = 8,
+ INTM_GLBL1_GPI1_RM,
+ INTM_GLBL1_SBB_TO_M,
+ INTM_GLBL1_LDO_M,
+ INTM_GLBL0_GPI0_FM = 16,
+ INTM_GLBL0_GPI0_RM,
+ INTM_GLBL0_nEN_FM,
+ INTM_GLBL0_nEN_RM,
+ INTM_GLBL0_TJAL1_RM,
+ INTM_GLBL0_TJAL2_RM,
+ INTM_GLBL0_DOD_RM,
+ INTM_NUM_OF_BIT
+ }reg_bit_int_mask_t;
+
+ /**
+ * @brief Set bit field of INT_M_CHG (0x07), INTM_GLBL1 (0x08) or INTM_GLBL0 (0x09) register.
+ *
+ * @param[in] bit_field Register bit field to be set.
+ * @param[out] maskBit 0x0: Interrupt is unmasked,
+ * 0x1: Interrupt is masked.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit);
+
+ /**
+ * @brief Get bit field of INT_M_CHG (0x07), INTM_GLBL0 (0x08) or INTM_GLBL1 (0x09) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] maskBit 0x0: Interrupt is unmasked,
+ * 0x1: Interrupt is masked.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_GLBL (0x10)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Event Recorder Flags.
+ */
+ typedef enum {
+ CNFG_GLBL_SFT_CTRL,
+ CNFG_GLBL_DBEN_nEN,
+ CNFG_GLBL_nEN_MODE,
+ CNFG_GLBL_SBIA_EN,
+ CNFG_GLBL_SBIA_LPM,
+ CNFG_GLBL_T_MRST,
+ CNFG_GLBL_PU_DIS
+ }reg_bit_cnfg_glbl_t;
+
+ /**
+ * @brief Set CNFG_GLBL (0x10) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[in] config Register bit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t config);
+
+ /**
+ * @brief Get CNFG_GLBL (0x10) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] config Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t *config);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_GPIO0 (0x11) or CNFG_GPIO1 (0x12)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Event Recorder Flags.
+ */
+ typedef enum {
+ CNFG_GPIO_DIR,
+ CNFG_GPIO_DI,
+ CNFG_GPIO_DRV,
+ CNFG_GPIO_DO,
+ CNFG_GPIO_DBEN_GPI,
+ CNFG_GPIO_ALT_GPIO,
+ CNFG_GPIO_RSVD
+ }reg_bit_cnfg_gpio_t;
+
+ /**
+ * @brief Set either CNFG_GPIO0 (0x11) or CNFG_GPIO1 (0x12).
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[in] channel Channel number: 0 or 1
+ * @param[in] config Register bit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config);
+
+ /**
+ * @brief Get either CNFG_GPIO0 (0x11) or CNFG_GPIO1 (0x12).
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[in] channel Channel number: 0 or 1
+ * @param[out] config Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config);
+
+ /**
+ * @brief Get bit field of CID (0x14) register.
+ *
+ * @return CID on success, error code on failure.
+ */
+ int get_cid(void);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_WDT (0x17)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Watchdog Timer Configuration.
+ */
+ typedef enum {
+ CNFG_WDT_WDT_LOCK,
+ CNFG_WDT_WDT_EN,
+ CNFG_WDT_WDT_CLR,
+ CNFG_WDT_WDT_MODE,
+ CNFG_WDT_WDT_PER,
+ CNFG_WDT_RSVD
+ }reg_bit_cnfg_wdt_t;
+
+ /**
+ * @brief Set CNFG_WDT (0x17) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[in] config Field value to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config);
+
+ /**
+ * @brief Get CNFG_WDT (0x17) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] config Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : STAT_CHG_A (0x02)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Watchdog Timer Configuration.
+ */
+ typedef enum {
+ STAT_CHG_A_THM_DTLS,
+ STAT_CHG_A_TJ_REG_STAT,
+ STAT_CHG_A_VSYS_MIN_STAT,
+ STAT_CHG_A_RSVD
+ }reg_bit_stat_chg_a_t;
+
+ /**
+ * @brief Get STAT_CHG_A (0x02) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] status Pointer of value to be read.
+ * For individual bit,
+ * 0x0 = It is not engaged,
+ * 0x1 = It is engaged.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_stat_chg_a(reg_bit_stat_chg_a_t bit_field, uint8_t *status);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : STAT_CHG_A (0x02)
+ * - Bit Fields : [2:0]
+ * - Default : 0x0
+ * - Description : Battery Temperature Details.
+ */
+ typedef enum {
+ THM_DTLS_THERMISTOR_DISABLED,
+ THM_DTLS_BATTERY_COLD,
+ THM_DTLS_BATTERY_COOL,
+ THM_DTLS_BATTERY_WARM,
+ THM_DTLS_BATTERY_HOT,
+ THM_DTLS_BATTERY_NORMAL,
+ THM_DTLS_RESERVED_0x06,
+ THM_DTLS_RESERVED_0x07
+ }decode_thm_dtls_t;
+
+ /**
+ * @brief Get Battery Temperature Details.
+ * Valid only when CHGIN_DTLS[1:0] = 0b11.
+ *
+ * @param[out] thm_dtls Battery temperature details field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_thm_dtls(decode_thm_dtls_t *thm_dtls);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : STAT_CHG_B (0x03)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Watchdog Timer Configuration.
+ */
+ typedef enum {
+ STAT_CHG_B_TIME_SUS,
+ STAT_CHG_B_CHG,
+ STAT_CHG_B_CHGIN_DTLS,
+ STAT_CHG_B_CHG_DTLS
+ }reg_bit_stat_chg_b_t;
+
+ /**
+ * @brief Get STAT_CHG_B (0x03) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] status Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_stat_chg_b(reg_bit_stat_chg_b_t bit_field, uint8_t *status);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : STAT_CHG_B (0x03)
+ * - Bit Fields : [7:4]
+ * - Default : 0x0
+ * - Description : CHG_DTLS[3:0] Charger Details.
+ */
+ typedef enum {
+ CHG_DTLS_OFF,
+ CHG_DTLS_PREQUALIFICATION_MODE,
+ CHG_DTLS_FAST_CHARGE_CC,
+ CHG_DTLS_JEITA_FAST_CHARGE_CC,
+ CHG_DTLS_FAST_CHARGE_CV,
+ CHG_DTLS_JEITA_FAST_CHARGE_CV,
+ CHG_DTLS_TOP_OFF_MODE,
+ CHG_DTLS_JEITA_MODIFIED_TOP_OFF_MODE,
+ CHG_DTLS_DONE,
+ CHG_DTLS_JEITA_MODIFIED_DONE,
+ CHG_DTLS_PREQUALIFICATION_TIMER_FAULT,
+ CHG_DTLS_FAST_CHARGE_TIMER_FAULT,
+ CHG_DTLS_BATTERY_TEMPERATURE_FAULT,
+ CHG_DTLS_RESERVED_0x0D,
+ CHG_DTLS_RESERVED_0x0E,
+ CHG_DTLS_RESERVED_0x0F
+ }decode_chg_dtls_t;
+
+ /**
+ * @brief Get Charger Details.
+ *
+ * @param[out] chg_dtls Charger details field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_chg_dtls(decode_chg_dtls_t *chg_dtls);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_A (0x20)
+ * - Bit Fields : [7:6]
+ * - Default : 0x0
+ * - Description : VHOT JEITA Temperature Threshold.
+ */
+ typedef enum {
+ THM_HOT_VOLT_0_411V,
+ THM_HOT_VOLT_0_367V,
+ THM_HOT_VOLT_0_327V,
+ THM_HOT_VOLT_0_291V
+ }decode_thm_hot_t;
+
+ /**
+ * @brief Set the VHOT JEITA Temperature Threshold.
+ *
+ * @param[in] thm_hot The VHOT JEITA temperature threshold field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_thm_hot(decode_thm_hot_t thm_hot);
+
+ /**
+ * @brief Get the VHOT JEITA Temperature Threshold.
+ *
+ * @param[out] thm_hot The VHOT JEITA temperature threshold field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_thm_hot(decode_thm_hot_t *thm_hot);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_A (0x20)
+ * - Bit Fields : [5:4]
+ * - Default : 0x0
+ * - Description : VWARM JEITA Temperature Threshold.
+ */
+ typedef enum {
+ THM_WARM_VOLT_0_511V,
+ THM_WARM_VOLT_0_459V,
+ THM_WARM_VOLT_0_411V,
+ THM_WARM_VOLT_0_367V
+ }decode_thm_warm_t;
+
+ /**
+ * @brief Set the VWARM JEITA Temperature Threshold.
+ *
+ * @param[in] thm_warm The VWARM JEITA temperature threshold field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_thm_warm(decode_thm_warm_t thm_warm);
+
+ /**
+ * @brief Get the VWARM JEITA Temperature Threshold.
+ *
+ * @param[out] thm_warm The VWARM JEITA temperature threshold field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_thm_warm(decode_thm_warm_t *thm_warm);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_A (0x20)
+ * - Bit Fields : [3:2]
+ * - Default : 0x0
+ * - Description : VCOOL JEITA Temperature Threshold.
+ */
+ typedef enum {
+ THM_COOL_VOLT_0_923V,
+ THM_COOL_VOLT_0_867V,
+ THM_COOL_VOLT_0_807V,
+ THM_COOL_VOLT_0_747V
+ }decode_thm_cool_t;
+
+ /**
+ * @brief Set the VCOOL JEITA Temperature Threshold.
+ *
+ * @param[in] thm_cool The VCOOL JEITA temperature threshold field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_thm_cool(decode_thm_cool_t thm_cool);
+
+ /**
+ * @brief Get the VCOOL JEITA Temperature Threshold.
+ *
+ * @param[out] thm_cool The VCOOL JEITA temperature threshold field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_thm_cool(decode_thm_cool_t *thm_cool);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_A (0x20)
+ * - Bit Fields : [1:0]
+ * - Default : 0x0
+ * - Description : VCOLD JEITA Temperature Threshold.
+ */
+ typedef enum {
+ THM_COLD_VOLT_1_024V,
+ THM_COLD_VOLT_0_976V,
+ THM_COLD_VOLT_0_923V,
+ THM_COLD_VOLT_0_867V
+ }decode_thm_cold_t;
+
+ /**
+ * @brief Set the VCOLD JEITA Temperature Threshold.
+ *
+ * @param[in] thm_cold The VCOLD JEITA temperature threshold field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_thm_cold(decode_thm_cold_t thm_cold);
+
+ /**
+ * @brief Get the VCOLD JEITA Temperature Threshold.
+ *
+ * @param[out] thm_cold The VCOLD JEITA temperature threshold field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_thm_cold(decode_thm_cold_t *thm_cold);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_B (0x21)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Watchdog Timer Configuration.
+ */
+ typedef enum {
+ CNFG_CHG_B_CHG_EN,
+ CNFG_CHG_B_I_PQ,
+ CNFG_CHG_B_RSVD
+ }reg_bit_cnfg_chg_b_t;
+
+ /**
+ * @brief Set CNFG_CHG_B (0x21) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[in] config Register bit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t config);
+
+ /**
+ * @brief Get CNFG_CHG_B (0x21) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] config Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t *config);
+
+ /**
+ * @brief Set Battery Prequalification Voltage Threshold (VPQ).
+ * Bit 7:5 of CNFG_CHG_C (0x22) register.
+ *
+ * @param[in] voltV
+ * 2.3V, 2.4V, 2.5V, 2.6V,
+ * 2.7V, 2.8V, 2.9V, 3.0V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_chg_pq(float voltV);
+
+ /**
+ * @brief Get Battery Prequalification Voltage Threshold (VPQ).
+ * Bit 7:5 of CNFG_CHG_C (0x22) register.
+ *
+ * @param[out] voltV Pointer of value to be read.
+ * 2.3V, 2.4V, 2.5V, 2.6V,
+ * 2.7V, 2.8V, 2.9V, 3.0V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_chg_pq(float *voltV);
+
+ /**
+ * @brief Set Charger Termination Current (ITERM).
+ * I_TERM[1:0] sets the charger termination current
+ * as a percentage of the fast charge current IFAST-CHG.
+ * Bit 4:3 of CNFG_CHG_C (0x22) register.
+ *
+ * @param[in] percent
+ * 5%, 7.5%, 10%, 15%.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_i_term(float percent);
+
+ /**
+ * @brief Get Charger Termination Current (ITERM).
+ * I_TERM[1:0] sets the charger termination current
+ * as a percentage of the fast charge current IFAST-CHG.
+ * Bit 4:3 of CNFG_CHG_C (0x22) register.
+ *
+ * @param[out] percent Pointer of value to be read.
+ * 5%, 7.5%, 10%, 15%.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_i_term(float *percent);
+
+ /**
+ * @brief Set Top-off Timer Value.
+ * Bit 2:0 of CNFG_CHG_C (0x22) register.
+ *
+ * @param[in] minute
+ * 0 minutes, 5 minutes, 10 minutes
+ * 15 minutes, 20 minutes, 25 minutes,
+ * 30 minutes, 35 minutes.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_t_topoff(uint8_t minute);
+
+ /**
+ * @brief Get Top-off Timer Value.
+ * Bit 2:0 of CNFG_CHG_C (0x22) register.
+ *
+ * @param[out] minute Pointer of value to be read.
+ 0 minutes, 5 minutes, 10 minutes
+ * 15 minutes, 20 minutes, 25 minutes,
+ * 30 minutes, 35 minutes.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_t_topoff(uint8_t *minute);
+
+ /**
+ * @brief Set the Die Junction Temperature Regulation Point, TJ-REG.
+ * Bit 7:5 of CNFG_CHG_D (0x23) register.
+ *
+ * @param[in] tempDegC 60ºC, 70ºC, 80ºC,
+ * 90ºC, 100ºC.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_tj_reg(uint8_t tempDegC);
+
+ /**
+ * @brief Get the Die Junction Temperature Regulation Point, TJ-REG.
+ * Bit 7:5 of CNFG_CHG_D (0x23) register.
+ *
+ * @param[out] tempDegC Pointer of value to be read.
+ * 60ºC, 70ºC, 80ºC, 90ºC, 100ºC.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_tj_reg(uint8_t *tempDegC);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_D (0x23)
+ * - Bit Fields : [4]
+ * - Default : 0x0
+ * - Description : SYS Headroom Voltage Regulation.
+ */
+ typedef enum {
+ VSYS_HDRM_VOLT_0_15,
+ VSYS_HDRM_VOLT_0_20
+ }decode_vsys_hdrm_t;
+
+ /**
+ * @brief Set SYS Headroom Voltage Regulation.
+ *
+ * @param[in] vsys_hdrm SYS Headroom Voltage field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_vsys_hdrm(decode_vsys_hdrm_t vsys_hdrm);
+
+ /**
+ * @brief Get SYS Headroom Voltage Regulation.
+ *
+ * @param[out] vsys_hdrm SYS Headroom Voltage field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_vsys_hdrm(decode_vsys_hdrm_t *vsys_hdrm);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_D (0x23)
+ * - Bit Fields : [1:0]
+ * - Default : 0x0
+ * - Description : Minimum SYS Voltage.
+ */
+ typedef enum {
+ VSYS_MIN_VOLT_3_2,
+ VSYS_MIN_VOLT_3_3,
+ VSYS_MIN_VOLT_3_4,
+ VSYS_MIN_VOLT_3_5
+ }decode_vsys_min_t;
+
+ /**
+ * @brief Set Minimum SYS Voltage.
+ * Bit 1:0 of CNFG_CHG_D (0x23) register.
+ *
+ * @param[in] vsys_min Decoded values for 3.2V, 3.3V, 3.4V, 3.5V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_vsys_min(decode_vsys_min_t vsys_min);
+
+ /**
+ * @brief Get Minimum SYS Voltage.
+ * Bit 1:0 of CNFG_CHG_D (0x23) register.
+ *
+ * @param[out] vsys_min Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_vsys_min(decode_vsys_min_t *vsys_min);
+
+ /**
+ * @brief Set the Fast-Charge Constant Current Value, IFAST-CHG.
+ * Bit 7:2 of CNFG_CHG_E (0x24) register.
+ *
+ * @param[in] currentmA 7.5mA, 15.0mA, 22.5mA, ...
+ * 292.5mA, 300.0mA.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_chg_cc(float currentmA);
+
+ /**
+ * @brief Get the Fast-Charge Constant Current Value, IFAST-CHG.
+ * Bit 7:2 of CNFG_CHG_E (0x24) register.
+ *
+ * @param[out] currentmA Pointer of value to be read.
+ * 7.5mA, 15.0mA, 22.5mA, ...
+ * 292.5mA, 300.0mA.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_chg_cc(float *currentmA);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_E (0x24)
+ * - Bit Fields : [1:0]
+ * - Default : 0x0
+ * - Description : Fast-charge Safety timer, tFC.
+ */
+ typedef enum {
+ T_FAST_CHG_TIMER_DISABLED,
+ T_FAST_CHG_HOUR_3H,
+ T_FAST_CHG_HOUR_5H,
+ T_FAST_CHG_HOUR_7H
+ }decode_t_fast_chg_t;
+
+ /**
+ * @brief Set the Fast-charge Safety timer, tFC.
+ * Bit 1:0 of CNFG_CHG_E (0x24) register.
+ *
+ * @param[in] t_fast_chg Fast-charge safety timer field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_t_fast_chg(decode_t_fast_chg_t t_fast_chg);
+
+ /**
+ * @brief Get the Fast-charge Safety timer, tFC.
+ * Bit 1:0 of CNFG_CHG_E (0x24) register.
+ *
+ * @param[out] t_fast_chg Fast-charge safety timer field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_t_fast_chg(decode_t_fast_chg_t *t_fast_chg);
+
+ /**
+ * @brief Set IFAST-CHG-JEITA
+ * when the battery is either cool or warm as defined by the
+ * VCOOL and VWARM temperature thresholds.
+ * Bit 7:2 of CNFG_CHG_F (0x25) register.
+ *
+ * @param[in] currentmA 7.5mA, 15.0mA, 22.5mA, ...
+ * 292.5mA, 300.0mA.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_chg_cc_jeita(float currentmA);
+
+ /**
+ * @brief Get IFAST-CHG-JEITA
+ * when the battery is either cool or warm as defined by the
+ * VCOOL and VWARM temperature thresholds.
+ * Bit 7:2 of CNFG_CHG_F (0x25) register.
+ *
+ * @param[out] currentmA Pointer of value to be read.
+ * 7.5mA, 15.0mA, 22.5mA, ...
+ * 292.5mA, 300.0mA.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_chg_cc_jeita(float *currentmA);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_F (0x25)
+ * - Bit Fields : [1]
+ * - Default : 0x0
+ * - Description : Thermistor Enable Bit
+ */
+ typedef enum {
+ THM_EN_DISABLED,
+ THM_EN_ENABLED
+ }decode_thm_en_t;
+
+ /**
+ * @brief Set Thermistor Enable Bit.
+ * Bit 1 of CNFG_CHG_F (0x25) register.
+ *
+ * @param[in] thm_en Thermistor Enable Bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_thm_en(decode_thm_en_t thm_en);
+
+ /**
+ * @brief Get Thermistor Enable Bit.
+ * Bit 1:0 of CNFG_CHG_F (0x25) register.
+ *
+ * @param[out] thm_en Thermistor Enable Bit field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_thm_en(decode_thm_en_t *thm_en);
+
+ /**
+ * @brief Set Fast-Charge Battery Regulation Voltage, VFAST-CHG.
+ * Bit 7:2 of CNFG_CHG_G (0x26) register.
+ *
+ * @param[in] voltV 3.600V, 3.625V, 3.650V, ...
+ * 4.575V, 4.600V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_chg_cv(float voltV);
+
+ /**
+ * @brief Get Fast-Charge Battery Regulation Voltage, VFAST-CHG.
+ * Bit 7:2 of CNFG_CHG_G (0x26) register.
+ *
+ * @param[out] voltV Pointer of value to be read.
+ * 3.600V, 3.625V, 3.650V, ...
+ * 4.575V, 4.600V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_chg_cv(float *voltV);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_G (0x26)
+ * - Bit Fields : [1]
+ * - Default : 0x0
+ * - Description : Setting this bit places CHGIN in USB suspend mode.
+ */
+ typedef enum {
+ USBS_CHGIN_NOT_SUSPENDED,
+ USBS_CHGIN_SUSPENDED
+ }decode_usbs_t;
+
+ /**
+ * @brief Set USB Suspend Mode Bit.
+ * Bit 1 of CNFG_CHG_G (0x26) register.
+ *
+ * @param[in] usbs CHGIN in USB suspend mode bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_usbs(decode_usbs_t usbs);
+
+ /**
+ * @brief Get USB Suspend Mode Bit.
+ * Bit 1:0 of CNFG_CHG_G (0x26) register.
+ *
+ * @param[out] usbs CHGIN in USB suspend mode bit field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_usbs(decode_usbs_t *usbs);
+
+ /**
+ * @brief Set the modified VFAST-CHG-JEITA for when the battery is either
+ * cool or warm as defined by the VCOOL and VWARM temperature thresholds.
+ * Bit 7:2 of CNFG_CHG_H (0x27) register.
+ *
+ * @param[in] voltV Pointer of value to be read.
+ * 3.600V, 3.625V, 3.650V, ...
+ * 4.575V, 4.600V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_chg_cv_jeita(float voltV);
+
+ /**
+ * @brief Get the modified VFAST-CHG-JEITA for when the battery is either
+ * cool or warm as defined by the VCOOL and VWARM temperature thresholds.
+ * Bit 7:2 of CNFG_CHG_H (0x27) register.
+ *
+ * @param[out] voltV Pointer of value to be read.
+ * 3.600V, 3.625V, 3.650V, ...
+ * 4.575V, 4.600V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_chg_cv_jeita(float *voltV);
+
+ /**
+ * @brief Set the Battery Discharge Current Full-Scale Current Value.
+ * Bit 7:4 of CNFG_CHG_I (0x28) register.
+ *
+ * @param[in] currentmA 8.2mA, 40.5mA, 72.3mA, 103.4mA,
+ * 134.1mA, 164.1mA, 193.7mA, 222.7mA,
+ * 251.2mA, 279.3mA, 300.0mA
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_imon_dischg_scale(float currentmA);
+
+ /**
+ * @brief Get the Battery Discharge Current Full-Scale Current Value.
+ * Bit 7:4 of CNFG_CHG_I (0x28) register.
+ *
+ * @param[out] currentmA Pointer of value to be read.
+ * 8.2mA, 40.5mA, 72.3mA, 103.4mA,
+ * 134.1mA, 164.1mA, 193.7mA, 222.7mA,
+ * 251.2mA, 279.3mA, 300.0mA
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_imon_dischg_scale(float *currentmA);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_CHG_I (0x28)
+ * - Bit Fields : [3:0]
+ * - Default : 0x0
+ * - Description : Analog channel to connect to AMUX.
+ */
+ typedef enum {
+ MUX_SEL_MULTIPLEXER_DISABLED,
+ MUX_SEL_CHGIN_VOLTAGE_MONITOR,
+ MUX_SEL_CHGIN_CURRENT_MONITOR,
+ MUX_SEL_BATTERY_VOLTAGE_MONITOR,
+ MUX_SEL_BATTERY_CHARGE_CURRENT_MONITOR,
+ MUX_SEL_BATTERY_DISCHARGE_CURRENT_MONITOR_NORMAL,
+ MUX_SEL_BATTERY_DISCHARGE_CURRENT_MONITOR_NULL,
+ MUX_SEL_RESERVED_0x07,
+ MUX_SEL_RESERVED_0x08,
+ MUX_SEL_AGND_VOLTAGE_MONITOR,
+ MUX_SEL_SYS_VOLTAGE_MONITOR,
+ MUX_SEL_SYS_VOLTAGE_MONITOR_0x0B,
+ MUX_SEL_SYS_VOLTAGE_MONITOR_0x0C,
+ MUX_SEL_SYS_VOLTAGE_MONITOR_0x0D,
+ MUX_SEL_SYS_VOLTAGE_MONITOR_0x0E,
+ MUX_SEL_SYS_VOLTAGE_MONITOR_0x0F
+ }decode_mux_sel_t;
+
+ /**
+ * @brief Set the analog channel to connect to AMUX.
+ *
+ * @param[in] selection AMUX value field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_mux_sel(decode_mux_sel_t selection);
+
+ /**
+ * @brief Get the analog channel to connect to AMUX.
+ *
+ * @param[out] selection AMUX value field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_mux_sel(decode_mux_sel_t *selection);
+
+ /**
+ * @brief Set SIMO Buck-Boost Channel x Target Output Voltage.
+ * CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D)
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[in] voltV SIMO buck-boost channel x target output voltage field to be written.
+ * SBBx = 500mV + 25mV x TV_SBBx[7:0]
+ * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V,
+ * 0.650V, 0.675V, 0.700V, ...
+ * 5.425V, 5.450V, 5.475V, 5.500V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_tv_sbb(uint8_t channel, float voltV);
+
+ /**
+ * @brief Get SIMO Buck-Boost Channel x Target Output Voltage.
+ * CNFG_SBB0_A (0x29), CNFG_SBB1_A (0x2B) and CNFG_SBB2_A (0x2D)
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[out] voltV SIMO buck-boost channel x target output voltage field to be read.
+ * SBBx = 500mV + 25mV x TV_SBBx[7:0]
+ * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V,
+ * 0.650V, 0.675V, 0.700V, ...
+ * 5.425V, 5.450V, 5.475V, 5.500V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_tv_sbb(uint8_t channel, float *voltV);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+ * - Bit Fields : [6]
+ * - Default : 0x0
+ * - Description : Operation mode of SBB0, 1 or 2.
+ */
+ typedef enum {
+ OP_MODE_BUCK_BOOST_MODE,
+ OP_MODE_BUCK_MODE
+ }decode_op_mode_t;
+
+ /**
+ * @brief Set Operation mode of SBBx.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[in] mode Operation mode of SBBx bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_op_mode(uint8_t channel, decode_op_mode_t mode);
+
+ /**
+ * @brief Get Operation mode of SBBx.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[out] mode Operation mode of SBBx bit to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_op_mode(uint8_t channel, decode_op_mode_t *mode);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+ * - Bit Fields : [3]
+ * - Default : 0x0
+ * - Description : SIMO Buck-Boost Channel 0, 1 or 2 Active-Discharge Enable.
+ */
+ typedef enum {
+ ADE_SBB_DISABLED,
+ ADE_SBB_ENABLED
+ }decode_ade_sbb_t;
+
+ /**
+ * @brief Set SIMO Buck-Boost Channel x Active-Discharge Enable.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[in] ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb);
+
+ /**
+ * @brief Get SIMO Buck-Boost Channel x Active-Discharge Enable.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[out] ade_sbb SIMO buck-boost channel 2 active-discharge enable bit to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB0_B (0x2A), CNFG_SBB1_B (0x2C) and CNFG_SBB2_B (0x2E)
+ * - Bit Fields : [2:0]
+ * - Default : 0x0
+ * - Description : Enable Control for SIMO Buck-Boost Channel 0, 1 or 2.
+ */
+ typedef enum {
+ EN_SBB_FPS_SLOT_0,
+ EN_SBB_FPS_SLOT_1,
+ EN_SBB_FPS_SLOT_2,
+ EN_SBB_FPS_SLOT_3,
+ EN_SBB_OFF,
+ EN_SBB_SAME_AS_0X04,
+ EN_SBB_ON,
+ EN_SBB_SAME_AS_0X06
+ }decode_en_sbb_t;
+
+ /**
+ * @brief Set Enable Control for SIMO Buck-Boost Channel x.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[in] en_sbb Enable control for SIMO buck-boost channel x field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb);
+
+ /**
+ * @brief Get Enable Control for SIMO Buck-Boost Channel x.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[out] en_sbb Enable control for SIMO buck-boost channel x field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB_TOP (0x2F)
+ * - Bit Fields : [7]
+ * - Default : 0x0
+ * - Description : Operation mode of the charging channel of SIMO
+ */
+ typedef enum {
+ OP_MODE_CHG_BUCK_BOOST,
+ OP_MODE_CHG_BUCK
+ }decode_op_mode_chg_t;
+
+ /**
+ * @brief Set Operation mode of the charging channel of SIMO.
+ *
+ * @param[in] op_mode_chg Operation mode of the charging channel of SIMO bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_op_mode_chg(decode_op_mode_chg_t op_mode_chg);
+
+ /**
+ * @brief Get Operation mode of the charging channel of SIMO.
+ *
+ * @param[out] op_mode_chg Operation mode of the charging channel of SIMO bit to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_op_mode_chg(decode_op_mode_chg_t *op_mode_chg);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB_TOP (0x2F)
+ * - Bit Fields : [1:0]
+ * - Default : 0x0
+ * - Description : SIMO Buck-Boost (all channels) Drive Strength Trim.
+ */
+ typedef enum {
+ DRV_SBB_FASTEST_TRANSITION_TIME,
+ DRV_SBB_A_LITTLE_SLOWER_THAN_0X00,
+ DRV_SBB_A_LITTLE_SLOWER_THAN_0X01,
+ DRV_SBB_A_LITTLE_SLOWER_THAN_0X02
+ }decode_drv_sbb_t;
+
+ /**
+ * @brief Set SIMO Buck-Boost (all channels) Drive Strength Trim.
+ *
+ * @param[in] drv_sbb SIMO buck-boost drive strength trim field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_drv_sbb(decode_drv_sbb_t drv_sbb);
+
+ /**
+ * @brief Get SIMO Buck-Boost (all channels) Drive Strength Trim.
+ *
+ * @param[out] drv_sbb SIMO buck-boost drive strength trim field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_drv_sbb(decode_drv_sbb_t *drv_sbb);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB_TOP_B (0x30)
+ * - Bit Fields : [7:6]
+ * - Default : 0x0
+ * - Description : SIMO Buck-Boost Charging Channel Peak Current Limit
+ */
+ typedef enum {
+ IP_CHG_AMP_2_000,
+ IP_CHG_AMP_1_500,
+ IP_CHG_AMP_1_000,
+ IP_CHG_AMP_0_500
+ }decode_ip_chg_t;
+
+ /**
+ * @brief Set SIMO Buck-Boost Charging Channel Peak Current Limit.
+ *
+ * @param[in] ip_chg SIMO Buck-Boost Charging Channel Peak Current Limit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_ip_chg(decode_ip_chg_t ip_chg);
+
+ /**
+ * @brief Get SIMO Buck-Boost Charging Channel Peak Current Limit.
+ *
+ * @param[out] ip_chg SIMO Buck-Boost Charging Channel Peak Current Limit field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ip_chg(decode_ip_chg_t *ip_chg);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB_TOP_B (0x30)
+ * - Bit Fields : [5:4], [3:2] and [1:0]
+ * - Default : 0x0
+ * - Description : SIMO Buck-Boost Channel 0, 1 or 2 Peak Current Limit
+ */
+ typedef enum {
+ IP_SBB_AMP_1_000,
+ IP_SBB_AMP_0_750,
+ IP_SBB_AMP_0_500,
+ IP_SBB_AMP_0_333
+ }decode_ip_sbb_t;
+
+ /**
+ * @brief Set SIMO Buck-Boost Channel 0, 1 or 2 Peak Current Limit.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[in] ip_sbb SIMO Buck-Boost Channel x Peak Current Limit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb);
+
+ /**
+ * @brief Get SIMO Buck-Boost Channel 0, 1 or 2 Peak Current Limit.
+ *
+ * @param[in] channel Channel number: 0, 1 or 2.
+ * @param[out] ip_sbb SIMO Buck-Boost Channel x Peak Current Limit field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_LDO0_A (0x38)
+ * - Bit Fields : [7]
+ * - Default : 0x0
+ * - Description : LDO Output Voltage. This bit applies a 1.325V offset to the output voltage of the LDO.
+ */
+ typedef enum {
+ TV_LDO_NO_OFFSET,
+ TV_LDO_NO_1_325V
+ }decode_tv_ldo_offset_t;
+
+ /**
+ * @brief Set LDO Output Channel 0 Target Output Voltage. Bit 7.
+ * CNFG_LDO0_A (0x38)
+ *
+ * @param[in] offset LDO Output Channel 0 target output voltage offset field to be read.
+ *
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_tv_ldo_offset(decode_tv_ldo_offset_t offset);
+
+ /**
+ * @brief Get LDO Output Channel 0 Target Output Voltage. Bit 7.
+ * CNFG_LDO0_A (0x38)
+ *
+ * @param[out] offset LDO Output Channel 0 target output voltage offset field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_tv_ldo_offset(decode_tv_ldo_offset_t *offset);
+
+ /**
+ * @brief Set LDO Output Channel 0 Target Output Voltage. Bit 6:0.
+ * CNFG_LDO0_A (0x38)
+ *
+ * @param[in] voltV LDO Output Channel 0 target output voltage field to be read.
+ * LDOx = 500mV + 25mV x TV_LDOx[6:0]
+ * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V,
+ * 0.650V, 0.675V, 0.700V, ...
+ * 3.650, 3.675.
+ *
+ * When TV_LDO[7] = 0, TV_LDO[6:0] sets the
+ * LDO's output voltage range from 0.5V to 3.675V.
+ * When TV_LDO[7] = 1, TV_LDO[6:0] sets the
+ * LDO's output voltage from 1.825V to 5V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_tv_ldo_volt(float voltV);
+
+ /**
+ * @brief Get LDO Output Channel 0 Target Output Voltage. Bit 6:0.
+ * CNFG_LDO0_A (0x38)
+ *
+ * @param[out] voltV LDO Output Channel 0 target output voltage field to be read.
+ * LDOx = 500mV + 25mV x TV_LDOx[6:0]
+ * 0.500V, 0.525V, 0.550V, 0.575V, 0.600V, 0.625V,
+ * 0.650V, 0.675V, 0.700V, ...
+ * 3.650, 3.675.
+ *
+ * When TV_LDO[7] = 0, TV_LDO[6:0] sets the
+ * LDO's output voltage range from 0.5V to 3.675V.
+ * When TV_LDO[7] = 1, TV_LDO[6:0] sets the
+ * LDO's output voltage from 1.825V to 5V.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_tv_ldo_volt(float *voltV);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_LDO0_B (0x39)
+ * - Bit Fields : [2:0]
+ * - Default : 0x0
+ * - Description : Enable Control for LDO0.
+ */
+ typedef enum {
+ EN_LDO_FPS_SLOT_0,
+ EN_LDO_FPS_SLOT_1,
+ EN_LDO_FPS_SLOT_2,
+ EN_LDO_FPS_SLOT_3,
+ EN_LDO_OFF,
+ EN_LDO_SAME_AS_0X04,
+ EN_LDO_ON,
+ EN_LDO_SAME_AS_0X06
+ }decode_en_ldo_t;
+
+ /**
+ * @brief Set Enable Control for LDO Channel0.
+ *
+ * @param[in] en_ldo Enable control for LDO channel x field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_en_ldo(decode_en_ldo_t en_ldo);
+
+ /**
+ * @brief Get Enable Control for LDO Channel x.
+ *
+ * @param[out] en_ldo Enable control for LDO channel x field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_en_ldo(decode_en_ldo_t *en_ldo);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_LDO0_B (0x39)
+ * - Bit Fields : [3]
+ * - Default : 0x0
+ * - Description : LDO0 Active-Discharge Enable.
+ */
+ typedef enum {
+ ADE_LDO_DISABLED,
+ ADE_LDO_ENABLED
+ }decode_ade_ldo_t;
+
+ /**
+ * @brief Set LDO0 Active-Discharge Enable.
+ *
+ * @param[in] ade_ldo LDO0 active-discharge enable bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_ade_ldo(decode_ade_ldo_t ade_ldo);
+
+ /**
+ * @brief Get LDO0 Active-Discharge Enable.
+ *
+ * @param[out] ade_ldo LDO0 active-discharge enable bit to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ade_ldo(decode_ade_ldo_t *ade_ldo);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_LDO0_B (0x39)
+ * - Bit Fields : [4]
+ * - Default : 0x0
+ * - Description : Operation mode of LDO0.
+ */
+ typedef enum {
+ LDO_MD_LDO_MODE,
+ LDO_MD_LSW_MODE
+ }decode_ldo_md_t;
+
+ /**
+ * @brief Set Operation mode of LDOx.
+ *
+ * @param[in] mode Operation mode of LDOx bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_ldo_md(decode_ldo_md_t mode);
+
+ /**
+ * @brief Get Operation mode of LDOx.
+ *
+ * @param[out] mode Operation mode of LDOx bit to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ldo_md(decode_ldo_md_t *mode);
+
+ /**
+ * @brief Disable all interrupts
+ *
+ * @return 0 on success, error code on failure
+ */
+ int irq_disable_all();
+
+ /**
+ * @brief Set Interrupt Handler for a Specific Interrupt ID.
+ *
+ * @param[in] id Interrupt id, one of INTR_ID_*.
+ * @param[in] func Interrupt handler function.
+ * @param[in] cb Interrupt handler data.
+ */
+ void set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb);
+};
+#endif /*_MAX77659_H_*/
diff -r 000000000000 -r 047a7089311e MAX77659_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77659_regs.h Mon Aug 22 19:05:12 2022 +0300
@@ -0,0 +1,968 @@
+/*******************************************************************************
+* Copyright (C) 2022 Analog Devices, Inc., All rights Reserved.
+*
+* This software is protected by copyright laws of the United States and
+* of foreign countries. This material may also be protected by patent laws
+* and technology transfer regulations of the United States and of foreign
+* countries. This software is furnished under a license agreement and/or a
+* nondisclosure agreement and may only be used or reproduced in accordance
+* with the terms of those agreements. Dissemination of this information to
+* any party or parties not specified in the license agreement and/or
+* nondisclosure agreement is expressly prohibited.
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Analog Devices, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+#ifndef MAX77659_REGS_H_
+#define MAX77659_REGS_H_
+
+/**
+ * @brief INT_GLBL0 Register
+ *
+ * Address : 0x00
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0.
+ Note that "GPI" refers to the GPIO programmed to be an input.
+ 0 = No GPI falling edges have occurred since the last time this bit was read.
+ 1 = A GPI falling edge has occurred since the last time this bit was read. */
+ unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1.
+ Note that "GPI" refers to the GPIO programmed to be an input.
+ 0 = No GPI rising edges have occurred since the last time this bit was read.
+ 1 = A GPI rising edge has occurred since the last time this bit was read. */
+ unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2.
+ 0 = No nEN falling edges have occurred since the last time this bit was read.
+ 1 = A nEN falling edge as occurred since the last time this bit was read. */
+ unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3.
+ 0 = No nEN rising edges have occurred since the last time this bit was read.
+ 1 = A nEN rising edge as occurred since the last time this bit was read. */
+ unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4.
+ 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read.
+ 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */
+ unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5.
+ 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read.
+ 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */
+ unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 6. */
+ unsigned char dod_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 7.
+ 0 = The LDO has not detected dropout since the last time this bit was read.
+ 1 = The LDO has detected dropout since the last time this bit was read. */
+ } bits;
+} reg_int_glbl0_t;
+
+/**
+ * @brief INT_GLBL1 Register
+ *
+ * Address : 0x04
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0.
+ Note that "GPI" refers to the GPIO programmed to be an input.
+ 0 = No GPI falling edges have occurred since the last time this bit was read.
+ 1 = A GPI falling edge has occurred since the last time this bit was read. */
+ unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1.
+ Note that "GPI" refers to the GPIO programmed to be an input.
+ 0 = No GPI rising edges have occurred since the last time this bit was read.
+ 1 = A GPI rising edge has occurred since the last time this bit was read. */
+ unsigned char rsvd1 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3:2. */
+ unsigned char sbb_to : 1; /**< SBB Timeout. Bit 4.
+ 0 = NO SBB timeout occurred since the last time this bit was read
+ 1 = SBB timeout occurred since the last time this bit was read */
+ unsigned char ldo_f : 1; /**< LDO Fault Interrupt. Bit 5.
+ 0 = No fault has occurred on LDO since the last time this bit was read.
+ 1 = LDO has fallen out of regulation since the last time this bit was read. */
+ unsigned char ldo1_f : 1; /**< LDO1 Fault Interrupt. Bit 6.
+ 0 = No fault has occurred on LDO1 since the last time this bit was read.
+ 1 = LDO1 has fallen out of regulation since the last time this bit was read. */
+ unsigned char rsvd2 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
+ } bits;
+} reg_int_glbl1_t;
+
+/**
+ * @brief ERCFLAG Register
+ *
+ * Address : 0x05
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char tovld : 1; /**< Thermal Overload. Bit 0.
+ 0 = Thermal overload has not occurred since the last read of this register.
+ 1 = Thermal overload has occurred since the list read of this register.
+ This indicates that the junction temperature has exceeded 165ºC. */
+ unsigned char sysovlo : 1; /**< SYS Domain Overvoltage Lockout. Bit 1.
+ 0 = The SYS domain overvoltage lockout has not occurred since this last read of this register.
+ 1 = The SYS domain overvoltage lockout has occurred since the last read of this register. */
+ unsigned char avluvlo : 1; /**< AVL Domain Undervoltage Lockout. Bit 2.
+ 0 = The AVL domain undervoltage lockout has not occurred since this last read of this register.
+ 1 = The AVL domain undervoltage lockout has occurred since the last read of this register. */
+ unsigned char mrst : 1; /**< Manual Reset Timer. Bit 3.
+ 0 = A Manual Reset has not occurred since this last read of this register.
+ 1 = A Manual Reset has occurred since this last read of this register. */
+ unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4.
+ 0 = The SFT_OFF function has not occurred since the last read of this register.
+ 1 = The SFT_OFF function has occurred since the last read of this register. */
+ unsigned char sft_crst_f: 1; /**< Software Cold Reset Flag. Bit 5.
+ 0 = The software cold reset has not occurred since the last read of this register.
+ 1 = The software cold reset has occurred since the last read of this register. */
+ unsigned char wdt_off : 1; /**< Watchdog Timer OFF Flag. Bit 6.
+ This bit sets when the watchdog timer expires and causes a power-off.
+ 0 = Watchdog timer has not caused a power-off since the last time this bit was read.
+ 1 = Watchdog timer has expired and caused a power-off since the last time this bit was read. */
+ unsigned char wdt_rst : 1; /**< Watchdog Timer Reset Flag. Bit 7.
+ This bit sets when the watchdog timer expires and causes a power-reset.
+ 0 = Watchdog timer has not caused a power-reset since the last time this bit was read.
+ 1 = Watchdog timer has expired and caused a power-reset since the last time this bit was read.*/
+ } bits;
+} reg_ercflag_t;
+
+/**
+ * @brief STAT_GLBL Register
+ *
+ * Address : 0x06
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0.
+ 0 = unmasked gate drive is logic low
+ 1 = unmasked gate drive is logic high */
+ unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1.
+ 0 = nEN is not active (logic high)
+ 1 = nEN is active (logic low) */
+ unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2.
+ 0 = The junction temperature is less than TJAL1
+ 1 = The junction temperature is greater than TJAL1 */
+ unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3.
+ 0 = The junction temperature is less than TJAL2
+ 1 = The junction temperature is greater than TJAL2 */
+ unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. */
+ unsigned char dod_s : 1; /**< LDO0 Dropout Detector Rising Status. Bit 5.
+ 0 = LDO0 is not in dropout
+ 1 = LDO0 is in dropout */
+ unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6.
+ 0 = Main Bias is not ready.
+ 1 = Main Bias enabled and ready. */
+ unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7.
+ 0 = MAX77659
+ 1 = Reserved */
+ } bits;
+} reg_stat_glbl_t;
+
+/**
+ * @brief INTM_GLBL1 Register
+ *
+ * Address : 0x08
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0.
+ 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to GPI_F. */
+ unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1.
+ 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to GPI_R. */
+ unsigned char rsvd1 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3:2. */
+ unsigned char sbb_to_m : 1; /**< SBB Timeout Mask. Bit 4.
+ 0 = Unmasked. If SBB_TO goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to SBB_TO */
+ unsigned char ldo_m : 1; /**< LDO0 Fault Interrupt. Bit 5.
+ 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to LDO0_F. */
+ unsigned char rsvd2 : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
+ } bits;
+} reg_intm_glbl1_t;
+
+/**
+ * @brief INTM_GLBL0 Register
+ *
+ * Address : 0x09
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0.
+ 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to GPI_F. */
+ unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1.
+ 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to GPI_R. */
+ unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2.
+ 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to nEN_F. */
+ unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3.
+ 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to nEN_R. */
+ unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4.
+ 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to TJAL1_R. */
+ unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5.
+ 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to TJAL2_R. */
+ unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 6. */
+ unsigned char dod_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 7.
+ 0 = Unmasked. If DOD0_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to DOD0_R. */
+ } bits;
+} reg_intm_glbl0_t;
+
+/**
+ * @brief CNFG_GLBL Register
+ *
+ * Address : 0x10
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0.
+ 0b00 = No Action
+ 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again.
+ 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event.
+ 0b11 = Factory-Ship Mode Enter (FSM). */
+ unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2.
+ 0 = 500μs Debounce
+ 1 = 30ms Debounce */
+ unsigned char nen_mode : 1; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 3.
+ 0 = Push-Button Mode
+ 1 = Slide-Switch Mode */
+ unsigned char sbia_en : 1; /**< Main Bias Enable Software Request. Bit 4.
+ 0 = Main Bias not enabled by software.
+ Note that the main bias may be on via the on/off controller.
+ 1 = Main Bias force enabled by software. */
+ unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5.
+ 0 = Main Bias requested to be in Normal-Power Mode by software.
+ 1 = Main Bias request to be in Low-Power Mode by software. */
+ unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6.
+ 0 = 8s
+ 1 = 3.3s */
+ unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7.
+ 0 = Strong internal nEN pullup (200kΩ)
+ 1 = Weak internal nEN pullup (10MΩ) */
+ } bits;
+} reg_cnfg_glbl_t;
+
+/**
+ * @brief CNFG_GPIO0 Register
+ *
+ * Address : 0x11
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0.
+ 0 = General purpose output (GPO)
+ 1 = General purpose input (GPI) */
+ unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1.
+ 0 = Input logic low
+ 1 = Input logic high */
+ unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2.
+ This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0):
+ 0 = Open-Drain
+ 1 = Push-Pull */
+ unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3.
+ This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0):
+ 0 = GPIO is output is logic low
+ 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */
+ unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4.
+ 0 = no debounce
+ 1 = 30ms debounce */
+ unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO0. Bit 5.
+ 0 = Standard GPIO.
+ 1 = Active-high input, enable control for low-power mode. */
+ unsigned char : 1; /**< Bit 6. */
+ unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_cnfg_gpio0_t;
+
+/**
+ * @brief CNFG_GPIO1 Register
+ *
+ * Address : 0x12
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0.
+ 0 = General purpose output (GPO)
+ 1 = General purpose input (GPI) */
+ unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1.
+ 0 = Input logic low
+ 1 = Input logic high */
+ unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2.
+ This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0):
+ 0 = Open-Drain
+ 1 = Push-Pull */
+ unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3.
+ This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0):
+ 0 = GPIO is output is logic low
+ 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */
+ unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4.
+ 0 = no debounce
+ 1 = 30ms debounce */
+ unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO1. Bit 5.
+ 0 = Standard GPIO.
+ 1 = Active-high input, enable control for the DVS feature for SBB0. */
+ unsigned char rsvd : 2; /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_cnfg_gpio1_t;
+
+/**
+ * @brief CID Register
+ *
+ * Address : 0x14
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char cid_3_0 : 4; /**< Bits 0 to 3 of the Chip Identification Code. Bit 3:0.
+ The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */
+ unsigned char : 3; /**< Bit 6:4. */
+ unsigned char cid_7 : 1; /**< Bit 4 of the Chip Identification Code. Bit 7.
+ The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */
+ } bits;
+} reg_cid_t;
+
+/**
+ * @brief CNFG_WDT Register
+ *
+ * Address : 0x17
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0.
+ 0 = Watchdog timer can be enabled and disabled with WDT_EN.
+ 1 = Watchdog timer can not be disabled with WDT_EN.
+ However, WDT_EN can still be used to enable the watchdog timer. */
+ unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1.
+ 0 = Watchdog timer is not enabled.
+ 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */
+ unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2.
+ 0 = Watchdog timer period is not reset.
+ 1 = Watchdog timer is reset back to tWD. */
+ unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3.
+ 0 = Watchdog timer expire causes power-off.
+ 1 = Watchdog timer expire causes power-reset. */
+ unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4.
+ 0b00 = 16 seconds 0b01 = 32 seconds
+ 0b10 = 64 seconds 0b11 = 128 seconds. */
+ unsigned char rsvd : 2; /**< Reserved. Bit 7:6.
+ Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_cnfg_wdt_t;
+
+/**
+ * @brief INT_CHG Register
+ *
+ * Address : 0x01
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char thm_i : 1; /**< Thermistor related interrupt. Bit 0.
+ 0 = The bits in THM_DTLS[2:0] have not changed since the last time this bit was read
+ 1 = The bits in THM_DTLS[2:0] have changed since the last time this bit was read */
+ unsigned char chg_i : 1; /**< Charger related interrupt. Bit 1.
+ 0 = The bits in CHG_DTLS[3:0] have not changed since the last time this bit was read
+ 1 = The bits in CHG_DTLS[3:0] have changed since the last time this bit was read */
+ unsigned char chgin_i : 1; /**< CHGIN related interrupt. Bit 2.
+ 0 = The bits in CHGIN_DTLS[1:0] have not changed since the last time this bit was read
+ 1 = The bits in CHGIN_DTLS[1:0] have changed since the last time this bit was read */
+ unsigned char tj_reg_i : 1; /**< Die junction temperature regulation interrupt. Bit 3.
+ 0 = The die temperature has not exceeded TJ-REG since the last time this bit was read
+ 1 = The die temperature has exceeded TJ-REG since the last time this bit was read */
+ unsigned char sys_ctrl_i : 1; /**< Minimum System Voltage Regulation-loop related interrupt. Bit 4.
+ 0 = The minimum system voltage regulation loop has not engaged since the last time this bit was read
+ 1 = The minimum system voltage regulation loop has engaged since the last time this bit was read */
+ unsigned char rsvd : 1; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_int_chg_t;
+
+/**
+ * @brief STAT_CHG_A
+ *
+ * Address : 0x02
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char thm_dtls : 3; /**< Battery Temperature Details. Bit 2:0.
+ 0b000 = Thermistor is disabled (THM_EN = 0)
+ 0b001 = Battery is cold as programmed by THM_COLD[1:0] If thermistor and charger are enabled while the battery is cold, a battery temperature fault will occur.
+ 0b010 = Battery is cool as programmed by THM_COOL[1:0]
+ 0b011 = Battery is warm as programmed by THM_WARM[1:0]
+ 0b100 = Battery is hot as programmed by THM_HOT[1:0]. If thermistor and charger are enabled while the battery is hot, a battery temperature fault will occur.
+ 0b101 = Battery is in the normal temperature region
+ 0b110 - 0b111 = reserved */
+ unsigned char tj_reg_stat : 1; /**< Maximum Junction Temperature Regulation Loop Status. Bit 3.
+ 0 = The maximum junction temperature regulation loop is not engaged
+ 1 = The maximum junction temperature regulation loop has engaged to regulate the junction temperature to less than TJ-REG */
+ unsigned char vsys_min_stat : 1; /**< Minimum System Voltage Regulation Loop Status. Bit 4.
+ 0 = The minimum system voltage regulation loop is not enganged
+ 1 = The minimum system voltage regulation loop is engaged to regulate VSYS ≥ VSYS-MIN */
+ unsigned char rsvd : 3; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_stat_chg_a_t;
+
+/**
+ * @brief STAT_CHG_B
+ *
+ * Address : 0x03
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char time_sus : 1; /**< Time Suspend Indicator. Bit 0.
+ 0 = The charger's timers are either not active, or not suspended
+ 1 = The charger's active timer is suspended due to one of three reasons:
+ charge current dropped below 20% of IFAST-CHG while the charger state machine is in FAST CHARGE CC mode,
+ the charger is in SUPPLEMENT mode, or the charger state machine is in BATTERY TEMPERATURE FAULT mode. */
+ unsigned char chg : 1; /**< Quick Charger Status. Bit 1.
+ 0 = Charging is not happening
+ 1 = Charging is happening */
+ unsigned char chgin_dtls : 2; /**< CHGIN Status Detail. Bit 3:2.
+ 0b00 = The CHGIN input voltage is below the UVLO threshold (VCHGIN < VUVLO)
+ 0b01 = The CHGIN input voltage is above the OVP threshold (VCHGIN > VOVP)
+ 0b10 = The CHGIN input is being debounced (no power accepted from CHGIN during debounce)
+ 0b11 = The CHGIN input is okay and debounced */
+ unsigned char chg_dtls : 4; /**< Charger Details. Bit 7:4.
+ 0b0000 = Off
+ 0b0001 = Prequalification mode
+ 0b0010 = Fast-charge constant-current (CC) mode
+ 0b0011 = JEITA modified fast-charge constant-current mode
+ 0b0100 = Fast-charge constant-voltage (CV) mode
+ 0b0101 = JEITA modified fast-charge constant-voltage mode
+ 0b0110 = Top-off mode
+ 0b0111 = JEITA modified top-off mode
+ 0b1000 = Done
+ 0b1001 = JEITA modified done (done was entered through the JEITA-modified fast-charge states)
+ 0b1010 = Prequalification timer fault
+ 0b1011 = Fast-charge timer fault
+ 0b1100 = Battery temperature fault
+ 0b1101 - 0b1111 = reserved */
+ } bits;
+} reg_stat_chg_b_t;
+
+/**
+ * @brief INT_M_CHG Register
+ *
+ * Address : 0x07
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char thm_m : 1; /**< Setting this bit prevents the THM_I bit from causing hardware IRQs. Bit 0.
+ 0 = THM_I is not masked
+ 1 = THM_I is masked */
+ unsigned char chg_m : 1; /**< Setting this bit prevents the CHG_I bit from causing hardware IRQs. Bit 1.
+ 0 = CHG_I is not masked
+ 1 = CHG_I is masked */
+ unsigned char chgin_m : 1; /**< Setting this bit prevents the CHGIN_I bit from causing hardware IRQs. Bit 2.
+ 0 = CHGIN_I is not masked
+ 1 = CHGIN_I is masked */
+ unsigned char tj_reg_m : 1; /**< Setting this bit prevents the TJREG_I bit from causing hardware IRQs. Bit 3.
+ 0 = TJREG_I is not masked
+ 1 = TJREG_I is masked */
+ unsigned char sys_ctrl_m : 1; /**< Setting this bit prevents the SYS_CTRL_I bit from causing hardware IRQs. Bit 4.
+ 0 = SYS_CTRL_I is not masked
+ 1 = SYS_CTRL_I is masked */
+ unsigned char rsvd : 3; /**< Reserved. Bit 7:5. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_int_m_chg_t;
+
+/**
+ * @brief CNFG_CHG_A
+ *
+ * Address : 0x20
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char thm_cold : 2; /**< Sets the VCOLD JEITA Temperature Threshold. Bit 1:0.
+ 0b00 = VCOLD = 1.024V (-10ºC for β = 3380K)
+ 0b01 = VCOLD = 0.976V (-5ºC for β = 3380K)
+ 0b10 = VCOLD = 0.923V (0ºC for β = 3380K)
+ 0b11 = VCOLD = 0.867V (5ºC for β = 3380K) */
+ unsigned char thm_cool : 2; /**< Sets the VCOOL JEITA Temperature Threshold. Bit 3:2.
+ 0b00 = VCOOL = 0.923V (0ºC for β = 3380K)
+ 0b01 = VCOOL = 0.867V (5ºC for β = 3380K)
+ 0b10 = VCOOL = 0.807V (10ºC for β = 3380K)
+ 0b11 = VCOOL = 0.747V (15ºC for β = 3380K) */
+ unsigned char thm_warm : 2; /**< Sets the VWARM JEITA Temperature Threshold. Bit 5:4.
+ 0b00 = VWARM = 0.511V (35ºC for β = 3380K)
+ 0b01 = VWARM = 0.459V (40ºC for β = 3380K)
+ 0b10 = VWARM = 0.411V (45ºC for β = 3380K)
+ 0b11 = VWARM = 0.367V (50ºC for β = 3380K) */
+ unsigned char thm_hot : 2; /**< Sets the VHOT JEITA Temperature Threshold. Bit 7:6.
+ 0b00 = VHOT = 0.411V (45ºC for β = 3380K)
+ 0b01 = VHOT = 0.367V (50ºC for β = 3380K)
+ 0b10 = VHOT = 0.327V (55ºC for β = 3380K)
+ 0b11 = VHOT = 0.291V (60ºC for β = 3380K) */
+ } bits;
+} reg_cnfg_chg_a_t;
+
+/**
+ * @brief CNFG_CHG_B
+ *
+ * Address : 0x21
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char chg_en : 1; /**< Charger Enable. Bit 0.
+ 0 = the battery charger is disabled
+ 1 = the battery charger is enabled */
+ unsigned char i_pq : 1; /**< Sets the prequalification charge current (IPQ) as a percentage of IFAST-CHG. Bit 1.
+ 0 = 10% 1 = 20% */
+ unsigned char rsvd : 6; /**< Reserved. Bit 7:2. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_cnfg_chg_b_t;
+
+/**
+ * @brief CNFG_CHG_C
+ *
+ * Address : 0x22
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char t_topoff : 3; /**< Top-off timer value (tTO). Bit 2:0.
+ 0b000 = 0 minutes 0b001 = 5 minutes
+ 0b010 = 10 minutes 0b011 = 15 minutes
+ 0b100 = 20 minutes 0b101 = 25 minutes
+ 0b110 = 30 minutes 0b111 = 35 minutes */
+ unsigned char i_term : 2; /**< Charger Termination Current (ITERM). Bit 4:3.
+ 00 = 5% 01 = 7.5%
+ 10 = 10% 11 = 15% */
+ unsigned char chg_pq : 3; /**< Battery prequalification voltage threshold (VPQ). Bit 7:5.
+ 0b000 = 2.3V 0b001 = 2.4V
+ 0b010 = 2.5V 0b011 = 2.6V
+ 0b100 = 2.7V 0b101 = 2.8V
+ 0b110 = 2.9V 0b111 = 3.0V */
+ } bits;
+} reg_cnfg_chg_c_t;
+
+/**
+ * @brief CNFG_CHG_D
+ *
+ * Address : 0x23
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char vsys_min : 2; /**< Minimum SYS Voltage . Bit 1:0.
+ 0x0 = 3.2V 0x1 = 3.3V
+ 0x2 = 3.4V 0x3 = 3.5V */
+ unsigned char rsvd : 2; /**< Reserved. Bit 3:2. Unutilized bit. Write to 0. Reads are don't care. */
+ unsigned char vsys_hdrm : 1; /**< SYS Headroom Voltage Regulation. Bit 4.
+ 0b0 = 0.15V 0b1 = 0.20V */
+ unsigned char tj_reg : 3; /**< Sets the die junction temperature regulation point, TJ-REG. Bit 7:5.
+ 0b000 = 60ºC 0b001 = 70ºC
+ 0b010 = 80ºC 0b011 = 90ºC
+ 0b100 - 0b111 = 100ºC */
+ } bits;
+} reg_cnfg_chg_d_t;
+
+/**
+ * @brief CNFG_CHG_E
+ *
+ * Address : 0x25
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char t_fast_chg : 2; /**< System voltage regulation (VSYS-REG). Bit 1:0.
+ 0b00 = timer disabled 0b01 = 3 hours
+ 0b10 = 5 hours 0b11 = 7 hours */
+ unsigned char chg_cc : 6; /**< Sets the fast-charge constant current value, IFAST-CHG. Bit 7:2.
+ 0x0 = 7.5mA 0x1 = 15.0mA
+ 0x2 = 22.5mA ...
+ 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */
+ } bits;
+} reg_cnfg_chg_e_t;
+
+/**
+ * @brief CNFG_CHG_F
+ *
+ * Address : 0x25
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char : 1; /**< Bit 0*/
+ unsigned char thm_en : 1; /**< Thermistor enable bit. Bit 1.
+ 0 = Thermistor is disabled
+ 1 = Thermistor is enabled */
+ unsigned char chg_cc_jeita : 6; /**< Sets IFAST-CHG-JEITA for when the battery is either cool or warm as defined
+ by the VCOOL and VWARM temperature thresholds. Bit 7:2.
+ 0x0 = 7.5mA 0x1 = 15.0mA
+ 0x2 = 22.5mA ...
+ 0x26 = 292.5mA 0x27 - 0x3F = 300.0mA */
+ } bits;
+} reg_cnfg_chg_f_t;
+
+/**
+ * @brief CNFG_CHG_G
+ *
+ * Address : 0x26
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char rsvd : 1; /**< Reserved. Bit 0. Unutilized bit. Write to 0. Reads are don't care.*/
+ unsigned char usbs : 1; /**< Setting this bit places CHGIN in USB suspend mode. Bit 1.
+ 0 = CHGIN is not suspended and may draw current from an adapter source
+ 1 = CHGIN is suspended and may draw no current from an adapter source */
+ unsigned char chg_cv : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2.
+ 0x0 = 3.600V 0x1 = 3.625V
+ 0x2 = 3.650V ...
+ 0x27 = 4.575V 0x28 - 0x3F = 4.600V */
+} bits;
+} reg_cnfg_chg_g_t;
+
+/**
+ * @brief CNFG_CHG_H
+ *
+ * Address : 0x27
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char rsvd : 2; /**< Reserved. Bit 1:0. Unutilized bit. Write to 0. Reads are don't care.*/
+ unsigned char chg_cv_jeita : 6; /**< Sets fast-charge battery regulation voltage, VFAST-CHG. Bit 7:2.
+ 0x0 = 3.600V 0x1 = 3.625V
+ 0x2 = 3.650V ...
+ 0x27 = 4.575V 0x28 - 0x3F = 4.600V */
+ } bits;
+} reg_cnfg_chg_h_t;
+
+/**
+ * @brief CNFG_CHG_I
+ *
+ * Address : 0x28
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char mux_sel : 4; /**< Selects the analog channel to connect to AMUX. Bit 3:0.
+ 0b0000 = Multiplexer is disabled and AMUX is high-impedance.
+ 0b0001 = CHGIN voltage monitor.
+ 0b0010 = CHGIN current monitor.
+ 0b0011 = BATT voltage monitor.
+ 0b0100 = BATT charge current monitor. Valid only while battery charging is happening (CHG = 1).
+ 0b0101 = BATT discharge current monitor normal measurement.
+ 0b0110 = BATT discharge current monitor nulling measurement.
+ 0b0111 = THM voltage monitor 0b1000 = TBIAS voltage monitor
+ 0b1001 = AGND voltage monitor (through 100Ω pull-down resistor)
+ 0b1010 - 0b1111 = SYS voltage monitor */
+ unsigned char imon_dischg_scale : 4; /**< Selects the battery discharge current full-scale current value. Bit 7:4.
+ 0x0 = 8.2mA 0x1 = 40.5mA 0x2 = 72.3mA
+ 0x3 = 103.4mA 0x4 = 134.1mA
+ 0x5 = 164.1mA 0x6 = 193.7mA
+ 0x7 = 222.7mA 0x8 = 251.2mA
+ 0x9 = 279.3mA 0xA - 0xF = 300.0mA */
+ } bits;
+} reg_cnfg_chg_i_t;
+
+/**
+ * @brief CNFG_SBB0_A
+ *
+ * Address : 0x29
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb0 : 7; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 6:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V
+ ...
+ 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V
+ ...
+ 0x7B = 5.450V 0x7C = 5.500V
+ 0x7D to 0x7F = Reserved */
+ unsigned char : 1; /**< Bit 7. */
+ } bits;
+} reg_cnfg_sbb0_a_t;
+
+/**
+ * @brief CNFG_SBB0_B
+ *
+ * Address : 0x2A
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char : 2; /**< Bit 5:4*/
+ unsigned char op_mode : 1; /**< Operation mode of SBB0. Bit 6.
+ 0 = Buck-Boost Mode
+ 1 = Buck Mode*/
+ unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/
+ } bits;
+} reg_cnfg_sbb0_b_t;
+
+/**
+ * @brief CNFG_SBB1_A
+ *
+ * Address : 0x2B
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb1 : 7; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 6:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V
+ ...
+ 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V
+ ...
+ 0x7B = 5.450V 0x7C = 5.500V
+ 0x7D to 0x7F = Reserved */
+ unsigned char : 1; /**< Bit 7. */
+ } bits;
+} reg_cnfg_sbb1_a_t;
+
+/**
+ * @brief CNFG_SBB1_B
+ *
+ * Address : 0x2C
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char : 2; /**< Bit 5:4.*/
+ unsigned char op_mode : 1; /**< Operation mode of SBB1. Bit 6.
+ 0 = Buck-Boost Mode
+ 1 = Buck Mode*/
+ unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/
+ } bits;
+} reg_cnfg_sbb1_b_t;
+
+/**
+ * @brief CNFG_SBB2_A
+ *
+ * Address : 0x2D
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb2 : 7; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 6:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V
+ ...
+ 0x30 = 1.700V 0x31 = 1.750V 0x32 = 1.800V
+ ...
+ 0x7B = 5.450V 0x7C = 5.500V
+ 0x7D to 0x7F = Reserved */
+ unsigned char : 1; /**< Bit 7. */
+ } bits;
+} reg_cnfg_sbb2_a_t;
+
+/**
+ * @brief CNFG_SBB2_B
+ *
+ * Address : 0x2E
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char : 2; /**< Bit 5:4. */
+ unsigned char op_mode : 1; /**< Operation mode of SBB2. Bit 6.
+ 0 = Buck-Boost Mode
+ 1 = Buck Mode*/
+ unsigned char rsvd : 1; /**< Reserved. Bit 7. Unutilized bit. Write to 0. Reads are don't care.*/
+ } bits;
+} reg_cnfg_sbb2_b_t;
+
+/**
+ * @brief CNFG_SBB_TOP
+ *
+ * Address : 0x2F
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0.
+ 0b00 = fastest transition time
+ 0b01 = a little slower than 0b00
+ 0b10 = a little slower than 0b01
+ 0b11 = a little slower than 0b10 */
+ unsigned char : 5; /**< Bit 6:2. */
+ unsigned char op_mode_chg : 1; /**< Operation mode of the charging channel of SIMO. Bit 7.
+ 0 = Buck-boost mode
+ 1 = Buck mode */
+ } bits;
+} reg_cnfg_sbb_top_t;
+
+/**
+ * @brief CNFG_SBB_TOP_B
+ *
+ * Address : 0x30
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 1:0.
+ 0b00 = 1.000A
+ 0b01 = 0.750A
+ 0b10 = 0.500A
+ 0b11 = 0.333A */
+ unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 3:2.
+ 0b00 = 1.000A
+ 0b01 = 0.750A
+ 0b10 = 0.500A
+ 0b11 = 0.333A */
+ unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4.
+ 0b00 = 1.000A
+ 0b01 = 0.750A
+ 0b10 = 0.500A
+ 0b11 = 0.333A */
+ unsigned char ip_chg : 2; /**< SIMO Buck-Boost Charging Channel Peak Current Limit. Bit 7:6.
+ 0b00 = 2.000A
+ 0b01 = 1.500A
+ 0b10 = 1.000A
+ 0b11 = 0.500A */
+ } bits;
+} reg_cnfg_sbb_top_b_t;
+
+/**
+ * @brief CNFG_LDO0_A
+ *
+ * Address : 0x38
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_ldo_volt : 7; /**< LDO Target Output Voltage This 7-bit configuration is a linear transfer function
+ that starts at 0.5V and ends at 3.675V, with 25mV increments. Bit 6:0.
+ 0x00 = 0.500V 0x01 = 0.525V
+ 0x02 = 0.550V 0x03 = 0.575V
+ 0x04 = 0.600V 0x05 = 0.625V
+ 0x06 = 0.650V ...
+ 0x7D = 3.625V 0x7E = 3.650V
+ 0x7F = 3.675V */
+ unsigned char tv_ldo_offset : 1; /**< LDO Output Voltage. This bit applies a 1.325V offset to the output voltage of the LDO. Bit 7.
+ 0b0 = No offset 0b1 = 1.325V offset*/
+ } bits;
+} reg_cnfg_ldo0_a_t;
+
+/**
+ * @brief CNFG_LDO0_B
+ *
+ * Address : 0x39
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_ldo : 3; /**< Enable Control for LDO0, selecting either an FPS slot the channel powers-up and
+ powers-down in or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100
+ 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_ldo : 1; /**< LDO0 Active-Discharge Enable. Bit 3.
+ 0 = The active discharge function is disabled.
+ 1 = The active discharge function is enabled. */
+ unsigned char ldo_md : 1; /**< Operation mode of LDO0. Bit 4.
+ 0 = Low Dropout Linear Regulator (LDO) Mode
+ 1 = Load Switch (LSW) Mode */
+ unsigned char rsvd : 3; /**< Bit 7:5. Reserved. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_cnfg_ldo0_b_t;
+
+#endif /* MAX77659_REGS_H_ */