Maxim Integrated
MAX77655 Low IQ SIMO PMIC with 4-Outputs Delivering up to 700mA Total Output Current Mbed Driver
MAX77655.h@0:08f763822dd3, 2022-08-23 (annotated)
- Committer:
- Okan Sahin
- Date:
- Tue Aug 23 18:11:21 2022 +0300
- Revision:
- 0:08f763822dd3
Initial Commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Okan Sahin |
0:08f763822dd3 | 1 | /******************************************************************************* |
| Okan Sahin |
0:08f763822dd3 | 2 | * Copyright(C) Analog Devices Inc., All Rights Reserved. |
| Okan Sahin |
0:08f763822dd3 | 3 | * |
| Okan Sahin |
0:08f763822dd3 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Okan Sahin |
0:08f763822dd3 | 5 | * copy of this software and associated documentation files(the "Software"), |
| Okan Sahin |
0:08f763822dd3 | 6 | * to deal in the Software without restriction, including without limitation |
| Okan Sahin |
0:08f763822dd3 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Okan Sahin |
0:08f763822dd3 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Okan Sahin |
0:08f763822dd3 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Okan Sahin |
0:08f763822dd3 | 10 | * |
| Okan Sahin |
0:08f763822dd3 | 11 | * The above copyright notice and this permission notice shall be included |
| Okan Sahin |
0:08f763822dd3 | 12 | * in all copies or substantial portions of the Software. |
| Okan Sahin |
0:08f763822dd3 | 13 | * |
| Okan Sahin |
0:08f763822dd3 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Okan Sahin |
0:08f763822dd3 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Okan Sahin |
0:08f763822dd3 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Okan Sahin |
0:08f763822dd3 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Okan Sahin |
0:08f763822dd3 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Okan Sahin |
0:08f763822dd3 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Okan Sahin |
0:08f763822dd3 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Okan Sahin |
0:08f763822dd3 | 21 | * |
| Okan Sahin |
0:08f763822dd3 | 22 | * Except as contained in this notice, the name of Analog Devices Inc. |
| Okan Sahin |
0:08f763822dd3 | 23 | * shall not be used except as stated in the Analog Devices Inc. |
| Okan Sahin |
0:08f763822dd3 | 24 | * Branding Policy. |
| Okan Sahin |
0:08f763822dd3 | 25 | * |
| Okan Sahin |
0:08f763822dd3 | 26 | * The mere transfer of this software does not imply any licenses |
| Okan Sahin |
0:08f763822dd3 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Okan Sahin |
0:08f763822dd3 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Okan Sahin |
0:08f763822dd3 | 29 | * property whatsoever. Analog Devices Inc.retains all ownership rights. |
| Okan Sahin |
0:08f763822dd3 | 30 | ******************************************************************************* |
| Okan Sahin |
0:08f763822dd3 | 31 | */ |
| Okan Sahin |
0:08f763822dd3 | 32 | |
| Okan Sahin |
0:08f763822dd3 | 33 | #ifndef _MAX77655_H_ |
| Okan Sahin |
0:08f763822dd3 | 34 | #define _MAX77655_H_ |
| Okan Sahin |
0:08f763822dd3 | 35 | |
| Okan Sahin |
0:08f763822dd3 | 36 | #include "mbed.h" |
| Okan Sahin |
0:08f763822dd3 | 37 | #include "MAX77655_regs.h" |
| Okan Sahin |
0:08f763822dd3 | 38 | |
| Okan Sahin |
0:08f763822dd3 | 39 | #define MAX77655_NO_ERROR 0 |
| Okan Sahin |
0:08f763822dd3 | 40 | #define MAX77655_VALUE_NULL -1 |
| Okan Sahin |
0:08f763822dd3 | 41 | #define MAX77655_WRITE_DATA_FAILED -2 |
| Okan Sahin |
0:08f763822dd3 | 42 | #define MAX77655_READ_DATA_FAILED -3 |
| Okan Sahin |
0:08f763822dd3 | 43 | #define MAX77655_INVALID_DATA -4 |
| Okan Sahin |
0:08f763822dd3 | 44 | |
| Okan Sahin |
0:08f763822dd3 | 45 | #define MAX77655_I2C_ADDRESS 0x88 |
| Okan Sahin |
0:08f763822dd3 | 46 | |
| Okan Sahin |
0:08f763822dd3 | 47 | /** |
| Okan Sahin |
0:08f763822dd3 | 48 | * @brief MAX77655 Low IQ SIMO PMIC with 4-Outputs Delivering up to |
| Okan Sahin |
0:08f763822dd3 | 49 | * 700mA Total Output Current |
| Okan Sahin |
0:08f763822dd3 | 50 | * |
| Okan Sahin |
0:08f763822dd3 | 51 | * @details The MAX77655 is a highly efficient, complete power supply for low-power, ultra-compact applications. |
| Okan Sahin |
0:08f763822dd3 | 52 | * |
| Okan Sahin |
0:08f763822dd3 | 53 | * @code |
| Okan Sahin |
0:08f763822dd3 | 54 | * @endcode |
| Okan Sahin |
0:08f763822dd3 | 55 | */ |
| Okan Sahin |
0:08f763822dd3 | 56 | |
| Okan Sahin |
0:08f763822dd3 | 57 | class MAX77655 |
| Okan Sahin |
0:08f763822dd3 | 58 | { |
| Okan Sahin |
0:08f763822dd3 | 59 | private: |
| Okan Sahin |
0:08f763822dd3 | 60 | I2C *i2c_handler; |
| Okan Sahin |
0:08f763822dd3 | 61 | InterruptIn *irq_pin; // interrupt pin |
| Okan Sahin |
0:08f763822dd3 | 62 | |
| Okan Sahin |
0:08f763822dd3 | 63 | /** |
| Okan Sahin |
0:08f763822dd3 | 64 | * @brief Register Addresses |
| Okan Sahin |
0:08f763822dd3 | 65 | * @details Enumerated MAX77655 register addresses |
| Okan Sahin |
0:08f763822dd3 | 66 | */ |
| Okan Sahin |
0:08f763822dd3 | 67 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 68 | CNFG_GLBL_A = 0x00, // Configuration Global A |
| Okan Sahin |
0:08f763822dd3 | 69 | CNFG_GLBL_B = 0x01, // Configuration Global B |
| Okan Sahin |
0:08f763822dd3 | 70 | INT_GLBL = 0x02, // Interrupt Global Status |
| Okan Sahin |
0:08f763822dd3 | 71 | INTM_GLBL = 0x03, // Interrupt Mask |
| Okan Sahin |
0:08f763822dd3 | 72 | STAT_GLBL = 0x04, // Global Status |
| Okan Sahin |
0:08f763822dd3 | 73 | ERCFLAG = 0x05, // Flags |
| Okan Sahin |
0:08f763822dd3 | 74 | CID = 0x06, // Chip Identification Code |
| Okan Sahin |
0:08f763822dd3 | 75 | CONFIG_SBB_TOP = 0x07, // SIMO Buck-Boost Configuration |
| Okan Sahin |
0:08f763822dd3 | 76 | CNFG_SBB0_A = 0x08, // SIMO Buck-Boost 0 Configuration A |
| Okan Sahin |
0:08f763822dd3 | 77 | CNFG_SBB0_B = 0x09, // SIMO Buck-Boost 0 Configuration B |
| Okan Sahin |
0:08f763822dd3 | 78 | CNFG_SBB1_A = 0x0A, // SIMO Buck-Boost 1 Configuration A |
| Okan Sahin |
0:08f763822dd3 | 79 | CNFG_SBB1_B = 0x0B, // SIMO Buck-Boost 1 Configuration B |
| Okan Sahin |
0:08f763822dd3 | 80 | CNFG_SBB2_A = 0x0C, // SIMO Buck-Boost 2 Configuration A |
| Okan Sahin |
0:08f763822dd3 | 81 | CNFG_SBB2_B = 0x0D, // SIMO Buck-Boost 2 Configuration B |
| Okan Sahin |
0:08f763822dd3 | 82 | CNFG_SBB3_A = 0x0E, // SIMO Buck-Boost 3 Configuration A |
| Okan Sahin |
0:08f763822dd3 | 83 | CNFG_SBB3_B = 0x0F, // SIMO Buck-Boost 3 Configuration B |
| Okan Sahin |
0:08f763822dd3 | 84 | } reg_t; |
| Okan Sahin |
0:08f763822dd3 | 85 | |
| Okan Sahin |
0:08f763822dd3 | 86 | void interrupt_handler(); |
| Okan Sahin |
0:08f763822dd3 | 87 | |
| Okan Sahin |
0:08f763822dd3 | 88 | void (MAX77655::*funcptr)(void); |
| Okan Sahin |
0:08f763822dd3 | 89 | |
| Okan Sahin |
0:08f763822dd3 | 90 | void post_interrupt_work(); |
| Okan Sahin |
0:08f763822dd3 | 91 | |
| Okan Sahin |
0:08f763822dd3 | 92 | Thread *post_intr_work_thread; |
| Okan Sahin |
0:08f763822dd3 | 93 | |
| Okan Sahin |
0:08f763822dd3 | 94 | struct handler { |
| Okan Sahin |
0:08f763822dd3 | 95 | void (*func)(void *); |
| Okan Sahin |
0:08f763822dd3 | 96 | void *cb; |
| Okan Sahin |
0:08f763822dd3 | 97 | }; |
| Okan Sahin |
0:08f763822dd3 | 98 | |
| Okan Sahin |
0:08f763822dd3 | 99 | handler interrupt_handler_list[8]; |
| Okan Sahin |
0:08f763822dd3 | 100 | |
| Okan Sahin |
0:08f763822dd3 | 101 | public: |
| Okan Sahin |
0:08f763822dd3 | 102 | /** |
| Okan Sahin |
0:08f763822dd3 | 103 | * @brief MAX77655 constructor. |
| Okan Sahin |
0:08f763822dd3 | 104 | */ |
| Okan Sahin |
0:08f763822dd3 | 105 | MAX77655(I2C *i2c, PinName IRQPin = NC); |
| Okan Sahin |
0:08f763822dd3 | 106 | |
| Okan Sahin |
0:08f763822dd3 | 107 | /** |
| Okan Sahin |
0:08f763822dd3 | 108 | * @brief MAX77655 destructor. |
| Okan Sahin |
0:08f763822dd3 | 109 | */ |
| Okan Sahin |
0:08f763822dd3 | 110 | ~MAX77655(); |
| Okan Sahin |
0:08f763822dd3 | 111 | |
| Okan Sahin |
0:08f763822dd3 | 112 | /** |
| Okan Sahin |
0:08f763822dd3 | 113 | * @brief Function pointer type to interrupt handler function |
| Okan Sahin |
0:08f763822dd3 | 114 | */ |
| Okan Sahin |
0:08f763822dd3 | 115 | typedef void (*interrupt_handler_function)(void *); |
| Okan Sahin |
0:08f763822dd3 | 116 | |
| Okan Sahin |
0:08f763822dd3 | 117 | /** |
| Okan Sahin |
0:08f763822dd3 | 118 | * @brief Read from a register. |
| Okan Sahin |
0:08f763822dd3 | 119 | * |
| Okan Sahin |
0:08f763822dd3 | 120 | * @param[in] reg Address of a register to be written. |
| Okan Sahin |
0:08f763822dd3 | 121 | * @param[out] value Pointer to save result value. |
| Okan Sahin |
0:08f763822dd3 | 122 | * |
| Okan Sahin |
0:08f763822dd3 | 123 | * @returns 0 on success, negative error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 124 | */ |
| Okan Sahin |
0:08f763822dd3 | 125 | int read_register(uint8_t reg, uint8_t *value); |
| Okan Sahin |
0:08f763822dd3 | 126 | |
| Okan Sahin |
0:08f763822dd3 | 127 | /** |
| Okan Sahin |
0:08f763822dd3 | 128 | * @brief Write to a register. |
| Okan Sahin |
0:08f763822dd3 | 129 | * |
| Okan Sahin |
0:08f763822dd3 | 130 | * @param[in] reg Address of a register to be written. |
| Okan Sahin |
0:08f763822dd3 | 131 | * @param[out] value Pointer of value to be written to register. |
| Okan Sahin |
0:08f763822dd3 | 132 | * |
| Okan Sahin |
0:08f763822dd3 | 133 | * @returns 0 on success, negative error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 134 | */ |
| Okan Sahin |
0:08f763822dd3 | 135 | int write_register(uint8_t reg, const uint8_t *value); |
| Okan Sahin |
0:08f763822dd3 | 136 | |
| Okan Sahin |
0:08f763822dd3 | 137 | /** |
| Okan Sahin |
0:08f763822dd3 | 138 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 139 | * |
| Okan Sahin |
0:08f763822dd3 | 140 | * @details |
| Okan Sahin |
0:08f763822dd3 | 141 | * - Register : CNFG_GLBL_A (0x00) |
| Okan Sahin |
0:08f763822dd3 | 142 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:08f763822dd3 | 143 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 144 | * - Description : Event Recorder Flags. |
| Okan Sahin |
0:08f763822dd3 | 145 | */ |
| Okan Sahin |
0:08f763822dd3 | 146 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 147 | CNFG_GLBL_A_DBEN_nEN, |
| Okan Sahin |
0:08f763822dd3 | 148 | CNFG_GLBL_A_nEN_MODE, |
| Okan Sahin |
0:08f763822dd3 | 149 | CNFG_GLBL_A_MRT, |
| Okan Sahin |
0:08f763822dd3 | 150 | CNFG_GLBL_A_BIAS_LPM, |
| Okan Sahin |
0:08f763822dd3 | 151 | CNFG_GLBL_A_PU_DIS, |
| Okan Sahin |
0:08f763822dd3 | 152 | CNFG_GLBL_A_RSVD |
| Okan Sahin |
0:08f763822dd3 | 153 | }reg_bit_cnfg_glbl_a_t; |
| Okan Sahin |
0:08f763822dd3 | 154 | |
| Okan Sahin |
0:08f763822dd3 | 155 | /** |
| Okan Sahin |
0:08f763822dd3 | 156 | * @brief Set CNFG_GLBL_A (0x00) register. |
| Okan Sahin |
0:08f763822dd3 | 157 | * |
| Okan Sahin |
0:08f763822dd3 | 158 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 159 | * @param[in] config Configuration bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 160 | * |
| Okan Sahin |
0:08f763822dd3 | 161 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 162 | */ |
| Okan Sahin |
0:08f763822dd3 | 163 | int set_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t config); |
| Okan Sahin |
0:08f763822dd3 | 164 | |
| Okan Sahin |
0:08f763822dd3 | 165 | /** |
| Okan Sahin |
0:08f763822dd3 | 166 | * @brief Get CNFG_GLBL_A (0x00) register. |
| Okan Sahin |
0:08f763822dd3 | 167 | * |
| Okan Sahin |
0:08f763822dd3 | 168 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 169 | * @param[out] config Pointer of value to be read. |
| Okan Sahin |
0:08f763822dd3 | 170 | * |
| Okan Sahin |
0:08f763822dd3 | 171 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 172 | */ |
| Okan Sahin |
0:08f763822dd3 | 173 | int get_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t *config); |
| Okan Sahin |
0:08f763822dd3 | 174 | |
| Okan Sahin |
0:08f763822dd3 | 175 | /** |
| Okan Sahin |
0:08f763822dd3 | 176 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 177 | * |
| Okan Sahin |
0:08f763822dd3 | 178 | * @details |
| Okan Sahin |
0:08f763822dd3 | 179 | * - Register : CNFG_GLBL_B (0x01) |
| Okan Sahin |
0:08f763822dd3 | 180 | * - Bit Fields : [2:0] |
| Okan Sahin |
0:08f763822dd3 | 181 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 182 | * - Description : Software Control Functions |
| Okan Sahin |
0:08f763822dd3 | 183 | */ |
| Okan Sahin |
0:08f763822dd3 | 184 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 185 | SFT_CTRL_NO_ACTION, |
| Okan Sahin |
0:08f763822dd3 | 186 | SFT_CTRL_SOFTWARE_COLD_RESET, |
| Okan Sahin |
0:08f763822dd3 | 187 | SFT_CTRL_SOFTWARE_OFF, |
| Okan Sahin |
0:08f763822dd3 | 188 | SFT_CTRL_SOFTWARE_STANDBY, |
| Okan Sahin |
0:08f763822dd3 | 189 | SFT_CTRL_RESERVED |
| Okan Sahin |
0:08f763822dd3 | 190 | }decode_sft_ctrl_t; |
| Okan Sahin |
0:08f763822dd3 | 191 | |
| Okan Sahin |
0:08f763822dd3 | 192 | /** |
| Okan Sahin |
0:08f763822dd3 | 193 | * @brief Set CNFG_GLBL_B (0x01) register. |
| Okan Sahin |
0:08f763822dd3 | 194 | * |
| Okan Sahin |
0:08f763822dd3 | 195 | * @param[in] config Register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 196 | * |
| Okan Sahin |
0:08f763822dd3 | 197 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 198 | */ |
| Okan Sahin |
0:08f763822dd3 | 199 | int set_sft_ctrl(decode_sft_ctrl_t config); |
| Okan Sahin |
0:08f763822dd3 | 200 | |
| Okan Sahin |
0:08f763822dd3 | 201 | /** |
| Okan Sahin |
0:08f763822dd3 | 202 | * @brief Get CNFG_GLBL_B (0x01) register. |
| Okan Sahin |
0:08f763822dd3 | 203 | * |
| Okan Sahin |
0:08f763822dd3 | 204 | * @param[in] config Register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 205 | * |
| Okan Sahin |
0:08f763822dd3 | 206 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 207 | */ |
| Okan Sahin |
0:08f763822dd3 | 208 | int get_sft_ctrl(decode_sft_ctrl_t *config); |
| Okan Sahin |
0:08f763822dd3 | 209 | |
| Okan Sahin |
0:08f763822dd3 | 210 | /** |
| Okan Sahin |
0:08f763822dd3 | 211 | * @brief Register Configuration. |
| Okan Sahin |
0:08f763822dd3 | 212 | * All Interrupt Flags combined from INT_GLBL0 (0x02) |
| Okan Sahin |
0:08f763822dd3 | 213 | * |
| Okan Sahin |
0:08f763822dd3 | 214 | * @details |
| Okan Sahin |
0:08f763822dd3 | 215 | * - Register : INT_GLBL (0x02) |
| Okan Sahin |
0:08f763822dd3 | 216 | * - Bit Fields : |
| Okan Sahin |
0:08f763822dd3 | 217 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 218 | * - Description : Enumerated interrupts. |
| Okan Sahin |
0:08f763822dd3 | 219 | */ |
| Okan Sahin |
0:08f763822dd3 | 220 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 221 | INT_GLBL_nEN_F, |
| Okan Sahin |
0:08f763822dd3 | 222 | INT_GLBL_nEN_R, |
| Okan Sahin |
0:08f763822dd3 | 223 | INT_GLBL_TJAL1_R, |
| Okan Sahin |
0:08f763822dd3 | 224 | INT_GLBL_TJAL2_R, |
| Okan Sahin |
0:08f763822dd3 | 225 | INT_GLBL_SBB0_FM, |
| Okan Sahin |
0:08f763822dd3 | 226 | INT_GLBL_SBB1_FM, |
| Okan Sahin |
0:08f763822dd3 | 227 | INT_GLBL_SBB2_FM, |
| Okan Sahin |
0:08f763822dd3 | 228 | INT_GLBL_SBB3_FM |
| Okan Sahin |
0:08f763822dd3 | 229 | } reg_bit_int_glbl_t; |
| Okan Sahin |
0:08f763822dd3 | 230 | |
| Okan Sahin |
0:08f763822dd3 | 231 | /** |
| Okan Sahin |
0:08f763822dd3 | 232 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 233 | * |
| Okan Sahin |
0:08f763822dd3 | 234 | * @details |
| Okan Sahin |
0:08f763822dd3 | 235 | * - Register : INTM_GLBL (0x03) |
| Okan Sahin |
0:08f763822dd3 | 236 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:08f763822dd3 | 237 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 238 | * - Description : All interrupt mask bits. |
| Okan Sahin |
0:08f763822dd3 | 239 | */ |
| Okan Sahin |
0:08f763822dd3 | 240 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 241 | INTM_GLBL_nEN_FM, |
| Okan Sahin |
0:08f763822dd3 | 242 | INTM_GLBL_nEN_RM, |
| Okan Sahin |
0:08f763822dd3 | 243 | INTM_GLBL_TJAL1_RM, |
| Okan Sahin |
0:08f763822dd3 | 244 | INTM_GLBL_TJAL2_RM, |
| Okan Sahin |
0:08f763822dd3 | 245 | INTM_GLBL_SBB0_FM, |
| Okan Sahin |
0:08f763822dd3 | 246 | INTM_GLBL_SBB1_FM, |
| Okan Sahin |
0:08f763822dd3 | 247 | INTM_GLBL_SBB2_FM, |
| Okan Sahin |
0:08f763822dd3 | 248 | INTM_GLBL_SBB3_FM |
| Okan Sahin |
0:08f763822dd3 | 249 | }reg_bit_int_mask_t; |
| Okan Sahin |
0:08f763822dd3 | 250 | |
| Okan Sahin |
0:08f763822dd3 | 251 | /** |
| Okan Sahin |
0:08f763822dd3 | 252 | * @brief Set bit field of INTM_GLBL (0x03) register. |
| Okan Sahin |
0:08f763822dd3 | 253 | * |
| Okan Sahin |
0:08f763822dd3 | 254 | * @param[in] bit_field Register bit field to be set. |
| Okan Sahin |
0:08f763822dd3 | 255 | * @param[out] maskBit 0x0: Interrupt is unmasked, |
| Okan Sahin |
0:08f763822dd3 | 256 | * 0x1: Interrupt is masked. |
| Okan Sahin |
0:08f763822dd3 | 257 | * |
| Okan Sahin |
0:08f763822dd3 | 258 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 259 | */ |
| Okan Sahin |
0:08f763822dd3 | 260 | int set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit); |
| Okan Sahin |
0:08f763822dd3 | 261 | |
| Okan Sahin |
0:08f763822dd3 | 262 | /** |
| Okan Sahin |
0:08f763822dd3 | 263 | * @brief Get bit field of INTM_GLBL (0x03) register. |
| Okan Sahin |
0:08f763822dd3 | 264 | * |
| Okan Sahin |
0:08f763822dd3 | 265 | * @param[in] bit_field Register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 266 | * @param[out] maskBit 0x0: Interrupt is unmasked, |
| Okan Sahin |
0:08f763822dd3 | 267 | * 0x1: Interrupt is masked. |
| Okan Sahin |
0:08f763822dd3 | 268 | * |
| Okan Sahin |
0:08f763822dd3 | 269 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 270 | */ |
| Okan Sahin |
0:08f763822dd3 | 271 | int get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit); |
| Okan Sahin |
0:08f763822dd3 | 272 | |
| Okan Sahin |
0:08f763822dd3 | 273 | /** |
| Okan Sahin |
0:08f763822dd3 | 274 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 275 | * |
| Okan Sahin |
0:08f763822dd3 | 276 | * @details |
| Okan Sahin |
0:08f763822dd3 | 277 | * - Register : STAT_GLBL (0x04) |
| Okan Sahin |
0:08f763822dd3 | 278 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:08f763822dd3 | 279 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 280 | * - Description : Global Status. |
| Okan Sahin |
0:08f763822dd3 | 281 | */ |
| Okan Sahin |
0:08f763822dd3 | 282 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 283 | STAT_GLBL_STAT_EN, |
| Okan Sahin |
0:08f763822dd3 | 284 | STAT_GLBL_TJAL1_S, |
| Okan Sahin |
0:08f763822dd3 | 285 | STAT_GLBL_TJAL2_S, |
| Okan Sahin |
0:08f763822dd3 | 286 | STAT_GLBL_RSVD, |
| Okan Sahin |
0:08f763822dd3 | 287 | STAT_GLBL_SBB0_S, |
| Okan Sahin |
0:08f763822dd3 | 288 | STAT_GLBL_SBB1_S, |
| Okan Sahin |
0:08f763822dd3 | 289 | STAT_GLBL_SBB2_S, |
| Okan Sahin |
0:08f763822dd3 | 290 | STAT_GLBL_SBB3_S |
| Okan Sahin |
0:08f763822dd3 | 291 | }reg_bit_stat_glbl_t; |
| Okan Sahin |
0:08f763822dd3 | 292 | |
| Okan Sahin |
0:08f763822dd3 | 293 | /** |
| Okan Sahin |
0:08f763822dd3 | 294 | * @brief Get bit field of STAT_GLBL (0x04) register. |
| Okan Sahin |
0:08f763822dd3 | 295 | * |
| Okan Sahin |
0:08f763822dd3 | 296 | * @param[in] bit_field STAT_GLBL register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 297 | * @param[out] status Pointer to save result of Status Global bit state. |
| Okan Sahin |
0:08f763822dd3 | 298 | * |
| Okan Sahin |
0:08f763822dd3 | 299 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 300 | */ |
| Okan Sahin |
0:08f763822dd3 | 301 | int get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status); |
| Okan Sahin |
0:08f763822dd3 | 302 | |
| Okan Sahin |
0:08f763822dd3 | 303 | /** |
| Okan Sahin |
0:08f763822dd3 | 304 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 305 | * |
| Okan Sahin |
0:08f763822dd3 | 306 | * @details |
| Okan Sahin |
0:08f763822dd3 | 307 | * - Register : ERCFLAG (0x05) |
| Okan Sahin |
0:08f763822dd3 | 308 | * - Bit Fields : [7:0] |
| Okan Sahin |
0:08f763822dd3 | 309 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 310 | * - Description : Event Recorder Flags. |
| Okan Sahin |
0:08f763822dd3 | 311 | */ |
| Okan Sahin |
0:08f763822dd3 | 312 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 313 | ERCFLAG_TOVLD, |
| Okan Sahin |
0:08f763822dd3 | 314 | ERCFLAG_OVLO, |
| Okan Sahin |
0:08f763822dd3 | 315 | ERCFLAG_UVLO, |
| Okan Sahin |
0:08f763822dd3 | 316 | ERCFLAG_MRST, |
| Okan Sahin |
0:08f763822dd3 | 317 | ERCFLAG_SFT_OFF_F, |
| Okan Sahin |
0:08f763822dd3 | 318 | ERCFLAG_SFT_CRST_F, |
| Okan Sahin |
0:08f763822dd3 | 319 | ERCFLAG_RSVD |
| Okan Sahin |
0:08f763822dd3 | 320 | }reg_bit_ercflag_t; |
| Okan Sahin |
0:08f763822dd3 | 321 | |
| Okan Sahin |
0:08f763822dd3 | 322 | /** |
| Okan Sahin |
0:08f763822dd3 | 323 | * @brief Get bit field of ERCFLAG (0x05) register. |
| Okan Sahin |
0:08f763822dd3 | 324 | * |
| Okan Sahin |
0:08f763822dd3 | 325 | * @param[in] bit_field ERCFLAG register bit field to be written. |
| Okan Sahin |
0:08f763822dd3 | 326 | * @param[out] flag Pointer to save result of ercglag bit states. |
| Okan Sahin |
0:08f763822dd3 | 327 | * For individual bit |
| Okan Sahin |
0:08f763822dd3 | 328 | * 0x0: ERCFLAG has not occurred, |
| Okan Sahin |
0:08f763822dd3 | 329 | * 0x1: ERCFLAG has occurred. |
| Okan Sahin |
0:08f763822dd3 | 330 | * |
| Okan Sahin |
0:08f763822dd3 | 331 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 332 | */ |
| Okan Sahin |
0:08f763822dd3 | 333 | int get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag); |
| Okan Sahin |
0:08f763822dd3 | 334 | |
| Okan Sahin |
0:08f763822dd3 | 335 | /** |
| Okan Sahin |
0:08f763822dd3 | 336 | * @brief Get bit field of CID (0x06) register. |
| Okan Sahin |
0:08f763822dd3 | 337 | * |
| Okan Sahin |
0:08f763822dd3 | 338 | * @return CID on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 339 | */ |
| Okan Sahin |
0:08f763822dd3 | 340 | int get_cid(void); |
| Okan Sahin |
0:08f763822dd3 | 341 | |
| Okan Sahin |
0:08f763822dd3 | 342 | /** |
| Okan Sahin |
0:08f763822dd3 | 343 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 344 | * |
| Okan Sahin |
0:08f763822dd3 | 345 | * @details |
| Okan Sahin |
0:08f763822dd3 | 346 | * - Register : CONFIG_SBB_TOP (0x07) |
| Okan Sahin |
0:08f763822dd3 | 347 | * - Bit Fields : [1:0] |
| Okan Sahin |
0:08f763822dd3 | 348 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 349 | * - Description : Configuration for SIMO Buck Boost |
| Okan Sahin |
0:08f763822dd3 | 350 | */ |
| Okan Sahin |
0:08f763822dd3 | 351 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 352 | DRV_SBB_FASTEST_TRANSITION_TIME, |
| Okan Sahin |
0:08f763822dd3 | 353 | DRV_SBB_A_LITTLE_SLOWER_THAN_0X00, |
| Okan Sahin |
0:08f763822dd3 | 354 | DRV_SBB_A_LITTLE_SLOWER_THAN_0X01, |
| Okan Sahin |
0:08f763822dd3 | 355 | DRV_SBB_A_LITTLE_SLOWER_THAN_0X02 |
| Okan Sahin |
0:08f763822dd3 | 356 | }decode_drv_sbb_t; |
| Okan Sahin |
0:08f763822dd3 | 357 | |
| Okan Sahin |
0:08f763822dd3 | 358 | /** |
| Okan Sahin |
0:08f763822dd3 | 359 | * @brief Set CONFIG_SBB_TOP (0x07) register. |
| Okan Sahin |
0:08f763822dd3 | 360 | * |
| Okan Sahin |
0:08f763822dd3 | 361 | * @param[in] config Configuration value to be written. |
| Okan Sahin |
0:08f763822dd3 | 362 | * 0x0: Fastest transition time (~0.6ns) |
| Okan Sahin |
0:08f763822dd3 | 363 | * 0x1: A little slower than 0b00 (~1.2ns) |
| Okan Sahin |
0:08f763822dd3 | 364 | * 0x2: A little slower than 0b01 (~1.8ns) |
| Okan Sahin |
0:08f763822dd3 | 365 | * 0x3: A little slower than 0b10 (~8ns) |
| Okan Sahin |
0:08f763822dd3 | 366 | * |
| Okan Sahin |
0:08f763822dd3 | 367 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 368 | */ |
| Okan Sahin |
0:08f763822dd3 | 369 | int set_drv_sbb(decode_drv_sbb_t config); |
| Okan Sahin |
0:08f763822dd3 | 370 | |
| Okan Sahin |
0:08f763822dd3 | 371 | /** |
| Okan Sahin |
0:08f763822dd3 | 372 | * @brief Get CONFIG_SBB_TOP (0x07) register. |
| Okan Sahin |
0:08f763822dd3 | 373 | * |
| Okan Sahin |
0:08f763822dd3 | 374 | * @param[out] config Configuration value to be read. |
| Okan Sahin |
0:08f763822dd3 | 375 | * 0x0: Fastest transition time (~0.6ns) |
| Okan Sahin |
0:08f763822dd3 | 376 | * 0x1: A little slower than 0b00 (~1.2ns) |
| Okan Sahin |
0:08f763822dd3 | 377 | * 0x2: A little slower than 0b01 (~1.8ns) |
| Okan Sahin |
0:08f763822dd3 | 378 | * 0x3: A little slower than 0b10 (~8ns) |
| Okan Sahin |
0:08f763822dd3 | 379 | * |
| Okan Sahin |
0:08f763822dd3 | 380 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 381 | */ |
| Okan Sahin |
0:08f763822dd3 | 382 | int get_drv_sbb(decode_drv_sbb_t *config); |
| Okan Sahin |
0:08f763822dd3 | 383 | |
| Okan Sahin |
0:08f763822dd3 | 384 | /** |
| Okan Sahin |
0:08f763822dd3 | 385 | * @brief Set SIMO Buck-Boost Channel x Target Output Voltage. |
| Okan Sahin |
0:08f763822dd3 | 386 | * CNFG_SBB0_A (0x08), CNFG_SBB1_A (0x0A), CNFG_SBB2_A (0x0C) and CNFG_SBB3_A (0x0E) |
| Okan Sahin |
0:08f763822dd3 | 387 | * |
| Okan Sahin |
0:08f763822dd3 | 388 | * @param[in] channel Channel number: 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 389 | * @param[in] voltV SIMO buck-boost channel x target output voltage field to be written. |
| Okan Sahin |
0:08f763822dd3 | 390 | * SBBx = 500mV + 25mV x TV_SBBx[7:0] |
| Okan Sahin |
0:08f763822dd3 | 391 | * 0x00: 0.500V 0x01: 0.525V 0x02: 0.550V |
| Okan Sahin |
0:08f763822dd3 | 392 | 0x03: 0.575V ... |
| Okan Sahin |
0:08f763822dd3 | 393 | 0x8B: 3.975V 0x8C: 4.000V 0x8D–0xFF: Reserved |
| Okan Sahin |
0:08f763822dd3 | 394 | * |
| Okan Sahin |
0:08f763822dd3 | 395 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 396 | */ |
| Okan Sahin |
0:08f763822dd3 | 397 | int set_tv_sbb(uint8_t channel, float voltV); |
| Okan Sahin |
0:08f763822dd3 | 398 | |
| Okan Sahin |
0:08f763822dd3 | 399 | /** |
| Okan Sahin |
0:08f763822dd3 | 400 | * @brief Get SIMO Buck-Boost Channel x Target Output Voltage. |
| Okan Sahin |
0:08f763822dd3 | 401 | * CNFG_SBB0_A (0x08), CNFG_SBB1_A (0x0A), CNFG_SBB2_A (0x0C) and CNFG_SBB3_A (0x0E) |
| Okan Sahin |
0:08f763822dd3 | 402 | * |
| Okan Sahin |
0:08f763822dd3 | 403 | * @param[in] channel Channel number: 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 404 | * @param[out] voltV SIMO buck-boost channel x target output voltage field to be read. |
| Okan Sahin |
0:08f763822dd3 | 405 | * SBBx = 500mV + 25mV x TV_SBBx[7:0] |
| Okan Sahin |
0:08f763822dd3 | 406 | * 0x00: 0.500V 0x01: 0.525V 0x02: 0.550V |
| Okan Sahin |
0:08f763822dd3 | 407 | 0x03: 0.575V ... |
| Okan Sahin |
0:08f763822dd3 | 408 | 0x8B: 3.975V 0x8C: 4.000V 0x8D–0xFF: Reserved |
| Okan Sahin |
0:08f763822dd3 | 409 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 410 | */ |
| Okan Sahin |
0:08f763822dd3 | 411 | int get_tv_sbb(uint8_t channel, float *voltV); |
| Okan Sahin |
0:08f763822dd3 | 412 | |
| Okan Sahin |
0:08f763822dd3 | 413 | /** |
| Okan Sahin |
0:08f763822dd3 | 414 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 415 | * |
| Okan Sahin |
0:08f763822dd3 | 416 | * @details |
| Okan Sahin |
0:08f763822dd3 | 417 | * - Register : CNFG_SBB0_B (0x09), CNFG_SBB1_B (0x0B), CNFG_SBB2_B (0x0D) and CNFG_SBB3_B (0x0F) |
| Okan Sahin |
0:08f763822dd3 | 418 | * - Bit Fields : [3] |
| Okan Sahin |
0:08f763822dd3 | 419 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 420 | * - Description : SIMO Buck-Boost Channel 0, 1, 2 or 3 Active-Discharge Enable. |
| Okan Sahin |
0:08f763822dd3 | 421 | */ |
| Okan Sahin |
0:08f763822dd3 | 422 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 423 | ADE_SBB_DISABLED, |
| Okan Sahin |
0:08f763822dd3 | 424 | ADE_SBB_ENABLED |
| Okan Sahin |
0:08f763822dd3 | 425 | }decode_ade_sbb_t; |
| Okan Sahin |
0:08f763822dd3 | 426 | |
| Okan Sahin |
0:08f763822dd3 | 427 | /** |
| Okan Sahin |
0:08f763822dd3 | 428 | * @brief Set SIMO Buck-Boost Channel x Active-Discharge Enable. |
| Okan Sahin |
0:08f763822dd3 | 429 | * |
| Okan Sahin |
0:08f763822dd3 | 430 | * @param[in] channel Channel number: 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 431 | * @param[in] ade_sbb SIMO buck-boost channel x active-discharge enable bit to be written. |
| Okan Sahin |
0:08f763822dd3 | 432 | * |
| Okan Sahin |
0:08f763822dd3 | 433 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 434 | */ |
| Okan Sahin |
0:08f763822dd3 | 435 | int set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb); |
| Okan Sahin |
0:08f763822dd3 | 436 | |
| Okan Sahin |
0:08f763822dd3 | 437 | /** |
| Okan Sahin |
0:08f763822dd3 | 438 | * @brief Get SIMO Buck-Boost Channel x Active-Discharge Enable. |
| Okan Sahin |
0:08f763822dd3 | 439 | * |
| Okan Sahin |
0:08f763822dd3 | 440 | * @param[in] channel Channel number: 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 441 | * @param[out] ade_sbb SIMO buck-boost channel x active-discharge enable bit to be read. |
| Okan Sahin |
0:08f763822dd3 | 442 | * |
| Okan Sahin |
0:08f763822dd3 | 443 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 444 | */ |
| Okan Sahin |
0:08f763822dd3 | 445 | int get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb); |
| Okan Sahin |
0:08f763822dd3 | 446 | |
| Okan Sahin |
0:08f763822dd3 | 447 | /** |
| Okan Sahin |
0:08f763822dd3 | 448 | * @brief Register Configuration |
| Okan Sahin |
0:08f763822dd3 | 449 | * |
| Okan Sahin |
0:08f763822dd3 | 450 | * @details |
| Okan Sahin |
0:08f763822dd3 | 451 | * - Register : CNFG_SBB0_B (0x09), CNFG_SBB1_B (0x0B), CNFG_SBB2_B (0x0D) and CNFG_SBB3_B (0x0F) |
| Okan Sahin |
0:08f763822dd3 | 452 | * - Bit Fields : [2:0] |
| Okan Sahin |
0:08f763822dd3 | 453 | * - Default : 0x0 |
| Okan Sahin |
0:08f763822dd3 | 454 | * - Description : Enable Control for SIMO Buck-Boost Channel 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 455 | */ |
| Okan Sahin |
0:08f763822dd3 | 456 | typedef enum { |
| Okan Sahin |
0:08f763822dd3 | 457 | EN_SBB_FPS_SLOT_0, |
| Okan Sahin |
0:08f763822dd3 | 458 | EN_SBB_FPS_SLOT_1, |
| Okan Sahin |
0:08f763822dd3 | 459 | EN_SBB_FPS_SLOT_2, |
| Okan Sahin |
0:08f763822dd3 | 460 | EN_SBB_FPS_SLOT_3, |
| Okan Sahin |
0:08f763822dd3 | 461 | EN_SBB_OFF, |
| Okan Sahin |
0:08f763822dd3 | 462 | EN_SBB_SAME_AS_0X04, |
| Okan Sahin |
0:08f763822dd3 | 463 | EN_SBB_ON, |
| Okan Sahin |
0:08f763822dd3 | 464 | EN_SBB_SAME_AS_0X06 |
| Okan Sahin |
0:08f763822dd3 | 465 | }decode_en_sbb_t; |
| Okan Sahin |
0:08f763822dd3 | 466 | |
| Okan Sahin |
0:08f763822dd3 | 467 | /** |
| Okan Sahin |
0:08f763822dd3 | 468 | * @brief Set Enable Control for SIMO Buck-Boost Channel x. |
| Okan Sahin |
0:08f763822dd3 | 469 | * |
| Okan Sahin |
0:08f763822dd3 | 470 | * @param[in] channel Channel number: 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 471 | * @param[in] en_sbb Enable control for SIMO buck-boost channel x field to be written. |
| Okan Sahin |
0:08f763822dd3 | 472 | * |
| Okan Sahin |
0:08f763822dd3 | 473 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 474 | */ |
| Okan Sahin |
0:08f763822dd3 | 475 | int set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb); |
| Okan Sahin |
0:08f763822dd3 | 476 | |
| Okan Sahin |
0:08f763822dd3 | 477 | /** |
| Okan Sahin |
0:08f763822dd3 | 478 | * @brief Get Enable Control for SIMO Buck-Boost Channel x. |
| Okan Sahin |
0:08f763822dd3 | 479 | * |
| Okan Sahin |
0:08f763822dd3 | 480 | * @param[in] channel Channel number: 0, 1, 2 or 3. |
| Okan Sahin |
0:08f763822dd3 | 481 | * @param[out] en_sbb Enable control for SIMO buck-boost channel x field to be read. |
| Okan Sahin |
0:08f763822dd3 | 482 | * |
| Okan Sahin |
0:08f763822dd3 | 483 | * @return 0 on success, error code on failure. |
| Okan Sahin |
0:08f763822dd3 | 484 | */ |
| Okan Sahin |
0:08f763822dd3 | 485 | int get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb); |
| Okan Sahin |
0:08f763822dd3 | 486 | |
| Okan Sahin |
0:08f763822dd3 | 487 | /** |
| Okan Sahin |
0:08f763822dd3 | 488 | * @brief Disable all interrupts |
| Okan Sahin |
0:08f763822dd3 | 489 | * |
| Okan Sahin |
0:08f763822dd3 | 490 | * @return 0 on success, error code on failure |
| Okan Sahin |
0:08f763822dd3 | 491 | */ |
| Okan Sahin |
0:08f763822dd3 | 492 | int irq_disable_all(); |
| Okan Sahin |
0:08f763822dd3 | 493 | |
| Okan Sahin |
0:08f763822dd3 | 494 | /** |
| Okan Sahin |
0:08f763822dd3 | 495 | * @brief Set Interrupt Handler for a Specific Interrupt ID. |
| Okan Sahin |
0:08f763822dd3 | 496 | * |
| Okan Sahin |
0:08f763822dd3 | 497 | * @param[in] id reg_bit_reg_bit_int_glbl_t id, one of INTR_ID_*. |
| Okan Sahin |
0:08f763822dd3 | 498 | * @param[in] func Interrupt handler function. |
| Okan Sahin |
0:08f763822dd3 | 499 | * @param[in] cb Interrupt handler data. |
| Okan Sahin |
0:08f763822dd3 | 500 | */ |
| Okan Sahin |
0:08f763822dd3 | 501 | void set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb); |
| Okan Sahin |
0:08f763822dd3 | 502 | }; |
| Okan Sahin |
0:08f763822dd3 | 503 | #endif |