Maxim Integrated / MAX77655

MAX77655 Low IQ SIMO PMIC with 4-Outputs Delivering up to 700mA Total Output Current Mbed Driver

MAX77655.cpp@0:08f763822dd3, 20 months ago (annotated)

Committer:
Okan Sahin
Date:
Tue Aug 23 18:11:21 2022 +0300
Revision:
0:08f763822dd3
Initial Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Okan Sahin 0:08f763822dd3 1 /*******************************************************************************
Okan Sahin 0:08f763822dd3 2 * Copyright(C) Analog Devices Inc., All Rights Reserved.
Okan Sahin 0:08f763822dd3 3 *
Okan Sahin 0:08f763822dd3 4 * Permission is hereby granted, free of charge, to any person obtaining a
Okan Sahin 0:08f763822dd3 5 * copy of this software and associated documentation files(the "Software"),
Okan Sahin 0:08f763822dd3 6 * to deal in the Software without restriction, including without limitation
Okan Sahin 0:08f763822dd3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Okan Sahin 0:08f763822dd3 8 * and/or sell copies of the Software, and to permit persons to whom the
Okan Sahin 0:08f763822dd3 9 * Software is furnished to do so, subject to the following conditions:
Okan Sahin 0:08f763822dd3 10 *
Okan Sahin 0:08f763822dd3 11 * The above copyright notice and this permission notice shall be included
Okan Sahin 0:08f763822dd3 12 * in all copies or substantial portions of the Software.
Okan Sahin 0:08f763822dd3 13 *
Okan Sahin 0:08f763822dd3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Okan Sahin 0:08f763822dd3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Okan Sahin 0:08f763822dd3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Okan Sahin 0:08f763822dd3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Okan Sahin 0:08f763822dd3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Okan Sahin 0:08f763822dd3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Okan Sahin 0:08f763822dd3 20 * OTHER DEALINGS IN THE SOFTWARE.
Okan Sahin 0:08f763822dd3 21 *
Okan Sahin 0:08f763822dd3 22 * Except as contained in this notice, the name of Analog Devices Inc.
Okan Sahin 0:08f763822dd3 23 * shall not be used except as stated in the Analog Devices Inc.
Okan Sahin 0:08f763822dd3 24 * Branding Policy.
Okan Sahin 0:08f763822dd3 25 *
Okan Sahin 0:08f763822dd3 26 * The mere transfer of this software does not imply any licenses
Okan Sahin 0:08f763822dd3 27 * of trade secrets, proprietary technology, copyrights, patents,
Okan Sahin 0:08f763822dd3 28 * trademarks, maskwork rights, or any other form of intellectual
Okan Sahin 0:08f763822dd3 29 * property whatsoever. Analog Devices Inc.retains all ownership rights.
Okan Sahin 0:08f763822dd3 30 *******************************************************************************
Okan Sahin 0:08f763822dd3 31 */
Okan Sahin 0:08f763822dd3 32
Okan Sahin 0:08f763822dd3 33 #include <Thread.h>
Okan Sahin 0:08f763822dd3 34 #include "MAX77655.h"
Okan Sahin 0:08f763822dd3 35 #include <math.h>
Okan Sahin 0:08f763822dd3 36
Okan Sahin 0:08f763822dd3 37 #define POST_INTR_WORK_SIGNAL_ID 0x1
Okan Sahin 0:08f763822dd3 38 #define TO_UINT8 0xFF
Okan Sahin 0:08f763822dd3 39 #define TO_UINT16 0xFFFF
Okan Sahin 0:08f763822dd3 40
Okan Sahin 0:08f763822dd3 41 MAX77655::MAX77655(I2C *i2c, PinName IRQPin):interrupt_handler_list{NULL}
Okan Sahin 0:08f763822dd3 42 {
Okan Sahin 0:08f763822dd3 43 if (i2c == NULL)
Okan Sahin 0:08f763822dd3 44 return;
Okan Sahin 0:08f763822dd3 45
Okan Sahin 0:08f763822dd3 46 i2c_handler = i2c;
Okan Sahin 0:08f763822dd3 47
Okan Sahin 0:08f763822dd3 48 if (IRQPin != NC) {
Okan Sahin 0:08f763822dd3 49 irq_disable_all();
Okan Sahin 0:08f763822dd3 50 post_intr_work_thread = new Thread();
Okan Sahin 0:08f763822dd3 51 post_intr_work_thread->start(Callback<void()>(this, &MAX77655::post_interrupt_work));
Okan Sahin 0:08f763822dd3 52
Okan Sahin 0:08f763822dd3 53 this->irq_pin = new InterruptIn(IRQPin);
Okan Sahin 0:08f763822dd3 54 this->irq_pin->fall(Callback<void()>(this, &MAX77655::interrupt_handler));
Okan Sahin 0:08f763822dd3 55 this->irq_pin->enable_irq();
Okan Sahin 0:08f763822dd3 56 } else {
Okan Sahin 0:08f763822dd3 57 this->irq_pin = NULL;
Okan Sahin 0:08f763822dd3 58 }
Okan Sahin 0:08f763822dd3 59 }
Okan Sahin 0:08f763822dd3 60
Okan Sahin 0:08f763822dd3 61 MAX77655::~MAX77655()
Okan Sahin 0:08f763822dd3 62 {
Okan Sahin 0:08f763822dd3 63 if (post_intr_work_thread)
Okan Sahin 0:08f763822dd3 64 delete post_intr_work_thread;
Okan Sahin 0:08f763822dd3 65
Okan Sahin 0:08f763822dd3 66 if (irq_pin)
Okan Sahin 0:08f763822dd3 67 delete irq_pin;
Okan Sahin 0:08f763822dd3 68 }
Okan Sahin 0:08f763822dd3 69
Okan Sahin 0:08f763822dd3 70 int MAX77655::read_register(uint8_t reg, uint8_t *value)
Okan Sahin 0:08f763822dd3 71 {
Okan Sahin 0:08f763822dd3 72 int rtn_val;
Okan Sahin 0:08f763822dd3 73
Okan Sahin 0:08f763822dd3 74 if (value == NULL)
Okan Sahin 0:08f763822dd3 75 return MAX77655_VALUE_NULL;
Okan Sahin 0:08f763822dd3 76
Okan Sahin 0:08f763822dd3 77 rtn_val = i2c_handler->write(MAX77655_I2C_ADDRESS, (const char *)&reg, 1, true);
Okan Sahin 0:08f763822dd3 78 if (rtn_val != 0)
Okan Sahin 0:08f763822dd3 79 return MAX77655_WRITE_DATA_FAILED;
Okan Sahin 0:08f763822dd3 80
Okan Sahin 0:08f763822dd3 81 rtn_val = i2c_handler->read(MAX77655_I2C_ADDRESS, (char *) value, 1, false);
Okan Sahin 0:08f763822dd3 82 if (rtn_val < 0)
Okan Sahin 0:08f763822dd3 83 return MAX77655_READ_DATA_FAILED;
Okan Sahin 0:08f763822dd3 84
Okan Sahin 0:08f763822dd3 85 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 86 }
Okan Sahin 0:08f763822dd3 87
Okan Sahin 0:08f763822dd3 88 int MAX77655::write_register(uint8_t reg, const uint8_t *value)
Okan Sahin 0:08f763822dd3 89 {
Okan Sahin 0:08f763822dd3 90 int rtn_val;
Okan Sahin 0:08f763822dd3 91 unsigned char local_data[2];
Okan Sahin 0:08f763822dd3 92
Okan Sahin 0:08f763822dd3 93 if (value == NULL)
Okan Sahin 0:08f763822dd3 94 return MAX77655_VALUE_NULL;
Okan Sahin 0:08f763822dd3 95
Okan Sahin 0:08f763822dd3 96 local_data[0] = reg;
Okan Sahin 0:08f763822dd3 97
Okan Sahin 0:08f763822dd3 98 memcpy(&local_data[1], value, 1);
Okan Sahin 0:08f763822dd3 99
Okan Sahin 0:08f763822dd3 100 rtn_val = i2c_handler->write(MAX77655_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
Okan Sahin 0:08f763822dd3 101 if (rtn_val != MAX77655_NO_ERROR)
Okan Sahin 0:08f763822dd3 102 return MAX77655_WRITE_DATA_FAILED;
Okan Sahin 0:08f763822dd3 103
Okan Sahin 0:08f763822dd3 104 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 105 }
Okan Sahin 0:08f763822dd3 106
Okan Sahin 0:08f763822dd3 107 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
Okan Sahin 0:08f763822dd3 108 int ret_val; \
Okan Sahin 0:08f763822dd3 109 ret_val = read_register(address, (uint8_t *)&(reg_name)); \
Okan Sahin 0:08f763822dd3 110 if (ret_val) { \
Okan Sahin 0:08f763822dd3 111 return ret_val; \
Okan Sahin 0:08f763822dd3 112 } \
Okan Sahin 0:08f763822dd3 113 bit_field_name = value; \
Okan Sahin 0:08f763822dd3 114 ret_val = write_register(address, (uint8_t *)&(reg_name)); \
Okan Sahin 0:08f763822dd3 115 if (ret_val) { \
Okan Sahin 0:08f763822dd3 116 return ret_val; \
Okan Sahin 0:08f763822dd3 117 }
Okan Sahin 0:08f763822dd3 118
Okan Sahin 0:08f763822dd3 119 int MAX77655::set_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t config)
Okan Sahin 0:08f763822dd3 120 {
Okan Sahin 0:08f763822dd3 121 int ret;
Okan Sahin 0:08f763822dd3 122 reg_cnfg_glbl_a_t reg_cnfg_glbl_a;
Okan Sahin 0:08f763822dd3 123
Okan Sahin 0:08f763822dd3 124 ret = read_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
Okan Sahin 0:08f763822dd3 125 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 126
Okan Sahin 0:08f763822dd3 127 switch (bit_field)
Okan Sahin 0:08f763822dd3 128 {
Okan Sahin 0:08f763822dd3 129 case CNFG_GLBL_A_DBEN_nEN:
Okan Sahin 0:08f763822dd3 130 reg_cnfg_glbl_a.bits.dben_nen = config;
Okan Sahin 0:08f763822dd3 131 break;
Okan Sahin 0:08f763822dd3 132 case CNFG_GLBL_A_nEN_MODE:
Okan Sahin 0:08f763822dd3 133 reg_cnfg_glbl_a.bits.nen_mode = config;
Okan Sahin 0:08f763822dd3 134 break;
Okan Sahin 0:08f763822dd3 135 case CNFG_GLBL_A_MRT:
Okan Sahin 0:08f763822dd3 136 reg_cnfg_glbl_a.bits.mrt = config;
Okan Sahin 0:08f763822dd3 137 break;
Okan Sahin 0:08f763822dd3 138 case CNFG_GLBL_A_BIAS_LPM:
Okan Sahin 0:08f763822dd3 139 reg_cnfg_glbl_a.bits.bias_lpm = config;
Okan Sahin 0:08f763822dd3 140 break;
Okan Sahin 0:08f763822dd3 141 case CNFG_GLBL_A_PU_DIS:
Okan Sahin 0:08f763822dd3 142 reg_cnfg_glbl_a.bits.pu_dis = config;
Okan Sahin 0:08f763822dd3 143 break;
Okan Sahin 0:08f763822dd3 144 default:
Okan Sahin 0:08f763822dd3 145 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 146 break;
Okan Sahin 0:08f763822dd3 147 }
Okan Sahin 0:08f763822dd3 148
Okan Sahin 0:08f763822dd3 149 return write_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
Okan Sahin 0:08f763822dd3 150 }
Okan Sahin 0:08f763822dd3 151
Okan Sahin 0:08f763822dd3 152 int MAX77655::get_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t *config)
Okan Sahin 0:08f763822dd3 153 {
Okan Sahin 0:08f763822dd3 154 int ret;
Okan Sahin 0:08f763822dd3 155 reg_cnfg_glbl_a_t reg_cnfg_glbl_a = {0};
Okan Sahin 0:08f763822dd3 156
Okan Sahin 0:08f763822dd3 157 ret = read_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
Okan Sahin 0:08f763822dd3 158 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 159
Okan Sahin 0:08f763822dd3 160 switch (bit_field)
Okan Sahin 0:08f763822dd3 161 {
Okan Sahin 0:08f763822dd3 162 case CNFG_GLBL_A_DBEN_nEN:
Okan Sahin 0:08f763822dd3 163 *config = (uint8_t)reg_cnfg_glbl_a.bits.dben_nen;
Okan Sahin 0:08f763822dd3 164 break;
Okan Sahin 0:08f763822dd3 165 case CNFG_GLBL_A_nEN_MODE:
Okan Sahin 0:08f763822dd3 166 *config = (uint8_t)reg_cnfg_glbl_a.bits.nen_mode;
Okan Sahin 0:08f763822dd3 167 break;
Okan Sahin 0:08f763822dd3 168 case CNFG_GLBL_A_MRT:
Okan Sahin 0:08f763822dd3 169 *config = (uint8_t)reg_cnfg_glbl_a.bits.mrt;
Okan Sahin 0:08f763822dd3 170 break;
Okan Sahin 0:08f763822dd3 171 case CNFG_GLBL_A_BIAS_LPM:
Okan Sahin 0:08f763822dd3 172 *config = (uint8_t)reg_cnfg_glbl_a.bits.bias_lpm;
Okan Sahin 0:08f763822dd3 173 break;
Okan Sahin 0:08f763822dd3 174 case CNFG_GLBL_A_PU_DIS:
Okan Sahin 0:08f763822dd3 175 *config = (uint8_t)reg_cnfg_glbl_a.bits.pu_dis;
Okan Sahin 0:08f763822dd3 176 break;
Okan Sahin 0:08f763822dd3 177 default:
Okan Sahin 0:08f763822dd3 178 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 179 break;
Okan Sahin 0:08f763822dd3 180 }
Okan Sahin 0:08f763822dd3 181
Okan Sahin 0:08f763822dd3 182 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 183 }
Okan Sahin 0:08f763822dd3 184
Okan Sahin 0:08f763822dd3 185 int MAX77655::set_sft_ctrl(decode_sft_ctrl_t config)
Okan Sahin 0:08f763822dd3 186 {
Okan Sahin 0:08f763822dd3 187 reg_cnfg_glbl_b_t reg_cnfg_glbl_b;
Okan Sahin 0:08f763822dd3 188
Okan Sahin 0:08f763822dd3 189 SET_BIT_FIELD(CNFG_GLBL_B, reg_cnfg_glbl_b, reg_cnfg_glbl_b.bits.sft_ctrl, config);
Okan Sahin 0:08f763822dd3 190
Okan Sahin 0:08f763822dd3 191 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 192 }
Okan Sahin 0:08f763822dd3 193
Okan Sahin 0:08f763822dd3 194 int MAX77655::get_sft_ctrl(decode_sft_ctrl_t *config)
Okan Sahin 0:08f763822dd3 195 {
Okan Sahin 0:08f763822dd3 196 int ret;
Okan Sahin 0:08f763822dd3 197 reg_cnfg_glbl_b_t reg_cnfg_glbl_b = {0};
Okan Sahin 0:08f763822dd3 198
Okan Sahin 0:08f763822dd3 199 ret = read_register(CNFG_GLBL_B, (uint8_t *)&(reg_cnfg_glbl_b));
Okan Sahin 0:08f763822dd3 200 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 201
Okan Sahin 0:08f763822dd3 202 *config = (decode_sft_ctrl_t)reg_cnfg_glbl_b.bits.sft_ctrl;
Okan Sahin 0:08f763822dd3 203
Okan Sahin 0:08f763822dd3 204 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 205 }
Okan Sahin 0:08f763822dd3 206
Okan Sahin 0:08f763822dd3 207 int MAX77655::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit)
Okan Sahin 0:08f763822dd3 208 {
Okan Sahin 0:08f763822dd3 209 int ret;
Okan Sahin 0:08f763822dd3 210 uint8_t reg_addr;
Okan Sahin 0:08f763822dd3 211 reg_intm_glbl_t reg_intm_glbl;
Okan Sahin 0:08f763822dd3 212
Okan Sahin 0:08f763822dd3 213 ret = read_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
Okan Sahin 0:08f763822dd3 214
Okan Sahin 0:08f763822dd3 215 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 216
Okan Sahin 0:08f763822dd3 217 switch (bit_field)
Okan Sahin 0:08f763822dd3 218 {
Okan Sahin 0:08f763822dd3 219 case INTM_GLBL_nEN_FM:
Okan Sahin 0:08f763822dd3 220 reg_intm_glbl.bits.nen_fm = maskBit;
Okan Sahin 0:08f763822dd3 221 break;
Okan Sahin 0:08f763822dd3 222 case INTM_GLBL_nEN_RM:
Okan Sahin 0:08f763822dd3 223 reg_intm_glbl.bits.nen_rm = maskBit;
Okan Sahin 0:08f763822dd3 224 break;
Okan Sahin 0:08f763822dd3 225 case INTM_GLBL_TJAL1_RM:
Okan Sahin 0:08f763822dd3 226 reg_intm_glbl.bits.tjal1_rm = maskBit;
Okan Sahin 0:08f763822dd3 227 break;
Okan Sahin 0:08f763822dd3 228 case INTM_GLBL_TJAL2_RM:
Okan Sahin 0:08f763822dd3 229 reg_intm_glbl.bits.tjal2_rm = maskBit;
Okan Sahin 0:08f763822dd3 230 break;
Okan Sahin 0:08f763822dd3 231 case INTM_GLBL_SBB0_FM:
Okan Sahin 0:08f763822dd3 232 reg_intm_glbl.bits.sbb0_fm = maskBit;
Okan Sahin 0:08f763822dd3 233 break;
Okan Sahin 0:08f763822dd3 234 case INTM_GLBL_SBB1_FM:
Okan Sahin 0:08f763822dd3 235 reg_intm_glbl.bits.sbb1_fm = maskBit;
Okan Sahin 0:08f763822dd3 236 break;
Okan Sahin 0:08f763822dd3 237 case INTM_GLBL_SBB2_FM:
Okan Sahin 0:08f763822dd3 238 reg_intm_glbl.bits.sbb2_fm = maskBit;
Okan Sahin 0:08f763822dd3 239 break;
Okan Sahin 0:08f763822dd3 240 case INTM_GLBL_SBB3_FM:
Okan Sahin 0:08f763822dd3 241 reg_intm_glbl.bits.sbb3_fm = maskBit;
Okan Sahin 0:08f763822dd3 242 break;
Okan Sahin 0:08f763822dd3 243 default:
Okan Sahin 0:08f763822dd3 244 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 245 break;
Okan Sahin 0:08f763822dd3 246 }
Okan Sahin 0:08f763822dd3 247
Okan Sahin 0:08f763822dd3 248 return write_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
Okan Sahin 0:08f763822dd3 249 }
Okan Sahin 0:08f763822dd3 250
Okan Sahin 0:08f763822dd3 251 int MAX77655::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit)
Okan Sahin 0:08f763822dd3 252 {
Okan Sahin 0:08f763822dd3 253 int ret;
Okan Sahin 0:08f763822dd3 254 uint8_t reg_addr;
Okan Sahin 0:08f763822dd3 255 reg_intm_glbl_t reg_intm_glbl = {0};
Okan Sahin 0:08f763822dd3 256
Okan Sahin 0:08f763822dd3 257 ret = read_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
Okan Sahin 0:08f763822dd3 258
Okan Sahin 0:08f763822dd3 259 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 260
Okan Sahin 0:08f763822dd3 261 switch (bit_field)
Okan Sahin 0:08f763822dd3 262 {
Okan Sahin 0:08f763822dd3 263 case INTM_GLBL_nEN_FM:
Okan Sahin 0:08f763822dd3 264 *maskBit = (uint8_t)reg_intm_glbl.bits.nen_fm;
Okan Sahin 0:08f763822dd3 265 break;
Okan Sahin 0:08f763822dd3 266 case INTM_GLBL_nEN_RM:
Okan Sahin 0:08f763822dd3 267 *maskBit = (uint8_t)reg_intm_glbl.bits.nen_rm;
Okan Sahin 0:08f763822dd3 268 break;
Okan Sahin 0:08f763822dd3 269 case INTM_GLBL_TJAL1_RM:
Okan Sahin 0:08f763822dd3 270 *maskBit = (uint8_t)reg_intm_glbl.bits.tjal1_rm;
Okan Sahin 0:08f763822dd3 271 break;
Okan Sahin 0:08f763822dd3 272 case INTM_GLBL_TJAL2_RM:
Okan Sahin 0:08f763822dd3 273 *maskBit = (uint8_t)reg_intm_glbl.bits.tjal2_rm;
Okan Sahin 0:08f763822dd3 274 break;
Okan Sahin 0:08f763822dd3 275 case INTM_GLBL_SBB0_FM:
Okan Sahin 0:08f763822dd3 276 *maskBit = (uint8_t)reg_intm_glbl.bits.sbb0_fm;
Okan Sahin 0:08f763822dd3 277 break;
Okan Sahin 0:08f763822dd3 278 case INTM_GLBL_SBB1_FM:
Okan Sahin 0:08f763822dd3 279 *maskBit = (uint8_t)reg_intm_glbl.bits.sbb1_fm;
Okan Sahin 0:08f763822dd3 280 break;
Okan Sahin 0:08f763822dd3 281 case INTM_GLBL_SBB2_FM:
Okan Sahin 0:08f763822dd3 282 *maskBit = (uint8_t)reg_intm_glbl.bits.sbb2_fm;
Okan Sahin 0:08f763822dd3 283 break;
Okan Sahin 0:08f763822dd3 284 case INTM_GLBL_SBB3_FM:
Okan Sahin 0:08f763822dd3 285 *maskBit = (uint8_t)reg_intm_glbl.bits.sbb3_fm;
Okan Sahin 0:08f763822dd3 286 break;
Okan Sahin 0:08f763822dd3 287 default:
Okan Sahin 0:08f763822dd3 288 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 289 break;
Okan Sahin 0:08f763822dd3 290 }
Okan Sahin 0:08f763822dd3 291
Okan Sahin 0:08f763822dd3 292 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 293 }
Okan Sahin 0:08f763822dd3 294
Okan Sahin 0:08f763822dd3 295 int MAX77655::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status)
Okan Sahin 0:08f763822dd3 296 {
Okan Sahin 0:08f763822dd3 297 int ret;
Okan Sahin 0:08f763822dd3 298 reg_stat_glbl_t reg_stat_glbl = {0};
Okan Sahin 0:08f763822dd3 299
Okan Sahin 0:08f763822dd3 300 ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
Okan Sahin 0:08f763822dd3 301 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 302
Okan Sahin 0:08f763822dd3 303 switch (bit_field)
Okan Sahin 0:08f763822dd3 304 {
Okan Sahin 0:08f763822dd3 305 case STAT_GLBL_STAT_EN:
Okan Sahin 0:08f763822dd3 306 *status = (uint8_t)reg_stat_glbl.bits.stat_en;
Okan Sahin 0:08f763822dd3 307 break;
Okan Sahin 0:08f763822dd3 308 case STAT_GLBL_TJAL1_S:
Okan Sahin 0:08f763822dd3 309 *status = (uint8_t)reg_stat_glbl.bits.tjal1_s;
Okan Sahin 0:08f763822dd3 310 break;
Okan Sahin 0:08f763822dd3 311 case STAT_GLBL_TJAL2_S:
Okan Sahin 0:08f763822dd3 312 *status = (uint8_t)reg_stat_glbl.bits.tjal2_s;
Okan Sahin 0:08f763822dd3 313 break;
Okan Sahin 0:08f763822dd3 314 case STAT_GLBL_SBB0_S:
Okan Sahin 0:08f763822dd3 315 *status = (uint8_t)reg_stat_glbl.bits.sbb0_s;
Okan Sahin 0:08f763822dd3 316 break;
Okan Sahin 0:08f763822dd3 317 case STAT_GLBL_SBB1_S:
Okan Sahin 0:08f763822dd3 318 *status = (uint8_t)reg_stat_glbl.bits.sbb1_s;
Okan Sahin 0:08f763822dd3 319 break;
Okan Sahin 0:08f763822dd3 320 case STAT_GLBL_SBB2_S:
Okan Sahin 0:08f763822dd3 321 *status = (uint8_t)reg_stat_glbl.bits.sbb2_s;
Okan Sahin 0:08f763822dd3 322 break;
Okan Sahin 0:08f763822dd3 323 case STAT_GLBL_SBB3_S:
Okan Sahin 0:08f763822dd3 324 *status = (uint8_t)reg_stat_glbl.bits.sbb3_s;
Okan Sahin 0:08f763822dd3 325 break;
Okan Sahin 0:08f763822dd3 326 default:
Okan Sahin 0:08f763822dd3 327 ret = MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 328 break;
Okan Sahin 0:08f763822dd3 329 }
Okan Sahin 0:08f763822dd3 330
Okan Sahin 0:08f763822dd3 331 return ret;
Okan Sahin 0:08f763822dd3 332 }
Okan Sahin 0:08f763822dd3 333
Okan Sahin 0:08f763822dd3 334 int MAX77655::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag)
Okan Sahin 0:08f763822dd3 335 {
Okan Sahin 0:08f763822dd3 336 int ret;
Okan Sahin 0:08f763822dd3 337 reg_ercflag_t reg_ercflag = {0};
Okan Sahin 0:08f763822dd3 338
Okan Sahin 0:08f763822dd3 339 ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
Okan Sahin 0:08f763822dd3 340 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 341
Okan Sahin 0:08f763822dd3 342 switch (bit_field)
Okan Sahin 0:08f763822dd3 343 {
Okan Sahin 0:08f763822dd3 344 case ERCFLAG_TOVLD:
Okan Sahin 0:08f763822dd3 345 *flag = (uint8_t)reg_ercflag.bits.tovld;
Okan Sahin 0:08f763822dd3 346 break;
Okan Sahin 0:08f763822dd3 347 case ERCFLAG_OVLO:
Okan Sahin 0:08f763822dd3 348 *flag = (uint8_t)reg_ercflag.bits.ovlo;
Okan Sahin 0:08f763822dd3 349 break;
Okan Sahin 0:08f763822dd3 350 case ERCFLAG_UVLO:
Okan Sahin 0:08f763822dd3 351 *flag = (uint8_t)reg_ercflag.bits.uvlo;
Okan Sahin 0:08f763822dd3 352 break;
Okan Sahin 0:08f763822dd3 353 case ERCFLAG_MRST:
Okan Sahin 0:08f763822dd3 354 *flag = (uint8_t)reg_ercflag.bits.mrst;
Okan Sahin 0:08f763822dd3 355 break;
Okan Sahin 0:08f763822dd3 356 case ERCFLAG_SFT_OFF_F:
Okan Sahin 0:08f763822dd3 357 *flag = (uint8_t)reg_ercflag.bits.sft_off_f;
Okan Sahin 0:08f763822dd3 358 break;
Okan Sahin 0:08f763822dd3 359 case ERCFLAG_SFT_CRST_F:
Okan Sahin 0:08f763822dd3 360 *flag = (uint8_t)reg_ercflag.bits.sft_crst_f;
Okan Sahin 0:08f763822dd3 361 break;
Okan Sahin 0:08f763822dd3 362 default:
Okan Sahin 0:08f763822dd3 363 ret = MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 364 break;
Okan Sahin 0:08f763822dd3 365 }
Okan Sahin 0:08f763822dd3 366
Okan Sahin 0:08f763822dd3 367 return ret;
Okan Sahin 0:08f763822dd3 368 }
Okan Sahin 0:08f763822dd3 369
Okan Sahin 0:08f763822dd3 370 int MAX77655::get_cid(void) {
Okan Sahin 0:08f763822dd3 371 char rbuf[1] = {0};
Okan Sahin 0:08f763822dd3 372 int ret;
Okan Sahin 0:08f763822dd3 373
Okan Sahin 0:08f763822dd3 374 ret = read_register(CID, (uint8_t *)&(rbuf));
Okan Sahin 0:08f763822dd3 375 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 376
Okan Sahin 0:08f763822dd3 377 return *rbuf;
Okan Sahin 0:08f763822dd3 378 }
Okan Sahin 0:08f763822dd3 379
Okan Sahin 0:08f763822dd3 380 int MAX77655::set_drv_sbb(decode_drv_sbb_t config)
Okan Sahin 0:08f763822dd3 381 {
Okan Sahin 0:08f763822dd3 382 reg_config_sbb_top_t reg_config_sbb_top;
Okan Sahin 0:08f763822dd3 383
Okan Sahin 0:08f763822dd3 384 SET_BIT_FIELD(CONFIG_SBB_TOP, reg_config_sbb_top, reg_config_sbb_top.bits.drv_sbb, config);
Okan Sahin 0:08f763822dd3 385
Okan Sahin 0:08f763822dd3 386 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 387 }
Okan Sahin 0:08f763822dd3 388
Okan Sahin 0:08f763822dd3 389 int MAX77655::get_drv_sbb(decode_drv_sbb_t *config)
Okan Sahin 0:08f763822dd3 390 {
Okan Sahin 0:08f763822dd3 391 int ret;
Okan Sahin 0:08f763822dd3 392 reg_config_sbb_top_t reg_config_sbb_top = {0};
Okan Sahin 0:08f763822dd3 393
Okan Sahin 0:08f763822dd3 394 ret = read_register(CONFIG_SBB_TOP, (uint8_t *)&(reg_config_sbb_top));
Okan Sahin 0:08f763822dd3 395 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 396
Okan Sahin 0:08f763822dd3 397 *config = (decode_drv_sbb_t)reg_config_sbb_top.bits.drv_sbb;
Okan Sahin 0:08f763822dd3 398
Okan Sahin 0:08f763822dd3 399 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 400 }
Okan Sahin 0:08f763822dd3 401
Okan Sahin 0:08f763822dd3 402 int MAX77655::set_tv_sbb(uint8_t channel, float voltV)
Okan Sahin 0:08f763822dd3 403 {
Okan Sahin 0:08f763822dd3 404 uint8_t value;
Okan Sahin 0:08f763822dd3 405 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a;
Okan Sahin 0:08f763822dd3 406 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a;
Okan Sahin 0:08f763822dd3 407 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a;
Okan Sahin 0:08f763822dd3 408 reg_cnfg_sbb3_a_t reg_cnfg_sbb3_a;
Okan Sahin 0:08f763822dd3 409 float voltmV = voltV * 1000;
Okan Sahin 0:08f763822dd3 410
Okan Sahin 0:08f763822dd3 411 if (voltmV < 500) voltmV = 500;
Okan Sahin 0:08f763822dd3 412 else if (voltmV > 4000) voltmV = 4000;
Okan Sahin 0:08f763822dd3 413
Okan Sahin 0:08f763822dd3 414 value = (voltmV - 500) / 25;
Okan Sahin 0:08f763822dd3 415
Okan Sahin 0:08f763822dd3 416 if (channel == 0) {
Okan Sahin 0:08f763822dd3 417 SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value);
Okan Sahin 0:08f763822dd3 418 }
Okan Sahin 0:08f763822dd3 419 else if (channel == 1) {
Okan Sahin 0:08f763822dd3 420 SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value);
Okan Sahin 0:08f763822dd3 421 }
Okan Sahin 0:08f763822dd3 422 else if (channel == 2) {
Okan Sahin 0:08f763822dd3 423 SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value);
Okan Sahin 0:08f763822dd3 424 }
Okan Sahin 0:08f763822dd3 425 else if (channel == 3) {
Okan Sahin 0:08f763822dd3 426 SET_BIT_FIELD(CNFG_SBB3_A, reg_cnfg_sbb3_a, reg_cnfg_sbb3_a.bits.tv_sbb3, value);
Okan Sahin 0:08f763822dd3 427 }
Okan Sahin 0:08f763822dd3 428 else {
Okan Sahin 0:08f763822dd3 429 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 430 }
Okan Sahin 0:08f763822dd3 431
Okan Sahin 0:08f763822dd3 432 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 433 }
Okan Sahin 0:08f763822dd3 434
Okan Sahin 0:08f763822dd3 435 int MAX77655::get_tv_sbb(uint8_t channel, float *voltV)
Okan Sahin 0:08f763822dd3 436 {
Okan Sahin 0:08f763822dd3 437 int ret;
Okan Sahin 0:08f763822dd3 438 uint8_t bit_value;
Okan Sahin 0:08f763822dd3 439 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
Okan Sahin 0:08f763822dd3 440 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
Okan Sahin 0:08f763822dd3 441 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
Okan Sahin 0:08f763822dd3 442 reg_cnfg_sbb3_a_t reg_cnfg_sbb3_a = {0};
Okan Sahin 0:08f763822dd3 443
Okan Sahin 0:08f763822dd3 444 if (channel == 0) {
Okan Sahin 0:08f763822dd3 445 ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
Okan Sahin 0:08f763822dd3 446 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 447
Okan Sahin 0:08f763822dd3 448 bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
Okan Sahin 0:08f763822dd3 449 }
Okan Sahin 0:08f763822dd3 450 else if (channel == 1) {
Okan Sahin 0:08f763822dd3 451 ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
Okan Sahin 0:08f763822dd3 452 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 453
Okan Sahin 0:08f763822dd3 454 bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
Okan Sahin 0:08f763822dd3 455 }
Okan Sahin 0:08f763822dd3 456 else if (channel == 2) {
Okan Sahin 0:08f763822dd3 457 ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
Okan Sahin 0:08f763822dd3 458 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 459
Okan Sahin 0:08f763822dd3 460 bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
Okan Sahin 0:08f763822dd3 461 }
Okan Sahin 0:08f763822dd3 462 else if (channel == 3) {
Okan Sahin 0:08f763822dd3 463 ret = read_register(CNFG_SBB3_A, (uint8_t *)&(reg_cnfg_sbb3_a));
Okan Sahin 0:08f763822dd3 464 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 465
Okan Sahin 0:08f763822dd3 466 bit_value = (uint8_t)reg_cnfg_sbb3_a.bits.tv_sbb3;
Okan Sahin 0:08f763822dd3 467 }
Okan Sahin 0:08f763822dd3 468 else {
Okan Sahin 0:08f763822dd3 469 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 470 }
Okan Sahin 0:08f763822dd3 471
Okan Sahin 0:08f763822dd3 472 if (bit_value > 141) bit_value = 141;
Okan Sahin 0:08f763822dd3 473 *voltV = (bit_value * 0.025f) + 0.5f;
Okan Sahin 0:08f763822dd3 474
Okan Sahin 0:08f763822dd3 475 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 476 }
Okan Sahin 0:08f763822dd3 477
Okan Sahin 0:08f763822dd3 478 int MAX77655::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb)
Okan Sahin 0:08f763822dd3 479 {
Okan Sahin 0:08f763822dd3 480 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b;
Okan Sahin 0:08f763822dd3 481 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b;
Okan Sahin 0:08f763822dd3 482 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b;
Okan Sahin 0:08f763822dd3 483 reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b;
Okan Sahin 0:08f763822dd3 484
Okan Sahin 0:08f763822dd3 485 if (channel == 0) {
Okan Sahin 0:08f763822dd3 486 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
Okan Sahin 0:08f763822dd3 487 }
Okan Sahin 0:08f763822dd3 488 else if (channel == 1) {
Okan Sahin 0:08f763822dd3 489 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
Okan Sahin 0:08f763822dd3 490 }
Okan Sahin 0:08f763822dd3 491 else if (channel == 2) {
Okan Sahin 0:08f763822dd3 492 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
Okan Sahin 0:08f763822dd3 493 }
Okan Sahin 0:08f763822dd3 494 else if (channel == 3) {
Okan Sahin 0:08f763822dd3 495 SET_BIT_FIELD(CNFG_SBB3_B, reg_cnfg_sbb3_b, reg_cnfg_sbb3_b.bits.ade_sbb3, ade_sbb);
Okan Sahin 0:08f763822dd3 496 }
Okan Sahin 0:08f763822dd3 497 else {
Okan Sahin 0:08f763822dd3 498 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 499 }
Okan Sahin 0:08f763822dd3 500
Okan Sahin 0:08f763822dd3 501 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 502 }
Okan Sahin 0:08f763822dd3 503
Okan Sahin 0:08f763822dd3 504 int MAX77655::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb)
Okan Sahin 0:08f763822dd3 505 {
Okan Sahin 0:08f763822dd3 506 int ret;
Okan Sahin 0:08f763822dd3 507 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:08f763822dd3 508 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:08f763822dd3 509 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:08f763822dd3 510 reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b = {0};
Okan Sahin 0:08f763822dd3 511
Okan Sahin 0:08f763822dd3 512 if (channel == 0) {
Okan Sahin 0:08f763822dd3 513 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
Okan Sahin 0:08f763822dd3 514 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 515
Okan Sahin 0:08f763822dd3 516 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
Okan Sahin 0:08f763822dd3 517 }
Okan Sahin 0:08f763822dd3 518 else if (channel == 1) {
Okan Sahin 0:08f763822dd3 519 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
Okan Sahin 0:08f763822dd3 520 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 521
Okan Sahin 0:08f763822dd3 522 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
Okan Sahin 0:08f763822dd3 523 }
Okan Sahin 0:08f763822dd3 524 else if (channel == 2) {
Okan Sahin 0:08f763822dd3 525 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
Okan Sahin 0:08f763822dd3 526 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 527
Okan Sahin 0:08f763822dd3 528 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
Okan Sahin 0:08f763822dd3 529 }
Okan Sahin 0:08f763822dd3 530 else if (channel == 3) {
Okan Sahin 0:08f763822dd3 531 ret = read_register(CNFG_SBB3_B, (uint8_t *)&(reg_cnfg_sbb3_b));
Okan Sahin 0:08f763822dd3 532 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 533
Okan Sahin 0:08f763822dd3 534 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb3_b.bits.ade_sbb3;
Okan Sahin 0:08f763822dd3 535 }
Okan Sahin 0:08f763822dd3 536 else {
Okan Sahin 0:08f763822dd3 537 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 538 }
Okan Sahin 0:08f763822dd3 539
Okan Sahin 0:08f763822dd3 540 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 541 }
Okan Sahin 0:08f763822dd3 542
Okan Sahin 0:08f763822dd3 543 int MAX77655::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb)
Okan Sahin 0:08f763822dd3 544 {
Okan Sahin 0:08f763822dd3 545 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b;
Okan Sahin 0:08f763822dd3 546 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b;
Okan Sahin 0:08f763822dd3 547 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b;
Okan Sahin 0:08f763822dd3 548 reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b;
Okan Sahin 0:08f763822dd3 549
Okan Sahin 0:08f763822dd3 550 if (channel == 0) {
Okan Sahin 0:08f763822dd3 551 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
Okan Sahin 0:08f763822dd3 552 }
Okan Sahin 0:08f763822dd3 553 else if (channel == 1) {
Okan Sahin 0:08f763822dd3 554 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
Okan Sahin 0:08f763822dd3 555 }
Okan Sahin 0:08f763822dd3 556 else if (channel == 2) {
Okan Sahin 0:08f763822dd3 557 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
Okan Sahin 0:08f763822dd3 558 }
Okan Sahin 0:08f763822dd3 559 else if (channel == 3) {
Okan Sahin 0:08f763822dd3 560 SET_BIT_FIELD(CNFG_SBB3_B, reg_cnfg_sbb3_b, reg_cnfg_sbb3_b.bits.en_sbb3, en_sbb);
Okan Sahin 0:08f763822dd3 561 }
Okan Sahin 0:08f763822dd3 562 else {
Okan Sahin 0:08f763822dd3 563 return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 564 }
Okan Sahin 0:08f763822dd3 565
Okan Sahin 0:08f763822dd3 566 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 567 }
Okan Sahin 0:08f763822dd3 568
Okan Sahin 0:08f763822dd3 569 int MAX77655::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb)
Okan Sahin 0:08f763822dd3 570 {
Okan Sahin 0:08f763822dd3 571 int ret;
Okan Sahin 0:08f763822dd3 572 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:08f763822dd3 573 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:08f763822dd3 574 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:08f763822dd3 575 reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b = {0};
Okan Sahin 0:08f763822dd3 576
Okan Sahin 0:08f763822dd3 577 if (channel == 0) {
Okan Sahin 0:08f763822dd3 578 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
Okan Sahin 0:08f763822dd3 579 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 580
Okan Sahin 0:08f763822dd3 581 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
Okan Sahin 0:08f763822dd3 582 }
Okan Sahin 0:08f763822dd3 583 else if (channel == 1) {
Okan Sahin 0:08f763822dd3 584 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
Okan Sahin 0:08f763822dd3 585 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 586
Okan Sahin 0:08f763822dd3 587 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
Okan Sahin 0:08f763822dd3 588 }
Okan Sahin 0:08f763822dd3 589 else if (channel == 2) {
Okan Sahin 0:08f763822dd3 590 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
Okan Sahin 0:08f763822dd3 591 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 592
Okan Sahin 0:08f763822dd3 593 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
Okan Sahin 0:08f763822dd3 594 }
Okan Sahin 0:08f763822dd3 595 else if (channel == 3) {
Okan Sahin 0:08f763822dd3 596 ret = read_register(CNFG_SBB3_B, (uint8_t *)&(reg_cnfg_sbb3_b));
Okan Sahin 0:08f763822dd3 597 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 598
Okan Sahin 0:08f763822dd3 599 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb3_b.bits.en_sbb3;
Okan Sahin 0:08f763822dd3 600 }
Okan Sahin 0:08f763822dd3 601 else return MAX77655_INVALID_DATA;
Okan Sahin 0:08f763822dd3 602
Okan Sahin 0:08f763822dd3 603 return MAX77655_NO_ERROR;
Okan Sahin 0:08f763822dd3 604 }
Okan Sahin 0:08f763822dd3 605
Okan Sahin 0:08f763822dd3 606 int MAX77655::irq_disable_all()
Okan Sahin 0:08f763822dd3 607 {
Okan Sahin 0:08f763822dd3 608 int ret;
Okan Sahin 0:08f763822dd3 609 uint8_t reg = 0;
Okan Sahin 0:08f763822dd3 610 uint8_t status = 0;
Okan Sahin 0:08f763822dd3 611
Okan Sahin 0:08f763822dd3 612 //Disable Masks in INTM_GLBL
Okan Sahin 0:08f763822dd3 613 ret = write_register(INTM_GLBL, &reg);
Okan Sahin 0:08f763822dd3 614 if (ret != MAX77655_NO_ERROR) return ret;
Okan Sahin 0:08f763822dd3 615
Okan Sahin 0:08f763822dd3 616 // Clear Interrupt Flags in INT_GLBL
Okan Sahin 0:08f763822dd3 617 return read_register(INT_GLBL, &status);
Okan Sahin 0:08f763822dd3 618 }
Okan Sahin 0:08f763822dd3 619
Okan Sahin 0:08f763822dd3 620 void MAX77655::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb)
Okan Sahin 0:08f763822dd3 621 {
Okan Sahin 0:08f763822dd3 622 interrupt_handler_list[id].func = func;
Okan Sahin 0:08f763822dd3 623 interrupt_handler_list[id].cb = cb;
Okan Sahin 0:08f763822dd3 624 }
Okan Sahin 0:08f763822dd3 625
Okan Sahin 0:08f763822dd3 626 void MAX77655::post_interrupt_work()
Okan Sahin 0:08f763822dd3 627 {
Okan Sahin 0:08f763822dd3 628 int ret;
Okan Sahin 0:08f763822dd3 629 uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0;
Okan Sahin 0:08f763822dd3 630
Okan Sahin 0:08f763822dd3 631 while (true) {
Okan Sahin 0:08f763822dd3 632
Okan Sahin 0:08f763822dd3 633 ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
Okan Sahin 0:08f763822dd3 634 // Check Interrupt Flags in INT_GLBL0
Okan Sahin 0:08f763822dd3 635 ret = read_register(INT_GLBL, &reg);
Okan Sahin 0:08f763822dd3 636 if (ret != MAX77655_NO_ERROR) return;
Okan Sahin 0:08f763822dd3 637
Okan Sahin 0:08f763822dd3 638 ret = read_register(INTM_GLBL, &inten);
Okan Sahin 0:08f763822dd3 639 if (ret != MAX77655_NO_ERROR) return;
Okan Sahin 0:08f763822dd3 640
Okan Sahin 0:08f763822dd3 641 not_inten = ~inten; // 0 means unmasked.
Okan Sahin 0:08f763822dd3 642
Okan Sahin 0:08f763822dd3 643 for (int i = 0; i <= INT_GLBL_SBB3_FM; i++) {
Okan Sahin 0:08f763822dd3 644 mask = (1 << i);
Okan Sahin 0:08f763822dd3 645 /*
Okan Sahin 0:08f763822dd3 646 ***************************************************
Okan Sahin 0:08f763822dd3 647 This is special case. when nEN is pulled high, the
Okan Sahin 0:08f763822dd3 648 on/off controller initiates a power-down sequence and
Okan Sahin 0:08f763822dd3 649 goes to shutdown mode.
Okan Sahin 0:08f763822dd3 650 ***************************************************
Okan Sahin 0:08f763822dd3 651 */
Okan Sahin 0:08f763822dd3 652 if (((reg & mask) && (not_inten & mask))
Okan Sahin 0:08f763822dd3 653 || ((reg & (1 << INT_GLBL_nEN_F)) && (i == INT_GLBL_nEN_F))
Okan Sahin 0:08f763822dd3 654 || ((reg & (1 << INT_GLBL_nEN_R)) && (i == INT_GLBL_nEN_R))) {
Okan Sahin 0:08f763822dd3 655 if (interrupt_handler_list[i].func != NULL) {
Okan Sahin 0:08f763822dd3 656 interrupt_handler_list[i]
Okan Sahin 0:08f763822dd3 657 .func(interrupt_handler_list[i].cb);
Okan Sahin 0:08f763822dd3 658 }
Okan Sahin 0:08f763822dd3 659 }
Okan Sahin 0:08f763822dd3 660 }
Okan Sahin 0:08f763822dd3 661 }
Okan Sahin 0:08f763822dd3 662 }
Okan Sahin 0:08f763822dd3 663
Okan Sahin 0:08f763822dd3 664 void MAX77655::interrupt_handler()
Okan Sahin 0:08f763822dd3 665 {
Okan Sahin 0:08f763822dd3 666 post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
Okan Sahin 0:08f763822dd3 667 }
Okan Sahin 0:08f763822dd3 668