Maxim Integrated
MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver
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MAX77643_2_regs.h
00001 /******************************************************************************* 00002 * Copyright(C) Analog Devices Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files(the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Analog Devices Inc. 00023 * shall not be used except as stated in the Analog Devices Inc. 00024 * Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Analog Devices Inc.retains all ownership rights. 00030 ******************************************************************************* 00031 */ 00032 00033 #ifndef MAX77643_2_REGS_H_ 00034 #define MAX77643_2_REGS_H_ 00035 00036 /** 00037 * @brief INT_GLBL0 Register 00038 * 00039 * Address : 0x00 00040 */ 00041 typedef union { 00042 unsigned char raw; 00043 struct { 00044 unsigned char gpi0_f : 1; /**< GPI Falling Interrupt. Bit 0. 00045 Note that "GPI" refers to the GPIO programmed to be an input. 00046 0 = No GPI falling edges have occurred since the last time this bit was read. 00047 1 = A GPI falling edge has occurred since the last time this bit was read. */ 00048 unsigned char gpi0_r : 1; /**< GPI Rising Interrupt. Bit 1. 00049 Note that "GPI" refers to the GPIO programmed to be an input. 00050 0 = No GPI rising edges have occurred since the last time this bit was read. 00051 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00052 unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 2. 00053 0 = No nEN falling edges have occurred since the last time this bit was read. 00054 1 = A nEN falling edge as occurred since the last time this bit was read. */ 00055 unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 3. 00056 0 = No nEN rising edges have occurred since the last time this bit was read. 00057 1 = A nEN rising edge as occurred since the last time this bit was read. */ 00058 unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 4. 00059 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. 00060 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */ 00061 unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 5. 00062 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. 00063 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */ 00064 unsigned char dod_r : 1; /**< LDO Dropout Detector Rising Interrupt. Bit 6. 00065 0 = The LDO has not detected dropout since the last time this bit was read. 00066 1 = The LDO has detected dropout since the last time this bit was read. */ 00067 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ 00068 } bits; 00069 } reg_int_glbl0_t; 00070 00071 /** 00072 * @brief INT_GLBL1 Register 00073 * 00074 * Address : 0x01 00075 */ 00076 typedef union { 00077 unsigned char raw; 00078 struct { 00079 unsigned char gpi1_f : 1; /**< GPI Falling Interrupt. Bit 0. 00080 Note that "GPI" refers to the GPIO programmed to be an input. 00081 0 = No GPI falling edges have occurred since the last time this bit was read. 00082 1 = A GPI falling edge has occurred since the last time this bit was read. */ 00083 unsigned char gpi1_r : 1; /**< GPI Rising Interrupt. Bit 1. 00084 Note that "GPI" refers to the GPIO programmed to be an input. 00085 0 = No GPI rising edges have occurred since the last time this bit was read. 00086 1 = A GPI rising edge has occurred since the last time this bit was read. */ 00087 unsigned char sbb0_f : 1; /**< SBB0 Fault Indicator. Bit 2. 00088 0 = No fault has occurred on SBB0 since the last time this bit was read. 00089 1 = SBB0 has fallen out of regulation since the last time this bit was read. */ 00090 unsigned char sbb1_f : 1; /**< SBB1 Fault Indicator. Bit 3. 00091 0 = No fault has occurred on SBB1 since the last time this bit was read. 00092 1 = SBB1 has fallen out of regulation since the last time this bit was read. */ 00093 unsigned char sbb2_f : 1; /**< SBB2 Fault Indicator. Bit 4. 00094 0 = No fault has occurred on SBB2 since the last time this bit was read. 00095 1 = SBB2 has fallen out of regulation since the last time this bit was read. */ 00096 unsigned char ldo_f : 1; /**< LDO0 Fault Interrupt. Bit 5. 00097 0 = No fault has occurred on LDO0 since the last time this bit was read. 00098 1 = LDO0 has fallen out of regulation since the last time this bit was read. */ 00099 unsigned char rsvd : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */ 00100 } bits; 00101 } reg_int_glbl1_t; 00102 00103 /** 00104 * @brief ERCFLAG Register 00105 * 00106 * Address : 0x02 00107 */ 00108 typedef union { 00109 unsigned char raw; 00110 struct { 00111 unsigned char tovld : 1; /**< Thermal Overload. Bit 0. 00112 0 = Thermal overload has not occurred since the last read of this register. 00113 1 = Thermal overload has occurred since the list read of this register. 00114 This indicates that the junction temperature has exceeded 165ºC. */ 00115 unsigned char inovlo : 1; /**< IN Domain Overvoltage Lockout. Bit 1. 00116 0 = The IN domain overvoltage lockout has not occurred since the last read of this register. 00117 1 = The IN domain overvoltage lockout has occurred since the last read of this register */ 00118 unsigned char inuvlo : 1; /**< IN Domain Undervoltage Lockout. Bit 2. 00119 0 = The IN domain undervoltage lockout has not occurred since the last read of this register. 00120 1 = The IN domain undervoltage lockout has occurred since the last read of this register */ 00121 unsigned char mrst_f : 1; /**< Manual Reset Timer. Bit 3. 00122 0 = A Manual Reset has not occurred since this last read of this register. 00123 1 = A Manual Reset has occurred since this last read of this register. */ 00124 unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4. 00125 0 = The SFT_OFF function has not occurred since the last read of this register. 00126 1 = The SFT_OFF function has occurred since the last read of this register. */ 00127 unsigned char sft_crst_f : 1; /**< Software Cold Reset Flag. Bit 5. 00128 0 = The software cold reset has not occurred since the last read of this register. 00129 1 = The software cold reset has occurred since the last read of this register. */ 00130 unsigned char wdt_exp_f : 1; /**< Watchdog Timer OFF or RESET Flag. Bit 6. 00131 This bit sets when the watchdog timer expires and causes a power-off or a reset; based on WDT_MODE bitfield setting. 00132 0 = Watchdog timer has not caused a power-off or reset since the last time this bit was read. 00133 1 = Watchdog timer has expired and caused a power-off or reset since the last time this bit was read. */ 00134 unsigned char sbb_fault_f : 1; /**< SBBx Fault and Shutdown Flag. Bit 7. 00135 This bit sets when a SBBx fault and consequent SBBx shutdown occurs. 00136 0 = No SBB shutdown occurred since the last time this bit was read. 00137 1 = SBBx fault and SBB shutdown occurred since the last time this bit was read. */ 00138 } bits; 00139 } reg_ercflag_t; 00140 00141 /** 00142 * @brief STAT_GLBL Register 00143 * 00144 * Address : 0x03 00145 */ 00146 typedef union { 00147 unsigned char raw; 00148 struct { 00149 unsigned char stat_irq : 1; /**< Software Version of the nIRQ MOSFET gate drive. Bit 0. 00150 0 = unmasked gate drive is logic low 00151 1 = unmasked gate drive is logic high */ 00152 unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 1. 00153 0 = nEN is not active (logic high) 00154 1 = nEN is active (logic low) */ 00155 unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 2. 00156 0 = The junction temperature is less than TJAL1 00157 1 = The junction temperature is greater than TJAL1 */ 00158 unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 3. 00159 0 = The junction temperature is less than TJAL2 00160 1 = The junction temperature is greater than TJAL2 */ 00161 unsigned char dod_s : 1; /**< LDO1 Dropout Detector Rising Status. Bit 4. 00162 0 = LDO1 is not in dropout 00163 1 = LDO1 is in dropout */ 00164 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 5. */ 00165 unsigned char bok : 1; /**< BOK Interrupt Status. Bit 6. 00166 0 = Main Bias is not ready. 00167 1 = Main Bias enabled and ready. */ 00168 unsigned char didm : 1; /**< Device Identification Bits for Metal Options. Bit 7. 00169 0 = MAX77643_2 00170 1 = Reserved */ 00171 } bits; 00172 } reg_stat_glbl_t; 00173 00174 /** 00175 * @brief INTM_GLBL0 Register 00176 * 00177 * Address : 0x04 00178 */ 00179 typedef union { 00180 unsigned char raw; 00181 struct { 00182 unsigned char gpi0_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. 00183 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00184 nIRQ goes high when all interrupt bits are cleared. 00185 1 = Masked. nIRQ does not go low due to GPI_F. */ 00186 unsigned char gpi0_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. 00187 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00188 nIRQ goes high when all interrupt bits are cleared. 00189 1 = Masked. nIRQ does not go low due to GPI_R. */ 00190 unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 2. 00191 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. 00192 nIRQ goes high when all interrupt bits are cleared. 00193 1 = Masked. nIRQ does not go low due to nEN_F. */ 00194 unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 3. 00195 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. 00196 nIRQ goes high when all interrupt bits are cleared. 00197 1 = Masked. nIRQ does not go low due to nEN_R. */ 00198 unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 4. 00199 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. 00200 nIRQ goes high when all interrupt bits are cleared. 00201 1 = Masked. nIRQ does not go low due to TJAL1_R. */ 00202 unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 5. 00203 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. 00204 nIRQ goes high when all interrupt bits are cleared. 00205 1 = Masked. nIRQ does not go low due to TJAL2_R. */ 00206 unsigned char dod_rm : 1; /**< LDO Dropout Detector Rising Interrupt Mask. Bit 6. 00207 0 = Unmasked. If DOD1_R goes from 0 to 1, then nIRQ goes low. 00208 nIRQ goes high when all interrupt bits are cleared. 00209 1 = Masked. nIRQ does not go low due to DOD1_R. */ 00210 unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7. */ 00211 } bits; 00212 } reg_intm_glbl0_t; 00213 00214 /** 00215 * @brief INTM_GLBL1 Register 00216 * 00217 * Address : 0x05 00218 */ 00219 typedef union { 00220 unsigned char raw; 00221 struct { 00222 unsigned char gpi1_fm : 1; /**< GPI Falling Interrupt Mask. Bit 0. 00223 0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. 00224 nIRQ goes high when all interrupt bits are cleared. 00225 1 = Masked. nIRQ does not go low due to GPI_F. */ 00226 unsigned char gpi1_rm : 1; /**< GPI Rising Interrupt Mask. Bit 1. 00227 0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. 00228 nIRQ goes high when all interrupt bits are cleared. 00229 1 = Masked. nIRQ does not go low due to GPI_R. */ 00230 unsigned char sbb0_fm : 1; /**< SBB0 Fault Interrupt Mask. Bit 2. 00231 0 = Unmasked. If SBB0_F goes from 0 to 1, then nIRQ goes low. 00232 nIRQ goes high when all interrupt bits are cleared.. 00233 1 = Masked. nIRQ does not go low due to SBB0_F. */ 00234 unsigned char sbb1_fm : 1; /**< SBB1 Fault Interrupt Mask. Bit 3. 00235 0 = Unmasked. If SBB1_F goes from 0 to 1, then nIRQ goes low. 00236 nIRQ goes high when all interrupt bits are cleared.. 00237 1 = Masked. nIRQ does not go low due to SBB1_F. */ 00238 unsigned char sbb2_fm : 1; /**< SBB2 Fault Interrupt Mask. Bit 4. 00239 0 = Unmasked. If SBB2_F goes from 0 to 1, then nIRQ goes low. 00240 nIRQ goes high when all interrupt bits are cleared.. 00241 1 = Masked. nIRQ does not go low due to SBB2_F. */ 00242 unsigned char ldo_m : 1; /**< LDO0 Fault Interrupt. Bit 5. 00243 0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. 00244 nIRQ goes high when all interrupt bits are cleared. 00245 1 = Masked. nIRQ does not go low due to LDO0_F. */ 00246 unsigned char rsvd : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */ 00247 } bits; 00248 } reg_intm_glbl1_t; 00249 00250 /** 00251 * @brief CNFG_GLBL0 Register 00252 * 00253 * Address : 0x06 00254 */ 00255 typedef union { 00256 unsigned char raw; 00257 struct { 00258 unsigned char sft_ctrl : 2; /**< Software Reset Functions. Bit 1:0. 00259 0b00 = No Action 00260 0b01 = Software Cold Reset (SFT_CRST). The device powers down, resets, and the powers up again. 00261 0b10 = Software Off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. 00262 0b11 = Auto Wake Up (SFT_AUTO). */ 00263 unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 2. 00264 0 = 500μs Debounce 00265 1 = 30ms Debounce */ 00266 unsigned char nen_mode : 2; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 4:3. 00267 0b00 = Push-button mode 00268 0b01 = Slide-switch mode 00269 0b10 = Logic mode 00270 0b11 = Reserved */ 00271 unsigned char sbia_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 5. 00272 0 = Main Bias requested to be in Normal-Power Mode by software. 00273 1 = Main Bias request to be in Low-Power Mode by software. */ 00274 unsigned char t_mrst : 1; /**< Sets the Manual Reset Time (tMRST). Bit 6. 00275 0 = 8s 00276 1 = 4s */ 00277 unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 7. 00278 0 = Strong internal nEN pullup (200kΩ) 00279 1 = Weak internal nEN pullup (10MΩ) */ 00280 } bits; 00281 } reg_cnfg_glbl0_t; 00282 00283 /** 00284 * @brief CNFG_GLBL1 Register 00285 * 00286 * Address : 0x07 00287 */ 00288 typedef union { 00289 unsigned char raw; 00290 struct { 00291 unsigned char auto_wkt : 2; /**< Auto Wake-Up Timer. Bit 1:0. 00292 0b00 = 100ms Auto Wake-up Time 00293 0b01 = 200ms Auto Wake-up Time 00294 0b10 = 500ms Auto Wake-up Time 00295 0b11 = 1000ms Auto Wake-up Time */ 00296 unsigned char sbb_f_shutdn : 1; /**< SBB Shutdown from SBB Fault. Bit 2. 00297 0 = 500μs Debounce 00298 1 = 30ms Debounce */ 00299 unsigned char rsvd : 5; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care */ 00300 } bits; 00301 } reg_cnfg_glbl1_t; 00302 00303 /** 00304 * @brief CNFG_GPIO0 Register 00305 * 00306 * Address : 0x08 00307 */ 00308 typedef union { 00309 unsigned char raw; 00310 struct { 00311 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00312 0 = General purpose output (GPO) 00313 1 = General purpose input (GPI) */ 00314 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00315 0 = Input logic low 00316 1 = Input logic high */ 00317 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00318 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00319 0 = Open-Drain 00320 1 = Push-Pull */ 00321 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00322 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00323 0 = GPIO is output is logic low 00324 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00325 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00326 0 = no debounce 00327 1 = 30ms debounce */ 00328 unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO0. Bit 5. 00329 0 = Standard GPIO. 00330 1 = Active-high input, Force USB Suspend (FUS). FUS is only active if the FUS_M bit is set to 0. */ 00331 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */ 00332 } bits; 00333 } reg_cnfg_gpio0_t; 00334 00335 /** 00336 * @brief CNFG_GPIO1 Register 00337 * 00338 * Address : 0x09 00339 */ 00340 typedef union { 00341 unsigned char raw; 00342 struct { 00343 unsigned char gpo_dir : 1; /**< GPIO Direction. Bit 0. 00344 0 = General purpose output (GPO) 00345 1 = General purpose input (GPI) */ 00346 unsigned char gpo_di : 1; /**< GPIO Digital Input Value. Bit 1. 00347 0 = Input logic low 00348 1 = Input logic high */ 00349 unsigned char gpo_drv : 1; /**< General Purpose Output Driver Type. Bit 2. 00350 This bit is a don't care when DIR = 1 (configured as input) When set for GPO (DIR = 0): 00351 0 = Open-Drain 00352 1 = Push-Pull */ 00353 unsigned char gpo_do : 1; /**< General Purpose Output Data Output. Bit 3. 00354 This bit is a don't care when DIR = 1 (configured as input). When set for GPO (DIR = 0): 00355 0 = GPIO is output is logic low 00356 1 = GPIO is output logic high when set as push-pull output (DRV = 1). */ 00357 unsigned char dben_gpi : 1; /**< General Purpose Input Debounce Timer Enable. Bit 4. 00358 0 = no debounce 00359 1 = 30ms debounce */ 00360 unsigned char alt_gpio : 1; /**< Alternate Mode Enable for GPIO1. Bit 5. 00361 0 = Standard GPIO. 00362 1 = Active-high output of SBB2's Flexible Power Sequencer (FPS) slot. */ 00363 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. 00364 Unutilized bit. Write to 0. Reads are don't care. */ 00365 } bits; 00366 } reg_cnfg_gpio1_t; 00367 00368 /** 00369 * @brief CID Register 00370 * 00371 * Address : 0x10 00372 */ 00373 typedef union { 00374 unsigned char raw; 00375 struct { 00376 unsigned char cid : 5; /**< Chip Identification Code. Bit 4:0. 00377 The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */ 00378 unsigned char : 3; /**< Bit 7:5. */ 00379 } bits; 00380 } reg_cid_t; 00381 00382 /** 00383 * @brief CNFG_WDT Register 00384 * 00385 * Address : 0x17 00386 */ 00387 typedef union { 00388 unsigned char raw; 00389 struct { 00390 unsigned char wdt_lock : 1; /**< Factory-Set Safety Bit for the Watchdog Timer. Bit 0. 00391 0 = Watchdog timer can be enabled and disabled with WDT_EN. 00392 1 = Watchdog timer can not be disabled with WDT_EN. 00393 However, WDT_EN can still be used to enable the watchdog timer. */ 00394 unsigned char wdt_en : 1; /**< Watchdog Timer Enable. Bit 1. 00395 0 = Watchdog timer is not enabled. 00396 1 = Watchdog timer is enabled. The timer will expire if not reset by setting WDT_CLR. */ 00397 unsigned char wdt_clr : 1; /**< Watchdog Timer Clear Control. Bit 2. 00398 0 = Watchdog timer period is not reset. 00399 1 = Watchdog timer is reset back to tWD. */ 00400 unsigned char wdt_mode : 1; /**< Watchdog Timer Expired Action. Bit 3. 00401 0 = Watchdog timer expire causes power-off. 00402 1 = Watchdog timer expire causes power-reset. */ 00403 unsigned char wdt_per : 2; /**< Watchdog Timer Period. Bit 5:4. 00404 0b00 = 16 seconds 0b01 = 32 seconds 00405 0b10 = 64 seconds 0b11 = 128 seconds. */ 00406 unsigned char rsvd : 2; /**< Reserved. Bit 7:6. 00407 Unutilized bit. Write to 0. Reads are don't care. */ 00408 } bits; 00409 } reg_cnfg_wdt_t; 00410 00411 /** 00412 * @brief CNFG_SBB_TOP 00413 * 00414 * Address : 0x28 00415 */ 00416 typedef union { 00417 unsigned char raw; 00418 struct 00419 { 00420 unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0. 00421 0b00 = Fastest transition time 00422 0b01 = A little slower than 0b00 00423 0b10 = A little slower than 0b01 00424 0b11 = A little slower than 0b10 */ 00425 unsigned char : 5; /**< Bit 6:2.*/ 00426 unsigned char dis_lpm : 1; /**< Disables the automatic Low Power Mode for Each SIMO Channel. Bit 7. 00427 0b0 = Automatic Low Power Mode for each SIMO channel 00428 0b1 = Disable LPM feature for each SIMO channel */ 00429 } bits; 00430 } reg_cnfg_sbb_top_t; 00431 00432 /** 00433 * @brief CNFG_SBB0_A 00434 * 00435 * Address : 0x29 00436 */ 00437 typedef union { 00438 unsigned char raw; 00439 struct 00440 { 00441 unsigned char tv_sbb0 : 8; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0. 00442 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00443 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 00444 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 00445 ... 00446 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 00447 0xC8 to 0xFF = 5.500V */ 00448 } bits; 00449 } reg_cnfg_sbb0_a_t; 00450 00451 /** 00452 * @brief CNFG_SBB0_B 00453 * 00454 * Address : 0x2A 00455 */ 00456 typedef union { 00457 unsigned char raw; 00458 struct 00459 { 00460 unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0, 00461 selecting either an FPS slot the channel powers-up and powers-down in 00462 or whether the channel is forced on or off. Bit 2:0. 00463 0b000 = FPS slot 0 0b001 = FPS slot 1 00464 0b010 = FPS slot 2 0b011 = FPS slot 3 00465 0b100 = Off irrespective of FPS 00466 0b101 = same as 0b100 0b110 = On irrespective of FPS 00467 0b111 = same as 0b110 */ 00468 unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3. 00469 0 = The active discharge function is disabled. 00470 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00471 1 = The active discharge function is enabled. 00472 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00473 unsigned char ip_sbb0 : 2; /**< SIMO Buck-Boost Channel 0 Peak Current Limit. Bit 5:4 00474 0b00 = 1.000A 0b01 = 0.750A 00475 0b10 = 0.500A 0b11 = 0.333A*/ 00476 unsigned char op_mode0 : 2; /**< Operation mode of SBB0. Bit 6. 00477 0b00 = Automatic 00478 0b01 = Buck mode 00479 0b10 = Boost mode 00480 0b11 = Buck-boost mode*/ 00481 } bits; 00482 } reg_cnfg_sbb0_b_t; 00483 00484 /** 00485 * @brief CNFG_SBB1_A 00486 * 00487 * Address : 0x2B 00488 */ 00489 typedef union { 00490 unsigned char raw; 00491 struct 00492 { 00493 unsigned char tv_sbb1 : 8; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 7:0. 00494 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00495 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 00496 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 00497 ... 00498 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 00499 0xC8 to 0xFF = 5.500V */ 00500 } bits; 00501 } reg_cnfg_sbb1_a_t; 00502 00503 /** 00504 * @brief CNFG_SBB1_B 00505 * 00506 * Address : 0x3C 00507 */ 00508 typedef union { 00509 unsigned char raw; 00510 struct 00511 { 00512 unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1, 00513 selecting either an FPS slot the channel powers-up and powers-down in 00514 or whether the channel is forced on or off. Bit 2:0. 00515 0b000 = FPS slot 0 0b001 = FPS slot 1 00516 0b010 = FPS slot 2 0b011 = FPS slot 3 00517 0b100 = Off irrespective of FPS 00518 0b101 = same as 0b100 0b110 = On irrespective of FPS 00519 0b111 = same as 0b110 */ 00520 unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3. 00521 0 = The active discharge function is disabled. 00522 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00523 1 = The active discharge function is enabled. 00524 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00525 unsigned char ip_sbb1 : 2; /**< SIMO Buck-Boost Channel 1 Peak Current Limit. Bit 5:4. 00526 0b00 = 1.000A 0b01 = 0.750A 00527 0b10 = 0.500A 0b11 = 0.333A*/ 00528 unsigned char op_mode1 : 2; /**< Operation mode of SBB1. Bit 7:6. 00529 0b00 = Automatic 00530 0b01 = Buck mode 00531 0b10 = Boost mode 00532 0b11 = Buck-boost mode*/ 00533 } bits; 00534 } reg_cnfg_sbb1_b_t; 00535 00536 /** 00537 * @brief CNFG_SBB2_A 00538 * 00539 * Address : 0x2D 00540 */ 00541 typedef union { 00542 unsigned char raw; 00543 struct 00544 { 00545 unsigned char tv_sbb2 : 8; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 7:0. 00546 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00547 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 00548 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 00549 ... 00550 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 00551 0xC8 to 0xFF = 5.500V */ 00552 } bits; 00553 } reg_cnfg_sbb2_a_t; 00554 00555 /** 00556 * @brief CNFG_SBB2_B 00557 * 00558 * Address : 0x2E 00559 */ 00560 typedef union { 00561 unsigned char raw; 00562 struct 00563 { 00564 unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2, 00565 selecting either an FPS slot the channel powers-up and powers-down in 00566 or whether the channel is forced on or off. Bit 2:0. 00567 0b000 = FPS slot 0 0b001 = FPS slot 1 00568 0b010 = FPS slot 2 0b011 = FPS slot 3 00569 0b100 = Off irrespective of FPS 00570 0b101 = same as 0b100 0b110 = On irrespective of FPS 00571 0b111 = same as 0b110 */ 00572 unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3. 00573 0 = The active discharge function is disabled. 00574 When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 00575 1 = The active discharge function is enabled. 00576 When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */ 00577 unsigned char ip_sbb2 : 2; /**< SIMO Buck-Boost Channel 2 Peak Current Limit. Bit 5:4. 00578 0b00 = 1.000A 0b01 = 0.750A 00579 0b10 = 0.500A 0b11 = 0.333A*/ 00580 unsigned char op_mode2 : 2; /**< Operation mode of SBB2. Bit 7:6. 00581 0b00 = Automatic 00582 0b01 = Buck mode 00583 0b10 = Boost mode 00584 0b11 = Buck-boost mode*/ 00585 } bits; 00586 } reg_cnfg_sbb2_b_t; 00587 00588 /** 00589 * @brief CNFG_DVS_SBB0_A 00590 * 00591 * Address : 0x2F 00592 */ 00593 typedef union { 00594 unsigned char raw; 00595 struct 00596 { 00597 unsigned char tv_sbb0_dvs : 8; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0. 00598 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00599 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 00600 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 00601 ... 00602 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 00603 0xC8 to 0xFF = 5.500V */ 00604 } bits; 00605 } reg_cnfg_dvs_sbb0_a_t; 00606 00607 /** 00608 * @brief CNFG_LDO0_A 00609 * 00610 * Address : 0x38 00611 */ 00612 typedef union { 00613 unsigned char raw; 00614 struct 00615 { 00616 unsigned char tv_ldo0 : 7; /**< LDO0 Target Output Voltage. Bit 6:0. 00617 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 00618 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 00619 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V 00620 ... 00621 0x7E = 3.650V 00622 0x7F = 3.675V 00623 When TV_LDO[7] = 0, TV_LDO[6:0] sets the 00624 LDO's output voltage range from 0.5V to 3.675V. 00625 When TV_LDO[7] = 1, TV_LDO[6:0] sets the 00626 LDO's output voltage from 1.825V to 5V. */ 00627 unsigned char tv_ofs_ldo : 1; /**< LDO0 Output Voltage. Bit7. 00628 This bit applies a 1.325V offset to the output voltage of the LDO0. 00629 0b0 = No Offset, 0b1 = 1.325V Offset 00630 */ 00631 00632 } bits; 00633 } reg_cnfg_ldo0_a_t; 00634 00635 /** 00636 * @brief CNFG_LDO0_B 00637 * 00638 * Address : 0x39 00639 */ 00640 typedef union { 00641 unsigned char raw; 00642 struct 00643 { 00644 unsigned char en_ldo : 3; /**< Enable Control for LDO0, 00645 selecting either an FPS slot the channel powers-up and 00646 powersdown in or whether the channel is forced on or off. Bit 2:0. 00647 0b000 = FPS slot 0 0b001 = FPS slot 1 00648 0b010 = FPS slot 2 0b011 = FPS slot 3 00649 0b100 = Off irrespective of FPS 00650 0b101 = same as 0b100 0b110 = On irrespective of FPS 00651 0b111 = same as 0b110 */ 00652 unsigned char ade_ldo : 1; /**< LDO0 Active-Discharge Enable. Bit 3. 00653 0 = The active discharge function is disabled. 00654 1 = The active discharge function is enabled.*/ 00655 unsigned char ldo_md : 1; /**< Operation Mode of LDO0. Bit 4. 00656 0b0 = Low dropout linear regulator (LDO) mode 00657 0b1 = Load switch (LSW) mode*/ 00658 unsigned char rsvd : 3; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. */ 00659 } bits; 00660 } reg_cnfg_ldo0_b_t; 00661 00662 #endif /* MAX77643_2_REGS_H_ */
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