Maxim Integrated
MAX7032 Transceiver Mbed Driver
Revision 0:65766360f6b9, committed 2021-08-02
- Comitter:
- Sinan Divarci
- Date:
- Mon Aug 02 16:42:52 2021 +0300
- Commit message:
- initial commit
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/Max7032.cpp Mon Aug 02 16:42:52 2021 +0300
@@ -0,0 +1,1891 @@
+/*******************************************************************************
+ * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc.shall not be used except as stated in the Maxim Integrated
+ * Products, Inc.Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc.retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <iostream>
+#include "Max7032.h"
+#include "math.h"
+
+using namespace std;
+
+const uint8_t rx_quick_start[Q_START_CONF_LEN] = {0xFA,0x04,0x00,0x02,0x00,0xB0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+const uint8_t tx_quick_start[Q_START_CONF_LEN] = {0xFE,0x04,0x40,0x02,0x00,0xB0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89,0xB5,0x00,0x00};
+
+MAX7032::MAX7032(SPI *spi, DigitalOut *cs, DigitalOut *powerPin, PinName dataPin, DigitalOut *dioPin, DigitalOut *trxPin)
+{
+ operation_mode = UNINITIALIZED;
+
+ if (spi == NULL || cs == NULL || powerPin == NULL || dataPin == NULL || dioPin == NULL || trxPin == NULL)
+ return;
+
+ max7032_reg_map_t reg;
+
+ reg_map = ®
+ spi_handler = spi;
+ ssel = cs;
+ power_pin = powerPin;
+ data_pin = dataPin;
+ dio = dioPin;
+ trx_pin = trxPin;
+ preset_mode = 0;
+
+ encoding = Manchester;
+ f_xtal = 16.0f;
+ f_rf = 315.0f;
+ fsk_dev = 0.05f;
+
+ data_rate = 1.0f;
+ data_read = NULL;
+ data_send = NULL;
+
+ if (initial_programming() < 0)
+ return;
+
+ operation_mode = INITIALIZED;
+}
+
+MAX7032::MAX7032(SPI *spi, DigitalOut *powerPin, PinName dataPin, DigitalOut *dioPin, DigitalOut *trxPin)
+{
+ operation_mode = UNINITIALIZED;
+
+ if (spi == NULL || powerPin == NULL || dataPin == NULL || dioPin == NULL || trxPin == NULL)
+ return;
+
+ max7032_reg_map_t reg;
+
+ reg_map = ®
+ spi_handler = spi;
+ ssel = NULL;
+ power_pin = powerPin;
+ data_pin = dataPin;
+ dio = dioPin;
+ trx_pin = trxPin;
+ preset_mode = 0;
+
+ encoding = Manchester;
+ f_xtal = 16.0f;
+ f_rf = 315.0f;
+ fsk_dev = 0.05f;
+
+ data_rate = 1.0f;
+ data_read = NULL;
+ data_send = NULL;
+
+ if (initial_programming() < 0)
+ return;
+
+ operation_mode = INITIALIZED;
+}
+
+MAX7032::~MAX7032()
+{
+ if(data_read != NULL)
+ delete data_read;
+
+ if(data_send != NULL)
+ delete data_send;
+}
+
+int MAX7032::read_register(uint8_t reg, uint8_t *value)
+{
+
+ int rtn_val = 0;
+//Since 3-wire spi is not supported by mbed, the read_register function must be implemented by the user.
+//Here you can find an implemented read_register function for the max32630fthr.
+#if defined(TARGET_MAX32630FTHR)
+ if (value == NULL) {
+ return -1;
+ }
+
+ if (this->reg_map == NULL) {
+ return -1;
+ }
+
+ spi_handler->format(8,0);
+ spi_handler->frequency(400000);
+
+ if (ssel != NULL) {
+ *ssel = 0;
+ }
+ spi_handler->write((uint8_t)0x80 | reg); // Set R/W bit 1 for reading
+ spi_handler->write(0x00); // dummy write command for waiting data read
+
+ MAX7032_SPI->mstr_cfg |= MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE;
+
+ // Disable SPI for General Control Configuration
+ MAX7032_SPI->gen_ctrl = 0;
+ MAX7032_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (1 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header
+
+ MAX7032_SPI->simple_headers &= 0x0000FFFF;
+ MAX7032_SPI->simple_headers |= 0x2016<<16;
+ MAX7032_SPI->gen_ctrl |=MXC_F_SPIM_GEN_CTRL_START_RX_ONLY;
+
+ if (ssel != NULL) {
+ *ssel = 1;
+ wait_us(5);
+ *ssel = 0;
+ }
+
+ // Enable the SPI
+ MAX7032_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN;
+
+ volatile mxc_spim_fifo_regs_t *fifo;
+
+ fifo = MXC_SPIM_GET_SPIM_FIFO(MXC_SPIM_GET_IDX(MAX7032_SPI));
+
+ int avail = ((MAX7032_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
+
+ Timer *t = NULL;
+ t = new Timer();
+
+ t->start();
+
+ while (avail < 1) {
+ if (t->read_ms() > 1000) {
+ rtn_val = -1;
+ break;
+ } else {
+ avail = ((MAX7032_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
+ }
+ }
+
+ t->stop();
+
+ *(value++) = fifo->rslts_8[0];
+
+ while (MAX7032_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) {
+ fifo->rslts_8[0];
+ }
+
+ MAX7032_SPI->gen_ctrl = 0;
+ MAX7032_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (0 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header
+
+ MAX7032_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN;
+
+ if (ssel != NULL) {
+ *ssel = 1;
+ }
+
+ t->~Timer();
+ delete t;
+#else
+ if (value == NULL) {
+ return -1;
+ }
+
+ if (this->reg_map == NULL) {
+ return -2;
+ }
+
+ spi_handler->format(8,0);
+ spi_handler->frequency(400000);
+
+ if (ssel != NULL) {
+ *ssel = 0;
+ }
+ spi_handler->write((uint8_t)0x80 | reg);
+
+ spi_handler->write(0x00); // dummy write command for waiting data read
+
+ *(value++) = spi_handler->write(0x00); // read back data bytes
+
+ if (ssel != NULL) {
+ *ssel = 1;
+ }
+#endif
+ *dio = 0;
+ return rtn_val;
+}
+
+int MAX7032::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
+{
+ int rtn_val = -1;
+ uint8_t local_data[1 + len];
+
+ if (value == NULL) {
+ return -1;
+ }
+
+ memcpy(&local_data[0], value, len);
+
+ if (ssel != NULL) {
+ *ssel = 0;
+ }
+
+ rtn_val = spi_handler->write(0x40 | reg); // write mode and adress send
+ for (int i = 0; i < len; i++) {
+ rtn_val = spi_handler->write(local_data[i]); // write adress
+ }
+
+ if (ssel != NULL) {
+ *ssel = 1;
+ }
+
+ *dio = 0;
+
+ if (rtn_val < 0) {
+ return rtn_val;
+ }
+
+ return 0;
+}
+
+#define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
+ do { \
+ int ret; \
+ ret = read_register(address, (uint8_t *)&(reg_name)); \
+ if (ret) { \
+ return ret; \
+ } \
+ bit_field_name = value; \
+ ret = write_register(address, (uint8_t *)&(reg_name), 1); \
+ if (ret) { \
+ return ret; \
+ } \
+ } while (0)
+
+int MAX7032::initial_programming(void)
+{
+ uint8_t address;
+
+ set_power_on_off(1);
+
+ rx_quich_start();
+
+ set_center_freq(f_rf);
+ adjust_osc_freq(f_xtal);
+ set_trx_state(MAX7032::RECEIVE_MODE);
+
+ return -1;
+}
+
+int MAX7032::rx_quich_start(void)
+{
+ uint8_t address;
+ int ret;
+
+ for(address = 0; address < Q_START_CONF_LEN; address++)
+ {
+ if(address == 4)
+ continue;
+
+ ret = write_register(address, (uint8_t *)&(rx_quick_start[address]), 1);
+ if (ret) {
+ return ret;
+ }
+
+// ((max7032_dummy_t *)(&this->reg_map->power + address))->raw = rx_quick_start[address];
+ }
+
+ this->reg_map->power.raw = rx_quick_start[POWER_ADDR];
+ this->reg_map->contrl.raw = rx_quick_start[CONTRL_ADDR];
+ this->reg_map->conf0.raw = rx_quick_start[CONF0_ADDR];
+ this->reg_map->conf1.raw = rx_quick_start[CONF1_ADDR];
+ this->reg_map->osc.raw = rx_quick_start[OSC_ADDR];
+ this->reg_map->toff_upper.raw = rx_quick_start[TOFFMSB_ADDR];
+ this->reg_map->toff_lower.raw = rx_quick_start[TOFFLSB_ADDR];
+ this->reg_map->tcpu.raw = rx_quick_start[TCPU_ADDR];
+ this->reg_map->trf_upper.raw = rx_quick_start[TRFMSB_ADDR];
+ this->reg_map->trf_lower.raw = rx_quick_start[TRFLSB_ADDR];
+ this->reg_map->ton_upper.raw = rx_quick_start[TONMSB_ADDR];
+ this->reg_map->ton_lower.raw = rx_quick_start[TONLSB_ADDR];
+ this->reg_map->txlow_upper.raw = rx_quick_start[TXLOWMSB_ADDR];
+ this->reg_map->txlow_lower.raw = rx_quick_start[TXLOWLSB_ADDR];
+ this->reg_map->txhigh_upper.raw = rx_quick_start[TXHIGHMSB_ADDR];
+ this->reg_map->txhigh_lower.raw = rx_quick_start[TXHIGHLSB_ADDR];
+
+ return 0;
+}
+
+int MAX7032::tx_quich_start(void)
+{
+ uint8_t address;
+ int ret;
+
+ for(address = 0; address < Q_START_CONF_LEN; address++)
+ {
+ if(address == 4)
+ continue;
+
+ ret = write_register(address, (uint8_t *)&(tx_quick_start[address]), 1);
+ if (ret) {
+ return ret;
+ }
+
+// ((max7032_dummy_t *)(&this->reg_map->power + address))->raw = tx_quick_start[address];
+ }
+
+ this->reg_map->power.raw = tx_quick_start[POWER_ADDR];
+ this->reg_map->contrl.raw = tx_quick_start[CONTRL_ADDR];
+ this->reg_map->conf0.raw = tx_quick_start[CONF0_ADDR];
+ this->reg_map->conf1.raw = tx_quick_start[CONF1_ADDR];
+ this->reg_map->osc.raw = tx_quick_start[OSC_ADDR];
+ this->reg_map->toff_upper.raw = tx_quick_start[TOFFMSB_ADDR];
+ this->reg_map->toff_lower.raw = tx_quick_start[TOFFLSB_ADDR];
+ this->reg_map->tcpu.raw = tx_quick_start[TCPU_ADDR];
+ this->reg_map->trf_upper.raw = tx_quick_start[TRFMSB_ADDR];
+ this->reg_map->trf_lower.raw = tx_quick_start[TRFLSB_ADDR];
+ this->reg_map->ton_upper.raw = tx_quick_start[TONMSB_ADDR];
+ this->reg_map->ton_lower.raw = tx_quick_start[TONLSB_ADDR];
+ this->reg_map->txlow_upper.raw = tx_quick_start[TXLOWMSB_ADDR];
+ this->reg_map->txlow_lower.raw = tx_quick_start[TXLOWLSB_ADDR];
+ this->reg_map->txhigh_upper.raw = tx_quick_start[TXHIGHMSB_ADDR];
+ this->reg_map->txhigh_lower.raw = tx_quick_start[TXHIGHLSB_ADDR];
+ return 0;
+}
+
+int MAX7032::set_power_on_off(uint8_t power)
+{
+
+ if (power == 0) { // Shut down the device
+
+ *this->power_pin = 0;
+
+ } else { // Turn on the device
+
+ *this->power_pin = 0;
+ wait_us(1500);
+ *this->power_pin = 1;
+ }
+
+ return 0;
+}
+
+int MAX7032::get_bit_field(reg_bits_t bit_field, uint8_t *val)
+{
+ uint8_t reg_addr, bit_pos, reg_val, reg_mask;
+
+ reg_addr = bit_field / 8;
+ bit_pos = bit_field % 8;
+
+ int ret;
+ ret = read_register(reg_addr, (uint8_t *)&(reg_val));
+ if (ret) {
+ return ret;
+ }
+
+ reg_mask = 0x01;
+ reg_val = reg_val >> bit_pos;
+ reg_val &= reg_mask;
+
+ *val = reg_val;
+
+ return 0;
+}
+
+int MAX7032::set_bit_field(reg_bits_t bit_field, uint8_t val)
+{
+ uint8_t reg_addr, bit_pos, reg_val, reg_mask;
+
+ reg_addr = bit_field / 8;
+ bit_pos = bit_field % 8;
+
+ int ret;
+ ret = read_register(reg_addr, (uint8_t *)&(reg_val));
+ if (ret) {
+ return ret;
+ }
+
+ reg_mask = 0x01;
+ reg_mask = reg_mask << bit_pos;
+
+ if(val == 0)
+ reg_val &= ~reg_mask;
+ else if(val == 1)
+ reg_val |= reg_mask;
+ else
+ return -1;
+
+ ret = write_register(reg_addr, (uint8_t *)®_val, 1);
+ if (ret) {
+ return ret;
+ }
+
+ if(reg_addr == POWER_ADDR)
+ this->reg_map->power.raw = reg_val;
+ else if(reg_addr == CONTRL_ADDR)
+ this->reg_map->contrl.raw = reg_val;
+ else if(reg_addr == CONF0_ADDR)
+ this->reg_map->conf0.raw = reg_val;
+ else if(reg_addr == CONF1_ADDR)
+ this->reg_map->conf1.raw = reg_val;
+ else
+ return -2;
+
+ return 0;
+}
+
+int MAX7032::set_lna(uint8_t lna)
+{
+ if(lna > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.lna, lna);
+
+ return 0;
+}
+
+int MAX7032::get_lna()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.lna;
+}
+
+int MAX7032::set_agc(uint8_t agc)
+{
+ if(agc > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.agc, agc);
+
+ return 0;
+}
+
+int MAX7032::get_agc()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.agc;
+}
+
+int MAX7032::set_mixer(uint8_t mixer)
+{
+ if(mixer > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.mixer, mixer);
+
+ return 0;
+}
+
+int MAX7032::get_mixer()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.mixer;
+}
+
+int MAX7032::set_baseb(uint8_t baseb)
+{
+ if(baseb > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.baseb, baseb);
+
+ return 0;
+}
+
+int MAX7032::get_baseb()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.baseb;
+}
+
+int MAX7032::set_pkdet(uint8_t pkdet)
+{
+ if(pkdet > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.pkdet, pkdet);
+
+ return 0;
+}
+
+int MAX7032::get_pkdet()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.pkdet;
+}
+
+int MAX7032::set_pa(uint8_t pa)
+{
+ if(pa > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.pa, pa);
+
+ return 0;
+}
+
+int MAX7032::get_pa()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.pa;
+}
+
+int MAX7032::set_rssio(uint8_t rssio)
+{
+ if(rssio > 1)
+ return -1;
+
+ SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.rssio, rssio);
+
+ return 0;
+}
+
+int MAX7032::get_rssio()
+{
+ int ret;
+
+ ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->power.bits.rssio;
+}
+
+
+int MAX7032::set_agclk(uint8_t agclk)
+{
+ if(agclk > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.agclk, agclk);
+
+ if(!get_mgain())
+ return -99;
+
+ return 0;
+}
+
+int MAX7032::get_agclk()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.agclk;
+}
+
+int MAX7032::set_gain(uint8_t gain)
+{
+ if(gain > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.gain, gain);
+
+ if(!get_mgain())
+ return -99;
+
+ return 0;
+}
+
+int MAX7032::get_gain()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.gain;
+}
+
+int MAX7032::set_trk_en(uint8_t trk_en)
+{
+ if(trk_en > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.trk_en, trk_en);
+
+ return 0;
+}
+
+int MAX7032::get_trk_en()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.trk_en;
+}
+
+int MAX7032::set_pcal()
+{
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.pcal, 1);
+
+ return 0;
+}
+
+int MAX7032::get_pcal()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.pcal;
+}
+
+int MAX7032::set_fcal()
+{
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.fcal, 1);
+
+ return 0;
+}
+
+int MAX7032::get_fcal()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.fcal;
+}
+
+int MAX7032::set_ckout(uint8_t ckout)
+{
+ if(ckout > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.ckout, ckout);
+
+ return 0;
+}
+
+int MAX7032::get_ckout()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.ckout;
+}
+
+int MAX7032::set_sleep(uint8_t sleep)
+{
+ if(sleep > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.sleep, sleep);
+
+ return 0;
+}
+
+int MAX7032::get_sleep()
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->contrl.bits.sleep;
+}
+
+int MAX7032::set_mode(ask_fsk_sel_t ask_fsk_sel)
+{
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.mode, ask_fsk_sel);
+
+ return 0;
+}
+
+int MAX7032::get_mode(ask_fsk_sel_t* ask_fsk_sel)
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ *ask_fsk_sel = (ask_fsk_sel_t)this->reg_map->conf0.bits.mode;
+
+ return 0;
+}
+
+int MAX7032::get_mode()
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf0.bits.mode;
+}
+
+int MAX7032::set_t_r(uint8_t t_r)
+{
+ if(t_r > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.t_r, t_r);
+
+ return 0;
+}
+
+int MAX7032::get_t_r()
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf0.bits.t_r;
+}
+
+int MAX7032::set_mgain(uint8_t mgain)
+{
+ if(mgain > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.mgain, mgain);
+
+ return 0;
+}
+
+int MAX7032::get_mgain()
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf0.bits.mgain;
+}
+
+int MAX7032::set_drx(uint8_t drx)
+{
+ if(drx > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.drx, drx);
+
+ return 0;
+}
+
+int MAX7032::get_drx()
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf0.bits.drx;
+}
+
+
+int MAX7032::set_acal(uint8_t acal)
+{
+ if(acal > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.acal, acal);
+
+ return 0;
+}
+
+int MAX7032::get_acal()
+{
+ int ret;
+
+ ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf1.bits.acal;
+}
+
+int MAX7032::set_clkof(uint8_t clkof)
+{
+ if(clkof > 1)
+ return -1;
+
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.clkof, clkof);
+
+ return 0;
+}
+
+int MAX7032::get_clkof()
+{
+ int ret;
+
+ ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf1.bits.clkof;
+}
+
+int MAX7032::set_cdiv(uint8_t cdiv)
+{
+ if(cdiv > 3)
+ return -1;
+
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, cdiv);
+
+ return 0;
+}
+
+int MAX7032::get_cdiv()
+{
+ int ret;
+
+ ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf1.bits.cdiv;
+}
+
+int MAX7032::set_dt(uint8_t dt)
+{
+ if(dt > 7)
+ return -1;
+
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.dt, dt);
+
+ return 0;
+}
+
+int MAX7032::get_dt()
+{
+ int ret;
+
+ ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->conf1.bits.dt;
+}
+
+int MAX7032::set_osc(uint8_t osc)
+{
+ SET_BIT_FIELD(OSC_ADDR, this->reg_map->osc, this->reg_map->osc.bits.osc, osc);
+
+ return 0;
+}
+
+int MAX7032::get_osc()
+{
+ int ret;
+
+ ret = read_register(OSC_ADDR, (uint8_t *) & (this->reg_map->osc));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->osc.bits.osc;
+}
+
+int MAX7032::set_toff(uint16_t toff)
+{
+ uint8_t toff_lsb, toff_msb;
+
+ if(toff > 65535)
+ return -99;
+
+ toff_lsb = (uint8_t)(toff & 0x00FF);
+ toff_msb = (uint8_t)((toff & 0xFF00) >> 8);
+
+ SET_BIT_FIELD(TOFFMSB_ADDR, this->reg_map->toff_upper, this->reg_map->toff_upper.bits.toff_upper, toff_msb);
+ SET_BIT_FIELD(TOFFLSB_ADDR, this->reg_map->toff_lower, this->reg_map->toff_lower.bits.toff_lower, toff_lsb);
+
+ return 0;
+}
+
+uint16_t MAX7032::get_toff()
+{
+ uint8_t toff_lsb, toff_msb;
+ uint16_t toff = 0;
+
+ if(read_register(TOFFLSB_ADDR, (uint8_t *) & (this->reg_map->toff_lower)) < 0)
+ return -1;
+
+ if(read_register(TOFFMSB_ADDR, (uint8_t *) & (this->reg_map->toff_upper)) < 0)
+ return -2;
+
+ toff = this->reg_map->toff_upper.bits.toff_upper;
+ toff = toff << 8;
+ toff |= this->reg_map->toff_lower.bits.toff_lower;
+
+ return toff;
+}
+
+int MAX7032::set_tcpu(uint8_t tcpu)
+{
+ SET_BIT_FIELD(TCPU_ADDR, this->reg_map->tcpu, this->reg_map->tcpu.bits.tcpu, tcpu);
+
+ return 0;
+}
+
+uint8_t MAX7032::get_tcpu()
+{
+ int ret;
+
+ ret = read_register(TCPU_ADDR, (uint8_t *) & (this->reg_map->tcpu));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->tcpu.bits.tcpu;
+}
+
+int MAX7032::set_trf(uint16_t trf)
+{
+ uint8_t trf_lsb, trf_msb;
+
+ if(trf > 65535)
+ return -99;
+
+ trf_lsb = (uint8_t)(trf & 0x00FF);
+ trf_msb = (uint8_t)((trf & 0xFF00) >> 8);
+
+ SET_BIT_FIELD(TRFMSB_ADDR, this->reg_map->trf_upper, this->reg_map->trf_upper.bits.trf_upper, trf_msb);
+ SET_BIT_FIELD(TRFLSB_ADDR, this->reg_map->trf_lower, this->reg_map->trf_lower.bits.trf_lower, trf_lsb);
+
+ return 0;
+}
+
+uint16_t MAX7032::get_trf()
+{
+ uint8_t trf_lsb, trf_msb;
+ uint16_t trf = 0;
+
+ if(read_register(TRFLSB_ADDR, (uint8_t *) & (this->reg_map->trf_lower)) < 0)
+ return -1;
+
+ if(read_register(TRFMSB_ADDR, (uint8_t *) & (this->reg_map->trf_upper)) < 0)
+ return -2;
+
+ trf = this->reg_map->trf_upper.bits.trf_upper;
+ trf = trf << 8;
+ trf |= this->reg_map->trf_lower.bits.trf_lower;
+
+ return trf;
+}
+
+int MAX7032::set_ton(uint16_t ton)
+{
+ uint8_t ton_lsb, ton_msb;
+
+ if(ton > 65535)
+ return -99;
+
+ ton_lsb = (uint8_t)(ton & 0x00FF);
+ ton_msb = (uint8_t)((ton & 0xFF00) >> 8);
+
+ SET_BIT_FIELD(TONMSB_ADDR, this->reg_map->ton_upper, this->reg_map->ton_upper.bits.ton_upper, ton_msb);
+ SET_BIT_FIELD(TONLSB_ADDR, this->reg_map->ton_lower, this->reg_map->ton_lower.bits.ton_lower, ton_lsb);
+
+ return 0;
+}
+
+uint16_t MAX7032::get_ton()
+{
+ uint8_t ton_lsb, ton_msb;
+ uint16_t ton = 0;
+
+ if(read_register(TONLSB_ADDR, (uint8_t *) & (this->reg_map->ton_lower)) < 0)
+ return -1;
+
+ if(read_register(TONMSB_ADDR, (uint8_t *) & (this->reg_map->ton_upper)) < 0)
+ return -2;
+
+ ton = this->reg_map->ton_upper.bits.ton_upper;
+ ton = ton << 8;
+ ton |= this->reg_map->ton_lower.bits.ton_lower;
+
+ return ton;
+}
+
+int MAX7032::set_txlow(int txlow_val)
+{
+ uint8_t tx_low_lsb, tx_low_msb;
+
+ if(txlow_val > 65535)
+ return -99;
+
+ tx_low_lsb = (uint8_t)(txlow_val & 0x00FF);
+ tx_low_msb = (uint8_t)((txlow_val & 0xFF00) >> 8);
+
+
+ SET_BIT_FIELD(TXLOWLSB_ADDR, this->reg_map->txlow_lower, this->reg_map->txlow_lower.bits.txlow_lower, tx_low_lsb);
+ SET_BIT_FIELD(TXLOWMSB_ADDR, this->reg_map->txlow_upper, this->reg_map->txlow_upper.bits.txlow_upper, tx_low_msb);
+
+ return 0;
+}
+
+int MAX7032::get_txlow()
+{
+ uint8_t tx_low_lsb, tx_low_msb;
+ uint32_t tx_low = 0;
+
+ if(read_register(TXLOWLSB_ADDR, (uint8_t *)&tx_low_lsb) < 0)
+ return -1;
+
+ if(read_register(TXLOWMSB_ADDR, (uint8_t *)&tx_low_msb) < 0)
+ return -2;
+
+ tx_low = tx_low_msb;
+ tx_low = tx_low << 8;
+ tx_low |= tx_low_lsb;
+
+ return tx_low;
+}
+
+int MAX7032::set_txhigh(int txhigh_val)
+{
+ uint8_t tx_high_lsb, tx_high_msb;
+
+ if(txhigh_val > 65535)
+ return -99;
+
+ tx_high_lsb = (uint8_t)(txhigh_val & 0x00FF);
+ tx_high_msb = (uint8_t)((txhigh_val & 0xFF00) >> 8);
+
+ SET_BIT_FIELD(TXHIGHLSB_ADDR, this->reg_map->txhigh_lower, this->reg_map->txhigh_lower.bits.txhigh_lower, tx_high_lsb);
+ SET_BIT_FIELD(TXHIGHMSB_ADDR, this->reg_map->txhigh_upper, this->reg_map->txhigh_upper.bits.txhigh_upper, tx_high_msb);
+
+ return 0;
+}
+
+int MAX7032::get_txhigh()
+{
+ uint8_t tx_high_lsb, tx_high_msb;
+ uint32_t tx_high = 0;
+
+ if(read_register(TXHIGHLSB_ADDR, (uint8_t *)&tx_high_lsb) < 0)
+ return -1;
+
+ if(read_register(TXHIGHMSB_ADDR, (uint8_t *)&tx_high_msb) < 0)
+ return -2;
+
+ tx_high = tx_high_msb;
+ tx_high = tx_high << 8;
+ tx_high |= tx_high_lsb;
+
+ return tx_high;
+}
+
+int MAX7032::get_lckd()
+{
+ int ret;
+
+ ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->status.bits.lckd;
+}
+
+int MAX7032::get_gains()
+{
+ int ret;
+
+ ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->status.bits.gains;
+}
+
+int MAX7032::get_clkon()
+{
+ int ret;
+
+ ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->status.bits.clkon;
+}
+
+int MAX7032::get_pcald()
+{
+ int ret;
+
+ ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->status.bits.pcald;
+}
+
+int MAX7032::get_fcald()
+{
+ int ret;
+
+ ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status));
+ if (ret < 0)
+ return ret;
+
+ return this->reg_map->status.bits.fcald;
+}
+
+int MAX7032::adjust_clockout(cdiv_t cdiv)
+{
+ if(cdiv == DISABLE) {
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.ckout, 0);
+ return 0;
+ }
+
+ if(cdiv == F_XTAL) {
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 0);
+ }else if(cdiv == F_XTAL_X0_5) {
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 1);
+ }else if(cdiv == F_XTAL_X0_25) {
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 2);
+ }else if(cdiv == F_XTAL_X0_125) {
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 3);
+ }else{
+ return -1;
+ }
+
+ SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.ckout, 1);
+ return 0;
+}
+
+int MAX7032::get_clockout_conf(cdiv_t *cdiv)
+{
+ int ret;
+
+ ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl));
+ if (ret < 0)
+ return ret;
+
+ if(this->reg_map->contrl.bits.ckout == 0){
+ *cdiv = DISABLE;
+ return 0;
+ }
+
+ ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1));
+ if (ret < 0)
+ return ret;
+
+ if(this->reg_map->conf1.bits.cdiv == 0)
+ *cdiv = F_XTAL;
+ else if(this->reg_map->conf1.bits.cdiv == 1)
+ *cdiv = F_XTAL_X0_5;
+ else if(this->reg_map->conf1.bits.cdiv == 2)
+ *cdiv = F_XTAL_X0_25;
+ else if(this->reg_map->conf1.bits.cdiv == 3)
+ *cdiv = F_XTAL_X0_125;
+ else
+ return -1;
+
+ return 0;
+}
+
+int MAX7032::set_ofps(uint8_t ofps)
+{
+ if(ofps > 3)
+ return -1;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.ofps, ofps);
+
+ return 0;
+}
+
+int MAX7032::get_ofps()
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ return (int)this->reg_map->conf0.bits.ofps;
+}
+
+int MAX7032::set_onps(uint8_t onps)
+{
+ if(onps > 3)
+ return -1;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.onps, onps);
+
+ return 0;
+}
+
+int MAX7032::get_onps()
+{
+ int ret;
+
+ ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0));
+ if (ret < 0)
+ return ret;
+
+ return (int)this->reg_map->conf0.bits.onps;
+}
+
+int MAX7032::adjust_osc_freq(float osc_freq)
+{
+ uint8_t osc_reg_val;
+
+ if (osc_freq < 12.05 || osc_freq > 18.31)
+ return -99;
+
+ osc_reg_val = (osc_freq*1000) / 100;
+
+ if(write_register(OSC_ADDR, &osc_reg_val, 1) >= 0)
+ {
+ f_xtal = osc_freq;
+ return 0;
+ }
+
+ return -1;
+}
+
+float MAX7032::get_osc_freq()
+{
+ return f_xtal;
+}
+
+int MAX7032::set_center_freq(float center_freq)
+{
+ uint8_t tx_low_msb, tx_low_lsb, tx_high_msb, tx_high_lsb;
+ uint16_t center_freq_reg_val;
+ int fsk_high, fsk_low, ask_fsk_sel;
+
+ if (center_freq < 300 || center_freq > 450)
+ return -99;
+
+ ask_fsk_sel = this->get_mode();
+
+ if(ask_fsk_sel < 0){
+ return -98;
+ }
+
+ if(ask_fsk_sel == ASK_FSK_SEL_ASK){
+ center_freq_reg_val = (uint16_t)round(((center_freq / f_xtal) - 16) * 4096);
+
+ tx_low_lsb = (uint8_t)(center_freq_reg_val & 0x00FF);
+ tx_low_msb = (uint8_t)((center_freq_reg_val & 0xFF00) >> 8);
+
+ if(write_register(TXLOWLSB_ADDR, &tx_low_lsb, 1) < 0)
+ return -1;
+ if(write_register(TXLOWMSB_ADDR, &tx_low_msb, 1) < 0)
+ return -2;
+ }
+ else{
+ fsk_high = round(((center_freq + fsk_dev) / f_xtal - 16) * 4096);
+ fsk_low = round(((center_freq - fsk_dev) / f_xtal - 16) * 4096);
+
+ tx_low_lsb = ((uint)(fsk_low) & 0X00FF);
+ tx_low_msb = ((uint)(fsk_low) & 0XFF00) >> 8;
+ tx_high_lsb = ((uint)(fsk_high) & 0X00FF);
+ tx_high_msb = ((uint)(fsk_high) & 0XFF00) >> 8;
+
+ if(write_register(TXLOWLSB_ADDR, &tx_low_lsb, 1) < 0)
+ return -3;
+ if(write_register(TXLOWMSB_ADDR, &tx_low_msb, 1) < 0)
+ return -4;
+ if(write_register(TXHIGHLSB_ADDR, &tx_high_lsb, 1) < 0)
+ return -5;
+ if(write_register(TXHIGHMSB_ADDR, &tx_high_msb, 1) < 0)
+ return -6;
+ }
+
+ f_rf = center_freq;
+
+ return 0;
+}
+
+float MAX7032::get_center_freq()
+{
+ return f_rf;
+}
+
+int MAX7032::set_data_rate(float data_rate_set)
+{
+ if(encoding == Manchester){
+ if(data_rate_set < 0 || data_rate_set > 33)
+ return -99;
+ }
+ else{
+ if(data_rate_set < 0 || data_rate_set > 66)
+ return -99;
+ }
+
+ this->data_rate = data_rate_set;
+ return 0;
+}
+
+float MAX7032::get_data_rate()
+{
+ return this->data_rate;
+}
+
+int MAX7032::set_fsk_dev(float fsk_dev_set)
+{
+ if(fsk_dev_set <= 0 || fsk_dev_set > fsk_dev_max)
+ return -99;
+
+ this->fsk_dev = fsk_dev_set;
+
+ return set_center_freq(f_rf);
+}
+
+float MAX7032::get_fsk_dev()
+{
+ return this->fsk_dev;
+}
+
+int MAX7032::set_encoding(encoding_t encoding_set)
+{
+ this->encoding = encoding_set;
+ return 0;
+}
+
+int MAX7032::get_encoding()
+{
+ return this->encoding;
+}
+
+int MAX7032::adjust_agc_dwell_timer(uint8_t k_val)
+{
+ if(k_val < 9 || k_val > 23)
+ return -99;
+
+ if(!(k_val & 0x01))
+ return -98;
+
+ k_val = (k_val - 9) / 2;
+
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.dt, k_val);
+ return 0;
+}
+
+int MAX7032::adjust_agc_dwell_timer(int dwell_time)
+{
+ float k_val;
+ uint8_t k_val_byte;
+
+ if(dwell_time <= 0)
+ return -99;
+
+ k_val = log10(dwell_time * f_xtal) * 3.3;
+ k_val_byte = (uint8_t)ceil(k_val);
+
+ if(!(k_val_byte & 0x01))
+ k_val_byte++;
+
+ if(k_val_byte < 9)
+ k_val_byte = 9;
+
+ if(k_val_byte > 23)
+ return -1;
+
+ k_val_byte = (k_val_byte - 9) / 2;
+
+ SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.dt, k_val_byte);
+ return 0;
+}
+
+int MAX7032::get_agc_dwell_timer()
+{
+ int ret;
+ uint8_t k_val;
+
+ ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1));
+ if (ret < 0)
+ return ret;
+
+ k_val = (2 * this->reg_map->conf1.bits.dt) + 9;
+
+ return (int)(pow(2, k_val) / f_xtal);
+}
+
+int MAX7032::adjust_off_timer(timer_base_t time_base, int timer_val)
+{
+ uint8_t toff_msb, toff_lsb;
+
+ if(timer_val < 1 || timer_val > 65535)
+ return -99;
+
+ toff_msb = (uint8_t)((timer_val & 0xFF00) >> 8);
+ toff_lsb = (uint8_t)(timer_val & 0x00FF);
+
+ if(write_register(TOFFMSB_ADDR, &toff_msb, 1) < 0)
+ return -1;
+ if(write_register(TOFFLSB_ADDR, &toff_lsb, 1) < 0)
+ return -2;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.ofps, time_base);
+
+ return 0;
+}
+
+int MAX7032::adjust_off_timer(int toff_time)
+{
+ int time_base, ton_reg_val;
+ timer_base_t timer_base_param;
+
+ if(toff_time < 7860000){ //7.86s
+ time_base = 120;
+ timer_base_param = US_120;
+ }else if(toff_time < 31460000){ //31.46s
+ time_base = 480;
+ timer_base_param = US_480;
+ }else if(toff_time < 126000000){ //2min 6s
+ time_base = 1920;
+ timer_base_param = US_1920;
+ }else if(toff_time < 503000000){ //8min 23s
+ time_base = 7680;
+ timer_base_param = US_7680;
+ }else{
+ return -99;
+ }
+
+ ton_reg_val = toff_time / time_base;
+
+ if((ton_reg_val * time_base) < toff_time)
+ ton_reg_val++;
+
+ adjust_off_timer(timer_base_param, ton_reg_val);
+
+ return 0;
+}
+
+int MAX7032::get_off_timer()
+{
+ uint8_t toff_msb, toff_lsb;
+ int timer_val, time_base, ret;
+
+ time_base = this->get_ofps();
+
+ if(time_base < 0)
+ return -1;
+
+ ret = read_register(TOFFMSB_ADDR, (uint8_t *)&toff_msb);
+ if (ret < 0)
+ return -2;
+
+ ret = read_register(TOFFLSB_ADDR, (uint8_t *)&toff_lsb);
+ if (ret < 0)
+ return -3;
+
+ timer_val = toff_msb;
+ timer_val = timer_val << 8;
+ timer_val += toff_lsb;
+
+ if(time_base == 0)
+ return timer_val * 120;
+ if(time_base == 1)
+ return timer_val * 480;
+ if(time_base == 2)
+ return timer_val * 1920;
+ if(time_base == 3)
+ return timer_val * 7680;
+
+ return -4;
+}
+
+int MAX7032::adjust_on_timer(timer_base_t time_base, int timer_val)
+{
+ uint8_t ton_msb, ton_lsb;
+
+ if(timer_val < 1 || timer_val > 65535)
+ return -99;
+
+ ton_msb = (uint8_t)((timer_val & 0xFF00) >> 8);
+ ton_lsb = (uint8_t)(timer_val & 0x00FF);
+
+ if(write_register(TONMSB_ADDR, &ton_msb, 1) < 0)
+ return -1;
+ if(write_register(TONLSB_ADDR, &ton_lsb, 1) < 0)
+ return -2;
+
+ SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.onps, time_base);
+
+ return 0;
+}
+
+int MAX7032::adjust_on_timer(int ton_time)
+{
+ int time_base, ton_reg_val;
+ timer_base_t timer_base_param;
+
+ if(ton_time < 7860000){ //7.86s
+ time_base = 120;
+ timer_base_param = US_120;
+ }else if(ton_time < 31460000){ //31.46s
+ time_base = 480;
+ timer_base_param = US_480;
+ }else if(ton_time < 126000000){ //2min 6s
+ time_base = 1920;
+ timer_base_param = US_1920;
+ }else if(ton_time < 503000000){ //8min 23s
+ time_base = 7680;
+ timer_base_param = US_7680;
+ }else{
+ return -99;
+ }
+
+ ton_reg_val = ton_time / time_base;
+
+ if((ton_reg_val * time_base) < ton_time)
+ ton_reg_val++;
+
+ adjust_on_timer(timer_base_param, ton_reg_val);
+
+ return 0;
+}
+
+int MAX7032::get_on_timer()
+{
+ uint8_t ton_msb, ton_lsb;
+ int timer_val, time_base, ret;
+
+ time_base = this->get_onps();
+
+ if(time_base < 0)
+ return -1;
+
+ ret = read_register(TONMSB_ADDR, (uint8_t *)&ton_msb);
+ if (ret < 0)
+ return -2;
+
+ ret = read_register(TONLSB_ADDR, (uint8_t *)&ton_lsb);
+ if (ret < 0)
+ return -3;
+
+ timer_val = ton_msb;
+ timer_val = timer_val << 8;
+ timer_val += ton_lsb;
+
+ if(time_base == 0)
+ return timer_val * 120;
+ if(time_base == 1)
+ return timer_val * 480;
+ if(time_base == 2)
+ return timer_val * 1920;
+ if(time_base == 3)
+ return timer_val * 7680;
+
+ return -4;
+}
+
+int MAX7032::adjust_cpu_recovery_timer(int tcpu_time)
+{
+ uint8_t tcpu;
+
+ if(tcpu_time > 30600)
+ return -99;
+
+ tcpu = tcpu_time / 120;
+
+ if((tcpu * 120) < tcpu_time)
+ tcpu++;
+
+ SET_BIT_FIELD(TCPU_ADDR, this->reg_map->tcpu, this->reg_map->tcpu.bits.tcpu, tcpu);
+
+ return 0;
+}
+
+int MAX7032::get_cpu_recovery_timer()
+{
+ uint8_t tcpu;
+ int ret;
+
+ ret = read_register(TCPU_ADDR, (uint8_t *)&tcpu);
+ if (ret < 0)
+ return -1;
+
+ return tcpu * 120;
+}
+
+int MAX7032::adjust_rf_settling_timer(int trf_time)
+{
+ uint8_t trf_msb, trf_lsb;
+ uint16_t timer_val;
+
+ if(trf_time > 7864200)
+ return -99;
+
+ timer_val = trf_time / 120;
+
+ if((timer_val*120) < trf_time)
+ timer_val++;
+
+ trf_msb = (uint8_t)((timer_val & 0xFF00) >> 8);
+ trf_lsb = (uint8_t)(timer_val & 0x00FF);
+
+ SET_BIT_FIELD(TRFMSB_ADDR, this->reg_map->trf_upper, this->reg_map->trf_upper.bits.trf_upper, trf_msb);
+ SET_BIT_FIELD(TRFLSB_ADDR, this->reg_map->trf_lower, this->reg_map->trf_lower.bits.trf_lower, trf_lsb);
+
+ return 0;
+}
+
+int MAX7032::get_rf_settling_timer()
+{
+ uint8_t trf_msb, trf_lsb;
+ int timer_val, ret;
+
+ ret = read_register(TRFMSB_ADDR, (uint8_t *)&trf_msb);
+ if (ret < 0)
+ return -1;
+
+ ret = read_register(TRFLSB_ADDR, (uint8_t *)&trf_lsb);
+ if (ret < 0)
+ return -2;
+
+ timer_val = trf_msb;
+ timer_val = timer_val << 8;
+ timer_val += trf_lsb;
+
+ return timer_val * 120;
+}
+
+int MAX7032::set_trx_state(trx_state_t trx_state)
+{
+ if(trx_state == RECEIVE_MODE){
+ if(data_send != NULL){
+ delete this->data_send;
+ this->data_send = NULL;
+ }
+
+ if(data_read == NULL){
+ this->data_read = new DigitalIn(data_pin);
+ this->data_read->mode(OpenDrain);
+ }
+
+ if( set_t_r(RECEIVE_MODE) < 0)
+ return -1;
+
+ if(trx_pin == NULL) //trx state depends on how the trx pin is connected
+ return -2;
+
+ trx_pin->write(RECEIVE_MODE);
+
+ return 0;
+
+ }else{
+ if(data_read != NULL){
+ delete this->data_read;
+ this->data_read = NULL;
+ }
+
+ if(data_send == NULL){
+ this->data_send = new DigitalOut(MAX7032_MBED_DATA_PIN);
+ *data_send = 0;
+ }
+
+ return set_t_r(TRANSMIT_MODE);
+ }
+}
+
+int MAX7032::get_trx_state()
+{
+ if(get_t_r())
+ return TRANSMIT_MODE;
+
+ if(trx_pin == NULL) //trx state depends on how the trx pin is connected
+ return -1;
+
+ return trx_pin->read();
+}
+
+int MAX7032::rf_transmit_data(uint8_t *data, uint8_t data_len)
+{
+ uint8_t *coded_data;
+ uint8_t byte_idx, bit_idx;
+ uint32_t bit_duration, coded_data_len, coded_data_idx, transmit_time = 0, curr_time;
+ Timer timer;
+
+ if(data == NULL)
+ return -99;
+
+ if(get_trx_state() == RECEIVE_MODE)
+ return -98;
+
+ if(encoding == Manchester){
+ coded_data = new uint8_t[data_len * 2];
+
+ if(coded_data == NULL)
+ return -97;
+
+ for(byte_idx = 0; byte_idx < data_len; byte_idx++)
+ {
+ for(bit_idx = 0; bit_idx < 8; bit_idx++)
+ {
+ if(data[byte_idx] & (0x80 >> bit_idx)){
+ coded_data[byte_idx * 2 + (bit_idx / 4)] |= (0x80>>((bit_idx % 4) * 2));
+ coded_data[byte_idx * 2 + (bit_idx / 4)] &= ~(0x80>>((bit_idx % 4) * 2 + 1));
+ } else{
+ coded_data[byte_idx * 2 + (bit_idx / 4)] &= ~(0x80>>((bit_idx % 4) * 2));
+ coded_data[byte_idx * 2 + (bit_idx / 4)] |= (0x80>>((bit_idx % 4) * 2 + 1));
+ }
+ }
+ }
+
+ bit_duration = 1000 / (data_rate*2); //us
+ coded_data_len = data_len * 2;
+ }
+ else if(encoding == NRZ){
+ coded_data = new uint8_t[data_len];
+
+ if(coded_data == NULL)
+ return -96;
+
+ for(byte_idx = 0; byte_idx < data_len; byte_idx++)
+ {
+ coded_data[byte_idx] = data[byte_idx];
+ }
+
+ bit_duration = 1000 / data_rate; //us
+ coded_data_len = data_len;
+ }
+
+ timer.start();
+
+ core_util_critical_section_enter();
+
+ for(coded_data_idx = 0; coded_data_idx < coded_data_len; coded_data_idx++)
+ {
+ for(bit_idx = 0; bit_idx < 8; bit_idx++)
+ {
+ while(1)
+ {
+ curr_time = timer.read_us();
+ if((curr_time - transmit_time) >= bit_duration){
+ transmit_time = curr_time;
+
+ if(coded_data[coded_data_idx] & (0x80 >> bit_idx))
+ *data_send = 1;
+ else
+ *data_send = 0;
+ break;
+ }
+ }
+ }
+ }
+
+ while(1)
+ {
+ curr_time = timer.read_us();
+ if((curr_time - transmit_time) >= bit_duration){
+ *data_send = 0;
+ break;
+ }
+ }
+
+ core_util_critical_section_exit();
+
+ delete coded_data;
+
+ return 0;
+}
+
+int MAX7032::rf_receive_data(uint8_t *coded_data, uint8_t coded_data_len)
+{
+ uint8_t byte_idx, bit_idx;
+ uint32_t bit_duration, coded_data_idx, read_time = 0, curr_time;
+ Timer timer;
+
+ if(coded_data == NULL)
+ return -99;
+
+ if(get_trx_state() == TRANSMIT_MODE)
+ return -98;
+
+ if(encoding == Manchester){
+ bit_duration = 1000 / (data_rate*4); //us
+ }else{
+ bit_duration = 1000 / (data_rate*2); //us
+ }
+
+ core_util_critical_section_enter();
+
+ timer.start();
+
+ for(coded_data_idx = 0; coded_data_idx < coded_data_len; coded_data_idx++)
+ {
+ for(bit_idx = 0; bit_idx < 8; bit_idx++)
+ {
+ while(1)
+ {
+ curr_time = timer.read_us();
+ if((curr_time - read_time) >= bit_duration){
+ if(data_read->read())
+ coded_data[coded_data_idx] |= (0x80 >> bit_idx);
+ else
+ coded_data[coded_data_idx] &= ~(0x80 >> bit_idx);
+
+ read_time = curr_time;
+ break;
+ }
+ }
+ }
+ core_util_critical_section_exit();
+ }
+
+ return 0;
+}
+
+int MAX7032::set_trx_pin(trx_state_t pin_state)
+{
+ if(trx_pin == NULL)
+ return -1;
+
+ trx_pin->write(pin_state);
+ return 0;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/Max7032.h Mon Aug 02 16:42:52 2021 +0300
@@ -0,0 +1,1097 @@
+/*******************************************************************************
+ * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc.shall not be used except as stated in the Maxim Integrated
+ * Products, Inc.Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc.retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MAX7032_MAX7032_H_
+#define MAX7032_MAX7032_H_
+
+#include "mbed.h"
+#include "Max7032_regs.h"
+#include "rtos.h"
+
+#define MAX7032_SPI MXC_SPIM2
+
+#define MAX7032_SPI MXC_SPIM2
+#define MAX7032_SPI_MOSI P5_1
+#define MAX7032_SPI_MISO P5_2
+#define MAX7032_SPI_SCK P5_0
+#define MAX7032_SPI_CS P5_5
+
+#define MAX7032_PIN_POWER P4_0
+#define MAX7032_PIN_RSSI AIN_1
+#define MAX7032_TRX_PIN P3_3
+
+#define MAX7032_MBED_DATA_PIN P5_6
+#define MAX7032_GPIO_DATA_PORT PORT_5
+#define MAX7032_GPIO_DATA_PIN PIN_6
+
+#define Q_START_CONF_LEN 17
+
+class MAX7032
+{
+private:
+ max7032_reg_map_t *reg_map;
+ SPI *spi_handler;
+ DigitalOut *ssel;
+ DigitalOut *power_pin;
+ DigitalOut *trx_pin;
+ DigitalOut *data_send;
+ PinName data_pin;
+ DigitalOut *dio;
+
+ DigitalIn *data_read;
+
+ uint8_t preset_mode;
+ float f_xtal ;
+ float f_rf;
+ float data_rate;
+ float fsk_dev;
+ const float fsk_dev_max = 0.1f; //100khz
+
+protected:
+
+
+public:
+
+ //Constructors
+ MAX7032(SPI *spi, DigitalOut *cs, DigitalOut *powerPin, PinName dataPin, DigitalOut *dioPin, DigitalOut *trxPin);
+
+ MAX7032(SPI *spi, DigitalOut *powerPin, PinName dataPin, DigitalOut *dioPin, DigitalOut *trxPin);
+
+ //Destructor
+ ~MAX7032();
+
+ typedef enum {
+ POWER_ADDR = 0x00,
+ CONTRL_ADDR = 0x01,
+ CONF0_ADDR = 0x02,
+ CONF1_ADDR = 0x03,
+ OSC_ADDR = 0x05,
+ TOFFMSB_ADDR = 0x06,
+ TOFFLSB_ADDR = 0x07,
+ TCPU_ADDR = 0x08,
+ TRFMSB_ADDR = 0x09,
+ TRFLSB_ADDR = 0x0A,
+ TONMSB_ADDR = 0x0B,
+ TONLSB_ADDR = 0x0C,
+ TXLOWMSB_ADDR = 0x0D,
+ TXLOWLSB_ADDR = 0x0E,
+ TXHIGHMSB_ADDR = 0x0F,
+ TXHIGHLSB_ADDR = 0x10,
+ STATUS_ADDR = 0x1A,
+ }register_address_t;
+
+ typedef enum {
+ X0,
+ RSSIO,
+ PA,
+ PkDet,
+ BaseB,
+ MIXER,
+ AGC,
+ LNA,
+ SLEEP,
+ CKOUT,
+ FCAL,
+ PCAL,
+ X1,
+ TRK_EN,
+ GAIN,
+ AGCLK,
+ ONPS0,
+ ONPS1,
+ OFPS0,
+ OFPS1,
+ DRX,
+ MGAIN,
+ T_R,
+ MODE,
+ DT0,
+ DT1,
+ DT2,
+ CDIV0,
+ CDIV1,
+ CLKOF,
+ ACAL,
+ X2,
+ NUM_OF_BIT
+ }reg_bits_t;
+
+ typedef enum
+ {
+ Manchester = 0,
+ NRZ = 1
+ }encoding_t;
+
+ encoding_t encoding;
+
+ /**
+ * @brief Operation state of the RF receiver
+ *
+ * @details
+ * - Default : 0x00
+ * - Description : Indicates whether initialization is successful
+ */
+ typedef enum {
+ INITIALIZED = 0,
+ UNINITIALIZED = 1,
+ UNKNOWN = 2,
+ } operation_mode_t;
+
+ operation_mode_t operation_mode;
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CONF0 (0x02)
+ * - Bit Fields : [7]
+ * - Default : 0x0
+ * - Description : ASK/FSK Selection for both receive and transmit
+ */
+ typedef enum {
+ ASK_FSK_SEL_ASK, /**< 0x0: ASK modulation */
+ ASK_FSK_SEL_FSK /**< 0x1: FSK modulation */
+ } ask_fsk_sel_t;
+
+
+ /* REGISTER SET & GET FUNCTION DECLARATIONS */
+
+
+ /**
+ * @brief Sets the specified bit.
+ *
+ * @param[in] bit_field Bit to be set.
+ * @param[in] val Value to be set.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_bit_field(reg_bits_t bit_field, uint8_t val);
+
+ /**
+ * @brief Gets the specified bit.
+ *
+ * @param[in] bit_field Bit to get value.
+ * @param[in] val The address to store the value of the Bit.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int get_bit_field(reg_bits_t bit_field, uint8_t *val);
+
+ /**
+ * @brief Sets Low-Noise Amplifier Power-Configuration Bit.
+ *
+ * @param[in] lna 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_lna(uint8_t lna);
+
+ /**
+ * @brief Gets Low-Noise Amplifier Power-Configuration Bit.
+ *
+ * @returns LNA Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_lna();
+
+ /**
+ * @brief Sets Automatic Gain Control Power-Configuration Bit.
+ *
+ * @param[in] agc 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_agc(uint8_t agc);
+
+ /**
+ * @brief Gets Automatic Gain Control Power-Configuration Bit.
+ *
+ * @returns AGC Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_agc();
+
+ /**
+ * @brief Sets Mixer Power-Configuration Bit.
+ *
+ * @param[in] mixer 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_mixer(uint8_t mixer);
+
+ /**
+ * @brief Gets Mixer Power-Configuration Bit.
+ *
+ * @returns Mixer Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_mixer();
+
+ /**
+ * @brief Sets Baseband Power-Configuration Bit.
+ *
+ * @param[in] baseb 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_baseb(uint8_t baseb);
+
+ /**
+ * @brief Gets Baseband Power-Configuration Bit.
+ *
+ * @returns Baseband Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_baseb();
+
+ /**
+ * @brief Sets Peak-detector Power-Configuration Bit.
+ *
+ * @param[in] pkdet 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_pkdet(uint8_t pkdet);
+
+ /**
+ * @brief Gets Peak-detector Power-Configuration Bit.
+ *
+ * @returns Peak-detector Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_pkdet();
+
+ /**
+ * @brief Sets Transmitter Power Amplifier Power-Configuration Bit.
+ *
+ * @param[in] pa 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_pa(uint8_t pa);
+
+ /**
+ * @brief Gets Transmitter Power Amplifier Power-Configuration Bit.
+ *
+ * @returns Transmitter Power Amplifier Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_pa();
+
+ /**
+ * @brief Sets RSSI Amplifier Power-Configuration Bit.
+ *
+ * @param[in] rssio 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_rssio(uint8_t rssio);
+
+ /**
+ * @brief Gets RSSI Amplifier Power-Configuration Bit.
+ *
+ * @returns RSSI Amplifier Power-Configuration Bit's State, negative error code on failure.
+ */
+ int get_rssio();
+
+ /**
+ * @brief Sets AGC Locking Feature Control Bit.
+ *
+ * @param[in] agclk 0x0: Disable, 0x1: Enable.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_agclk(uint8_t agclk);
+
+ /**
+ * @brief Gets AGC Locking Feature Control Bit.
+ *
+ * @returns AGC Locking Feature Control Bit's State, negative error code on failure.
+ */
+ int get_agclk();
+
+ /**
+ * @brief Sets Gain State Control Bit.
+ *
+ * @param[in] gain 0x0: Force manual low-gain state if MGAIN = 1,
+ * 0x1: Force manual high-gain state if MGAIN = 1.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_gain(uint8_t gain);
+
+ /**
+ * @brief Gets Gain State Control Bit.
+ *
+ * @returns Gain State Control Bit's State, negative error code on failure.
+ */
+ int get_gain();
+
+ /**
+ * @brief Sets Manual Peak-Detector Tracking Control Bit.
+ *
+ * @param[in] trk_en 0x0: Release peak-detector tracking,
+ * 0x1: Force manual peak-detector tracking.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_trk_en(uint8_t trk_en);
+
+ /**
+ * @brief Gets Manual Peak-Detector Tracking Control Bit.
+ *
+ * @returns Manual Peak-Detector Tracking Control Bit's State, negative error code on failure.
+ */
+ int get_trk_en();
+
+ /**
+ * @brief Sets Polling Timer Calibration Control Bit.
+ *
+ * @description Sets PCAL Bit to 1 to Perform polling timer calibration.
+ * Automatically reset to zero once calibration is completed
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_pcal();
+
+ /**
+ * @brief Gets Polling Timer Calibration Control Bit.
+ *
+ * @returns Polling Timer Calibration Control Bit's State, negative error code on failure.
+ */
+ int get_pcal();
+
+ /**
+ * @brief Sets FSK calibration Control Bit.
+ *
+ * @description Sets FCAL Bit to 1 to Perform FSK calibration.
+ * Automatically reset to zero once calibration is completed
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_fcal();
+
+ /**
+ * @brief Gets FSK calibration Control Bit.
+ *
+ * @returns FSK calibration Control Bit's State, negative error code on failure.
+ */
+ int get_fcal();
+
+ /**
+ * @brief Sets Crystal Clock Output Enable Control Bit.
+ *
+ * @param[in] sleep 0x0: Disable crystal clock output,
+ * 0x1: Enable crystal clock output.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_ckout(uint8_t ckout);
+
+ /**
+ * @brief Gets Crystal Clock Output Enable Control Bit.
+ *
+ * @returns Sleep Mode Control Bit's State, negative error code on failure.
+ */
+ int get_ckout();
+
+ /**
+ * @brief Sets Sleep Mode Control Bit.
+ *
+ * @param[in] sleep 0x0: Normal operation,
+ * 0x1: Deep-sleep mode, regardless the state of ENABLE pin.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_sleep(uint8_t sleep);
+
+ /**
+ * @brief Gets Sleep Mode Control Bit.
+ *
+ * @returns Sleep Mode Control Bit's State, negative error code on failure.
+ */
+ int get_sleep();
+
+ /**
+ * @brief Sets FSK or ASK modulation Configuration Bit.
+ *
+ * @param[in] ask_fsk_sel 0x0: Enable ASK for both receive and transmit,
+ * 0x1: Enable FSK for both receive and transmit.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_mode(ask_fsk_sel_t ask_fsk_sel);
+
+ /**
+ * @brief Gets FSK or ASK modulation Configuration Bit.
+ *
+ * @param[in] ask_fsk_sel
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int get_mode(ask_fsk_sel_t* ask_fsk_sel);
+
+ /**
+ * @brief Gets FSK or ASK modulation Configuration Bit.
+ *
+ * @returns FSK or ASK modulation Configuration Bit's State, negative error code on failure.
+ */
+ int get_mode();
+
+ /**
+ * @brief Sets Transmit or Receive Configuration Bit.
+ *
+ * @param[in] t_r 0x0: Enable receive mode of the transceiver when pin T/R = 0,
+ * 0x1: Enable transmit mode of the transceiver, regardless the state of pin T/R.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_t_r(uint8_t t_r);
+
+ /**
+ * @brief Gets Transmit or Receive Configuration Bit.
+ *
+ * @returns Transmit or Receive Configuration Bit's State, negative error code on failure.
+ */
+ int get_t_r();
+
+ /**
+ * @brief Sets Manual Gain Mode Configuration Bit.
+ *
+ * @param[in] mgain 0x0: Disable manual-gain mode,
+ * 0x1: Enable manual-gain mode.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_mgain(uint8_t mgain);
+
+ /**
+ * @brief Gets Manual Gain Mode Configuration Bit.
+ *
+ * @returns Manual Gain Mode Configuration Bit's State, negative error code on failure.
+ */
+ int get_mgain();
+
+ /**
+ * @brief Sets Discontinuous Receive Mode Configuration Bit.
+ *
+ * @param[in] drx 0x0: Disable DRX,
+ * 0x1: Enable DRX.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_drx(uint8_t drx);
+
+ /**
+ * @brief Gets Discontinuous Receive Mode Configuration Bit.
+ *
+ * @returns Discontinuous Receive Mode Configuration Bit's State, negative error code on failure.
+ */
+ int get_drx();
+
+ /**
+ * @brief Sets Off-timer Prescaler Configuration Bits.
+ *
+ * @param[in] ofps Off-timer Prescaler Configuration Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_ofps(uint8_t ofps);
+
+ /**
+ * @brief Gets Off-timer Prescaler Configuration Bits.
+ *
+ * @returns Off-timer Prescaler Configuration Bit's value, negative error code on failure.
+ */
+ int get_ofps();
+
+ /**
+ * @brief Sets On-timer Prescaler Configuration Bits.
+ *
+ * @param[in] onps On-timer Prescaler Configuration Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_onps(uint8_t onps);
+
+ /**
+ * @brief Gets On-timer Prescaler Configuration Bits.
+ *
+ * @returns On-timer Prescaler Configuration Bit's value, negative error code on failure.
+ */
+ int get_onps();
+
+ /**
+ * @brief Sets Automatic FSK Calibration Configuration Bit.
+ *
+ * @param[in] acal 0x0: Disable automatic FSK calibration,
+ * 0x1: Enable automatic FSK calibration when coming out of the sleep state in DRX mode.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_acal(uint8_t acal);
+
+ /**
+ * @brief Gets Automatic FSK Calibration Configuration Bit.
+ *
+ * @returns Automatic FSK Calibration Configuration Bit's State, negative error code on failure.
+ */
+ int get_acal();
+
+ /**
+ * @brief Sets Continuous Clock Output (even during tOFF or when ENABLE pin is low) Configuration Bit.
+ *
+ * @param[in] clkof 0x0: Continuous clock output; if CKOUT = 1, clock output is active during tON (DRX mode) or
+ * when ENABLE pin is high (continuous receive mode),
+ * 0x1: Enable continuous clock output when CKOUT = 1.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_clkof(uint8_t clkof);
+
+ /**
+ * @brief Gets Continuous Clock Output Configuration Bit.
+ *
+ * @returns Continuous Clock Output Configuration Bit's State, negative error code on failure.
+ */
+ int get_clkof();
+
+ /**
+ * @brief Sets Crystal Divider Configuration Bits.
+ *
+ * @param[in] cdiv Crystal Divider Configuration Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_cdiv(uint8_t cdiv);
+
+ /**
+ * @brief Gets Crystal Divider Configuration Bits Value.
+ *
+ * @returns Crystal Divider Configuration Bit's value, negative error code on failure.
+ */
+ int get_cdiv();
+
+ /**
+ * @brief Sets AGC Dwell Timer Configuration Bits.
+ *
+ * @param[in] dt AGC Dwell Timer Configuration Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_dt(uint8_t dt);
+
+ /**
+ * @brief Gets AGC Dwell Timer Configuration Bits Value.
+ *
+ * @returns AGC Dwell Timer Configuration Bit's value, negative error code on failure.
+ */
+ int get_dt();
+
+ /**
+ * @brief Sets the OSC Register.
+ *
+ * @param[in] osc OSC Register Value.
+ *
+ * @description This register must be set to the integer result of fXTAL/100kHz.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_osc(uint8_t osc);
+
+ /**
+ * @brief Gets the OSC Register Value.
+ *
+ * @returns OSC Register Value, negative error code on failure.
+ */
+ int get_osc();
+
+ /**
+ * @brief Sets the tOFF Registers.
+ *
+ * @param[in] toff OSC Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_toff(uint16_t toff);
+
+ /**
+ * @brief Gets the tOFF Registers Value.
+ *
+ * @returns tOFF Registers Value, negative error code on failure.
+ */
+ uint16_t get_toff();
+
+ /**
+ * @brief Sets the tCPU Register.
+ *
+ * @param[in] tcpu tCPU Register Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_tcpu(uint8_t tcpu);
+
+ /**
+ * @brief Gets the tCPU Register Value.
+ *
+ * @returns tCPU Register Value, negative error code on failure.
+ */
+ uint8_t get_tcpu();
+
+ /**
+ * @brief Sets the tRF Registers.
+ *
+ * @param[in] trf tRF Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_trf(uint16_t trf);
+
+ /**
+ * @brief Gets the tRF Registers Value.
+ *
+ * @returns tRF Registers Value, negative error code on failure.
+ */
+ uint16_t get_trf();
+
+ /**
+ * @brief Sets the tON Registers.
+ *
+ * @param[in] ton tON Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_ton(uint16_t ton);
+
+ /**
+ * @brief Gets the tON Registers Value.
+ *
+ * @returns tON Registers Value, negative error code on failure.
+ */
+ uint16_t get_ton();
+
+ /**
+ * @brief Sets the TxLOW Registers.
+ *
+ * @param[in] txlow_val TxLOW Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_txlow(int txlow_val);
+
+ /**
+ * @brief Gets the TxLOW Registers Value.
+ *
+ * @returns the TxLOW Registers Value, negative error code on failure.
+ */
+ int get_txlow();
+
+ /**
+ * @brief Sets the TxHIGH Registers.
+ *
+ * @param[in] txhigh_val TxHIGH Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_txhigh(int txhigh_val);
+
+ /**
+ * @brief Gets the TxHIGH Registers Value.
+ *
+ * @returns the TxHIGH Registers Value, negative error code on failure.
+ */
+ int get_txhigh();
+
+ /**
+ * @brief Gets Lock Detect Status Bit.
+ *
+ * @returns Lock Detect Status Bit's State, negative error code on failure.
+ */
+ int get_lckd();
+
+ /**
+ * @brief Gets AGC Gain State Status Bit.
+ *
+ * @returns AGC Gain State Status Bit's State, negative error code on failure.
+ */
+ int get_gains();
+
+ /**
+ * @brief Gets Clock/Crystal Alive Status Bit.
+ *
+ * @returns Clock/Crystal Alive Status Bit's State, negative error code on failure.
+ */
+ int get_clkon();
+
+ /**
+ * @brief Gets Polling Timer Calibration Done Status Bit.
+ *
+ * @returns Polling Timer Calibration Done Status Bit's State, negative error code on failure.
+ */
+ int get_pcald();
+
+ /**
+ * @brief Gets FSK Calibration Done Status Bit.
+ *
+ * @returns FSK Calibration Done Status Bit's State, negative error code on failure.
+ */
+ int get_fcald();
+
+ /* END OF REGISTER SET & GET FUNCTION DECLARATIONS */
+
+ /* DEVICE CONFIGURATION FUNCTION DECLARATIONS */
+ typedef enum {
+ DISABLE, /**< 0x0: Disable */
+ F_XTAL, /**< 0x1: fXTAL */
+ F_XTAL_X0_5, /**< 0x2: fXTAL/2 */
+ F_XTAL_X0_25, /**< 0x3: fXTAL/4 */
+ F_XTAL_X0_125 /**< 0x4: fXTAL/8 */
+ } cdiv_t;
+
+ /**
+ * @brief Configures Crystal Clock Output.
+ *
+ * @param[in] cdiv Clock Output Configuration.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_clockout(cdiv_t cdiv);
+
+ /**
+ * @brief Gets Clock Output Configuration.
+ *
+ * @param[in] cdiv Clock Output Configuration.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int get_clockout_conf(cdiv_t *cdiv);
+
+ /**
+ * @brief Configures Internal Clock Frequency Divisor.
+ *
+ * @param[in] osc_freq Oscillator Frequency.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_osc_freq(float osc_freq);
+
+ /**
+ * @brief Gets Oscillator Frequency.
+ *
+ * @returns Oscillator Frequency.
+ */
+ float get_osc_freq();
+
+ typedef enum {
+ US_120, /**< 0x0: 120 us */
+ US_480, /**< 0x1: 480 us */
+ US_1920, /**< 0x2: 1920 us */
+ US_7680 /**< 0x3: 7680 us */
+ } timer_base_t;
+
+ /**
+ * @brief Configures the off timer.
+ *
+ * @param[in] time_base Timer Base Configuration.
+ * @param[in] timer_val tOFF Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_off_timer(timer_base_t time_base, int timer_val);
+
+ /**
+ * @brief Configures the off timer.
+ *
+ * @param[in] toff_time Off Time in microseconds.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_off_timer(int toff_time);
+
+ /**
+ * @brief Gets the off time in us.
+ *
+ * @returns the off time in us, negative error code on failure.
+ */
+ int get_off_timer();
+
+ /**
+ * @brief Configures the CPU recovery timer.
+ *
+ * @param[in] tcpu_time desired CPU recovery time in us.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_cpu_recovery_timer(int tcpu_time);
+
+ /**
+ * @brief Gets the CPU recovery time in us.
+ *
+ * @returns the CPU recovery time in us, negative error code on failure.
+ */
+ int get_cpu_recovery_timer();
+
+ /**
+ * @brief Configures the RF settling timer.
+ *
+ * @param[in] trf_time RF settling time in us.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_rf_settling_timer(int trf_time);
+
+ /**
+ * @brief Gets the RF settling time in us.
+ *
+ * @returns the RF settling time in us, negative error code on failure.
+ */
+ int get_rf_settling_timer();
+
+ /**
+ * @brief Configures the on timer.
+ *
+ * @param[in] time_base Timer Base Configuration.
+ * @param[in] timer_val tON Registers Value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_on_timer(timer_base_t time_base, int timer_val);
+
+ /**
+ * @brief Configures the on timer.
+ *
+ * @param[in] ton_time On Time in microseconds.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_on_timer(int ton_time);
+
+ /**
+ * @brief Gets the on time in us.
+ *
+ * @returns the on time in us, negative error code on failure.
+ */
+ int get_on_timer();
+
+ /**
+ * @brief Sets the devices center frequency.
+ *
+ * @param[in] center_freq desired center frequency
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_center_freq(float center_freq);
+
+ /**
+ * @brief Gets the devices center frequency.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ float get_center_freq();
+
+ /**
+ * @brief Sets the devices data rate.
+ *
+ * @param[in] data_rate_set desired data rate
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_data_rate(float data_rate_set);
+
+ /**
+ * @brief Gets the devices data rate.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ float get_data_rate();
+
+ /**
+ * @brief Sets the FSK deviation.
+ *
+ * @param[in] fsk_dev_set desired FSK deviation
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_fsk_dev(float fsk_dev_set);
+
+ /**
+ * @brief Gets the FSK deviation.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ float get_fsk_dev();
+
+ /**
+ * @brief Sets the encoding type.
+ *
+ * @param[in] encoding_set desired encoding type
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_encoding(encoding_t encoding_set);
+
+ /**
+ * @brief Gets the encoding type.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int get_encoding();
+
+ /**
+ * @brief Configures the AGC Dwell Timer.
+ *
+ * @param[in] k_val K value for dwell timer configuration.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_agc_dwell_timer(uint8_t k_val);
+
+ /**
+ * @brief Configures the AGC Dwell Timer.
+ *
+ * @param[in] dwell_time desired dwell time.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int adjust_agc_dwell_timer(int dwell_time);
+
+ /**
+ * @brief Gets the AGC Dwell Time Value.
+ *
+ * @returns the AGC Dwell Time Value, negative error code on failure.
+ */
+ int get_agc_dwell_timer();
+
+ /* END OF DEVICE CONFIGURATION FUNCTION DECLARATIONS */
+
+ /* PUBLIC FUNCTION DECLARATIONS */
+
+ /**
+ * @brief Set power on/off
+ *
+ * @param[in] power 0 : power ON, 1: power OFF
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_power_on_off(uint8_t power);
+
+ /**
+ * @brief Read from a register. Since 3-wire spi is not supported by mbed, the read_register function must be implemented by the user.
+ *
+ * @param[in] reg Address of a register to be read.
+ * @param[out] value Pointer to save result value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int read_register(uint8_t reg, uint8_t *value);
+
+ /**
+ * @brief Write to a register.
+ *
+ * @param[in] reg Address of a register to be written.
+ * @param[out] value Pointer of value to be written to register.
+ * @param[in] len Size of result to be written.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int write_register(uint8_t reg, const uint8_t *value, uint8_t len);
+
+ /**
+ * @brief Initial programming steps after power on or soft reset.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int initial_programming(void);
+
+ /**
+ * @brief Loads the Quick Start configuration to the device for RX mode.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int rx_quich_start(void);
+
+ /**
+ * @brief Loads the Quick Start configuration to the device for TX mode.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int tx_quich_start(void);
+
+ typedef enum{
+ RECEIVE_MODE,
+ TRANSMIT_MODE
+ }trx_state_t;
+
+ /**
+ * @brief Sets the Device to Receiver or Transmitter Mode.
+ *
+ * @param[in] trx_state desired mode.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_trx_state(trx_state_t trx_state);
+
+ /**
+ * @brief Gets the Mode the Device is in.
+ *
+ * @returns the mode the Device is in, negative error code on failure.
+ */
+ int get_trx_state();
+
+ /**
+ * @brief Transmits the RF data.
+ *
+ * @param[in] data Address of the data to be transmit.
+ * @param[in] data_len Size of the data to be transmit.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int rf_transmit_data(uint8_t *data, uint8_t data_len);
+
+ /**
+ * @brief Receives the RF data.
+ *
+ * @param[in] coded_data the address where the received data will be stored.
+ * @param[in] coded_data_len the length of the data to be received.
+ *
+ * @description The coded data is sampled at twice the data rate. The coded data must be filtered.
+ * @returns 0 on success, negative error code on failure.
+ */
+ int rf_receive_data(uint8_t *coded_data, uint8_t coded_data_len);
+
+ /**
+ * @brief Sets the T/R Pin if defined.
+ *
+ * @param[in] pin_state desired pin state.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int set_trx_pin(trx_state_t pin_state);
+};
+
+#endif /* MAX7032_MAX7032_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/Max7032_regs.h Mon Aug 02 16:42:52 2021 +0300
@@ -0,0 +1,325 @@
+/*******************************************************************************
+ * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc.shall not be used except as stated in the Maxim Integrated
+ * Products, Inc.Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc.retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MAX7032_REGS_H_
+#define MAX7032_REGS_H_
+
+/**
+ * @brief POWER Register
+ *
+ * Address : 0x00
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char x : 1; /**< None Not used */
+ unsigned char rssio : 1; /**< RSSI amplifier enable 1 = Enable buffer 0 = Disable buffer */
+ unsigned char pa : 1; /**< Transmitter PA enable 1 = Enable PA 0 = Disable PA */
+ unsigned char pkdet : 1; /**< Peak-detector enable 1 = Enable peak detector 0 = Disable peak detector */
+ unsigned char baseb : 1; /**< Baseband enable 1 = Enable baseband 0 = Disable baseband */
+ unsigned char mixer : 1; /**< Mixer enable 1 = Enable mixer 0 = Disable mixer */
+ unsigned char agc : 1; /**< AGC enable 1 = Enable AGC 0 = Disable AGC */
+ unsigned char lna : 1; /**< LNA enable 1 = Enable LNA 0 = Disable LNA */
+ } bits;
+} max7032_power_t;
+
+/**
+ * @brief CONTRL Register
+ *
+ * Address : 0x01
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char sleep : 1; /**< Sleep mode 1 = Deep-sleep
+ 0 = Normal operation */
+ unsigned char ckout : 1; /**< Crystal clock output enable 1 = Enable crystal clock output
+ 0 = Disable crystal clock output */
+ unsigned char fcal : 1; /**< FSK calibration 1 = Perform FSK calibration Automatically */
+ unsigned char pcal : 1; /**< Polling timer calibration 1 = Perform polling timer calibration Automatically*/
+ unsigned char x : 1; /**< None Not used*/
+ unsigned char trk_en : 1; /**< Manual peak-detector tracking 1 = Force manual peak-detector tracking
+ 0 = Release peak-detector tracking*/
+ unsigned char gain : 1; /**< Gain state 1 = Force manual high-gain state if MGAIN = 1
+ 0 = Force manual low-gain state if MGAIN = 1*/
+ unsigned char agclk : 1; /**< AGC locking feature 1 = Enable AGC lock
+ 0 = Disable AGC lock*/
+ } bits;
+} max7032_contrl_t;
+
+/**
+ * @brief CONF0 Register
+ *
+ * Address : 0x02
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char onps : 2; /**< On-timer prescaler Sets the time base for the on timer */
+ unsigned char ofps : 2; /**< Off-timer prescaler Sets the time base for the off timer */
+ unsigned char drx : 1; /**< Discontinuous receive mode 1 = Enable DRX
+ 0 = Disable DRX */
+ unsigned char mgain : 1; /**< Manual gain mode 1 = Enable manual-gain mode
+ 0 = Disable manual-gain mode */
+ unsigned char t_r : 1; /**< Transmit or receive 1 = Enable transmit mode of the transceiver
+ 0 = Enable receive mode of the transceiver */
+ unsigned char mode : 1; /**< FSK or ASK modulation 1 = Enable FSK for both receive and transmit
+ 0 = Enable ASK for both receive and transmit */
+ } bits;
+} max7032_conf0_t;
+
+/**
+ * @brief CONF1 Register
+ *
+ * Address : 0x03
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char dt : 3; /**< AGC dwell timer AGC dwell timer */
+ unsigned char cdiv : 2; /**< Crystal divider CLKOUT crystal-divider */
+ unsigned char clkof : 1; /**< Continuous clock output 1 = Enable continuous clock output when CKOUT = 1
+ 0 = Continuous clock output */
+ unsigned char acal : 1; /**< Automatic FSK calibration 1 = Enable automatic FSK calibration
+ 0 = Disable automatic FSK calibration*/
+ unsigned char x : 1; /**< None Not used*/
+ } bits;
+} max7032_conf1_t;
+
+/**
+ * @brief OSC Register
+ *
+ * Address : 0x05
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char osc;
+ } bits;
+} max7032_osc_t;
+
+/**
+ * @brief tOFF Register (Upper Byte)
+ *
+ * Address : 0x06
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char toff_upper;
+ } bits;
+} max7032_toff_upper_t;
+
+/**
+ * @brief tOFF Register (Lower Byte)
+ *
+ * Address : 0x07
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char toff_lower;
+ } bits;
+} max7032_toff_lower_t;
+
+/**
+ * @brief tCPU Register
+ *
+ * Address : 0x08
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char tcpu;
+ } bits;
+} max7032_tcpu_t;
+
+/**
+ * @brief tRF Register (Upper Byte)
+ *
+ * Address : 0x09
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char trf_upper;
+ } bits;
+} max7032_trf_upper_t;
+
+/**
+ * @brief tRF Register (Lower Byte)
+ *
+ * Address : 0x0A
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char trf_lower;
+ } bits;
+} max7032_trf_lower_t;
+
+/**
+ * @brief tON Register (Upper Byte)
+ *
+ * Address : 0x0B
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char ton_upper;
+ } bits;
+} max7032_ton_upper_t;
+
+/**
+ * @brief tON Register (Lower Byte)
+ *
+ * Address : 0x0C
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char ton_lower;
+ } bits;
+} max7032_ton_lower_t;
+
+/**
+ * @brief TxLOW Register (Upper Byte)
+ *
+ * Address : 0x0D
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char txlow_upper;
+ } bits;
+} max7032_txlow_upper_t;
+
+/**
+ * @brief TxLOW Register (Lower Byte)
+ *
+ * Address : 0x0E
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char txlow_lower;
+ } bits;
+} max7032_txlow_lower_t;
+
+/**
+ * @brief TxHIGH Register (Upper Byte)
+ *
+ * Address : 0x0F
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char txhigh_upper;
+ } bits;
+} max7032_txhigh_upper_t;
+
+/**
+ * @brief TxHIGH Register (Lower Byte)
+ *
+ * Address : 0x10
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char txhigh_lower;
+ } bits;
+} max7032_txhigh_lower_t;
+
+/**
+ * @brief STATUS Register
+ *
+ * Address : 0x1A
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char fcald : 1; /**< FSK calibration done 1 = FSK calibration is completed
+ 0 = FSK calibration is in progress or not completed*/
+ unsigned char pcald : 1; /**< Polling timer calibration done 1 = Polling timer calibration is completed
+ 0 = Polling timer calibration is in progress or not completed*/
+ unsigned char x0 : 1; /**< None Zero*/
+ unsigned char x1 : 1; /**< None Zero*/
+ unsigned char x2 : 1; /**< None Zero*/
+ unsigned char clkon : 1; /**< Clock/crystal alive 1 = Valid clock at crystal inputs
+ 0 = No valid clock signal seen at the crystal inputs*/
+ unsigned char gains : 1; /**< AGC gain state 1 = LNA in high-gain state
+ 0 = LNA in low-gain state*/
+ unsigned char lckd : 1; /**< Lock detect 1 = Internal PLL is locked
+ 0 = Internal PLL is not locked */
+ } bits;
+} max7032_status_t;
+
+/**
+ * @brief DEMOD Register
+ *
+ * Address : 0x00
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char dummy_byte;
+
+ } bits;
+} max7032_dummy_t;
+
+/**
+ * @brief Register Set
+ *
+ *
+ */
+typedef struct {
+ max7032_power_t power;
+ max7032_contrl_t contrl;
+ max7032_conf0_t conf0;
+ max7032_conf1_t conf1;
+ max7032_osc_t osc;
+ max7032_toff_upper_t toff_upper;
+ max7032_toff_lower_t toff_lower;
+ max7032_tcpu_t tcpu;
+ max7032_trf_upper_t trf_upper;
+ max7032_trf_lower_t trf_lower;
+ max7032_ton_upper_t ton_upper;
+ max7032_ton_lower_t ton_lower;
+ max7032_txlow_upper_t txlow_upper;
+ max7032_txlow_lower_t txlow_lower;
+ max7032_txhigh_upper_t txhigh_upper;
+ max7032_txhigh_lower_t txhigh_lower;
+ max7032_status_t status;
+} max7032_reg_map_t;
+
+#endif /* MAX7032_REGS_H_ */