MAX7032 Transceiver Mbed Driver
Max7032.cpp@0:65766360f6b9, 2021-08-02 (annotated)
- Committer:
- Sinan Divarci
- Date:
- Mon Aug 02 16:42:52 2021 +0300
- Revision:
- 0:65766360f6b9
initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Sinan Divarci |
0:65766360f6b9 | 1 | /******************************************************************************* |
Sinan Divarci |
0:65766360f6b9 | 2 | * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. |
Sinan Divarci |
0:65766360f6b9 | 3 | * |
Sinan Divarci |
0:65766360f6b9 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Sinan Divarci |
0:65766360f6b9 | 5 | * copy of this software and associated documentation files(the "Software"), |
Sinan Divarci |
0:65766360f6b9 | 6 | * to deal in the Software without restriction, including without limitation |
Sinan Divarci |
0:65766360f6b9 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Sinan Divarci |
0:65766360f6b9 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Sinan Divarci |
0:65766360f6b9 | 9 | * Software is furnished to do so, subject to the following conditions: |
Sinan Divarci |
0:65766360f6b9 | 10 | * |
Sinan Divarci |
0:65766360f6b9 | 11 | * The above copyright notice and this permission notice shall be included |
Sinan Divarci |
0:65766360f6b9 | 12 | * in all copies or substantial portions of the Software. |
Sinan Divarci |
0:65766360f6b9 | 13 | * |
Sinan Divarci |
0:65766360f6b9 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Sinan Divarci |
0:65766360f6b9 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Sinan Divarci |
0:65766360f6b9 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Sinan Divarci |
0:65766360f6b9 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Sinan Divarci |
0:65766360f6b9 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Sinan Divarci |
0:65766360f6b9 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Sinan Divarci |
0:65766360f6b9 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Sinan Divarci |
0:65766360f6b9 | 21 | * |
Sinan Divarci |
0:65766360f6b9 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
Sinan Divarci |
0:65766360f6b9 | 23 | * Products, Inc.shall not be used except as stated in the Maxim Integrated |
Sinan Divarci |
0:65766360f6b9 | 24 | * Products, Inc.Branding Policy. |
Sinan Divarci |
0:65766360f6b9 | 25 | * |
Sinan Divarci |
0:65766360f6b9 | 26 | * The mere transfer of this software does not imply any licenses |
Sinan Divarci |
0:65766360f6b9 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Sinan Divarci |
0:65766360f6b9 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Sinan Divarci |
0:65766360f6b9 | 29 | * property whatsoever. Maxim Integrated Products, Inc.retains all |
Sinan Divarci |
0:65766360f6b9 | 30 | * ownership rights. |
Sinan Divarci |
0:65766360f6b9 | 31 | ******************************************************************************* |
Sinan Divarci |
0:65766360f6b9 | 32 | */ |
Sinan Divarci |
0:65766360f6b9 | 33 | |
Sinan Divarci |
0:65766360f6b9 | 34 | #include <iostream> |
Sinan Divarci |
0:65766360f6b9 | 35 | #include "Max7032.h" |
Sinan Divarci |
0:65766360f6b9 | 36 | #include "math.h" |
Sinan Divarci |
0:65766360f6b9 | 37 | |
Sinan Divarci |
0:65766360f6b9 | 38 | using namespace std; |
Sinan Divarci |
0:65766360f6b9 | 39 | |
Sinan Divarci |
0:65766360f6b9 | 40 | const uint8_t rx_quick_start[Q_START_CONF_LEN] = {0xFA,0x04,0x00,0x02,0x00,0xB0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; |
Sinan Divarci |
0:65766360f6b9 | 41 | const uint8_t tx_quick_start[Q_START_CONF_LEN] = {0xFE,0x04,0x40,0x02,0x00,0xB0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89,0xB5,0x00,0x00}; |
Sinan Divarci |
0:65766360f6b9 | 42 | |
Sinan Divarci |
0:65766360f6b9 | 43 | MAX7032::MAX7032(SPI *spi, DigitalOut *cs, DigitalOut *powerPin, PinName dataPin, DigitalOut *dioPin, DigitalOut *trxPin) |
Sinan Divarci |
0:65766360f6b9 | 44 | { |
Sinan Divarci |
0:65766360f6b9 | 45 | operation_mode = UNINITIALIZED; |
Sinan Divarci |
0:65766360f6b9 | 46 | |
Sinan Divarci |
0:65766360f6b9 | 47 | if (spi == NULL || cs == NULL || powerPin == NULL || dataPin == NULL || dioPin == NULL || trxPin == NULL) |
Sinan Divarci |
0:65766360f6b9 | 48 | return; |
Sinan Divarci |
0:65766360f6b9 | 49 | |
Sinan Divarci |
0:65766360f6b9 | 50 | max7032_reg_map_t reg; |
Sinan Divarci |
0:65766360f6b9 | 51 | |
Sinan Divarci |
0:65766360f6b9 | 52 | reg_map = ® |
Sinan Divarci |
0:65766360f6b9 | 53 | spi_handler = spi; |
Sinan Divarci |
0:65766360f6b9 | 54 | ssel = cs; |
Sinan Divarci |
0:65766360f6b9 | 55 | power_pin = powerPin; |
Sinan Divarci |
0:65766360f6b9 | 56 | data_pin = dataPin; |
Sinan Divarci |
0:65766360f6b9 | 57 | dio = dioPin; |
Sinan Divarci |
0:65766360f6b9 | 58 | trx_pin = trxPin; |
Sinan Divarci |
0:65766360f6b9 | 59 | preset_mode = 0; |
Sinan Divarci |
0:65766360f6b9 | 60 | |
Sinan Divarci |
0:65766360f6b9 | 61 | encoding = Manchester; |
Sinan Divarci |
0:65766360f6b9 | 62 | f_xtal = 16.0f; |
Sinan Divarci |
0:65766360f6b9 | 63 | f_rf = 315.0f; |
Sinan Divarci |
0:65766360f6b9 | 64 | fsk_dev = 0.05f; |
Sinan Divarci |
0:65766360f6b9 | 65 | |
Sinan Divarci |
0:65766360f6b9 | 66 | data_rate = 1.0f; |
Sinan Divarci |
0:65766360f6b9 | 67 | data_read = NULL; |
Sinan Divarci |
0:65766360f6b9 | 68 | data_send = NULL; |
Sinan Divarci |
0:65766360f6b9 | 69 | |
Sinan Divarci |
0:65766360f6b9 | 70 | if (initial_programming() < 0) |
Sinan Divarci |
0:65766360f6b9 | 71 | return; |
Sinan Divarci |
0:65766360f6b9 | 72 | |
Sinan Divarci |
0:65766360f6b9 | 73 | operation_mode = INITIALIZED; |
Sinan Divarci |
0:65766360f6b9 | 74 | } |
Sinan Divarci |
0:65766360f6b9 | 75 | |
Sinan Divarci |
0:65766360f6b9 | 76 | MAX7032::MAX7032(SPI *spi, DigitalOut *powerPin, PinName dataPin, DigitalOut *dioPin, DigitalOut *trxPin) |
Sinan Divarci |
0:65766360f6b9 | 77 | { |
Sinan Divarci |
0:65766360f6b9 | 78 | operation_mode = UNINITIALIZED; |
Sinan Divarci |
0:65766360f6b9 | 79 | |
Sinan Divarci |
0:65766360f6b9 | 80 | if (spi == NULL || powerPin == NULL || dataPin == NULL || dioPin == NULL || trxPin == NULL) |
Sinan Divarci |
0:65766360f6b9 | 81 | return; |
Sinan Divarci |
0:65766360f6b9 | 82 | |
Sinan Divarci |
0:65766360f6b9 | 83 | max7032_reg_map_t reg; |
Sinan Divarci |
0:65766360f6b9 | 84 | |
Sinan Divarci |
0:65766360f6b9 | 85 | reg_map = ® |
Sinan Divarci |
0:65766360f6b9 | 86 | spi_handler = spi; |
Sinan Divarci |
0:65766360f6b9 | 87 | ssel = NULL; |
Sinan Divarci |
0:65766360f6b9 | 88 | power_pin = powerPin; |
Sinan Divarci |
0:65766360f6b9 | 89 | data_pin = dataPin; |
Sinan Divarci |
0:65766360f6b9 | 90 | dio = dioPin; |
Sinan Divarci |
0:65766360f6b9 | 91 | trx_pin = trxPin; |
Sinan Divarci |
0:65766360f6b9 | 92 | preset_mode = 0; |
Sinan Divarci |
0:65766360f6b9 | 93 | |
Sinan Divarci |
0:65766360f6b9 | 94 | encoding = Manchester; |
Sinan Divarci |
0:65766360f6b9 | 95 | f_xtal = 16.0f; |
Sinan Divarci |
0:65766360f6b9 | 96 | f_rf = 315.0f; |
Sinan Divarci |
0:65766360f6b9 | 97 | fsk_dev = 0.05f; |
Sinan Divarci |
0:65766360f6b9 | 98 | |
Sinan Divarci |
0:65766360f6b9 | 99 | data_rate = 1.0f; |
Sinan Divarci |
0:65766360f6b9 | 100 | data_read = NULL; |
Sinan Divarci |
0:65766360f6b9 | 101 | data_send = NULL; |
Sinan Divarci |
0:65766360f6b9 | 102 | |
Sinan Divarci |
0:65766360f6b9 | 103 | if (initial_programming() < 0) |
Sinan Divarci |
0:65766360f6b9 | 104 | return; |
Sinan Divarci |
0:65766360f6b9 | 105 | |
Sinan Divarci |
0:65766360f6b9 | 106 | operation_mode = INITIALIZED; |
Sinan Divarci |
0:65766360f6b9 | 107 | } |
Sinan Divarci |
0:65766360f6b9 | 108 | |
Sinan Divarci |
0:65766360f6b9 | 109 | MAX7032::~MAX7032() |
Sinan Divarci |
0:65766360f6b9 | 110 | { |
Sinan Divarci |
0:65766360f6b9 | 111 | if(data_read != NULL) |
Sinan Divarci |
0:65766360f6b9 | 112 | delete data_read; |
Sinan Divarci |
0:65766360f6b9 | 113 | |
Sinan Divarci |
0:65766360f6b9 | 114 | if(data_send != NULL) |
Sinan Divarci |
0:65766360f6b9 | 115 | delete data_send; |
Sinan Divarci |
0:65766360f6b9 | 116 | } |
Sinan Divarci |
0:65766360f6b9 | 117 | |
Sinan Divarci |
0:65766360f6b9 | 118 | int MAX7032::read_register(uint8_t reg, uint8_t *value) |
Sinan Divarci |
0:65766360f6b9 | 119 | { |
Sinan Divarci |
0:65766360f6b9 | 120 | |
Sinan Divarci |
0:65766360f6b9 | 121 | int rtn_val = 0; |
Sinan Divarci |
0:65766360f6b9 | 122 | //Since 3-wire spi is not supported by mbed, the read_register function must be implemented by the user. |
Sinan Divarci |
0:65766360f6b9 | 123 | //Here you can find an implemented read_register function for the max32630fthr. |
Sinan Divarci |
0:65766360f6b9 | 124 | #if defined(TARGET_MAX32630FTHR) |
Sinan Divarci |
0:65766360f6b9 | 125 | if (value == NULL) { |
Sinan Divarci |
0:65766360f6b9 | 126 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 127 | } |
Sinan Divarci |
0:65766360f6b9 | 128 | |
Sinan Divarci |
0:65766360f6b9 | 129 | if (this->reg_map == NULL) { |
Sinan Divarci |
0:65766360f6b9 | 130 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 131 | } |
Sinan Divarci |
0:65766360f6b9 | 132 | |
Sinan Divarci |
0:65766360f6b9 | 133 | spi_handler->format(8,0); |
Sinan Divarci |
0:65766360f6b9 | 134 | spi_handler->frequency(400000); |
Sinan Divarci |
0:65766360f6b9 | 135 | |
Sinan Divarci |
0:65766360f6b9 | 136 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 137 | *ssel = 0; |
Sinan Divarci |
0:65766360f6b9 | 138 | } |
Sinan Divarci |
0:65766360f6b9 | 139 | spi_handler->write((uint8_t)0x80 | reg); // Set R/W bit 1 for reading |
Sinan Divarci |
0:65766360f6b9 | 140 | spi_handler->write(0x00); // dummy write command for waiting data read |
Sinan Divarci |
0:65766360f6b9 | 141 | |
Sinan Divarci |
0:65766360f6b9 | 142 | MAX7032_SPI->mstr_cfg |= MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE; |
Sinan Divarci |
0:65766360f6b9 | 143 | |
Sinan Divarci |
0:65766360f6b9 | 144 | // Disable SPI for General Control Configuration |
Sinan Divarci |
0:65766360f6b9 | 145 | MAX7032_SPI->gen_ctrl = 0; |
Sinan Divarci |
0:65766360f6b9 | 146 | MAX7032_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (1 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header |
Sinan Divarci |
0:65766360f6b9 | 147 | |
Sinan Divarci |
0:65766360f6b9 | 148 | MAX7032_SPI->simple_headers &= 0x0000FFFF; |
Sinan Divarci |
0:65766360f6b9 | 149 | MAX7032_SPI->simple_headers |= 0x2016<<16; |
Sinan Divarci |
0:65766360f6b9 | 150 | MAX7032_SPI->gen_ctrl |=MXC_F_SPIM_GEN_CTRL_START_RX_ONLY; |
Sinan Divarci |
0:65766360f6b9 | 151 | |
Sinan Divarci |
0:65766360f6b9 | 152 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 153 | *ssel = 1; |
Sinan Divarci |
0:65766360f6b9 | 154 | wait_us(5); |
Sinan Divarci |
0:65766360f6b9 | 155 | *ssel = 0; |
Sinan Divarci |
0:65766360f6b9 | 156 | } |
Sinan Divarci |
0:65766360f6b9 | 157 | |
Sinan Divarci |
0:65766360f6b9 | 158 | // Enable the SPI |
Sinan Divarci |
0:65766360f6b9 | 159 | MAX7032_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN; |
Sinan Divarci |
0:65766360f6b9 | 160 | |
Sinan Divarci |
0:65766360f6b9 | 161 | volatile mxc_spim_fifo_regs_t *fifo; |
Sinan Divarci |
0:65766360f6b9 | 162 | |
Sinan Divarci |
0:65766360f6b9 | 163 | fifo = MXC_SPIM_GET_SPIM_FIFO(MXC_SPIM_GET_IDX(MAX7032_SPI)); |
Sinan Divarci |
0:65766360f6b9 | 164 | |
Sinan Divarci |
0:65766360f6b9 | 165 | int avail = ((MAX7032_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); |
Sinan Divarci |
0:65766360f6b9 | 166 | |
Sinan Divarci |
0:65766360f6b9 | 167 | Timer *t = NULL; |
Sinan Divarci |
0:65766360f6b9 | 168 | t = new Timer(); |
Sinan Divarci |
0:65766360f6b9 | 169 | |
Sinan Divarci |
0:65766360f6b9 | 170 | t->start(); |
Sinan Divarci |
0:65766360f6b9 | 171 | |
Sinan Divarci |
0:65766360f6b9 | 172 | while (avail < 1) { |
Sinan Divarci |
0:65766360f6b9 | 173 | if (t->read_ms() > 1000) { |
Sinan Divarci |
0:65766360f6b9 | 174 | rtn_val = -1; |
Sinan Divarci |
0:65766360f6b9 | 175 | break; |
Sinan Divarci |
0:65766360f6b9 | 176 | } else { |
Sinan Divarci |
0:65766360f6b9 | 177 | avail = ((MAX7032_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS); |
Sinan Divarci |
0:65766360f6b9 | 178 | } |
Sinan Divarci |
0:65766360f6b9 | 179 | } |
Sinan Divarci |
0:65766360f6b9 | 180 | |
Sinan Divarci |
0:65766360f6b9 | 181 | t->stop(); |
Sinan Divarci |
0:65766360f6b9 | 182 | |
Sinan Divarci |
0:65766360f6b9 | 183 | *(value++) = fifo->rslts_8[0]; |
Sinan Divarci |
0:65766360f6b9 | 184 | |
Sinan Divarci |
0:65766360f6b9 | 185 | while (MAX7032_SPI->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) { |
Sinan Divarci |
0:65766360f6b9 | 186 | fifo->rslts_8[0]; |
Sinan Divarci |
0:65766360f6b9 | 187 | } |
Sinan Divarci |
0:65766360f6b9 | 188 | |
Sinan Divarci |
0:65766360f6b9 | 189 | MAX7032_SPI->gen_ctrl = 0; |
Sinan Divarci |
0:65766360f6b9 | 190 | MAX7032_SPI->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE | (0 << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)); // simple header |
Sinan Divarci |
0:65766360f6b9 | 191 | |
Sinan Divarci |
0:65766360f6b9 | 192 | MAX7032_SPI->gen_ctrl |= MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN; |
Sinan Divarci |
0:65766360f6b9 | 193 | |
Sinan Divarci |
0:65766360f6b9 | 194 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 195 | *ssel = 1; |
Sinan Divarci |
0:65766360f6b9 | 196 | } |
Sinan Divarci |
0:65766360f6b9 | 197 | |
Sinan Divarci |
0:65766360f6b9 | 198 | t->~Timer(); |
Sinan Divarci |
0:65766360f6b9 | 199 | delete t; |
Sinan Divarci |
0:65766360f6b9 | 200 | #else |
Sinan Divarci |
0:65766360f6b9 | 201 | if (value == NULL) { |
Sinan Divarci |
0:65766360f6b9 | 202 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 203 | } |
Sinan Divarci |
0:65766360f6b9 | 204 | |
Sinan Divarci |
0:65766360f6b9 | 205 | if (this->reg_map == NULL) { |
Sinan Divarci |
0:65766360f6b9 | 206 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 207 | } |
Sinan Divarci |
0:65766360f6b9 | 208 | |
Sinan Divarci |
0:65766360f6b9 | 209 | spi_handler->format(8,0); |
Sinan Divarci |
0:65766360f6b9 | 210 | spi_handler->frequency(400000); |
Sinan Divarci |
0:65766360f6b9 | 211 | |
Sinan Divarci |
0:65766360f6b9 | 212 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 213 | *ssel = 0; |
Sinan Divarci |
0:65766360f6b9 | 214 | } |
Sinan Divarci |
0:65766360f6b9 | 215 | spi_handler->write((uint8_t)0x80 | reg); |
Sinan Divarci |
0:65766360f6b9 | 216 | |
Sinan Divarci |
0:65766360f6b9 | 217 | spi_handler->write(0x00); // dummy write command for waiting data read |
Sinan Divarci |
0:65766360f6b9 | 218 | |
Sinan Divarci |
0:65766360f6b9 | 219 | *(value++) = spi_handler->write(0x00); // read back data bytes |
Sinan Divarci |
0:65766360f6b9 | 220 | |
Sinan Divarci |
0:65766360f6b9 | 221 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 222 | *ssel = 1; |
Sinan Divarci |
0:65766360f6b9 | 223 | } |
Sinan Divarci |
0:65766360f6b9 | 224 | #endif |
Sinan Divarci |
0:65766360f6b9 | 225 | *dio = 0; |
Sinan Divarci |
0:65766360f6b9 | 226 | return rtn_val; |
Sinan Divarci |
0:65766360f6b9 | 227 | } |
Sinan Divarci |
0:65766360f6b9 | 228 | |
Sinan Divarci |
0:65766360f6b9 | 229 | int MAX7032::write_register(uint8_t reg, const uint8_t *value, uint8_t len) |
Sinan Divarci |
0:65766360f6b9 | 230 | { |
Sinan Divarci |
0:65766360f6b9 | 231 | int rtn_val = -1; |
Sinan Divarci |
0:65766360f6b9 | 232 | uint8_t local_data[1 + len]; |
Sinan Divarci |
0:65766360f6b9 | 233 | |
Sinan Divarci |
0:65766360f6b9 | 234 | if (value == NULL) { |
Sinan Divarci |
0:65766360f6b9 | 235 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 236 | } |
Sinan Divarci |
0:65766360f6b9 | 237 | |
Sinan Divarci |
0:65766360f6b9 | 238 | memcpy(&local_data[0], value, len); |
Sinan Divarci |
0:65766360f6b9 | 239 | |
Sinan Divarci |
0:65766360f6b9 | 240 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 241 | *ssel = 0; |
Sinan Divarci |
0:65766360f6b9 | 242 | } |
Sinan Divarci |
0:65766360f6b9 | 243 | |
Sinan Divarci |
0:65766360f6b9 | 244 | rtn_val = spi_handler->write(0x40 | reg); // write mode and adress send |
Sinan Divarci |
0:65766360f6b9 | 245 | for (int i = 0; i < len; i++) { |
Sinan Divarci |
0:65766360f6b9 | 246 | rtn_val = spi_handler->write(local_data[i]); // write adress |
Sinan Divarci |
0:65766360f6b9 | 247 | } |
Sinan Divarci |
0:65766360f6b9 | 248 | |
Sinan Divarci |
0:65766360f6b9 | 249 | if (ssel != NULL) { |
Sinan Divarci |
0:65766360f6b9 | 250 | *ssel = 1; |
Sinan Divarci |
0:65766360f6b9 | 251 | } |
Sinan Divarci |
0:65766360f6b9 | 252 | |
Sinan Divarci |
0:65766360f6b9 | 253 | *dio = 0; |
Sinan Divarci |
0:65766360f6b9 | 254 | |
Sinan Divarci |
0:65766360f6b9 | 255 | if (rtn_val < 0) { |
Sinan Divarci |
0:65766360f6b9 | 256 | return rtn_val; |
Sinan Divarci |
0:65766360f6b9 | 257 | } |
Sinan Divarci |
0:65766360f6b9 | 258 | |
Sinan Divarci |
0:65766360f6b9 | 259 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 260 | } |
Sinan Divarci |
0:65766360f6b9 | 261 | |
Sinan Divarci |
0:65766360f6b9 | 262 | #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \ |
Sinan Divarci |
0:65766360f6b9 | 263 | do { \ |
Sinan Divarci |
0:65766360f6b9 | 264 | int ret; \ |
Sinan Divarci |
0:65766360f6b9 | 265 | ret = read_register(address, (uint8_t *)&(reg_name)); \ |
Sinan Divarci |
0:65766360f6b9 | 266 | if (ret) { \ |
Sinan Divarci |
0:65766360f6b9 | 267 | return ret; \ |
Sinan Divarci |
0:65766360f6b9 | 268 | } \ |
Sinan Divarci |
0:65766360f6b9 | 269 | bit_field_name = value; \ |
Sinan Divarci |
0:65766360f6b9 | 270 | ret = write_register(address, (uint8_t *)&(reg_name), 1); \ |
Sinan Divarci |
0:65766360f6b9 | 271 | if (ret) { \ |
Sinan Divarci |
0:65766360f6b9 | 272 | return ret; \ |
Sinan Divarci |
0:65766360f6b9 | 273 | } \ |
Sinan Divarci |
0:65766360f6b9 | 274 | } while (0) |
Sinan Divarci |
0:65766360f6b9 | 275 | |
Sinan Divarci |
0:65766360f6b9 | 276 | int MAX7032::initial_programming(void) |
Sinan Divarci |
0:65766360f6b9 | 277 | { |
Sinan Divarci |
0:65766360f6b9 | 278 | uint8_t address; |
Sinan Divarci |
0:65766360f6b9 | 279 | |
Sinan Divarci |
0:65766360f6b9 | 280 | set_power_on_off(1); |
Sinan Divarci |
0:65766360f6b9 | 281 | |
Sinan Divarci |
0:65766360f6b9 | 282 | rx_quich_start(); |
Sinan Divarci |
0:65766360f6b9 | 283 | |
Sinan Divarci |
0:65766360f6b9 | 284 | set_center_freq(f_rf); |
Sinan Divarci |
0:65766360f6b9 | 285 | adjust_osc_freq(f_xtal); |
Sinan Divarci |
0:65766360f6b9 | 286 | set_trx_state(MAX7032::RECEIVE_MODE); |
Sinan Divarci |
0:65766360f6b9 | 287 | |
Sinan Divarci |
0:65766360f6b9 | 288 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 289 | } |
Sinan Divarci |
0:65766360f6b9 | 290 | |
Sinan Divarci |
0:65766360f6b9 | 291 | int MAX7032::rx_quich_start(void) |
Sinan Divarci |
0:65766360f6b9 | 292 | { |
Sinan Divarci |
0:65766360f6b9 | 293 | uint8_t address; |
Sinan Divarci |
0:65766360f6b9 | 294 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 295 | |
Sinan Divarci |
0:65766360f6b9 | 296 | for(address = 0; address < Q_START_CONF_LEN; address++) |
Sinan Divarci |
0:65766360f6b9 | 297 | { |
Sinan Divarci |
0:65766360f6b9 | 298 | if(address == 4) |
Sinan Divarci |
0:65766360f6b9 | 299 | continue; |
Sinan Divarci |
0:65766360f6b9 | 300 | |
Sinan Divarci |
0:65766360f6b9 | 301 | ret = write_register(address, (uint8_t *)&(rx_quick_start[address]), 1); |
Sinan Divarci |
0:65766360f6b9 | 302 | if (ret) { |
Sinan Divarci |
0:65766360f6b9 | 303 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 304 | } |
Sinan Divarci |
0:65766360f6b9 | 305 | |
Sinan Divarci |
0:65766360f6b9 | 306 | // ((max7032_dummy_t *)(&this->reg_map->power + address))->raw = rx_quick_start[address]; |
Sinan Divarci |
0:65766360f6b9 | 307 | } |
Sinan Divarci |
0:65766360f6b9 | 308 | |
Sinan Divarci |
0:65766360f6b9 | 309 | this->reg_map->power.raw = rx_quick_start[POWER_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 310 | this->reg_map->contrl.raw = rx_quick_start[CONTRL_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 311 | this->reg_map->conf0.raw = rx_quick_start[CONF0_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 312 | this->reg_map->conf1.raw = rx_quick_start[CONF1_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 313 | this->reg_map->osc.raw = rx_quick_start[OSC_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 314 | this->reg_map->toff_upper.raw = rx_quick_start[TOFFMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 315 | this->reg_map->toff_lower.raw = rx_quick_start[TOFFLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 316 | this->reg_map->tcpu.raw = rx_quick_start[TCPU_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 317 | this->reg_map->trf_upper.raw = rx_quick_start[TRFMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 318 | this->reg_map->trf_lower.raw = rx_quick_start[TRFLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 319 | this->reg_map->ton_upper.raw = rx_quick_start[TONMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 320 | this->reg_map->ton_lower.raw = rx_quick_start[TONLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 321 | this->reg_map->txlow_upper.raw = rx_quick_start[TXLOWMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 322 | this->reg_map->txlow_lower.raw = rx_quick_start[TXLOWLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 323 | this->reg_map->txhigh_upper.raw = rx_quick_start[TXHIGHMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 324 | this->reg_map->txhigh_lower.raw = rx_quick_start[TXHIGHLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 325 | |
Sinan Divarci |
0:65766360f6b9 | 326 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 327 | } |
Sinan Divarci |
0:65766360f6b9 | 328 | |
Sinan Divarci |
0:65766360f6b9 | 329 | int MAX7032::tx_quich_start(void) |
Sinan Divarci |
0:65766360f6b9 | 330 | { |
Sinan Divarci |
0:65766360f6b9 | 331 | uint8_t address; |
Sinan Divarci |
0:65766360f6b9 | 332 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 333 | |
Sinan Divarci |
0:65766360f6b9 | 334 | for(address = 0; address < Q_START_CONF_LEN; address++) |
Sinan Divarci |
0:65766360f6b9 | 335 | { |
Sinan Divarci |
0:65766360f6b9 | 336 | if(address == 4) |
Sinan Divarci |
0:65766360f6b9 | 337 | continue; |
Sinan Divarci |
0:65766360f6b9 | 338 | |
Sinan Divarci |
0:65766360f6b9 | 339 | ret = write_register(address, (uint8_t *)&(tx_quick_start[address]), 1); |
Sinan Divarci |
0:65766360f6b9 | 340 | if (ret) { |
Sinan Divarci |
0:65766360f6b9 | 341 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 342 | } |
Sinan Divarci |
0:65766360f6b9 | 343 | |
Sinan Divarci |
0:65766360f6b9 | 344 | // ((max7032_dummy_t *)(&this->reg_map->power + address))->raw = tx_quick_start[address]; |
Sinan Divarci |
0:65766360f6b9 | 345 | } |
Sinan Divarci |
0:65766360f6b9 | 346 | |
Sinan Divarci |
0:65766360f6b9 | 347 | this->reg_map->power.raw = tx_quick_start[POWER_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 348 | this->reg_map->contrl.raw = tx_quick_start[CONTRL_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 349 | this->reg_map->conf0.raw = tx_quick_start[CONF0_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 350 | this->reg_map->conf1.raw = tx_quick_start[CONF1_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 351 | this->reg_map->osc.raw = tx_quick_start[OSC_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 352 | this->reg_map->toff_upper.raw = tx_quick_start[TOFFMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 353 | this->reg_map->toff_lower.raw = tx_quick_start[TOFFLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 354 | this->reg_map->tcpu.raw = tx_quick_start[TCPU_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 355 | this->reg_map->trf_upper.raw = tx_quick_start[TRFMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 356 | this->reg_map->trf_lower.raw = tx_quick_start[TRFLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 357 | this->reg_map->ton_upper.raw = tx_quick_start[TONMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 358 | this->reg_map->ton_lower.raw = tx_quick_start[TONLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 359 | this->reg_map->txlow_upper.raw = tx_quick_start[TXLOWMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 360 | this->reg_map->txlow_lower.raw = tx_quick_start[TXLOWLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 361 | this->reg_map->txhigh_upper.raw = tx_quick_start[TXHIGHMSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 362 | this->reg_map->txhigh_lower.raw = tx_quick_start[TXHIGHLSB_ADDR]; |
Sinan Divarci |
0:65766360f6b9 | 363 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 364 | } |
Sinan Divarci |
0:65766360f6b9 | 365 | |
Sinan Divarci |
0:65766360f6b9 | 366 | int MAX7032::set_power_on_off(uint8_t power) |
Sinan Divarci |
0:65766360f6b9 | 367 | { |
Sinan Divarci |
0:65766360f6b9 | 368 | |
Sinan Divarci |
0:65766360f6b9 | 369 | if (power == 0) { // Shut down the device |
Sinan Divarci |
0:65766360f6b9 | 370 | |
Sinan Divarci |
0:65766360f6b9 | 371 | *this->power_pin = 0; |
Sinan Divarci |
0:65766360f6b9 | 372 | |
Sinan Divarci |
0:65766360f6b9 | 373 | } else { // Turn on the device |
Sinan Divarci |
0:65766360f6b9 | 374 | |
Sinan Divarci |
0:65766360f6b9 | 375 | *this->power_pin = 0; |
Sinan Divarci |
0:65766360f6b9 | 376 | wait_us(1500); |
Sinan Divarci |
0:65766360f6b9 | 377 | *this->power_pin = 1; |
Sinan Divarci |
0:65766360f6b9 | 378 | } |
Sinan Divarci |
0:65766360f6b9 | 379 | |
Sinan Divarci |
0:65766360f6b9 | 380 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 381 | } |
Sinan Divarci |
0:65766360f6b9 | 382 | |
Sinan Divarci |
0:65766360f6b9 | 383 | int MAX7032::get_bit_field(reg_bits_t bit_field, uint8_t *val) |
Sinan Divarci |
0:65766360f6b9 | 384 | { |
Sinan Divarci |
0:65766360f6b9 | 385 | uint8_t reg_addr, bit_pos, reg_val, reg_mask; |
Sinan Divarci |
0:65766360f6b9 | 386 | |
Sinan Divarci |
0:65766360f6b9 | 387 | reg_addr = bit_field / 8; |
Sinan Divarci |
0:65766360f6b9 | 388 | bit_pos = bit_field % 8; |
Sinan Divarci |
0:65766360f6b9 | 389 | |
Sinan Divarci |
0:65766360f6b9 | 390 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 391 | ret = read_register(reg_addr, (uint8_t *)&(reg_val)); |
Sinan Divarci |
0:65766360f6b9 | 392 | if (ret) { |
Sinan Divarci |
0:65766360f6b9 | 393 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 394 | } |
Sinan Divarci |
0:65766360f6b9 | 395 | |
Sinan Divarci |
0:65766360f6b9 | 396 | reg_mask = 0x01; |
Sinan Divarci |
0:65766360f6b9 | 397 | reg_val = reg_val >> bit_pos; |
Sinan Divarci |
0:65766360f6b9 | 398 | reg_val &= reg_mask; |
Sinan Divarci |
0:65766360f6b9 | 399 | |
Sinan Divarci |
0:65766360f6b9 | 400 | *val = reg_val; |
Sinan Divarci |
0:65766360f6b9 | 401 | |
Sinan Divarci |
0:65766360f6b9 | 402 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 403 | } |
Sinan Divarci |
0:65766360f6b9 | 404 | |
Sinan Divarci |
0:65766360f6b9 | 405 | int MAX7032::set_bit_field(reg_bits_t bit_field, uint8_t val) |
Sinan Divarci |
0:65766360f6b9 | 406 | { |
Sinan Divarci |
0:65766360f6b9 | 407 | uint8_t reg_addr, bit_pos, reg_val, reg_mask; |
Sinan Divarci |
0:65766360f6b9 | 408 | |
Sinan Divarci |
0:65766360f6b9 | 409 | reg_addr = bit_field / 8; |
Sinan Divarci |
0:65766360f6b9 | 410 | bit_pos = bit_field % 8; |
Sinan Divarci |
0:65766360f6b9 | 411 | |
Sinan Divarci |
0:65766360f6b9 | 412 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 413 | ret = read_register(reg_addr, (uint8_t *)&(reg_val)); |
Sinan Divarci |
0:65766360f6b9 | 414 | if (ret) { |
Sinan Divarci |
0:65766360f6b9 | 415 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 416 | } |
Sinan Divarci |
0:65766360f6b9 | 417 | |
Sinan Divarci |
0:65766360f6b9 | 418 | reg_mask = 0x01; |
Sinan Divarci |
0:65766360f6b9 | 419 | reg_mask = reg_mask << bit_pos; |
Sinan Divarci |
0:65766360f6b9 | 420 | |
Sinan Divarci |
0:65766360f6b9 | 421 | if(val == 0) |
Sinan Divarci |
0:65766360f6b9 | 422 | reg_val &= ~reg_mask; |
Sinan Divarci |
0:65766360f6b9 | 423 | else if(val == 1) |
Sinan Divarci |
0:65766360f6b9 | 424 | reg_val |= reg_mask; |
Sinan Divarci |
0:65766360f6b9 | 425 | else |
Sinan Divarci |
0:65766360f6b9 | 426 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 427 | |
Sinan Divarci |
0:65766360f6b9 | 428 | ret = write_register(reg_addr, (uint8_t *)®_val, 1); |
Sinan Divarci |
0:65766360f6b9 | 429 | if (ret) { |
Sinan Divarci |
0:65766360f6b9 | 430 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 431 | } |
Sinan Divarci |
0:65766360f6b9 | 432 | |
Sinan Divarci |
0:65766360f6b9 | 433 | if(reg_addr == POWER_ADDR) |
Sinan Divarci |
0:65766360f6b9 | 434 | this->reg_map->power.raw = reg_val; |
Sinan Divarci |
0:65766360f6b9 | 435 | else if(reg_addr == CONTRL_ADDR) |
Sinan Divarci |
0:65766360f6b9 | 436 | this->reg_map->contrl.raw = reg_val; |
Sinan Divarci |
0:65766360f6b9 | 437 | else if(reg_addr == CONF0_ADDR) |
Sinan Divarci |
0:65766360f6b9 | 438 | this->reg_map->conf0.raw = reg_val; |
Sinan Divarci |
0:65766360f6b9 | 439 | else if(reg_addr == CONF1_ADDR) |
Sinan Divarci |
0:65766360f6b9 | 440 | this->reg_map->conf1.raw = reg_val; |
Sinan Divarci |
0:65766360f6b9 | 441 | else |
Sinan Divarci |
0:65766360f6b9 | 442 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 443 | |
Sinan Divarci |
0:65766360f6b9 | 444 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 445 | } |
Sinan Divarci |
0:65766360f6b9 | 446 | |
Sinan Divarci |
0:65766360f6b9 | 447 | int MAX7032::set_lna(uint8_t lna) |
Sinan Divarci |
0:65766360f6b9 | 448 | { |
Sinan Divarci |
0:65766360f6b9 | 449 | if(lna > 1) |
Sinan Divarci |
0:65766360f6b9 | 450 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 451 | |
Sinan Divarci |
0:65766360f6b9 | 452 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.lna, lna); |
Sinan Divarci |
0:65766360f6b9 | 453 | |
Sinan Divarci |
0:65766360f6b9 | 454 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 455 | } |
Sinan Divarci |
0:65766360f6b9 | 456 | |
Sinan Divarci |
0:65766360f6b9 | 457 | int MAX7032::get_lna() |
Sinan Divarci |
0:65766360f6b9 | 458 | { |
Sinan Divarci |
0:65766360f6b9 | 459 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 460 | |
Sinan Divarci |
0:65766360f6b9 | 461 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 462 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 463 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 464 | |
Sinan Divarci |
0:65766360f6b9 | 465 | return this->reg_map->power.bits.lna; |
Sinan Divarci |
0:65766360f6b9 | 466 | } |
Sinan Divarci |
0:65766360f6b9 | 467 | |
Sinan Divarci |
0:65766360f6b9 | 468 | int MAX7032::set_agc(uint8_t agc) |
Sinan Divarci |
0:65766360f6b9 | 469 | { |
Sinan Divarci |
0:65766360f6b9 | 470 | if(agc > 1) |
Sinan Divarci |
0:65766360f6b9 | 471 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 472 | |
Sinan Divarci |
0:65766360f6b9 | 473 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.agc, agc); |
Sinan Divarci |
0:65766360f6b9 | 474 | |
Sinan Divarci |
0:65766360f6b9 | 475 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 476 | } |
Sinan Divarci |
0:65766360f6b9 | 477 | |
Sinan Divarci |
0:65766360f6b9 | 478 | int MAX7032::get_agc() |
Sinan Divarci |
0:65766360f6b9 | 479 | { |
Sinan Divarci |
0:65766360f6b9 | 480 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 481 | |
Sinan Divarci |
0:65766360f6b9 | 482 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 483 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 484 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 485 | |
Sinan Divarci |
0:65766360f6b9 | 486 | return this->reg_map->power.bits.agc; |
Sinan Divarci |
0:65766360f6b9 | 487 | } |
Sinan Divarci |
0:65766360f6b9 | 488 | |
Sinan Divarci |
0:65766360f6b9 | 489 | int MAX7032::set_mixer(uint8_t mixer) |
Sinan Divarci |
0:65766360f6b9 | 490 | { |
Sinan Divarci |
0:65766360f6b9 | 491 | if(mixer > 1) |
Sinan Divarci |
0:65766360f6b9 | 492 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 493 | |
Sinan Divarci |
0:65766360f6b9 | 494 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.mixer, mixer); |
Sinan Divarci |
0:65766360f6b9 | 495 | |
Sinan Divarci |
0:65766360f6b9 | 496 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 497 | } |
Sinan Divarci |
0:65766360f6b9 | 498 | |
Sinan Divarci |
0:65766360f6b9 | 499 | int MAX7032::get_mixer() |
Sinan Divarci |
0:65766360f6b9 | 500 | { |
Sinan Divarci |
0:65766360f6b9 | 501 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 502 | |
Sinan Divarci |
0:65766360f6b9 | 503 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 504 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 505 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 506 | |
Sinan Divarci |
0:65766360f6b9 | 507 | return this->reg_map->power.bits.mixer; |
Sinan Divarci |
0:65766360f6b9 | 508 | } |
Sinan Divarci |
0:65766360f6b9 | 509 | |
Sinan Divarci |
0:65766360f6b9 | 510 | int MAX7032::set_baseb(uint8_t baseb) |
Sinan Divarci |
0:65766360f6b9 | 511 | { |
Sinan Divarci |
0:65766360f6b9 | 512 | if(baseb > 1) |
Sinan Divarci |
0:65766360f6b9 | 513 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 514 | |
Sinan Divarci |
0:65766360f6b9 | 515 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.baseb, baseb); |
Sinan Divarci |
0:65766360f6b9 | 516 | |
Sinan Divarci |
0:65766360f6b9 | 517 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 518 | } |
Sinan Divarci |
0:65766360f6b9 | 519 | |
Sinan Divarci |
0:65766360f6b9 | 520 | int MAX7032::get_baseb() |
Sinan Divarci |
0:65766360f6b9 | 521 | { |
Sinan Divarci |
0:65766360f6b9 | 522 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 523 | |
Sinan Divarci |
0:65766360f6b9 | 524 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 525 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 526 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 527 | |
Sinan Divarci |
0:65766360f6b9 | 528 | return this->reg_map->power.bits.baseb; |
Sinan Divarci |
0:65766360f6b9 | 529 | } |
Sinan Divarci |
0:65766360f6b9 | 530 | |
Sinan Divarci |
0:65766360f6b9 | 531 | int MAX7032::set_pkdet(uint8_t pkdet) |
Sinan Divarci |
0:65766360f6b9 | 532 | { |
Sinan Divarci |
0:65766360f6b9 | 533 | if(pkdet > 1) |
Sinan Divarci |
0:65766360f6b9 | 534 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 535 | |
Sinan Divarci |
0:65766360f6b9 | 536 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.pkdet, pkdet); |
Sinan Divarci |
0:65766360f6b9 | 537 | |
Sinan Divarci |
0:65766360f6b9 | 538 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 539 | } |
Sinan Divarci |
0:65766360f6b9 | 540 | |
Sinan Divarci |
0:65766360f6b9 | 541 | int MAX7032::get_pkdet() |
Sinan Divarci |
0:65766360f6b9 | 542 | { |
Sinan Divarci |
0:65766360f6b9 | 543 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 544 | |
Sinan Divarci |
0:65766360f6b9 | 545 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 546 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 547 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 548 | |
Sinan Divarci |
0:65766360f6b9 | 549 | return this->reg_map->power.bits.pkdet; |
Sinan Divarci |
0:65766360f6b9 | 550 | } |
Sinan Divarci |
0:65766360f6b9 | 551 | |
Sinan Divarci |
0:65766360f6b9 | 552 | int MAX7032::set_pa(uint8_t pa) |
Sinan Divarci |
0:65766360f6b9 | 553 | { |
Sinan Divarci |
0:65766360f6b9 | 554 | if(pa > 1) |
Sinan Divarci |
0:65766360f6b9 | 555 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 556 | |
Sinan Divarci |
0:65766360f6b9 | 557 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.pa, pa); |
Sinan Divarci |
0:65766360f6b9 | 558 | |
Sinan Divarci |
0:65766360f6b9 | 559 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 560 | } |
Sinan Divarci |
0:65766360f6b9 | 561 | |
Sinan Divarci |
0:65766360f6b9 | 562 | int MAX7032::get_pa() |
Sinan Divarci |
0:65766360f6b9 | 563 | { |
Sinan Divarci |
0:65766360f6b9 | 564 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 565 | |
Sinan Divarci |
0:65766360f6b9 | 566 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 567 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 568 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 569 | |
Sinan Divarci |
0:65766360f6b9 | 570 | return this->reg_map->power.bits.pa; |
Sinan Divarci |
0:65766360f6b9 | 571 | } |
Sinan Divarci |
0:65766360f6b9 | 572 | |
Sinan Divarci |
0:65766360f6b9 | 573 | int MAX7032::set_rssio(uint8_t rssio) |
Sinan Divarci |
0:65766360f6b9 | 574 | { |
Sinan Divarci |
0:65766360f6b9 | 575 | if(rssio > 1) |
Sinan Divarci |
0:65766360f6b9 | 576 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 577 | |
Sinan Divarci |
0:65766360f6b9 | 578 | SET_BIT_FIELD(POWER_ADDR, this->reg_map->power, this->reg_map->power.bits.rssio, rssio); |
Sinan Divarci |
0:65766360f6b9 | 579 | |
Sinan Divarci |
0:65766360f6b9 | 580 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 581 | } |
Sinan Divarci |
0:65766360f6b9 | 582 | |
Sinan Divarci |
0:65766360f6b9 | 583 | int MAX7032::get_rssio() |
Sinan Divarci |
0:65766360f6b9 | 584 | { |
Sinan Divarci |
0:65766360f6b9 | 585 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 586 | |
Sinan Divarci |
0:65766360f6b9 | 587 | ret = read_register(POWER_ADDR, (uint8_t *) & (this->reg_map->power)); |
Sinan Divarci |
0:65766360f6b9 | 588 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 589 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 590 | |
Sinan Divarci |
0:65766360f6b9 | 591 | return this->reg_map->power.bits.rssio; |
Sinan Divarci |
0:65766360f6b9 | 592 | } |
Sinan Divarci |
0:65766360f6b9 | 593 | |
Sinan Divarci |
0:65766360f6b9 | 594 | |
Sinan Divarci |
0:65766360f6b9 | 595 | int MAX7032::set_agclk(uint8_t agclk) |
Sinan Divarci |
0:65766360f6b9 | 596 | { |
Sinan Divarci |
0:65766360f6b9 | 597 | if(agclk > 1) |
Sinan Divarci |
0:65766360f6b9 | 598 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 599 | |
Sinan Divarci |
0:65766360f6b9 | 600 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.agclk, agclk); |
Sinan Divarci |
0:65766360f6b9 | 601 | |
Sinan Divarci |
0:65766360f6b9 | 602 | if(!get_mgain()) |
Sinan Divarci |
0:65766360f6b9 | 603 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 604 | |
Sinan Divarci |
0:65766360f6b9 | 605 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 606 | } |
Sinan Divarci |
0:65766360f6b9 | 607 | |
Sinan Divarci |
0:65766360f6b9 | 608 | int MAX7032::get_agclk() |
Sinan Divarci |
0:65766360f6b9 | 609 | { |
Sinan Divarci |
0:65766360f6b9 | 610 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 611 | |
Sinan Divarci |
0:65766360f6b9 | 612 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 613 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 614 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 615 | |
Sinan Divarci |
0:65766360f6b9 | 616 | return this->reg_map->contrl.bits.agclk; |
Sinan Divarci |
0:65766360f6b9 | 617 | } |
Sinan Divarci |
0:65766360f6b9 | 618 | |
Sinan Divarci |
0:65766360f6b9 | 619 | int MAX7032::set_gain(uint8_t gain) |
Sinan Divarci |
0:65766360f6b9 | 620 | { |
Sinan Divarci |
0:65766360f6b9 | 621 | if(gain > 1) |
Sinan Divarci |
0:65766360f6b9 | 622 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 623 | |
Sinan Divarci |
0:65766360f6b9 | 624 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.gain, gain); |
Sinan Divarci |
0:65766360f6b9 | 625 | |
Sinan Divarci |
0:65766360f6b9 | 626 | if(!get_mgain()) |
Sinan Divarci |
0:65766360f6b9 | 627 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 628 | |
Sinan Divarci |
0:65766360f6b9 | 629 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 630 | } |
Sinan Divarci |
0:65766360f6b9 | 631 | |
Sinan Divarci |
0:65766360f6b9 | 632 | int MAX7032::get_gain() |
Sinan Divarci |
0:65766360f6b9 | 633 | { |
Sinan Divarci |
0:65766360f6b9 | 634 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 635 | |
Sinan Divarci |
0:65766360f6b9 | 636 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 637 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 638 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 639 | |
Sinan Divarci |
0:65766360f6b9 | 640 | return this->reg_map->contrl.bits.gain; |
Sinan Divarci |
0:65766360f6b9 | 641 | } |
Sinan Divarci |
0:65766360f6b9 | 642 | |
Sinan Divarci |
0:65766360f6b9 | 643 | int MAX7032::set_trk_en(uint8_t trk_en) |
Sinan Divarci |
0:65766360f6b9 | 644 | { |
Sinan Divarci |
0:65766360f6b9 | 645 | if(trk_en > 1) |
Sinan Divarci |
0:65766360f6b9 | 646 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 647 | |
Sinan Divarci |
0:65766360f6b9 | 648 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.trk_en, trk_en); |
Sinan Divarci |
0:65766360f6b9 | 649 | |
Sinan Divarci |
0:65766360f6b9 | 650 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 651 | } |
Sinan Divarci |
0:65766360f6b9 | 652 | |
Sinan Divarci |
0:65766360f6b9 | 653 | int MAX7032::get_trk_en() |
Sinan Divarci |
0:65766360f6b9 | 654 | { |
Sinan Divarci |
0:65766360f6b9 | 655 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 656 | |
Sinan Divarci |
0:65766360f6b9 | 657 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 658 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 659 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 660 | |
Sinan Divarci |
0:65766360f6b9 | 661 | return this->reg_map->contrl.bits.trk_en; |
Sinan Divarci |
0:65766360f6b9 | 662 | } |
Sinan Divarci |
0:65766360f6b9 | 663 | |
Sinan Divarci |
0:65766360f6b9 | 664 | int MAX7032::set_pcal() |
Sinan Divarci |
0:65766360f6b9 | 665 | { |
Sinan Divarci |
0:65766360f6b9 | 666 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.pcal, 1); |
Sinan Divarci |
0:65766360f6b9 | 667 | |
Sinan Divarci |
0:65766360f6b9 | 668 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 669 | } |
Sinan Divarci |
0:65766360f6b9 | 670 | |
Sinan Divarci |
0:65766360f6b9 | 671 | int MAX7032::get_pcal() |
Sinan Divarci |
0:65766360f6b9 | 672 | { |
Sinan Divarci |
0:65766360f6b9 | 673 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 674 | |
Sinan Divarci |
0:65766360f6b9 | 675 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 676 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 677 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 678 | |
Sinan Divarci |
0:65766360f6b9 | 679 | return this->reg_map->contrl.bits.pcal; |
Sinan Divarci |
0:65766360f6b9 | 680 | } |
Sinan Divarci |
0:65766360f6b9 | 681 | |
Sinan Divarci |
0:65766360f6b9 | 682 | int MAX7032::set_fcal() |
Sinan Divarci |
0:65766360f6b9 | 683 | { |
Sinan Divarci |
0:65766360f6b9 | 684 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.fcal, 1); |
Sinan Divarci |
0:65766360f6b9 | 685 | |
Sinan Divarci |
0:65766360f6b9 | 686 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 687 | } |
Sinan Divarci |
0:65766360f6b9 | 688 | |
Sinan Divarci |
0:65766360f6b9 | 689 | int MAX7032::get_fcal() |
Sinan Divarci |
0:65766360f6b9 | 690 | { |
Sinan Divarci |
0:65766360f6b9 | 691 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 692 | |
Sinan Divarci |
0:65766360f6b9 | 693 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 694 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 695 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 696 | |
Sinan Divarci |
0:65766360f6b9 | 697 | return this->reg_map->contrl.bits.fcal; |
Sinan Divarci |
0:65766360f6b9 | 698 | } |
Sinan Divarci |
0:65766360f6b9 | 699 | |
Sinan Divarci |
0:65766360f6b9 | 700 | int MAX7032::set_ckout(uint8_t ckout) |
Sinan Divarci |
0:65766360f6b9 | 701 | { |
Sinan Divarci |
0:65766360f6b9 | 702 | if(ckout > 1) |
Sinan Divarci |
0:65766360f6b9 | 703 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 704 | |
Sinan Divarci |
0:65766360f6b9 | 705 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.ckout, ckout); |
Sinan Divarci |
0:65766360f6b9 | 706 | |
Sinan Divarci |
0:65766360f6b9 | 707 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 708 | } |
Sinan Divarci |
0:65766360f6b9 | 709 | |
Sinan Divarci |
0:65766360f6b9 | 710 | int MAX7032::get_ckout() |
Sinan Divarci |
0:65766360f6b9 | 711 | { |
Sinan Divarci |
0:65766360f6b9 | 712 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 713 | |
Sinan Divarci |
0:65766360f6b9 | 714 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 715 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 716 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 717 | |
Sinan Divarci |
0:65766360f6b9 | 718 | return this->reg_map->contrl.bits.ckout; |
Sinan Divarci |
0:65766360f6b9 | 719 | } |
Sinan Divarci |
0:65766360f6b9 | 720 | |
Sinan Divarci |
0:65766360f6b9 | 721 | int MAX7032::set_sleep(uint8_t sleep) |
Sinan Divarci |
0:65766360f6b9 | 722 | { |
Sinan Divarci |
0:65766360f6b9 | 723 | if(sleep > 1) |
Sinan Divarci |
0:65766360f6b9 | 724 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 725 | |
Sinan Divarci |
0:65766360f6b9 | 726 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.sleep, sleep); |
Sinan Divarci |
0:65766360f6b9 | 727 | |
Sinan Divarci |
0:65766360f6b9 | 728 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 729 | } |
Sinan Divarci |
0:65766360f6b9 | 730 | |
Sinan Divarci |
0:65766360f6b9 | 731 | int MAX7032::get_sleep() |
Sinan Divarci |
0:65766360f6b9 | 732 | { |
Sinan Divarci |
0:65766360f6b9 | 733 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 734 | |
Sinan Divarci |
0:65766360f6b9 | 735 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 736 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 737 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 738 | |
Sinan Divarci |
0:65766360f6b9 | 739 | return this->reg_map->contrl.bits.sleep; |
Sinan Divarci |
0:65766360f6b9 | 740 | } |
Sinan Divarci |
0:65766360f6b9 | 741 | |
Sinan Divarci |
0:65766360f6b9 | 742 | int MAX7032::set_mode(ask_fsk_sel_t ask_fsk_sel) |
Sinan Divarci |
0:65766360f6b9 | 743 | { |
Sinan Divarci |
0:65766360f6b9 | 744 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.mode, ask_fsk_sel); |
Sinan Divarci |
0:65766360f6b9 | 745 | |
Sinan Divarci |
0:65766360f6b9 | 746 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 747 | } |
Sinan Divarci |
0:65766360f6b9 | 748 | |
Sinan Divarci |
0:65766360f6b9 | 749 | int MAX7032::get_mode(ask_fsk_sel_t* ask_fsk_sel) |
Sinan Divarci |
0:65766360f6b9 | 750 | { |
Sinan Divarci |
0:65766360f6b9 | 751 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 752 | |
Sinan Divarci |
0:65766360f6b9 | 753 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 754 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 755 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 756 | |
Sinan Divarci |
0:65766360f6b9 | 757 | *ask_fsk_sel = (ask_fsk_sel_t)this->reg_map->conf0.bits.mode; |
Sinan Divarci |
0:65766360f6b9 | 758 | |
Sinan Divarci |
0:65766360f6b9 | 759 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 760 | } |
Sinan Divarci |
0:65766360f6b9 | 761 | |
Sinan Divarci |
0:65766360f6b9 | 762 | int MAX7032::get_mode() |
Sinan Divarci |
0:65766360f6b9 | 763 | { |
Sinan Divarci |
0:65766360f6b9 | 764 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 765 | |
Sinan Divarci |
0:65766360f6b9 | 766 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 767 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 768 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 769 | |
Sinan Divarci |
0:65766360f6b9 | 770 | return this->reg_map->conf0.bits.mode; |
Sinan Divarci |
0:65766360f6b9 | 771 | } |
Sinan Divarci |
0:65766360f6b9 | 772 | |
Sinan Divarci |
0:65766360f6b9 | 773 | int MAX7032::set_t_r(uint8_t t_r) |
Sinan Divarci |
0:65766360f6b9 | 774 | { |
Sinan Divarci |
0:65766360f6b9 | 775 | if(t_r > 1) |
Sinan Divarci |
0:65766360f6b9 | 776 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 777 | |
Sinan Divarci |
0:65766360f6b9 | 778 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.t_r, t_r); |
Sinan Divarci |
0:65766360f6b9 | 779 | |
Sinan Divarci |
0:65766360f6b9 | 780 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 781 | } |
Sinan Divarci |
0:65766360f6b9 | 782 | |
Sinan Divarci |
0:65766360f6b9 | 783 | int MAX7032::get_t_r() |
Sinan Divarci |
0:65766360f6b9 | 784 | { |
Sinan Divarci |
0:65766360f6b9 | 785 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 786 | |
Sinan Divarci |
0:65766360f6b9 | 787 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 788 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 789 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 790 | |
Sinan Divarci |
0:65766360f6b9 | 791 | return this->reg_map->conf0.bits.t_r; |
Sinan Divarci |
0:65766360f6b9 | 792 | } |
Sinan Divarci |
0:65766360f6b9 | 793 | |
Sinan Divarci |
0:65766360f6b9 | 794 | int MAX7032::set_mgain(uint8_t mgain) |
Sinan Divarci |
0:65766360f6b9 | 795 | { |
Sinan Divarci |
0:65766360f6b9 | 796 | if(mgain > 1) |
Sinan Divarci |
0:65766360f6b9 | 797 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 798 | |
Sinan Divarci |
0:65766360f6b9 | 799 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.mgain, mgain); |
Sinan Divarci |
0:65766360f6b9 | 800 | |
Sinan Divarci |
0:65766360f6b9 | 801 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 802 | } |
Sinan Divarci |
0:65766360f6b9 | 803 | |
Sinan Divarci |
0:65766360f6b9 | 804 | int MAX7032::get_mgain() |
Sinan Divarci |
0:65766360f6b9 | 805 | { |
Sinan Divarci |
0:65766360f6b9 | 806 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 807 | |
Sinan Divarci |
0:65766360f6b9 | 808 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 809 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 810 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 811 | |
Sinan Divarci |
0:65766360f6b9 | 812 | return this->reg_map->conf0.bits.mgain; |
Sinan Divarci |
0:65766360f6b9 | 813 | } |
Sinan Divarci |
0:65766360f6b9 | 814 | |
Sinan Divarci |
0:65766360f6b9 | 815 | int MAX7032::set_drx(uint8_t drx) |
Sinan Divarci |
0:65766360f6b9 | 816 | { |
Sinan Divarci |
0:65766360f6b9 | 817 | if(drx > 1) |
Sinan Divarci |
0:65766360f6b9 | 818 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 819 | |
Sinan Divarci |
0:65766360f6b9 | 820 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.drx, drx); |
Sinan Divarci |
0:65766360f6b9 | 821 | |
Sinan Divarci |
0:65766360f6b9 | 822 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 823 | } |
Sinan Divarci |
0:65766360f6b9 | 824 | |
Sinan Divarci |
0:65766360f6b9 | 825 | int MAX7032::get_drx() |
Sinan Divarci |
0:65766360f6b9 | 826 | { |
Sinan Divarci |
0:65766360f6b9 | 827 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 828 | |
Sinan Divarci |
0:65766360f6b9 | 829 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 830 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 831 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 832 | |
Sinan Divarci |
0:65766360f6b9 | 833 | return this->reg_map->conf0.bits.drx; |
Sinan Divarci |
0:65766360f6b9 | 834 | } |
Sinan Divarci |
0:65766360f6b9 | 835 | |
Sinan Divarci |
0:65766360f6b9 | 836 | |
Sinan Divarci |
0:65766360f6b9 | 837 | int MAX7032::set_acal(uint8_t acal) |
Sinan Divarci |
0:65766360f6b9 | 838 | { |
Sinan Divarci |
0:65766360f6b9 | 839 | if(acal > 1) |
Sinan Divarci |
0:65766360f6b9 | 840 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 841 | |
Sinan Divarci |
0:65766360f6b9 | 842 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.acal, acal); |
Sinan Divarci |
0:65766360f6b9 | 843 | |
Sinan Divarci |
0:65766360f6b9 | 844 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 845 | } |
Sinan Divarci |
0:65766360f6b9 | 846 | |
Sinan Divarci |
0:65766360f6b9 | 847 | int MAX7032::get_acal() |
Sinan Divarci |
0:65766360f6b9 | 848 | { |
Sinan Divarci |
0:65766360f6b9 | 849 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 850 | |
Sinan Divarci |
0:65766360f6b9 | 851 | ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1)); |
Sinan Divarci |
0:65766360f6b9 | 852 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 853 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 854 | |
Sinan Divarci |
0:65766360f6b9 | 855 | return this->reg_map->conf1.bits.acal; |
Sinan Divarci |
0:65766360f6b9 | 856 | } |
Sinan Divarci |
0:65766360f6b9 | 857 | |
Sinan Divarci |
0:65766360f6b9 | 858 | int MAX7032::set_clkof(uint8_t clkof) |
Sinan Divarci |
0:65766360f6b9 | 859 | { |
Sinan Divarci |
0:65766360f6b9 | 860 | if(clkof > 1) |
Sinan Divarci |
0:65766360f6b9 | 861 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 862 | |
Sinan Divarci |
0:65766360f6b9 | 863 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.clkof, clkof); |
Sinan Divarci |
0:65766360f6b9 | 864 | |
Sinan Divarci |
0:65766360f6b9 | 865 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 866 | } |
Sinan Divarci |
0:65766360f6b9 | 867 | |
Sinan Divarci |
0:65766360f6b9 | 868 | int MAX7032::get_clkof() |
Sinan Divarci |
0:65766360f6b9 | 869 | { |
Sinan Divarci |
0:65766360f6b9 | 870 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 871 | |
Sinan Divarci |
0:65766360f6b9 | 872 | ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1)); |
Sinan Divarci |
0:65766360f6b9 | 873 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 874 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 875 | |
Sinan Divarci |
0:65766360f6b9 | 876 | return this->reg_map->conf1.bits.clkof; |
Sinan Divarci |
0:65766360f6b9 | 877 | } |
Sinan Divarci |
0:65766360f6b9 | 878 | |
Sinan Divarci |
0:65766360f6b9 | 879 | int MAX7032::set_cdiv(uint8_t cdiv) |
Sinan Divarci |
0:65766360f6b9 | 880 | { |
Sinan Divarci |
0:65766360f6b9 | 881 | if(cdiv > 3) |
Sinan Divarci |
0:65766360f6b9 | 882 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 883 | |
Sinan Divarci |
0:65766360f6b9 | 884 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, cdiv); |
Sinan Divarci |
0:65766360f6b9 | 885 | |
Sinan Divarci |
0:65766360f6b9 | 886 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 887 | } |
Sinan Divarci |
0:65766360f6b9 | 888 | |
Sinan Divarci |
0:65766360f6b9 | 889 | int MAX7032::get_cdiv() |
Sinan Divarci |
0:65766360f6b9 | 890 | { |
Sinan Divarci |
0:65766360f6b9 | 891 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 892 | |
Sinan Divarci |
0:65766360f6b9 | 893 | ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1)); |
Sinan Divarci |
0:65766360f6b9 | 894 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 895 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 896 | |
Sinan Divarci |
0:65766360f6b9 | 897 | return this->reg_map->conf1.bits.cdiv; |
Sinan Divarci |
0:65766360f6b9 | 898 | } |
Sinan Divarci |
0:65766360f6b9 | 899 | |
Sinan Divarci |
0:65766360f6b9 | 900 | int MAX7032::set_dt(uint8_t dt) |
Sinan Divarci |
0:65766360f6b9 | 901 | { |
Sinan Divarci |
0:65766360f6b9 | 902 | if(dt > 7) |
Sinan Divarci |
0:65766360f6b9 | 903 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 904 | |
Sinan Divarci |
0:65766360f6b9 | 905 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.dt, dt); |
Sinan Divarci |
0:65766360f6b9 | 906 | |
Sinan Divarci |
0:65766360f6b9 | 907 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 908 | } |
Sinan Divarci |
0:65766360f6b9 | 909 | |
Sinan Divarci |
0:65766360f6b9 | 910 | int MAX7032::get_dt() |
Sinan Divarci |
0:65766360f6b9 | 911 | { |
Sinan Divarci |
0:65766360f6b9 | 912 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 913 | |
Sinan Divarci |
0:65766360f6b9 | 914 | ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1)); |
Sinan Divarci |
0:65766360f6b9 | 915 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 916 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 917 | |
Sinan Divarci |
0:65766360f6b9 | 918 | return this->reg_map->conf1.bits.dt; |
Sinan Divarci |
0:65766360f6b9 | 919 | } |
Sinan Divarci |
0:65766360f6b9 | 920 | |
Sinan Divarci |
0:65766360f6b9 | 921 | int MAX7032::set_osc(uint8_t osc) |
Sinan Divarci |
0:65766360f6b9 | 922 | { |
Sinan Divarci |
0:65766360f6b9 | 923 | SET_BIT_FIELD(OSC_ADDR, this->reg_map->osc, this->reg_map->osc.bits.osc, osc); |
Sinan Divarci |
0:65766360f6b9 | 924 | |
Sinan Divarci |
0:65766360f6b9 | 925 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 926 | } |
Sinan Divarci |
0:65766360f6b9 | 927 | |
Sinan Divarci |
0:65766360f6b9 | 928 | int MAX7032::get_osc() |
Sinan Divarci |
0:65766360f6b9 | 929 | { |
Sinan Divarci |
0:65766360f6b9 | 930 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 931 | |
Sinan Divarci |
0:65766360f6b9 | 932 | ret = read_register(OSC_ADDR, (uint8_t *) & (this->reg_map->osc)); |
Sinan Divarci |
0:65766360f6b9 | 933 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 934 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 935 | |
Sinan Divarci |
0:65766360f6b9 | 936 | return this->reg_map->osc.bits.osc; |
Sinan Divarci |
0:65766360f6b9 | 937 | } |
Sinan Divarci |
0:65766360f6b9 | 938 | |
Sinan Divarci |
0:65766360f6b9 | 939 | int MAX7032::set_toff(uint16_t toff) |
Sinan Divarci |
0:65766360f6b9 | 940 | { |
Sinan Divarci |
0:65766360f6b9 | 941 | uint8_t toff_lsb, toff_msb; |
Sinan Divarci |
0:65766360f6b9 | 942 | |
Sinan Divarci |
0:65766360f6b9 | 943 | if(toff > 65535) |
Sinan Divarci |
0:65766360f6b9 | 944 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 945 | |
Sinan Divarci |
0:65766360f6b9 | 946 | toff_lsb = (uint8_t)(toff & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 947 | toff_msb = (uint8_t)((toff & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 948 | |
Sinan Divarci |
0:65766360f6b9 | 949 | SET_BIT_FIELD(TOFFMSB_ADDR, this->reg_map->toff_upper, this->reg_map->toff_upper.bits.toff_upper, toff_msb); |
Sinan Divarci |
0:65766360f6b9 | 950 | SET_BIT_FIELD(TOFFLSB_ADDR, this->reg_map->toff_lower, this->reg_map->toff_lower.bits.toff_lower, toff_lsb); |
Sinan Divarci |
0:65766360f6b9 | 951 | |
Sinan Divarci |
0:65766360f6b9 | 952 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 953 | } |
Sinan Divarci |
0:65766360f6b9 | 954 | |
Sinan Divarci |
0:65766360f6b9 | 955 | uint16_t MAX7032::get_toff() |
Sinan Divarci |
0:65766360f6b9 | 956 | { |
Sinan Divarci |
0:65766360f6b9 | 957 | uint8_t toff_lsb, toff_msb; |
Sinan Divarci |
0:65766360f6b9 | 958 | uint16_t toff = 0; |
Sinan Divarci |
0:65766360f6b9 | 959 | |
Sinan Divarci |
0:65766360f6b9 | 960 | if(read_register(TOFFLSB_ADDR, (uint8_t *) & (this->reg_map->toff_lower)) < 0) |
Sinan Divarci |
0:65766360f6b9 | 961 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 962 | |
Sinan Divarci |
0:65766360f6b9 | 963 | if(read_register(TOFFMSB_ADDR, (uint8_t *) & (this->reg_map->toff_upper)) < 0) |
Sinan Divarci |
0:65766360f6b9 | 964 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 965 | |
Sinan Divarci |
0:65766360f6b9 | 966 | toff = this->reg_map->toff_upper.bits.toff_upper; |
Sinan Divarci |
0:65766360f6b9 | 967 | toff = toff << 8; |
Sinan Divarci |
0:65766360f6b9 | 968 | toff |= this->reg_map->toff_lower.bits.toff_lower; |
Sinan Divarci |
0:65766360f6b9 | 969 | |
Sinan Divarci |
0:65766360f6b9 | 970 | return toff; |
Sinan Divarci |
0:65766360f6b9 | 971 | } |
Sinan Divarci |
0:65766360f6b9 | 972 | |
Sinan Divarci |
0:65766360f6b9 | 973 | int MAX7032::set_tcpu(uint8_t tcpu) |
Sinan Divarci |
0:65766360f6b9 | 974 | { |
Sinan Divarci |
0:65766360f6b9 | 975 | SET_BIT_FIELD(TCPU_ADDR, this->reg_map->tcpu, this->reg_map->tcpu.bits.tcpu, tcpu); |
Sinan Divarci |
0:65766360f6b9 | 976 | |
Sinan Divarci |
0:65766360f6b9 | 977 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 978 | } |
Sinan Divarci |
0:65766360f6b9 | 979 | |
Sinan Divarci |
0:65766360f6b9 | 980 | uint8_t MAX7032::get_tcpu() |
Sinan Divarci |
0:65766360f6b9 | 981 | { |
Sinan Divarci |
0:65766360f6b9 | 982 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 983 | |
Sinan Divarci |
0:65766360f6b9 | 984 | ret = read_register(TCPU_ADDR, (uint8_t *) & (this->reg_map->tcpu)); |
Sinan Divarci |
0:65766360f6b9 | 985 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 986 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 987 | |
Sinan Divarci |
0:65766360f6b9 | 988 | return this->reg_map->tcpu.bits.tcpu; |
Sinan Divarci |
0:65766360f6b9 | 989 | } |
Sinan Divarci |
0:65766360f6b9 | 990 | |
Sinan Divarci |
0:65766360f6b9 | 991 | int MAX7032::set_trf(uint16_t trf) |
Sinan Divarci |
0:65766360f6b9 | 992 | { |
Sinan Divarci |
0:65766360f6b9 | 993 | uint8_t trf_lsb, trf_msb; |
Sinan Divarci |
0:65766360f6b9 | 994 | |
Sinan Divarci |
0:65766360f6b9 | 995 | if(trf > 65535) |
Sinan Divarci |
0:65766360f6b9 | 996 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 997 | |
Sinan Divarci |
0:65766360f6b9 | 998 | trf_lsb = (uint8_t)(trf & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 999 | trf_msb = (uint8_t)((trf & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1000 | |
Sinan Divarci |
0:65766360f6b9 | 1001 | SET_BIT_FIELD(TRFMSB_ADDR, this->reg_map->trf_upper, this->reg_map->trf_upper.bits.trf_upper, trf_msb); |
Sinan Divarci |
0:65766360f6b9 | 1002 | SET_BIT_FIELD(TRFLSB_ADDR, this->reg_map->trf_lower, this->reg_map->trf_lower.bits.trf_lower, trf_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1003 | |
Sinan Divarci |
0:65766360f6b9 | 1004 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1005 | } |
Sinan Divarci |
0:65766360f6b9 | 1006 | |
Sinan Divarci |
0:65766360f6b9 | 1007 | uint16_t MAX7032::get_trf() |
Sinan Divarci |
0:65766360f6b9 | 1008 | { |
Sinan Divarci |
0:65766360f6b9 | 1009 | uint8_t trf_lsb, trf_msb; |
Sinan Divarci |
0:65766360f6b9 | 1010 | uint16_t trf = 0; |
Sinan Divarci |
0:65766360f6b9 | 1011 | |
Sinan Divarci |
0:65766360f6b9 | 1012 | if(read_register(TRFLSB_ADDR, (uint8_t *) & (this->reg_map->trf_lower)) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1013 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1014 | |
Sinan Divarci |
0:65766360f6b9 | 1015 | if(read_register(TRFMSB_ADDR, (uint8_t *) & (this->reg_map->trf_upper)) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1016 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1017 | |
Sinan Divarci |
0:65766360f6b9 | 1018 | trf = this->reg_map->trf_upper.bits.trf_upper; |
Sinan Divarci |
0:65766360f6b9 | 1019 | trf = trf << 8; |
Sinan Divarci |
0:65766360f6b9 | 1020 | trf |= this->reg_map->trf_lower.bits.trf_lower; |
Sinan Divarci |
0:65766360f6b9 | 1021 | |
Sinan Divarci |
0:65766360f6b9 | 1022 | return trf; |
Sinan Divarci |
0:65766360f6b9 | 1023 | } |
Sinan Divarci |
0:65766360f6b9 | 1024 | |
Sinan Divarci |
0:65766360f6b9 | 1025 | int MAX7032::set_ton(uint16_t ton) |
Sinan Divarci |
0:65766360f6b9 | 1026 | { |
Sinan Divarci |
0:65766360f6b9 | 1027 | uint8_t ton_lsb, ton_msb; |
Sinan Divarci |
0:65766360f6b9 | 1028 | |
Sinan Divarci |
0:65766360f6b9 | 1029 | if(ton > 65535) |
Sinan Divarci |
0:65766360f6b9 | 1030 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1031 | |
Sinan Divarci |
0:65766360f6b9 | 1032 | ton_lsb = (uint8_t)(ton & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1033 | ton_msb = (uint8_t)((ton & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1034 | |
Sinan Divarci |
0:65766360f6b9 | 1035 | SET_BIT_FIELD(TONMSB_ADDR, this->reg_map->ton_upper, this->reg_map->ton_upper.bits.ton_upper, ton_msb); |
Sinan Divarci |
0:65766360f6b9 | 1036 | SET_BIT_FIELD(TONLSB_ADDR, this->reg_map->ton_lower, this->reg_map->ton_lower.bits.ton_lower, ton_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1037 | |
Sinan Divarci |
0:65766360f6b9 | 1038 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1039 | } |
Sinan Divarci |
0:65766360f6b9 | 1040 | |
Sinan Divarci |
0:65766360f6b9 | 1041 | uint16_t MAX7032::get_ton() |
Sinan Divarci |
0:65766360f6b9 | 1042 | { |
Sinan Divarci |
0:65766360f6b9 | 1043 | uint8_t ton_lsb, ton_msb; |
Sinan Divarci |
0:65766360f6b9 | 1044 | uint16_t ton = 0; |
Sinan Divarci |
0:65766360f6b9 | 1045 | |
Sinan Divarci |
0:65766360f6b9 | 1046 | if(read_register(TONLSB_ADDR, (uint8_t *) & (this->reg_map->ton_lower)) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1047 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1048 | |
Sinan Divarci |
0:65766360f6b9 | 1049 | if(read_register(TONMSB_ADDR, (uint8_t *) & (this->reg_map->ton_upper)) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1050 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1051 | |
Sinan Divarci |
0:65766360f6b9 | 1052 | ton = this->reg_map->ton_upper.bits.ton_upper; |
Sinan Divarci |
0:65766360f6b9 | 1053 | ton = ton << 8; |
Sinan Divarci |
0:65766360f6b9 | 1054 | ton |= this->reg_map->ton_lower.bits.ton_lower; |
Sinan Divarci |
0:65766360f6b9 | 1055 | |
Sinan Divarci |
0:65766360f6b9 | 1056 | return ton; |
Sinan Divarci |
0:65766360f6b9 | 1057 | } |
Sinan Divarci |
0:65766360f6b9 | 1058 | |
Sinan Divarci |
0:65766360f6b9 | 1059 | int MAX7032::set_txlow(int txlow_val) |
Sinan Divarci |
0:65766360f6b9 | 1060 | { |
Sinan Divarci |
0:65766360f6b9 | 1061 | uint8_t tx_low_lsb, tx_low_msb; |
Sinan Divarci |
0:65766360f6b9 | 1062 | |
Sinan Divarci |
0:65766360f6b9 | 1063 | if(txlow_val > 65535) |
Sinan Divarci |
0:65766360f6b9 | 1064 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1065 | |
Sinan Divarci |
0:65766360f6b9 | 1066 | tx_low_lsb = (uint8_t)(txlow_val & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1067 | tx_low_msb = (uint8_t)((txlow_val & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1068 | |
Sinan Divarci |
0:65766360f6b9 | 1069 | |
Sinan Divarci |
0:65766360f6b9 | 1070 | SET_BIT_FIELD(TXLOWLSB_ADDR, this->reg_map->txlow_lower, this->reg_map->txlow_lower.bits.txlow_lower, tx_low_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1071 | SET_BIT_FIELD(TXLOWMSB_ADDR, this->reg_map->txlow_upper, this->reg_map->txlow_upper.bits.txlow_upper, tx_low_msb); |
Sinan Divarci |
0:65766360f6b9 | 1072 | |
Sinan Divarci |
0:65766360f6b9 | 1073 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1074 | } |
Sinan Divarci |
0:65766360f6b9 | 1075 | |
Sinan Divarci |
0:65766360f6b9 | 1076 | int MAX7032::get_txlow() |
Sinan Divarci |
0:65766360f6b9 | 1077 | { |
Sinan Divarci |
0:65766360f6b9 | 1078 | uint8_t tx_low_lsb, tx_low_msb; |
Sinan Divarci |
0:65766360f6b9 | 1079 | uint32_t tx_low = 0; |
Sinan Divarci |
0:65766360f6b9 | 1080 | |
Sinan Divarci |
0:65766360f6b9 | 1081 | if(read_register(TXLOWLSB_ADDR, (uint8_t *)&tx_low_lsb) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1082 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1083 | |
Sinan Divarci |
0:65766360f6b9 | 1084 | if(read_register(TXLOWMSB_ADDR, (uint8_t *)&tx_low_msb) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1085 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1086 | |
Sinan Divarci |
0:65766360f6b9 | 1087 | tx_low = tx_low_msb; |
Sinan Divarci |
0:65766360f6b9 | 1088 | tx_low = tx_low << 8; |
Sinan Divarci |
0:65766360f6b9 | 1089 | tx_low |= tx_low_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1090 | |
Sinan Divarci |
0:65766360f6b9 | 1091 | return tx_low; |
Sinan Divarci |
0:65766360f6b9 | 1092 | } |
Sinan Divarci |
0:65766360f6b9 | 1093 | |
Sinan Divarci |
0:65766360f6b9 | 1094 | int MAX7032::set_txhigh(int txhigh_val) |
Sinan Divarci |
0:65766360f6b9 | 1095 | { |
Sinan Divarci |
0:65766360f6b9 | 1096 | uint8_t tx_high_lsb, tx_high_msb; |
Sinan Divarci |
0:65766360f6b9 | 1097 | |
Sinan Divarci |
0:65766360f6b9 | 1098 | if(txhigh_val > 65535) |
Sinan Divarci |
0:65766360f6b9 | 1099 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1100 | |
Sinan Divarci |
0:65766360f6b9 | 1101 | tx_high_lsb = (uint8_t)(txhigh_val & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1102 | tx_high_msb = (uint8_t)((txhigh_val & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1103 | |
Sinan Divarci |
0:65766360f6b9 | 1104 | SET_BIT_FIELD(TXHIGHLSB_ADDR, this->reg_map->txhigh_lower, this->reg_map->txhigh_lower.bits.txhigh_lower, tx_high_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1105 | SET_BIT_FIELD(TXHIGHMSB_ADDR, this->reg_map->txhigh_upper, this->reg_map->txhigh_upper.bits.txhigh_upper, tx_high_msb); |
Sinan Divarci |
0:65766360f6b9 | 1106 | |
Sinan Divarci |
0:65766360f6b9 | 1107 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1108 | } |
Sinan Divarci |
0:65766360f6b9 | 1109 | |
Sinan Divarci |
0:65766360f6b9 | 1110 | int MAX7032::get_txhigh() |
Sinan Divarci |
0:65766360f6b9 | 1111 | { |
Sinan Divarci |
0:65766360f6b9 | 1112 | uint8_t tx_high_lsb, tx_high_msb; |
Sinan Divarci |
0:65766360f6b9 | 1113 | uint32_t tx_high = 0; |
Sinan Divarci |
0:65766360f6b9 | 1114 | |
Sinan Divarci |
0:65766360f6b9 | 1115 | if(read_register(TXHIGHLSB_ADDR, (uint8_t *)&tx_high_lsb) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1116 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1117 | |
Sinan Divarci |
0:65766360f6b9 | 1118 | if(read_register(TXHIGHMSB_ADDR, (uint8_t *)&tx_high_msb) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1119 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1120 | |
Sinan Divarci |
0:65766360f6b9 | 1121 | tx_high = tx_high_msb; |
Sinan Divarci |
0:65766360f6b9 | 1122 | tx_high = tx_high << 8; |
Sinan Divarci |
0:65766360f6b9 | 1123 | tx_high |= tx_high_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1124 | |
Sinan Divarci |
0:65766360f6b9 | 1125 | return tx_high; |
Sinan Divarci |
0:65766360f6b9 | 1126 | } |
Sinan Divarci |
0:65766360f6b9 | 1127 | |
Sinan Divarci |
0:65766360f6b9 | 1128 | int MAX7032::get_lckd() |
Sinan Divarci |
0:65766360f6b9 | 1129 | { |
Sinan Divarci |
0:65766360f6b9 | 1130 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1131 | |
Sinan Divarci |
0:65766360f6b9 | 1132 | ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status)); |
Sinan Divarci |
0:65766360f6b9 | 1133 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1134 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1135 | |
Sinan Divarci |
0:65766360f6b9 | 1136 | return this->reg_map->status.bits.lckd; |
Sinan Divarci |
0:65766360f6b9 | 1137 | } |
Sinan Divarci |
0:65766360f6b9 | 1138 | |
Sinan Divarci |
0:65766360f6b9 | 1139 | int MAX7032::get_gains() |
Sinan Divarci |
0:65766360f6b9 | 1140 | { |
Sinan Divarci |
0:65766360f6b9 | 1141 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1142 | |
Sinan Divarci |
0:65766360f6b9 | 1143 | ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status)); |
Sinan Divarci |
0:65766360f6b9 | 1144 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1145 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1146 | |
Sinan Divarci |
0:65766360f6b9 | 1147 | return this->reg_map->status.bits.gains; |
Sinan Divarci |
0:65766360f6b9 | 1148 | } |
Sinan Divarci |
0:65766360f6b9 | 1149 | |
Sinan Divarci |
0:65766360f6b9 | 1150 | int MAX7032::get_clkon() |
Sinan Divarci |
0:65766360f6b9 | 1151 | { |
Sinan Divarci |
0:65766360f6b9 | 1152 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1153 | |
Sinan Divarci |
0:65766360f6b9 | 1154 | ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status)); |
Sinan Divarci |
0:65766360f6b9 | 1155 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1156 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1157 | |
Sinan Divarci |
0:65766360f6b9 | 1158 | return this->reg_map->status.bits.clkon; |
Sinan Divarci |
0:65766360f6b9 | 1159 | } |
Sinan Divarci |
0:65766360f6b9 | 1160 | |
Sinan Divarci |
0:65766360f6b9 | 1161 | int MAX7032::get_pcald() |
Sinan Divarci |
0:65766360f6b9 | 1162 | { |
Sinan Divarci |
0:65766360f6b9 | 1163 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1164 | |
Sinan Divarci |
0:65766360f6b9 | 1165 | ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status)); |
Sinan Divarci |
0:65766360f6b9 | 1166 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1167 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1168 | |
Sinan Divarci |
0:65766360f6b9 | 1169 | return this->reg_map->status.bits.pcald; |
Sinan Divarci |
0:65766360f6b9 | 1170 | } |
Sinan Divarci |
0:65766360f6b9 | 1171 | |
Sinan Divarci |
0:65766360f6b9 | 1172 | int MAX7032::get_fcald() |
Sinan Divarci |
0:65766360f6b9 | 1173 | { |
Sinan Divarci |
0:65766360f6b9 | 1174 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1175 | |
Sinan Divarci |
0:65766360f6b9 | 1176 | ret = read_register(STATUS_ADDR, (uint8_t *) & (this->reg_map->status)); |
Sinan Divarci |
0:65766360f6b9 | 1177 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1178 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1179 | |
Sinan Divarci |
0:65766360f6b9 | 1180 | return this->reg_map->status.bits.fcald; |
Sinan Divarci |
0:65766360f6b9 | 1181 | } |
Sinan Divarci |
0:65766360f6b9 | 1182 | |
Sinan Divarci |
0:65766360f6b9 | 1183 | int MAX7032::adjust_clockout(cdiv_t cdiv) |
Sinan Divarci |
0:65766360f6b9 | 1184 | { |
Sinan Divarci |
0:65766360f6b9 | 1185 | if(cdiv == DISABLE) { |
Sinan Divarci |
0:65766360f6b9 | 1186 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.ckout, 0); |
Sinan Divarci |
0:65766360f6b9 | 1187 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1188 | } |
Sinan Divarci |
0:65766360f6b9 | 1189 | |
Sinan Divarci |
0:65766360f6b9 | 1190 | if(cdiv == F_XTAL) { |
Sinan Divarci |
0:65766360f6b9 | 1191 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 0); |
Sinan Divarci |
0:65766360f6b9 | 1192 | }else if(cdiv == F_XTAL_X0_5) { |
Sinan Divarci |
0:65766360f6b9 | 1193 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 1); |
Sinan Divarci |
0:65766360f6b9 | 1194 | }else if(cdiv == F_XTAL_X0_25) { |
Sinan Divarci |
0:65766360f6b9 | 1195 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 2); |
Sinan Divarci |
0:65766360f6b9 | 1196 | }else if(cdiv == F_XTAL_X0_125) { |
Sinan Divarci |
0:65766360f6b9 | 1197 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.cdiv, 3); |
Sinan Divarci |
0:65766360f6b9 | 1198 | }else{ |
Sinan Divarci |
0:65766360f6b9 | 1199 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1200 | } |
Sinan Divarci |
0:65766360f6b9 | 1201 | |
Sinan Divarci |
0:65766360f6b9 | 1202 | SET_BIT_FIELD(CONTRL_ADDR, this->reg_map->contrl, this->reg_map->contrl.bits.ckout, 1); |
Sinan Divarci |
0:65766360f6b9 | 1203 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1204 | } |
Sinan Divarci |
0:65766360f6b9 | 1205 | |
Sinan Divarci |
0:65766360f6b9 | 1206 | int MAX7032::get_clockout_conf(cdiv_t *cdiv) |
Sinan Divarci |
0:65766360f6b9 | 1207 | { |
Sinan Divarci |
0:65766360f6b9 | 1208 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1209 | |
Sinan Divarci |
0:65766360f6b9 | 1210 | ret = read_register(CONTRL_ADDR, (uint8_t *) & (this->reg_map->contrl)); |
Sinan Divarci |
0:65766360f6b9 | 1211 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1212 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1213 | |
Sinan Divarci |
0:65766360f6b9 | 1214 | if(this->reg_map->contrl.bits.ckout == 0){ |
Sinan Divarci |
0:65766360f6b9 | 1215 | *cdiv = DISABLE; |
Sinan Divarci |
0:65766360f6b9 | 1216 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1217 | } |
Sinan Divarci |
0:65766360f6b9 | 1218 | |
Sinan Divarci |
0:65766360f6b9 | 1219 | ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1)); |
Sinan Divarci |
0:65766360f6b9 | 1220 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1221 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1222 | |
Sinan Divarci |
0:65766360f6b9 | 1223 | if(this->reg_map->conf1.bits.cdiv == 0) |
Sinan Divarci |
0:65766360f6b9 | 1224 | *cdiv = F_XTAL; |
Sinan Divarci |
0:65766360f6b9 | 1225 | else if(this->reg_map->conf1.bits.cdiv == 1) |
Sinan Divarci |
0:65766360f6b9 | 1226 | *cdiv = F_XTAL_X0_5; |
Sinan Divarci |
0:65766360f6b9 | 1227 | else if(this->reg_map->conf1.bits.cdiv == 2) |
Sinan Divarci |
0:65766360f6b9 | 1228 | *cdiv = F_XTAL_X0_25; |
Sinan Divarci |
0:65766360f6b9 | 1229 | else if(this->reg_map->conf1.bits.cdiv == 3) |
Sinan Divarci |
0:65766360f6b9 | 1230 | *cdiv = F_XTAL_X0_125; |
Sinan Divarci |
0:65766360f6b9 | 1231 | else |
Sinan Divarci |
0:65766360f6b9 | 1232 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1233 | |
Sinan Divarci |
0:65766360f6b9 | 1234 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1235 | } |
Sinan Divarci |
0:65766360f6b9 | 1236 | |
Sinan Divarci |
0:65766360f6b9 | 1237 | int MAX7032::set_ofps(uint8_t ofps) |
Sinan Divarci |
0:65766360f6b9 | 1238 | { |
Sinan Divarci |
0:65766360f6b9 | 1239 | if(ofps > 3) |
Sinan Divarci |
0:65766360f6b9 | 1240 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1241 | |
Sinan Divarci |
0:65766360f6b9 | 1242 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.ofps, ofps); |
Sinan Divarci |
0:65766360f6b9 | 1243 | |
Sinan Divarci |
0:65766360f6b9 | 1244 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1245 | } |
Sinan Divarci |
0:65766360f6b9 | 1246 | |
Sinan Divarci |
0:65766360f6b9 | 1247 | int MAX7032::get_ofps() |
Sinan Divarci |
0:65766360f6b9 | 1248 | { |
Sinan Divarci |
0:65766360f6b9 | 1249 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1250 | |
Sinan Divarci |
0:65766360f6b9 | 1251 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 1252 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1253 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1254 | |
Sinan Divarci |
0:65766360f6b9 | 1255 | return (int)this->reg_map->conf0.bits.ofps; |
Sinan Divarci |
0:65766360f6b9 | 1256 | } |
Sinan Divarci |
0:65766360f6b9 | 1257 | |
Sinan Divarci |
0:65766360f6b9 | 1258 | int MAX7032::set_onps(uint8_t onps) |
Sinan Divarci |
0:65766360f6b9 | 1259 | { |
Sinan Divarci |
0:65766360f6b9 | 1260 | if(onps > 3) |
Sinan Divarci |
0:65766360f6b9 | 1261 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1262 | |
Sinan Divarci |
0:65766360f6b9 | 1263 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.onps, onps); |
Sinan Divarci |
0:65766360f6b9 | 1264 | |
Sinan Divarci |
0:65766360f6b9 | 1265 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1266 | } |
Sinan Divarci |
0:65766360f6b9 | 1267 | |
Sinan Divarci |
0:65766360f6b9 | 1268 | int MAX7032::get_onps() |
Sinan Divarci |
0:65766360f6b9 | 1269 | { |
Sinan Divarci |
0:65766360f6b9 | 1270 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1271 | |
Sinan Divarci |
0:65766360f6b9 | 1272 | ret = read_register(CONF0_ADDR, (uint8_t *) & (this->reg_map->conf0)); |
Sinan Divarci |
0:65766360f6b9 | 1273 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1274 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1275 | |
Sinan Divarci |
0:65766360f6b9 | 1276 | return (int)this->reg_map->conf0.bits.onps; |
Sinan Divarci |
0:65766360f6b9 | 1277 | } |
Sinan Divarci |
0:65766360f6b9 | 1278 | |
Sinan Divarci |
0:65766360f6b9 | 1279 | int MAX7032::adjust_osc_freq(float osc_freq) |
Sinan Divarci |
0:65766360f6b9 | 1280 | { |
Sinan Divarci |
0:65766360f6b9 | 1281 | uint8_t osc_reg_val; |
Sinan Divarci |
0:65766360f6b9 | 1282 | |
Sinan Divarci |
0:65766360f6b9 | 1283 | if (osc_freq < 12.05 || osc_freq > 18.31) |
Sinan Divarci |
0:65766360f6b9 | 1284 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1285 | |
Sinan Divarci |
0:65766360f6b9 | 1286 | osc_reg_val = (osc_freq*1000) / 100; |
Sinan Divarci |
0:65766360f6b9 | 1287 | |
Sinan Divarci |
0:65766360f6b9 | 1288 | if(write_register(OSC_ADDR, &osc_reg_val, 1) >= 0) |
Sinan Divarci |
0:65766360f6b9 | 1289 | { |
Sinan Divarci |
0:65766360f6b9 | 1290 | f_xtal = osc_freq; |
Sinan Divarci |
0:65766360f6b9 | 1291 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1292 | } |
Sinan Divarci |
0:65766360f6b9 | 1293 | |
Sinan Divarci |
0:65766360f6b9 | 1294 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1295 | } |
Sinan Divarci |
0:65766360f6b9 | 1296 | |
Sinan Divarci |
0:65766360f6b9 | 1297 | float MAX7032::get_osc_freq() |
Sinan Divarci |
0:65766360f6b9 | 1298 | { |
Sinan Divarci |
0:65766360f6b9 | 1299 | return f_xtal; |
Sinan Divarci |
0:65766360f6b9 | 1300 | } |
Sinan Divarci |
0:65766360f6b9 | 1301 | |
Sinan Divarci |
0:65766360f6b9 | 1302 | int MAX7032::set_center_freq(float center_freq) |
Sinan Divarci |
0:65766360f6b9 | 1303 | { |
Sinan Divarci |
0:65766360f6b9 | 1304 | uint8_t tx_low_msb, tx_low_lsb, tx_high_msb, tx_high_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1305 | uint16_t center_freq_reg_val; |
Sinan Divarci |
0:65766360f6b9 | 1306 | int fsk_high, fsk_low, ask_fsk_sel; |
Sinan Divarci |
0:65766360f6b9 | 1307 | |
Sinan Divarci |
0:65766360f6b9 | 1308 | if (center_freq < 300 || center_freq > 450) |
Sinan Divarci |
0:65766360f6b9 | 1309 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1310 | |
Sinan Divarci |
0:65766360f6b9 | 1311 | ask_fsk_sel = this->get_mode(); |
Sinan Divarci |
0:65766360f6b9 | 1312 | |
Sinan Divarci |
0:65766360f6b9 | 1313 | if(ask_fsk_sel < 0){ |
Sinan Divarci |
0:65766360f6b9 | 1314 | return -98; |
Sinan Divarci |
0:65766360f6b9 | 1315 | } |
Sinan Divarci |
0:65766360f6b9 | 1316 | |
Sinan Divarci |
0:65766360f6b9 | 1317 | if(ask_fsk_sel == ASK_FSK_SEL_ASK){ |
Sinan Divarci |
0:65766360f6b9 | 1318 | center_freq_reg_val = (uint16_t)round(((center_freq / f_xtal) - 16) * 4096); |
Sinan Divarci |
0:65766360f6b9 | 1319 | |
Sinan Divarci |
0:65766360f6b9 | 1320 | tx_low_lsb = (uint8_t)(center_freq_reg_val & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1321 | tx_low_msb = (uint8_t)((center_freq_reg_val & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1322 | |
Sinan Divarci |
0:65766360f6b9 | 1323 | if(write_register(TXLOWLSB_ADDR, &tx_low_lsb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1324 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1325 | if(write_register(TXLOWMSB_ADDR, &tx_low_msb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1326 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1327 | } |
Sinan Divarci |
0:65766360f6b9 | 1328 | else{ |
Sinan Divarci |
0:65766360f6b9 | 1329 | fsk_high = round(((center_freq + fsk_dev) / f_xtal - 16) * 4096); |
Sinan Divarci |
0:65766360f6b9 | 1330 | fsk_low = round(((center_freq - fsk_dev) / f_xtal - 16) * 4096); |
Sinan Divarci |
0:65766360f6b9 | 1331 | |
Sinan Divarci |
0:65766360f6b9 | 1332 | tx_low_lsb = ((uint)(fsk_low) & 0X00FF); |
Sinan Divarci |
0:65766360f6b9 | 1333 | tx_low_msb = ((uint)(fsk_low) & 0XFF00) >> 8; |
Sinan Divarci |
0:65766360f6b9 | 1334 | tx_high_lsb = ((uint)(fsk_high) & 0X00FF); |
Sinan Divarci |
0:65766360f6b9 | 1335 | tx_high_msb = ((uint)(fsk_high) & 0XFF00) >> 8; |
Sinan Divarci |
0:65766360f6b9 | 1336 | |
Sinan Divarci |
0:65766360f6b9 | 1337 | if(write_register(TXLOWLSB_ADDR, &tx_low_lsb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1338 | return -3; |
Sinan Divarci |
0:65766360f6b9 | 1339 | if(write_register(TXLOWMSB_ADDR, &tx_low_msb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1340 | return -4; |
Sinan Divarci |
0:65766360f6b9 | 1341 | if(write_register(TXHIGHLSB_ADDR, &tx_high_lsb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1342 | return -5; |
Sinan Divarci |
0:65766360f6b9 | 1343 | if(write_register(TXHIGHMSB_ADDR, &tx_high_msb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1344 | return -6; |
Sinan Divarci |
0:65766360f6b9 | 1345 | } |
Sinan Divarci |
0:65766360f6b9 | 1346 | |
Sinan Divarci |
0:65766360f6b9 | 1347 | f_rf = center_freq; |
Sinan Divarci |
0:65766360f6b9 | 1348 | |
Sinan Divarci |
0:65766360f6b9 | 1349 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1350 | } |
Sinan Divarci |
0:65766360f6b9 | 1351 | |
Sinan Divarci |
0:65766360f6b9 | 1352 | float MAX7032::get_center_freq() |
Sinan Divarci |
0:65766360f6b9 | 1353 | { |
Sinan Divarci |
0:65766360f6b9 | 1354 | return f_rf; |
Sinan Divarci |
0:65766360f6b9 | 1355 | } |
Sinan Divarci |
0:65766360f6b9 | 1356 | |
Sinan Divarci |
0:65766360f6b9 | 1357 | int MAX7032::set_data_rate(float data_rate_set) |
Sinan Divarci |
0:65766360f6b9 | 1358 | { |
Sinan Divarci |
0:65766360f6b9 | 1359 | if(encoding == Manchester){ |
Sinan Divarci |
0:65766360f6b9 | 1360 | if(data_rate_set < 0 || data_rate_set > 33) |
Sinan Divarci |
0:65766360f6b9 | 1361 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1362 | } |
Sinan Divarci |
0:65766360f6b9 | 1363 | else{ |
Sinan Divarci |
0:65766360f6b9 | 1364 | if(data_rate_set < 0 || data_rate_set > 66) |
Sinan Divarci |
0:65766360f6b9 | 1365 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1366 | } |
Sinan Divarci |
0:65766360f6b9 | 1367 | |
Sinan Divarci |
0:65766360f6b9 | 1368 | this->data_rate = data_rate_set; |
Sinan Divarci |
0:65766360f6b9 | 1369 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1370 | } |
Sinan Divarci |
0:65766360f6b9 | 1371 | |
Sinan Divarci |
0:65766360f6b9 | 1372 | float MAX7032::get_data_rate() |
Sinan Divarci |
0:65766360f6b9 | 1373 | { |
Sinan Divarci |
0:65766360f6b9 | 1374 | return this->data_rate; |
Sinan Divarci |
0:65766360f6b9 | 1375 | } |
Sinan Divarci |
0:65766360f6b9 | 1376 | |
Sinan Divarci |
0:65766360f6b9 | 1377 | int MAX7032::set_fsk_dev(float fsk_dev_set) |
Sinan Divarci |
0:65766360f6b9 | 1378 | { |
Sinan Divarci |
0:65766360f6b9 | 1379 | if(fsk_dev_set <= 0 || fsk_dev_set > fsk_dev_max) |
Sinan Divarci |
0:65766360f6b9 | 1380 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1381 | |
Sinan Divarci |
0:65766360f6b9 | 1382 | this->fsk_dev = fsk_dev_set; |
Sinan Divarci |
0:65766360f6b9 | 1383 | |
Sinan Divarci |
0:65766360f6b9 | 1384 | return set_center_freq(f_rf); |
Sinan Divarci |
0:65766360f6b9 | 1385 | } |
Sinan Divarci |
0:65766360f6b9 | 1386 | |
Sinan Divarci |
0:65766360f6b9 | 1387 | float MAX7032::get_fsk_dev() |
Sinan Divarci |
0:65766360f6b9 | 1388 | { |
Sinan Divarci |
0:65766360f6b9 | 1389 | return this->fsk_dev; |
Sinan Divarci |
0:65766360f6b9 | 1390 | } |
Sinan Divarci |
0:65766360f6b9 | 1391 | |
Sinan Divarci |
0:65766360f6b9 | 1392 | int MAX7032::set_encoding(encoding_t encoding_set) |
Sinan Divarci |
0:65766360f6b9 | 1393 | { |
Sinan Divarci |
0:65766360f6b9 | 1394 | this->encoding = encoding_set; |
Sinan Divarci |
0:65766360f6b9 | 1395 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1396 | } |
Sinan Divarci |
0:65766360f6b9 | 1397 | |
Sinan Divarci |
0:65766360f6b9 | 1398 | int MAX7032::get_encoding() |
Sinan Divarci |
0:65766360f6b9 | 1399 | { |
Sinan Divarci |
0:65766360f6b9 | 1400 | return this->encoding; |
Sinan Divarci |
0:65766360f6b9 | 1401 | } |
Sinan Divarci |
0:65766360f6b9 | 1402 | |
Sinan Divarci |
0:65766360f6b9 | 1403 | int MAX7032::adjust_agc_dwell_timer(uint8_t k_val) |
Sinan Divarci |
0:65766360f6b9 | 1404 | { |
Sinan Divarci |
0:65766360f6b9 | 1405 | if(k_val < 9 || k_val > 23) |
Sinan Divarci |
0:65766360f6b9 | 1406 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1407 | |
Sinan Divarci |
0:65766360f6b9 | 1408 | if(!(k_val & 0x01)) |
Sinan Divarci |
0:65766360f6b9 | 1409 | return -98; |
Sinan Divarci |
0:65766360f6b9 | 1410 | |
Sinan Divarci |
0:65766360f6b9 | 1411 | k_val = (k_val - 9) / 2; |
Sinan Divarci |
0:65766360f6b9 | 1412 | |
Sinan Divarci |
0:65766360f6b9 | 1413 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.dt, k_val); |
Sinan Divarci |
0:65766360f6b9 | 1414 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1415 | } |
Sinan Divarci |
0:65766360f6b9 | 1416 | |
Sinan Divarci |
0:65766360f6b9 | 1417 | int MAX7032::adjust_agc_dwell_timer(int dwell_time) |
Sinan Divarci |
0:65766360f6b9 | 1418 | { |
Sinan Divarci |
0:65766360f6b9 | 1419 | float k_val; |
Sinan Divarci |
0:65766360f6b9 | 1420 | uint8_t k_val_byte; |
Sinan Divarci |
0:65766360f6b9 | 1421 | |
Sinan Divarci |
0:65766360f6b9 | 1422 | if(dwell_time <= 0) |
Sinan Divarci |
0:65766360f6b9 | 1423 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1424 | |
Sinan Divarci |
0:65766360f6b9 | 1425 | k_val = log10(dwell_time * f_xtal) * 3.3; |
Sinan Divarci |
0:65766360f6b9 | 1426 | k_val_byte = (uint8_t)ceil(k_val); |
Sinan Divarci |
0:65766360f6b9 | 1427 | |
Sinan Divarci |
0:65766360f6b9 | 1428 | if(!(k_val_byte & 0x01)) |
Sinan Divarci |
0:65766360f6b9 | 1429 | k_val_byte++; |
Sinan Divarci |
0:65766360f6b9 | 1430 | |
Sinan Divarci |
0:65766360f6b9 | 1431 | if(k_val_byte < 9) |
Sinan Divarci |
0:65766360f6b9 | 1432 | k_val_byte = 9; |
Sinan Divarci |
0:65766360f6b9 | 1433 | |
Sinan Divarci |
0:65766360f6b9 | 1434 | if(k_val_byte > 23) |
Sinan Divarci |
0:65766360f6b9 | 1435 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1436 | |
Sinan Divarci |
0:65766360f6b9 | 1437 | k_val_byte = (k_val_byte - 9) / 2; |
Sinan Divarci |
0:65766360f6b9 | 1438 | |
Sinan Divarci |
0:65766360f6b9 | 1439 | SET_BIT_FIELD(CONF1_ADDR, this->reg_map->conf1, this->reg_map->conf1.bits.dt, k_val_byte); |
Sinan Divarci |
0:65766360f6b9 | 1440 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1441 | } |
Sinan Divarci |
0:65766360f6b9 | 1442 | |
Sinan Divarci |
0:65766360f6b9 | 1443 | int MAX7032::get_agc_dwell_timer() |
Sinan Divarci |
0:65766360f6b9 | 1444 | { |
Sinan Divarci |
0:65766360f6b9 | 1445 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1446 | uint8_t k_val; |
Sinan Divarci |
0:65766360f6b9 | 1447 | |
Sinan Divarci |
0:65766360f6b9 | 1448 | ret = read_register(CONF1_ADDR, (uint8_t *) & (this->reg_map->conf1)); |
Sinan Divarci |
0:65766360f6b9 | 1449 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1450 | return ret; |
Sinan Divarci |
0:65766360f6b9 | 1451 | |
Sinan Divarci |
0:65766360f6b9 | 1452 | k_val = (2 * this->reg_map->conf1.bits.dt) + 9; |
Sinan Divarci |
0:65766360f6b9 | 1453 | |
Sinan Divarci |
0:65766360f6b9 | 1454 | return (int)(pow(2, k_val) / f_xtal); |
Sinan Divarci |
0:65766360f6b9 | 1455 | } |
Sinan Divarci |
0:65766360f6b9 | 1456 | |
Sinan Divarci |
0:65766360f6b9 | 1457 | int MAX7032::adjust_off_timer(timer_base_t time_base, int timer_val) |
Sinan Divarci |
0:65766360f6b9 | 1458 | { |
Sinan Divarci |
0:65766360f6b9 | 1459 | uint8_t toff_msb, toff_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1460 | |
Sinan Divarci |
0:65766360f6b9 | 1461 | if(timer_val < 1 || timer_val > 65535) |
Sinan Divarci |
0:65766360f6b9 | 1462 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1463 | |
Sinan Divarci |
0:65766360f6b9 | 1464 | toff_msb = (uint8_t)((timer_val & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1465 | toff_lsb = (uint8_t)(timer_val & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1466 | |
Sinan Divarci |
0:65766360f6b9 | 1467 | if(write_register(TOFFMSB_ADDR, &toff_msb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1468 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1469 | if(write_register(TOFFLSB_ADDR, &toff_lsb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1470 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1471 | |
Sinan Divarci |
0:65766360f6b9 | 1472 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.ofps, time_base); |
Sinan Divarci |
0:65766360f6b9 | 1473 | |
Sinan Divarci |
0:65766360f6b9 | 1474 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1475 | } |
Sinan Divarci |
0:65766360f6b9 | 1476 | |
Sinan Divarci |
0:65766360f6b9 | 1477 | int MAX7032::adjust_off_timer(int toff_time) |
Sinan Divarci |
0:65766360f6b9 | 1478 | { |
Sinan Divarci |
0:65766360f6b9 | 1479 | int time_base, ton_reg_val; |
Sinan Divarci |
0:65766360f6b9 | 1480 | timer_base_t timer_base_param; |
Sinan Divarci |
0:65766360f6b9 | 1481 | |
Sinan Divarci |
0:65766360f6b9 | 1482 | if(toff_time < 7860000){ //7.86s |
Sinan Divarci |
0:65766360f6b9 | 1483 | time_base = 120; |
Sinan Divarci |
0:65766360f6b9 | 1484 | timer_base_param = US_120; |
Sinan Divarci |
0:65766360f6b9 | 1485 | }else if(toff_time < 31460000){ //31.46s |
Sinan Divarci |
0:65766360f6b9 | 1486 | time_base = 480; |
Sinan Divarci |
0:65766360f6b9 | 1487 | timer_base_param = US_480; |
Sinan Divarci |
0:65766360f6b9 | 1488 | }else if(toff_time < 126000000){ //2min 6s |
Sinan Divarci |
0:65766360f6b9 | 1489 | time_base = 1920; |
Sinan Divarci |
0:65766360f6b9 | 1490 | timer_base_param = US_1920; |
Sinan Divarci |
0:65766360f6b9 | 1491 | }else if(toff_time < 503000000){ //8min 23s |
Sinan Divarci |
0:65766360f6b9 | 1492 | time_base = 7680; |
Sinan Divarci |
0:65766360f6b9 | 1493 | timer_base_param = US_7680; |
Sinan Divarci |
0:65766360f6b9 | 1494 | }else{ |
Sinan Divarci |
0:65766360f6b9 | 1495 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1496 | } |
Sinan Divarci |
0:65766360f6b9 | 1497 | |
Sinan Divarci |
0:65766360f6b9 | 1498 | ton_reg_val = toff_time / time_base; |
Sinan Divarci |
0:65766360f6b9 | 1499 | |
Sinan Divarci |
0:65766360f6b9 | 1500 | if((ton_reg_val * time_base) < toff_time) |
Sinan Divarci |
0:65766360f6b9 | 1501 | ton_reg_val++; |
Sinan Divarci |
0:65766360f6b9 | 1502 | |
Sinan Divarci |
0:65766360f6b9 | 1503 | adjust_off_timer(timer_base_param, ton_reg_val); |
Sinan Divarci |
0:65766360f6b9 | 1504 | |
Sinan Divarci |
0:65766360f6b9 | 1505 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1506 | } |
Sinan Divarci |
0:65766360f6b9 | 1507 | |
Sinan Divarci |
0:65766360f6b9 | 1508 | int MAX7032::get_off_timer() |
Sinan Divarci |
0:65766360f6b9 | 1509 | { |
Sinan Divarci |
0:65766360f6b9 | 1510 | uint8_t toff_msb, toff_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1511 | int timer_val, time_base, ret; |
Sinan Divarci |
0:65766360f6b9 | 1512 | |
Sinan Divarci |
0:65766360f6b9 | 1513 | time_base = this->get_ofps(); |
Sinan Divarci |
0:65766360f6b9 | 1514 | |
Sinan Divarci |
0:65766360f6b9 | 1515 | if(time_base < 0) |
Sinan Divarci |
0:65766360f6b9 | 1516 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1517 | |
Sinan Divarci |
0:65766360f6b9 | 1518 | ret = read_register(TOFFMSB_ADDR, (uint8_t *)&toff_msb); |
Sinan Divarci |
0:65766360f6b9 | 1519 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1520 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1521 | |
Sinan Divarci |
0:65766360f6b9 | 1522 | ret = read_register(TOFFLSB_ADDR, (uint8_t *)&toff_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1523 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1524 | return -3; |
Sinan Divarci |
0:65766360f6b9 | 1525 | |
Sinan Divarci |
0:65766360f6b9 | 1526 | timer_val = toff_msb; |
Sinan Divarci |
0:65766360f6b9 | 1527 | timer_val = timer_val << 8; |
Sinan Divarci |
0:65766360f6b9 | 1528 | timer_val += toff_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1529 | |
Sinan Divarci |
0:65766360f6b9 | 1530 | if(time_base == 0) |
Sinan Divarci |
0:65766360f6b9 | 1531 | return timer_val * 120; |
Sinan Divarci |
0:65766360f6b9 | 1532 | if(time_base == 1) |
Sinan Divarci |
0:65766360f6b9 | 1533 | return timer_val * 480; |
Sinan Divarci |
0:65766360f6b9 | 1534 | if(time_base == 2) |
Sinan Divarci |
0:65766360f6b9 | 1535 | return timer_val * 1920; |
Sinan Divarci |
0:65766360f6b9 | 1536 | if(time_base == 3) |
Sinan Divarci |
0:65766360f6b9 | 1537 | return timer_val * 7680; |
Sinan Divarci |
0:65766360f6b9 | 1538 | |
Sinan Divarci |
0:65766360f6b9 | 1539 | return -4; |
Sinan Divarci |
0:65766360f6b9 | 1540 | } |
Sinan Divarci |
0:65766360f6b9 | 1541 | |
Sinan Divarci |
0:65766360f6b9 | 1542 | int MAX7032::adjust_on_timer(timer_base_t time_base, int timer_val) |
Sinan Divarci |
0:65766360f6b9 | 1543 | { |
Sinan Divarci |
0:65766360f6b9 | 1544 | uint8_t ton_msb, ton_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1545 | |
Sinan Divarci |
0:65766360f6b9 | 1546 | if(timer_val < 1 || timer_val > 65535) |
Sinan Divarci |
0:65766360f6b9 | 1547 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1548 | |
Sinan Divarci |
0:65766360f6b9 | 1549 | ton_msb = (uint8_t)((timer_val & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1550 | ton_lsb = (uint8_t)(timer_val & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1551 | |
Sinan Divarci |
0:65766360f6b9 | 1552 | if(write_register(TONMSB_ADDR, &ton_msb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1553 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1554 | if(write_register(TONLSB_ADDR, &ton_lsb, 1) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1555 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1556 | |
Sinan Divarci |
0:65766360f6b9 | 1557 | SET_BIT_FIELD(CONF0_ADDR, this->reg_map->conf0, this->reg_map->conf0.bits.onps, time_base); |
Sinan Divarci |
0:65766360f6b9 | 1558 | |
Sinan Divarci |
0:65766360f6b9 | 1559 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1560 | } |
Sinan Divarci |
0:65766360f6b9 | 1561 | |
Sinan Divarci |
0:65766360f6b9 | 1562 | int MAX7032::adjust_on_timer(int ton_time) |
Sinan Divarci |
0:65766360f6b9 | 1563 | { |
Sinan Divarci |
0:65766360f6b9 | 1564 | int time_base, ton_reg_val; |
Sinan Divarci |
0:65766360f6b9 | 1565 | timer_base_t timer_base_param; |
Sinan Divarci |
0:65766360f6b9 | 1566 | |
Sinan Divarci |
0:65766360f6b9 | 1567 | if(ton_time < 7860000){ //7.86s |
Sinan Divarci |
0:65766360f6b9 | 1568 | time_base = 120; |
Sinan Divarci |
0:65766360f6b9 | 1569 | timer_base_param = US_120; |
Sinan Divarci |
0:65766360f6b9 | 1570 | }else if(ton_time < 31460000){ //31.46s |
Sinan Divarci |
0:65766360f6b9 | 1571 | time_base = 480; |
Sinan Divarci |
0:65766360f6b9 | 1572 | timer_base_param = US_480; |
Sinan Divarci |
0:65766360f6b9 | 1573 | }else if(ton_time < 126000000){ //2min 6s |
Sinan Divarci |
0:65766360f6b9 | 1574 | time_base = 1920; |
Sinan Divarci |
0:65766360f6b9 | 1575 | timer_base_param = US_1920; |
Sinan Divarci |
0:65766360f6b9 | 1576 | }else if(ton_time < 503000000){ //8min 23s |
Sinan Divarci |
0:65766360f6b9 | 1577 | time_base = 7680; |
Sinan Divarci |
0:65766360f6b9 | 1578 | timer_base_param = US_7680; |
Sinan Divarci |
0:65766360f6b9 | 1579 | }else{ |
Sinan Divarci |
0:65766360f6b9 | 1580 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1581 | } |
Sinan Divarci |
0:65766360f6b9 | 1582 | |
Sinan Divarci |
0:65766360f6b9 | 1583 | ton_reg_val = ton_time / time_base; |
Sinan Divarci |
0:65766360f6b9 | 1584 | |
Sinan Divarci |
0:65766360f6b9 | 1585 | if((ton_reg_val * time_base) < ton_time) |
Sinan Divarci |
0:65766360f6b9 | 1586 | ton_reg_val++; |
Sinan Divarci |
0:65766360f6b9 | 1587 | |
Sinan Divarci |
0:65766360f6b9 | 1588 | adjust_on_timer(timer_base_param, ton_reg_val); |
Sinan Divarci |
0:65766360f6b9 | 1589 | |
Sinan Divarci |
0:65766360f6b9 | 1590 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1591 | } |
Sinan Divarci |
0:65766360f6b9 | 1592 | |
Sinan Divarci |
0:65766360f6b9 | 1593 | int MAX7032::get_on_timer() |
Sinan Divarci |
0:65766360f6b9 | 1594 | { |
Sinan Divarci |
0:65766360f6b9 | 1595 | uint8_t ton_msb, ton_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1596 | int timer_val, time_base, ret; |
Sinan Divarci |
0:65766360f6b9 | 1597 | |
Sinan Divarci |
0:65766360f6b9 | 1598 | time_base = this->get_onps(); |
Sinan Divarci |
0:65766360f6b9 | 1599 | |
Sinan Divarci |
0:65766360f6b9 | 1600 | if(time_base < 0) |
Sinan Divarci |
0:65766360f6b9 | 1601 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1602 | |
Sinan Divarci |
0:65766360f6b9 | 1603 | ret = read_register(TONMSB_ADDR, (uint8_t *)&ton_msb); |
Sinan Divarci |
0:65766360f6b9 | 1604 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1605 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1606 | |
Sinan Divarci |
0:65766360f6b9 | 1607 | ret = read_register(TONLSB_ADDR, (uint8_t *)&ton_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1608 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1609 | return -3; |
Sinan Divarci |
0:65766360f6b9 | 1610 | |
Sinan Divarci |
0:65766360f6b9 | 1611 | timer_val = ton_msb; |
Sinan Divarci |
0:65766360f6b9 | 1612 | timer_val = timer_val << 8; |
Sinan Divarci |
0:65766360f6b9 | 1613 | timer_val += ton_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1614 | |
Sinan Divarci |
0:65766360f6b9 | 1615 | if(time_base == 0) |
Sinan Divarci |
0:65766360f6b9 | 1616 | return timer_val * 120; |
Sinan Divarci |
0:65766360f6b9 | 1617 | if(time_base == 1) |
Sinan Divarci |
0:65766360f6b9 | 1618 | return timer_val * 480; |
Sinan Divarci |
0:65766360f6b9 | 1619 | if(time_base == 2) |
Sinan Divarci |
0:65766360f6b9 | 1620 | return timer_val * 1920; |
Sinan Divarci |
0:65766360f6b9 | 1621 | if(time_base == 3) |
Sinan Divarci |
0:65766360f6b9 | 1622 | return timer_val * 7680; |
Sinan Divarci |
0:65766360f6b9 | 1623 | |
Sinan Divarci |
0:65766360f6b9 | 1624 | return -4; |
Sinan Divarci |
0:65766360f6b9 | 1625 | } |
Sinan Divarci |
0:65766360f6b9 | 1626 | |
Sinan Divarci |
0:65766360f6b9 | 1627 | int MAX7032::adjust_cpu_recovery_timer(int tcpu_time) |
Sinan Divarci |
0:65766360f6b9 | 1628 | { |
Sinan Divarci |
0:65766360f6b9 | 1629 | uint8_t tcpu; |
Sinan Divarci |
0:65766360f6b9 | 1630 | |
Sinan Divarci |
0:65766360f6b9 | 1631 | if(tcpu_time > 30600) |
Sinan Divarci |
0:65766360f6b9 | 1632 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1633 | |
Sinan Divarci |
0:65766360f6b9 | 1634 | tcpu = tcpu_time / 120; |
Sinan Divarci |
0:65766360f6b9 | 1635 | |
Sinan Divarci |
0:65766360f6b9 | 1636 | if((tcpu * 120) < tcpu_time) |
Sinan Divarci |
0:65766360f6b9 | 1637 | tcpu++; |
Sinan Divarci |
0:65766360f6b9 | 1638 | |
Sinan Divarci |
0:65766360f6b9 | 1639 | SET_BIT_FIELD(TCPU_ADDR, this->reg_map->tcpu, this->reg_map->tcpu.bits.tcpu, tcpu); |
Sinan Divarci |
0:65766360f6b9 | 1640 | |
Sinan Divarci |
0:65766360f6b9 | 1641 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1642 | } |
Sinan Divarci |
0:65766360f6b9 | 1643 | |
Sinan Divarci |
0:65766360f6b9 | 1644 | int MAX7032::get_cpu_recovery_timer() |
Sinan Divarci |
0:65766360f6b9 | 1645 | { |
Sinan Divarci |
0:65766360f6b9 | 1646 | uint8_t tcpu; |
Sinan Divarci |
0:65766360f6b9 | 1647 | int ret; |
Sinan Divarci |
0:65766360f6b9 | 1648 | |
Sinan Divarci |
0:65766360f6b9 | 1649 | ret = read_register(TCPU_ADDR, (uint8_t *)&tcpu); |
Sinan Divarci |
0:65766360f6b9 | 1650 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1651 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1652 | |
Sinan Divarci |
0:65766360f6b9 | 1653 | return tcpu * 120; |
Sinan Divarci |
0:65766360f6b9 | 1654 | } |
Sinan Divarci |
0:65766360f6b9 | 1655 | |
Sinan Divarci |
0:65766360f6b9 | 1656 | int MAX7032::adjust_rf_settling_timer(int trf_time) |
Sinan Divarci |
0:65766360f6b9 | 1657 | { |
Sinan Divarci |
0:65766360f6b9 | 1658 | uint8_t trf_msb, trf_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1659 | uint16_t timer_val; |
Sinan Divarci |
0:65766360f6b9 | 1660 | |
Sinan Divarci |
0:65766360f6b9 | 1661 | if(trf_time > 7864200) |
Sinan Divarci |
0:65766360f6b9 | 1662 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1663 | |
Sinan Divarci |
0:65766360f6b9 | 1664 | timer_val = trf_time / 120; |
Sinan Divarci |
0:65766360f6b9 | 1665 | |
Sinan Divarci |
0:65766360f6b9 | 1666 | if((timer_val*120) < trf_time) |
Sinan Divarci |
0:65766360f6b9 | 1667 | timer_val++; |
Sinan Divarci |
0:65766360f6b9 | 1668 | |
Sinan Divarci |
0:65766360f6b9 | 1669 | trf_msb = (uint8_t)((timer_val & 0xFF00) >> 8); |
Sinan Divarci |
0:65766360f6b9 | 1670 | trf_lsb = (uint8_t)(timer_val & 0x00FF); |
Sinan Divarci |
0:65766360f6b9 | 1671 | |
Sinan Divarci |
0:65766360f6b9 | 1672 | SET_BIT_FIELD(TRFMSB_ADDR, this->reg_map->trf_upper, this->reg_map->trf_upper.bits.trf_upper, trf_msb); |
Sinan Divarci |
0:65766360f6b9 | 1673 | SET_BIT_FIELD(TRFLSB_ADDR, this->reg_map->trf_lower, this->reg_map->trf_lower.bits.trf_lower, trf_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1674 | |
Sinan Divarci |
0:65766360f6b9 | 1675 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1676 | } |
Sinan Divarci |
0:65766360f6b9 | 1677 | |
Sinan Divarci |
0:65766360f6b9 | 1678 | int MAX7032::get_rf_settling_timer() |
Sinan Divarci |
0:65766360f6b9 | 1679 | { |
Sinan Divarci |
0:65766360f6b9 | 1680 | uint8_t trf_msb, trf_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1681 | int timer_val, ret; |
Sinan Divarci |
0:65766360f6b9 | 1682 | |
Sinan Divarci |
0:65766360f6b9 | 1683 | ret = read_register(TRFMSB_ADDR, (uint8_t *)&trf_msb); |
Sinan Divarci |
0:65766360f6b9 | 1684 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1685 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1686 | |
Sinan Divarci |
0:65766360f6b9 | 1687 | ret = read_register(TRFLSB_ADDR, (uint8_t *)&trf_lsb); |
Sinan Divarci |
0:65766360f6b9 | 1688 | if (ret < 0) |
Sinan Divarci |
0:65766360f6b9 | 1689 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1690 | |
Sinan Divarci |
0:65766360f6b9 | 1691 | timer_val = trf_msb; |
Sinan Divarci |
0:65766360f6b9 | 1692 | timer_val = timer_val << 8; |
Sinan Divarci |
0:65766360f6b9 | 1693 | timer_val += trf_lsb; |
Sinan Divarci |
0:65766360f6b9 | 1694 | |
Sinan Divarci |
0:65766360f6b9 | 1695 | return timer_val * 120; |
Sinan Divarci |
0:65766360f6b9 | 1696 | } |
Sinan Divarci |
0:65766360f6b9 | 1697 | |
Sinan Divarci |
0:65766360f6b9 | 1698 | int MAX7032::set_trx_state(trx_state_t trx_state) |
Sinan Divarci |
0:65766360f6b9 | 1699 | { |
Sinan Divarci |
0:65766360f6b9 | 1700 | if(trx_state == RECEIVE_MODE){ |
Sinan Divarci |
0:65766360f6b9 | 1701 | if(data_send != NULL){ |
Sinan Divarci |
0:65766360f6b9 | 1702 | delete this->data_send; |
Sinan Divarci |
0:65766360f6b9 | 1703 | this->data_send = NULL; |
Sinan Divarci |
0:65766360f6b9 | 1704 | } |
Sinan Divarci |
0:65766360f6b9 | 1705 | |
Sinan Divarci |
0:65766360f6b9 | 1706 | if(data_read == NULL){ |
Sinan Divarci |
0:65766360f6b9 | 1707 | this->data_read = new DigitalIn(data_pin); |
Sinan Divarci |
0:65766360f6b9 | 1708 | this->data_read->mode(OpenDrain); |
Sinan Divarci |
0:65766360f6b9 | 1709 | } |
Sinan Divarci |
0:65766360f6b9 | 1710 | |
Sinan Divarci |
0:65766360f6b9 | 1711 | if( set_t_r(RECEIVE_MODE) < 0) |
Sinan Divarci |
0:65766360f6b9 | 1712 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1713 | |
Sinan Divarci |
0:65766360f6b9 | 1714 | if(trx_pin == NULL) //trx state depends on how the trx pin is connected |
Sinan Divarci |
0:65766360f6b9 | 1715 | return -2; |
Sinan Divarci |
0:65766360f6b9 | 1716 | |
Sinan Divarci |
0:65766360f6b9 | 1717 | trx_pin->write(RECEIVE_MODE); |
Sinan Divarci |
0:65766360f6b9 | 1718 | |
Sinan Divarci |
0:65766360f6b9 | 1719 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1720 | |
Sinan Divarci |
0:65766360f6b9 | 1721 | }else{ |
Sinan Divarci |
0:65766360f6b9 | 1722 | if(data_read != NULL){ |
Sinan Divarci |
0:65766360f6b9 | 1723 | delete this->data_read; |
Sinan Divarci |
0:65766360f6b9 | 1724 | this->data_read = NULL; |
Sinan Divarci |
0:65766360f6b9 | 1725 | } |
Sinan Divarci |
0:65766360f6b9 | 1726 | |
Sinan Divarci |
0:65766360f6b9 | 1727 | if(data_send == NULL){ |
Sinan Divarci |
0:65766360f6b9 | 1728 | this->data_send = new DigitalOut(MAX7032_MBED_DATA_PIN); |
Sinan Divarci |
0:65766360f6b9 | 1729 | *data_send = 0; |
Sinan Divarci |
0:65766360f6b9 | 1730 | } |
Sinan Divarci |
0:65766360f6b9 | 1731 | |
Sinan Divarci |
0:65766360f6b9 | 1732 | return set_t_r(TRANSMIT_MODE); |
Sinan Divarci |
0:65766360f6b9 | 1733 | } |
Sinan Divarci |
0:65766360f6b9 | 1734 | } |
Sinan Divarci |
0:65766360f6b9 | 1735 | |
Sinan Divarci |
0:65766360f6b9 | 1736 | int MAX7032::get_trx_state() |
Sinan Divarci |
0:65766360f6b9 | 1737 | { |
Sinan Divarci |
0:65766360f6b9 | 1738 | if(get_t_r()) |
Sinan Divarci |
0:65766360f6b9 | 1739 | return TRANSMIT_MODE; |
Sinan Divarci |
0:65766360f6b9 | 1740 | |
Sinan Divarci |
0:65766360f6b9 | 1741 | if(trx_pin == NULL) //trx state depends on how the trx pin is connected |
Sinan Divarci |
0:65766360f6b9 | 1742 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1743 | |
Sinan Divarci |
0:65766360f6b9 | 1744 | return trx_pin->read(); |
Sinan Divarci |
0:65766360f6b9 | 1745 | } |
Sinan Divarci |
0:65766360f6b9 | 1746 | |
Sinan Divarci |
0:65766360f6b9 | 1747 | int MAX7032::rf_transmit_data(uint8_t *data, uint8_t data_len) |
Sinan Divarci |
0:65766360f6b9 | 1748 | { |
Sinan Divarci |
0:65766360f6b9 | 1749 | uint8_t *coded_data; |
Sinan Divarci |
0:65766360f6b9 | 1750 | uint8_t byte_idx, bit_idx; |
Sinan Divarci |
0:65766360f6b9 | 1751 | uint32_t bit_duration, coded_data_len, coded_data_idx, transmit_time = 0, curr_time; |
Sinan Divarci |
0:65766360f6b9 | 1752 | Timer timer; |
Sinan Divarci |
0:65766360f6b9 | 1753 | |
Sinan Divarci |
0:65766360f6b9 | 1754 | if(data == NULL) |
Sinan Divarci |
0:65766360f6b9 | 1755 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1756 | |
Sinan Divarci |
0:65766360f6b9 | 1757 | if(get_trx_state() == RECEIVE_MODE) |
Sinan Divarci |
0:65766360f6b9 | 1758 | return -98; |
Sinan Divarci |
0:65766360f6b9 | 1759 | |
Sinan Divarci |
0:65766360f6b9 | 1760 | if(encoding == Manchester){ |
Sinan Divarci |
0:65766360f6b9 | 1761 | coded_data = new uint8_t[data_len * 2]; |
Sinan Divarci |
0:65766360f6b9 | 1762 | |
Sinan Divarci |
0:65766360f6b9 | 1763 | if(coded_data == NULL) |
Sinan Divarci |
0:65766360f6b9 | 1764 | return -97; |
Sinan Divarci |
0:65766360f6b9 | 1765 | |
Sinan Divarci |
0:65766360f6b9 | 1766 | for(byte_idx = 0; byte_idx < data_len; byte_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1767 | { |
Sinan Divarci |
0:65766360f6b9 | 1768 | for(bit_idx = 0; bit_idx < 8; bit_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1769 | { |
Sinan Divarci |
0:65766360f6b9 | 1770 | if(data[byte_idx] & (0x80 >> bit_idx)){ |
Sinan Divarci |
0:65766360f6b9 | 1771 | coded_data[byte_idx * 2 + (bit_idx / 4)] |= (0x80>>((bit_idx % 4) * 2)); |
Sinan Divarci |
0:65766360f6b9 | 1772 | coded_data[byte_idx * 2 + (bit_idx / 4)] &= ~(0x80>>((bit_idx % 4) * 2 + 1)); |
Sinan Divarci |
0:65766360f6b9 | 1773 | } else{ |
Sinan Divarci |
0:65766360f6b9 | 1774 | coded_data[byte_idx * 2 + (bit_idx / 4)] &= ~(0x80>>((bit_idx % 4) * 2)); |
Sinan Divarci |
0:65766360f6b9 | 1775 | coded_data[byte_idx * 2 + (bit_idx / 4)] |= (0x80>>((bit_idx % 4) * 2 + 1)); |
Sinan Divarci |
0:65766360f6b9 | 1776 | } |
Sinan Divarci |
0:65766360f6b9 | 1777 | } |
Sinan Divarci |
0:65766360f6b9 | 1778 | } |
Sinan Divarci |
0:65766360f6b9 | 1779 | |
Sinan Divarci |
0:65766360f6b9 | 1780 | bit_duration = 1000 / (data_rate*2); //us |
Sinan Divarci |
0:65766360f6b9 | 1781 | coded_data_len = data_len * 2; |
Sinan Divarci |
0:65766360f6b9 | 1782 | } |
Sinan Divarci |
0:65766360f6b9 | 1783 | else if(encoding == NRZ){ |
Sinan Divarci |
0:65766360f6b9 | 1784 | coded_data = new uint8_t[data_len]; |
Sinan Divarci |
0:65766360f6b9 | 1785 | |
Sinan Divarci |
0:65766360f6b9 | 1786 | if(coded_data == NULL) |
Sinan Divarci |
0:65766360f6b9 | 1787 | return -96; |
Sinan Divarci |
0:65766360f6b9 | 1788 | |
Sinan Divarci |
0:65766360f6b9 | 1789 | for(byte_idx = 0; byte_idx < data_len; byte_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1790 | { |
Sinan Divarci |
0:65766360f6b9 | 1791 | coded_data[byte_idx] = data[byte_idx]; |
Sinan Divarci |
0:65766360f6b9 | 1792 | } |
Sinan Divarci |
0:65766360f6b9 | 1793 | |
Sinan Divarci |
0:65766360f6b9 | 1794 | bit_duration = 1000 / data_rate; //us |
Sinan Divarci |
0:65766360f6b9 | 1795 | coded_data_len = data_len; |
Sinan Divarci |
0:65766360f6b9 | 1796 | } |
Sinan Divarci |
0:65766360f6b9 | 1797 | |
Sinan Divarci |
0:65766360f6b9 | 1798 | timer.start(); |
Sinan Divarci |
0:65766360f6b9 | 1799 | |
Sinan Divarci |
0:65766360f6b9 | 1800 | core_util_critical_section_enter(); |
Sinan Divarci |
0:65766360f6b9 | 1801 | |
Sinan Divarci |
0:65766360f6b9 | 1802 | for(coded_data_idx = 0; coded_data_idx < coded_data_len; coded_data_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1803 | { |
Sinan Divarci |
0:65766360f6b9 | 1804 | for(bit_idx = 0; bit_idx < 8; bit_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1805 | { |
Sinan Divarci |
0:65766360f6b9 | 1806 | while(1) |
Sinan Divarci |
0:65766360f6b9 | 1807 | { |
Sinan Divarci |
0:65766360f6b9 | 1808 | curr_time = timer.read_us(); |
Sinan Divarci |
0:65766360f6b9 | 1809 | if((curr_time - transmit_time) >= bit_duration){ |
Sinan Divarci |
0:65766360f6b9 | 1810 | transmit_time = curr_time; |
Sinan Divarci |
0:65766360f6b9 | 1811 | |
Sinan Divarci |
0:65766360f6b9 | 1812 | if(coded_data[coded_data_idx] & (0x80 >> bit_idx)) |
Sinan Divarci |
0:65766360f6b9 | 1813 | *data_send = 1; |
Sinan Divarci |
0:65766360f6b9 | 1814 | else |
Sinan Divarci |
0:65766360f6b9 | 1815 | *data_send = 0; |
Sinan Divarci |
0:65766360f6b9 | 1816 | break; |
Sinan Divarci |
0:65766360f6b9 | 1817 | } |
Sinan Divarci |
0:65766360f6b9 | 1818 | } |
Sinan Divarci |
0:65766360f6b9 | 1819 | } |
Sinan Divarci |
0:65766360f6b9 | 1820 | } |
Sinan Divarci |
0:65766360f6b9 | 1821 | |
Sinan Divarci |
0:65766360f6b9 | 1822 | while(1) |
Sinan Divarci |
0:65766360f6b9 | 1823 | { |
Sinan Divarci |
0:65766360f6b9 | 1824 | curr_time = timer.read_us(); |
Sinan Divarci |
0:65766360f6b9 | 1825 | if((curr_time - transmit_time) >= bit_duration){ |
Sinan Divarci |
0:65766360f6b9 | 1826 | *data_send = 0; |
Sinan Divarci |
0:65766360f6b9 | 1827 | break; |
Sinan Divarci |
0:65766360f6b9 | 1828 | } |
Sinan Divarci |
0:65766360f6b9 | 1829 | } |
Sinan Divarci |
0:65766360f6b9 | 1830 | |
Sinan Divarci |
0:65766360f6b9 | 1831 | core_util_critical_section_exit(); |
Sinan Divarci |
0:65766360f6b9 | 1832 | |
Sinan Divarci |
0:65766360f6b9 | 1833 | delete coded_data; |
Sinan Divarci |
0:65766360f6b9 | 1834 | |
Sinan Divarci |
0:65766360f6b9 | 1835 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1836 | } |
Sinan Divarci |
0:65766360f6b9 | 1837 | |
Sinan Divarci |
0:65766360f6b9 | 1838 | int MAX7032::rf_receive_data(uint8_t *coded_data, uint8_t coded_data_len) |
Sinan Divarci |
0:65766360f6b9 | 1839 | { |
Sinan Divarci |
0:65766360f6b9 | 1840 | uint8_t byte_idx, bit_idx; |
Sinan Divarci |
0:65766360f6b9 | 1841 | uint32_t bit_duration, coded_data_idx, read_time = 0, curr_time; |
Sinan Divarci |
0:65766360f6b9 | 1842 | Timer timer; |
Sinan Divarci |
0:65766360f6b9 | 1843 | |
Sinan Divarci |
0:65766360f6b9 | 1844 | if(coded_data == NULL) |
Sinan Divarci |
0:65766360f6b9 | 1845 | return -99; |
Sinan Divarci |
0:65766360f6b9 | 1846 | |
Sinan Divarci |
0:65766360f6b9 | 1847 | if(get_trx_state() == TRANSMIT_MODE) |
Sinan Divarci |
0:65766360f6b9 | 1848 | return -98; |
Sinan Divarci |
0:65766360f6b9 | 1849 | |
Sinan Divarci |
0:65766360f6b9 | 1850 | if(encoding == Manchester){ |
Sinan Divarci |
0:65766360f6b9 | 1851 | bit_duration = 1000 / (data_rate*4); //us |
Sinan Divarci |
0:65766360f6b9 | 1852 | }else{ |
Sinan Divarci |
0:65766360f6b9 | 1853 | bit_duration = 1000 / (data_rate*2); //us |
Sinan Divarci |
0:65766360f6b9 | 1854 | } |
Sinan Divarci |
0:65766360f6b9 | 1855 | |
Sinan Divarci |
0:65766360f6b9 | 1856 | core_util_critical_section_enter(); |
Sinan Divarci |
0:65766360f6b9 | 1857 | |
Sinan Divarci |
0:65766360f6b9 | 1858 | timer.start(); |
Sinan Divarci |
0:65766360f6b9 | 1859 | |
Sinan Divarci |
0:65766360f6b9 | 1860 | for(coded_data_idx = 0; coded_data_idx < coded_data_len; coded_data_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1861 | { |
Sinan Divarci |
0:65766360f6b9 | 1862 | for(bit_idx = 0; bit_idx < 8; bit_idx++) |
Sinan Divarci |
0:65766360f6b9 | 1863 | { |
Sinan Divarci |
0:65766360f6b9 | 1864 | while(1) |
Sinan Divarci |
0:65766360f6b9 | 1865 | { |
Sinan Divarci |
0:65766360f6b9 | 1866 | curr_time = timer.read_us(); |
Sinan Divarci |
0:65766360f6b9 | 1867 | if((curr_time - read_time) >= bit_duration){ |
Sinan Divarci |
0:65766360f6b9 | 1868 | if(data_read->read()) |
Sinan Divarci |
0:65766360f6b9 | 1869 | coded_data[coded_data_idx] |= (0x80 >> bit_idx); |
Sinan Divarci |
0:65766360f6b9 | 1870 | else |
Sinan Divarci |
0:65766360f6b9 | 1871 | coded_data[coded_data_idx] &= ~(0x80 >> bit_idx); |
Sinan Divarci |
0:65766360f6b9 | 1872 | |
Sinan Divarci |
0:65766360f6b9 | 1873 | read_time = curr_time; |
Sinan Divarci |
0:65766360f6b9 | 1874 | break; |
Sinan Divarci |
0:65766360f6b9 | 1875 | } |
Sinan Divarci |
0:65766360f6b9 | 1876 | } |
Sinan Divarci |
0:65766360f6b9 | 1877 | } |
Sinan Divarci |
0:65766360f6b9 | 1878 | core_util_critical_section_exit(); |
Sinan Divarci |
0:65766360f6b9 | 1879 | } |
Sinan Divarci |
0:65766360f6b9 | 1880 | |
Sinan Divarci |
0:65766360f6b9 | 1881 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1882 | } |
Sinan Divarci |
0:65766360f6b9 | 1883 | |
Sinan Divarci |
0:65766360f6b9 | 1884 | int MAX7032::set_trx_pin(trx_state_t pin_state) |
Sinan Divarci |
0:65766360f6b9 | 1885 | { |
Sinan Divarci |
0:65766360f6b9 | 1886 | if(trx_pin == NULL) |
Sinan Divarci |
0:65766360f6b9 | 1887 | return -1; |
Sinan Divarci |
0:65766360f6b9 | 1888 | |
Sinan Divarci |
0:65766360f6b9 | 1889 | trx_pin->write(pin_state); |
Sinan Divarci |
0:65766360f6b9 | 1890 | return 0; |
Sinan Divarci |
0:65766360f6b9 | 1891 | } |