Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.
Dependencies: MaximTinyTester CmdLine MAX541 USBDevice
MAX11410.h@22:3e03687b7e95, 2019-07-25 (annotated)
- Committer:
- whismanoid
- Date:
- Thu Jul 25 03:24:47 2019 -0700
- Revision:
- 22:3e03687b7e95
- Parent:
- 21:498357e216b0
- Child:
- 23:e0c36767f98b
CodeGenerator MAX11410 WIP Configure_Voltage (not buildable yet)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
whismanoid | 20:97dccb1c9b61 | 1 | // /******************************************************************************* |
whismanoid | 20:97dccb1c9b61 | 2 | // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved. |
whismanoid | 20:97dccb1c9b61 | 3 | // * |
whismanoid | 20:97dccb1c9b61 | 4 | // * Permission is hereby granted, free of charge, to any person obtaining a |
whismanoid | 20:97dccb1c9b61 | 5 | // * copy of this software and associated documentation files (the "Software"), |
whismanoid | 20:97dccb1c9b61 | 6 | // * to deal in the Software without restriction, including without limitation |
whismanoid | 20:97dccb1c9b61 | 7 | // * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
whismanoid | 20:97dccb1c9b61 | 8 | // * and/or sell copies of the Software, and to permit persons to whom the |
whismanoid | 20:97dccb1c9b61 | 9 | // * Software is furnished to do so, subject to the following conditions: |
whismanoid | 20:97dccb1c9b61 | 10 | // * |
whismanoid | 20:97dccb1c9b61 | 11 | // * The above copyright notice and this permission notice shall be included |
whismanoid | 20:97dccb1c9b61 | 12 | // * in all copies or substantial portions of the Software. |
whismanoid | 20:97dccb1c9b61 | 13 | // * |
whismanoid | 20:97dccb1c9b61 | 14 | // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
whismanoid | 20:97dccb1c9b61 | 15 | // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
whismanoid | 20:97dccb1c9b61 | 16 | // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
whismanoid | 20:97dccb1c9b61 | 17 | // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
whismanoid | 20:97dccb1c9b61 | 18 | // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
whismanoid | 20:97dccb1c9b61 | 19 | // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
whismanoid | 20:97dccb1c9b61 | 20 | // * OTHER DEALINGS IN THE SOFTWARE. |
whismanoid | 20:97dccb1c9b61 | 21 | // * |
whismanoid | 20:97dccb1c9b61 | 22 | // * Except as contained in this notice, the name of Maxim Integrated |
whismanoid | 20:97dccb1c9b61 | 23 | // * Products, Inc. shall not be used except as stated in the Maxim Integrated |
whismanoid | 20:97dccb1c9b61 | 24 | // * Products, Inc. Branding Policy. |
whismanoid | 20:97dccb1c9b61 | 25 | // * |
whismanoid | 20:97dccb1c9b61 | 26 | // * The mere transfer of this software does not imply any licenses |
whismanoid | 20:97dccb1c9b61 | 27 | // * of trade secrets, proprietary technology, copyrights, patents, |
whismanoid | 20:97dccb1c9b61 | 28 | // * trademarks, maskwork rights, or any other form of intellectual |
whismanoid | 20:97dccb1c9b61 | 29 | // * property whatsoever. Maxim Integrated Products, Inc. retains all |
whismanoid | 20:97dccb1c9b61 | 30 | // * ownership rights. |
whismanoid | 20:97dccb1c9b61 | 31 | // ******************************************************************************* |
whismanoid | 20:97dccb1c9b61 | 32 | // */ |
whismanoid | 20:97dccb1c9b61 | 33 | // ********************************************************************* |
whismanoid | 20:97dccb1c9b61 | 34 | // @file MAX11410.h |
whismanoid | 20:97dccb1c9b61 | 35 | // ********************************************************************* |
whismanoid | 20:97dccb1c9b61 | 36 | // Header file |
whismanoid | 20:97dccb1c9b61 | 37 | // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file. |
whismanoid | 20:97dccb1c9b61 | 38 | // generated by XMLSystemOfDevicesToMBED.py |
whismanoid | 20:97dccb1c9b61 | 39 | // System Name = ExampleSystem |
whismanoid | 20:97dccb1c9b61 | 40 | // System Description = Device driver example |
whismanoid | 20:97dccb1c9b61 | 41 | // Device Name = MAX11410 |
whismanoid | 20:97dccb1c9b61 | 42 | // Device Description = 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC |
whismanoid | 20:97dccb1c9b61 | 43 | // Device Manufacturer = Maxim Integrated |
whismanoid | 20:97dccb1c9b61 | 44 | // Device PartNumber = MAX11410ATI+ |
whismanoid | 20:97dccb1c9b61 | 45 | // Device RegValue_Width = DataWidth16bit_HL |
whismanoid | 20:97dccb1c9b61 | 46 | // |
whismanoid | 20:97dccb1c9b61 | 47 | // SPI CS = ActiveLow |
whismanoid | 20:97dccb1c9b61 | 48 | // SPI FrameStart = CS |
whismanoid | 20:97dccb1c9b61 | 49 | // SPI CPOL = 0 |
whismanoid | 20:97dccb1c9b61 | 50 | // SPI CPHA = 0 |
whismanoid | 20:97dccb1c9b61 | 51 | // SPI MOSI and MISO Data are both stable on Rising edge of SCLK |
whismanoid | 20:97dccb1c9b61 | 52 | // SPI SCLK Idle Low |
whismanoid | 20:97dccb1c9b61 | 53 | // SPI SCLKMaxMHz = 8 |
whismanoid | 20:97dccb1c9b61 | 54 | // SPI SCLKMinMHz = 0 |
whismanoid | 20:97dccb1c9b61 | 55 | // |
whismanoid | 20:97dccb1c9b61 | 56 | |
whismanoid | 20:97dccb1c9b61 | 57 | |
whismanoid | 20:97dccb1c9b61 | 58 | // Prevent multiple declaration |
whismanoid | 20:97dccb1c9b61 | 59 | #ifndef __MAX11410_H__ |
whismanoid | 20:97dccb1c9b61 | 60 | #define __MAX11410_H__ |
whismanoid | 20:97dccb1c9b61 | 61 | |
whismanoid | 20:97dccb1c9b61 | 62 | // standard include for target platform |
whismanoid | 20:97dccb1c9b61 | 63 | #include "mbed.h" |
whismanoid | 20:97dccb1c9b61 | 64 | |
whismanoid | 20:97dccb1c9b61 | 65 | // CODE GENERATOR: conditional defines |
whismanoid | 20:97dccb1c9b61 | 66 | // CODE GENERATOR: class declaration and docstrings |
whismanoid | 20:97dccb1c9b61 | 67 | /** |
whismanoid | 20:97dccb1c9b61 | 68 | * @brief MAX11410 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC |
whismanoid | 20:97dccb1c9b61 | 69 | * |
whismanoid | 20:97dccb1c9b61 | 70 | * |
whismanoid | 20:97dccb1c9b61 | 71 | * |
whismanoid | 20:97dccb1c9b61 | 72 | * Datasheet: https://www.maximintegrated.com/MAX11410 |
whismanoid | 20:97dccb1c9b61 | 73 | * |
whismanoid | 20:97dccb1c9b61 | 74 | * |
whismanoid | 20:97dccb1c9b61 | 75 | * |
whismanoid | 20:97dccb1c9b61 | 76 | * //---------- CODE GENERATOR: helloCppCodeList |
whismanoid | 20:97dccb1c9b61 | 77 | * @code |
whismanoid | 20:97dccb1c9b61 | 78 | * // CODE GENERATOR: example code includes |
whismanoid | 20:97dccb1c9b61 | 79 | * // example code includes |
whismanoid | 20:97dccb1c9b61 | 80 | * // standard include for target platform |
whismanoid | 20:97dccb1c9b61 | 81 | * #include "mbed.h" |
whismanoid | 20:97dccb1c9b61 | 82 | * //#include "max32625.h" |
whismanoid | 20:97dccb1c9b61 | 83 | * #include "MAX11410.h" |
whismanoid | 20:97dccb1c9b61 | 84 | * |
whismanoid | 20:97dccb1c9b61 | 85 | * // example code board support |
whismanoid | 20:97dccb1c9b61 | 86 | * //MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3); |
whismanoid | 20:97dccb1c9b61 | 87 | * //DigitalOut rLED(LED1); |
whismanoid | 20:97dccb1c9b61 | 88 | * //DigitalOut gLED(LED2); |
whismanoid | 20:97dccb1c9b61 | 89 | * //DigitalOut bLED(LED3); |
whismanoid | 20:97dccb1c9b61 | 90 | * // |
whismanoid | 20:97dccb1c9b61 | 91 | * // Arduino "shield" connector port definitions (MAX32625MBED shown) |
whismanoid | 20:97dccb1c9b61 | 92 | * #if defined(TARGET_MAX32625MBED) |
whismanoid | 20:97dccb1c9b61 | 93 | * #define A0 AIN_0 |
whismanoid | 20:97dccb1c9b61 | 94 | * #define A1 AIN_1 |
whismanoid | 20:97dccb1c9b61 | 95 | * #define A2 AIN_2 |
whismanoid | 20:97dccb1c9b61 | 96 | * #define A3 AIN_3 |
whismanoid | 20:97dccb1c9b61 | 97 | * #define D0 P0_0 |
whismanoid | 20:97dccb1c9b61 | 98 | * #define D1 P0_1 |
whismanoid | 20:97dccb1c9b61 | 99 | * #define D2 P0_2 |
whismanoid | 20:97dccb1c9b61 | 100 | * #define D3 P0_3 |
whismanoid | 20:97dccb1c9b61 | 101 | * #define D4 P0_4 |
whismanoid | 20:97dccb1c9b61 | 102 | * #define D5 P0_5 |
whismanoid | 20:97dccb1c9b61 | 103 | * #define D6 P0_6 |
whismanoid | 20:97dccb1c9b61 | 104 | * #define D7 P0_7 |
whismanoid | 20:97dccb1c9b61 | 105 | * #define D8 P1_4 |
whismanoid | 20:97dccb1c9b61 | 106 | * #define D9 P1_5 |
whismanoid | 20:97dccb1c9b61 | 107 | * #define D10 P1_3 |
whismanoid | 20:97dccb1c9b61 | 108 | * #define D11 P1_1 |
whismanoid | 20:97dccb1c9b61 | 109 | * #define D12 P1_2 |
whismanoid | 20:97dccb1c9b61 | 110 | * #define D13 P1_0 |
whismanoid | 20:97dccb1c9b61 | 111 | * #endif |
whismanoid | 20:97dccb1c9b61 | 112 | * |
whismanoid | 20:97dccb1c9b61 | 113 | * // example code declare SPI interface |
whismanoid | 20:97dccb1c9b61 | 114 | * #if defined(TARGET_MAX32625MBED) |
whismanoid | 20:97dccb1c9b61 | 115 | * SPI spi(SPI1_MOSI, SPI1_MISO, SPI1_SCK); // mosi, miso, sclk spi1 TARGET_MAX32625MBED: P1_1 P1_2 P1_0 Arduino 10-pin header D11 D12 D13 |
whismanoid | 20:97dccb1c9b61 | 116 | * DigitalOut spi_cs(SPI1_SS); // TARGET_MAX32625MBED: P1_3 Arduino 10-pin header D10 |
whismanoid | 20:97dccb1c9b61 | 117 | * #elif defined(TARGET_MAX32600MBED) |
whismanoid | 20:97dccb1c9b61 | 118 | * SPI spi(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13 |
whismanoid | 20:97dccb1c9b61 | 119 | * DigitalOut spi_cs(SPI2_SS); // Generic: Arduino 10-pin header D10 |
whismanoid | 20:97dccb1c9b61 | 120 | * #else |
whismanoid | 20:97dccb1c9b61 | 121 | * SPI spi(D11, D12, D13); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13 |
whismanoid | 20:97dccb1c9b61 | 122 | * DigitalOut spi_cs(D10); // Generic: Arduino 10-pin header D10 |
whismanoid | 20:97dccb1c9b61 | 123 | * #endif |
whismanoid | 20:97dccb1c9b61 | 124 | * |
whismanoid | 20:97dccb1c9b61 | 125 | * // example code declare GPIO interface pins |
whismanoid | 20:97dccb1c9b61 | 126 | * // example code declare device instance |
whismanoid | 20:97dccb1c9b61 | 127 | * MAX11410 g_MAX11410_device(spi, spi_cs, MAX11410::MAX11410_IC); |
whismanoid | 20:97dccb1c9b61 | 128 | * |
whismanoid | 20:97dccb1c9b61 | 129 | * // example code main function |
whismanoid | 20:97dccb1c9b61 | 130 | * int main() |
whismanoid | 20:97dccb1c9b61 | 131 | * { |
whismanoid | 20:97dccb1c9b61 | 132 | * while (1) |
whismanoid | 20:97dccb1c9b61 | 133 | * { |
whismanoid | 20:97dccb1c9b61 | 134 | * // CODE GENERATOR: example code: member function Init |
whismanoid | 20:97dccb1c9b61 | 135 | * g_MAX11410_device.Init(); |
whismanoid | 20:97dccb1c9b61 | 136 | * |
whismanoid | 20:97dccb1c9b61 | 137 | * // CODE GENERATOR: example code: has no member function REF |
whismanoid | 20:97dccb1c9b61 | 138 | * // CODE GENERATOR: example code: has no member function CODE_LOAD |
whismanoid | 20:97dccb1c9b61 | 139 | * // CODE GENERATOR: example code: has no member function CODEallLOADall |
whismanoid | 20:97dccb1c9b61 | 140 | * // CODE GENERATOR: example code: has no member function CODEnLOADn |
whismanoid | 20:97dccb1c9b61 | 141 | * // CODE GENERATOR: example code: has no member function ScanManual |
whismanoid | 20:97dccb1c9b61 | 142 | * // CODE GENERATOR: example code: has no member function ReadAINcode |
whismanoid | 20:97dccb1c9b61 | 143 | * wait(3.0); |
whismanoid | 20:97dccb1c9b61 | 144 | * } |
whismanoid | 20:97dccb1c9b61 | 145 | * } |
whismanoid | 20:97dccb1c9b61 | 146 | * @endcode |
whismanoid | 20:97dccb1c9b61 | 147 | * //---------- CODE GENERATOR: end helloCppCodeList |
whismanoid | 20:97dccb1c9b61 | 148 | */ |
whismanoid | 20:97dccb1c9b61 | 149 | class MAX11410 { |
whismanoid | 20:97dccb1c9b61 | 150 | public: |
whismanoid | 20:97dccb1c9b61 | 151 | // CODE GENERATOR: TypedefEnum EnumItem declarations |
whismanoid | 20:97dccb1c9b61 | 152 | // CODE GENERATOR: TypedefEnum MAX11410_CMD_enum_t |
whismanoid | 20:97dccb1c9b61 | 153 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 154 | /// Register Addresses |
whismanoid | 20:97dccb1c9b61 | 155 | /// |
whismanoid | 20:97dccb1c9b61 | 156 | /// Naming convention is CMD_bitstream_FUNCTION_NAME |
whismanoid | 20:97dccb1c9b61 | 157 | /// - r = read/write bit (1=read, 0=write) |
whismanoid | 20:97dccb1c9b61 | 158 | /// - xaaa_aaaa = 7-bit register address field |
whismanoid | 20:97dccb1c9b61 | 159 | /// - dddd_dddd = 8-bit register data field |
whismanoid | 20:97dccb1c9b61 | 160 | /// - dddd_dddd_dddd_dddd = 16-bit register data field |
whismanoid | 20:97dccb1c9b61 | 161 | /// - dddd_dddd_dddd_dddd_dddd_dddd = 24-bit register data field |
whismanoid | 20:97dccb1c9b61 | 162 | /// - xxxx = don't care |
whismanoid | 20:97dccb1c9b61 | 163 | typedef enum MAX11410_CMD_enum_t { |
whismanoid | 20:97dccb1c9b61 | 164 | CMD_r000_0000_xxxx_xxdd_PD = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 165 | CMD_r000_0001_xddd_xxdd_CONV_START = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 166 | CMD_r000_0010_xddd_dddd_SEQ_START = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 167 | CMD_r000_0011_xxxx_xddd_CAL_START = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 168 | CMD_r000_0100_dddd_xddd_GP0_CTRL = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 169 | CMD_r000_0101_dddd_xddd_GP1_CTRL = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 170 | CMD_r000_0110_xddd_xxdd_GP_CONV = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 171 | CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 172 | CMD_r000_1000_x0dd_dddd_FILTER = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 173 | CMD_r000_1001_dddd_dddd_CTRL = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 174 | CMD_r000_1010_dddd_dddd_SOURCE = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 175 | CMD_r000_1011_dddd_dddd_MUX_CTRL0 = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 176 | CMD_r000_1100_dddd_dddd_MUX_CTRL1 = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 177 | CMD_r000_1101_dddd_dddd_MUX_CTRL2 = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 178 | CMD_r000_1110_xxdd_xddd_PGA = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 179 | CMD_r000_1111_dddd_dddd_WAIT_EXT = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 180 | CMD_r001_0000_xxxx_xxxx_WAIT_START = 0x10, //!< 8'b00010000 |
whismanoid | 20:97dccb1c9b61 | 181 | CMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID = 0x11, //!< 8'b00010001 |
whismanoid | 20:97dccb1c9b61 | 182 | CMD_r001_0010_xxxx_xxxx_dddd_xxdd_dddd_dddd_SYSC_SEL = 0x12, //!< 8'b00010010 |
whismanoid | 20:97dccb1c9b61 | 183 | CMD_r001_0011_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_A = 0x13, //!< 8'b00010011 |
whismanoid | 20:97dccb1c9b61 | 184 | CMD_r001_0100_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_B = 0x14, //!< 8'b00010100 |
whismanoid | 20:97dccb1c9b61 | 185 | CMD_r001_0101_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_A = 0x15, //!< 8'b00010101 |
whismanoid | 20:97dccb1c9b61 | 186 | CMD_r001_0110_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_B = 0x16, //!< 8'b00010110 |
whismanoid | 20:97dccb1c9b61 | 187 | CMD_r001_0111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_OFF = 0x17, //!< 8'b00010111 |
whismanoid | 20:97dccb1c9b61 | 188 | CMD_r001_1000_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_1 = 0x18, //!< 8'b00011000 |
whismanoid | 20:97dccb1c9b61 | 189 | CMD_r001_1001_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_2 = 0x19, //!< 8'b00011001 |
whismanoid | 20:97dccb1c9b61 | 190 | CMD_r001_1010_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_4 = 0x1a, //!< 8'b00011010 |
whismanoid | 20:97dccb1c9b61 | 191 | CMD_r001_1011_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_8 = 0x1b, //!< 8'b00011011 |
whismanoid | 20:97dccb1c9b61 | 192 | CMD_r001_1100_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_16 = 0x1c, //!< 8'b00011100 |
whismanoid | 20:97dccb1c9b61 | 193 | CMD_r001_1101_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_32 = 0x1d, //!< 8'b00011101 |
whismanoid | 20:97dccb1c9b61 | 194 | CMD_r001_1110_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_64 = 0x1e, //!< 8'b00011110 |
whismanoid | 20:97dccb1c9b61 | 195 | CMD_r001_1111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_128 = 0x1f, //!< 8'b00011111 |
whismanoid | 20:97dccb1c9b61 | 196 | CMD_r010_0000_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH0 = 0x20, //!< 8'b00100000 |
whismanoid | 20:97dccb1c9b61 | 197 | CMD_r010_0001_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH1 = 0x21, //!< 8'b00100001 |
whismanoid | 20:97dccb1c9b61 | 198 | CMD_r010_0010_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH2 = 0x22, //!< 8'b00100010 |
whismanoid | 20:97dccb1c9b61 | 199 | CMD_r010_0011_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH3 = 0x23, //!< 8'b00100011 |
whismanoid | 20:97dccb1c9b61 | 200 | CMD_r010_0100_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH4 = 0x24, //!< 8'b00100100 |
whismanoid | 20:97dccb1c9b61 | 201 | CMD_r010_0101_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH5 = 0x25, //!< 8'b00100101 |
whismanoid | 20:97dccb1c9b61 | 202 | CMD_r010_0110_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH6 = 0x26, //!< 8'b00100110 |
whismanoid | 20:97dccb1c9b61 | 203 | CMD_r010_0111_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH7 = 0x27, //!< 8'b00100111 |
whismanoid | 20:97dccb1c9b61 | 204 | CMD_r010_1000_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH0 = 0x28, //!< 8'b00101000 |
whismanoid | 20:97dccb1c9b61 | 205 | CMD_r010_1001_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH1 = 0x29, //!< 8'b00101001 |
whismanoid | 20:97dccb1c9b61 | 206 | CMD_r010_1010_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH2 = 0x2a, //!< 8'b00101010 |
whismanoid | 20:97dccb1c9b61 | 207 | CMD_r010_1011_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH3 = 0x2b, //!< 8'b00101011 |
whismanoid | 20:97dccb1c9b61 | 208 | CMD_r010_1100_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH4 = 0x2c, //!< 8'b00101100 |
whismanoid | 20:97dccb1c9b61 | 209 | CMD_r010_1101_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH5 = 0x2d, //!< 8'b00101101 |
whismanoid | 20:97dccb1c9b61 | 210 | CMD_r010_1110_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH6 = 0x2e, //!< 8'b00101110 |
whismanoid | 20:97dccb1c9b61 | 211 | CMD_r010_1111_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH7 = 0x2f, //!< 8'b00101111 |
whismanoid | 20:97dccb1c9b61 | 212 | CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0 = 0x30, //!< 8'b00110000 |
whismanoid | 20:97dccb1c9b61 | 213 | CMD_r011_0001_dddd_dddd_dddd_dddd_dddd_dddd_DATA1 = 0x31, //!< 8'b00110001 |
whismanoid | 20:97dccb1c9b61 | 214 | CMD_r011_0010_dddd_dddd_dddd_dddd_dddd_dddd_DATA2 = 0x32, //!< 8'b00110010 |
whismanoid | 20:97dccb1c9b61 | 215 | CMD_r011_0011_dddd_dddd_dddd_dddd_dddd_dddd_DATA3 = 0x33, //!< 8'b00110011 |
whismanoid | 20:97dccb1c9b61 | 216 | CMD_r011_0100_dddd_dddd_dddd_dddd_dddd_dddd_DATA4 = 0x34, //!< 8'b00110100 |
whismanoid | 20:97dccb1c9b61 | 217 | CMD_r011_0101_dddd_dddd_dddd_dddd_dddd_dddd_DATA5 = 0x35, //!< 8'b00110101 |
whismanoid | 20:97dccb1c9b61 | 218 | CMD_r011_0110_dddd_dddd_dddd_dddd_dddd_dddd_DATA6 = 0x36, //!< 8'b00110110 |
whismanoid | 20:97dccb1c9b61 | 219 | CMD_r011_0111_dddd_dddd_dddd_dddd_dddd_dddd_DATA7 = 0x37, //!< 8'b00110111 |
whismanoid | 20:97dccb1c9b61 | 220 | CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS = 0x38, //!< 8'b00111000 |
whismanoid | 20:97dccb1c9b61 | 221 | CMD_r011_1001_dddd_dddd_dddd_dddd_dxxd_dddd_STATUS_IE = 0x39, //!< 8'b00111001 |
whismanoid | 20:97dccb1c9b61 | 222 | CMD_r011_1010_xaaa_aaaa_dddd_dddd_UC_0 = 0x3a, //!< 8'b00111010 |
whismanoid | 20:97dccb1c9b61 | 223 | CMD_r011_1011_xaaa_aaaa_dddd_dddd_UC_1 = 0x3b, //!< 8'b00111011 |
whismanoid | 20:97dccb1c9b61 | 224 | CMD_r011_1100_xaaa_aaaa_dddd_dddd_UC_2 = 0x3c, //!< 8'b00111100 |
whismanoid | 20:97dccb1c9b61 | 225 | CMD_r011_1101_xaaa_aaaa_dddd_dddd_UC_3 = 0x3d, //!< 8'b00111101 |
whismanoid | 20:97dccb1c9b61 | 226 | CMD_r011_1110_xaaa_aaaa_dddd_dddd_UC_4 = 0x3e, //!< 8'b00111110 |
whismanoid | 20:97dccb1c9b61 | 227 | CMD_r011_1111_xaaa_aaaa_dddd_dddd_UC_5 = 0x3f, //!< 8'b00111111 |
whismanoid | 20:97dccb1c9b61 | 228 | CMD_r100_0000_xaaa_aaaa_dddd_dddd_UC_6 = 0x40, //!< 8'b01000000 |
whismanoid | 20:97dccb1c9b61 | 229 | CMD_r100_0001_xaaa_aaaa_dddd_dddd_UC_7 = 0x41, //!< 8'b01000001 |
whismanoid | 20:97dccb1c9b61 | 230 | CMD_r100_0010_xaaa_aaaa_dddd_dddd_UC_8 = 0x42, //!< 8'b01000010 |
whismanoid | 20:97dccb1c9b61 | 231 | CMD_r100_0011_xaaa_aaaa_dddd_dddd_UC_9 = 0x43, //!< 8'b01000011 |
whismanoid | 20:97dccb1c9b61 | 232 | CMD_r100_0100_xaaa_aaaa_dddd_dddd_UC_10 = 0x44, //!< 8'b01000100 |
whismanoid | 20:97dccb1c9b61 | 233 | CMD_r100_0101_xaaa_aaaa_dddd_dddd_UC_11 = 0x45, //!< 8'b01000101 |
whismanoid | 20:97dccb1c9b61 | 234 | CMD_r100_0110_xaaa_aaaa_dddd_dddd_UC_12 = 0x46, //!< 8'b01000110 |
whismanoid | 20:97dccb1c9b61 | 235 | CMD_r100_0111_xaaa_aaaa_dddd_dddd_UC_13 = 0x47, //!< 8'b01000111 |
whismanoid | 20:97dccb1c9b61 | 236 | CMD_r100_1000_xaaa_aaaa_dddd_dddd_UC_14 = 0x48, //!< 8'b01001000 |
whismanoid | 20:97dccb1c9b61 | 237 | CMD_r100_1001_xaaa_aaaa_dddd_dddd_UC_15 = 0x49, //!< 8'b01001001 |
whismanoid | 20:97dccb1c9b61 | 238 | CMD_r100_1010_xaaa_aaaa_dddd_dddd_UC_16 = 0x4a, //!< 8'b01001010 |
whismanoid | 20:97dccb1c9b61 | 239 | CMD_r100_1011_xaaa_aaaa_dddd_dddd_UC_17 = 0x4b, //!< 8'b01001011 |
whismanoid | 20:97dccb1c9b61 | 240 | CMD_r100_1100_xaaa_aaaa_dddd_dddd_UC_18 = 0x4c, //!< 8'b01001100 |
whismanoid | 20:97dccb1c9b61 | 241 | CMD_r100_1101_xaaa_aaaa_dddd_dddd_UC_19 = 0x4d, //!< 8'b01001101 |
whismanoid | 20:97dccb1c9b61 | 242 | CMD_r100_1110_xaaa_aaaa_dddd_dddd_UC_20 = 0x4e, //!< 8'b01001110 |
whismanoid | 20:97dccb1c9b61 | 243 | CMD_r100_1111_xaaa_aaaa_dddd_dddd_UC_21 = 0x4f, //!< 8'b01001111 |
whismanoid | 20:97dccb1c9b61 | 244 | CMD_r101_0000_xaaa_aaaa_dddd_dddd_UC_22 = 0x50, //!< 8'b01010000 |
whismanoid | 20:97dccb1c9b61 | 245 | CMD_r101_0001_xaaa_aaaa_dddd_dddd_UC_23 = 0x51, //!< 8'b01010001 |
whismanoid | 20:97dccb1c9b61 | 246 | CMD_r101_0010_xaaa_aaaa_dddd_dddd_UC_24 = 0x52, //!< 8'b01010010 |
whismanoid | 20:97dccb1c9b61 | 247 | CMD_r101_0011_xaaa_aaaa_dddd_dddd_UC_25 = 0x53, //!< 8'b01010011 |
whismanoid | 20:97dccb1c9b61 | 248 | CMD_r101_0100_xaaa_aaaa_dddd_dddd_UC_26 = 0x54, //!< 8'b01010100 |
whismanoid | 20:97dccb1c9b61 | 249 | CMD_r101_0101_xaaa_aaaa_dddd_dddd_UC_27 = 0x55, //!< 8'b01010101 |
whismanoid | 20:97dccb1c9b61 | 250 | CMD_r101_0110_xaaa_aaaa_dddd_dddd_UC_28 = 0x56, //!< 8'b01010110 |
whismanoid | 20:97dccb1c9b61 | 251 | CMD_r101_0111_xaaa_aaaa_dddd_dddd_UC_29 = 0x57, //!< 8'b01010111 |
whismanoid | 20:97dccb1c9b61 | 252 | CMD_r101_1000_xaaa_aaaa_dddd_dddd_UC_30 = 0x58, //!< 8'b01011000 |
whismanoid | 20:97dccb1c9b61 | 253 | CMD_r101_1001_xaaa_aaaa_dddd_dddd_UC_31 = 0x59, //!< 8'b01011001 |
whismanoid | 20:97dccb1c9b61 | 254 | CMD_r101_1010_xaaa_aaaa_dddd_dddd_UC_32 = 0x5a, //!< 8'b01011010 |
whismanoid | 20:97dccb1c9b61 | 255 | CMD_r101_1011_xaaa_aaaa_dddd_dddd_UC_33 = 0x5b, //!< 8'b01011011 |
whismanoid | 20:97dccb1c9b61 | 256 | CMD_r101_1100_xaaa_aaaa_dddd_dddd_UC_34 = 0x5c, //!< 8'b01011100 |
whismanoid | 20:97dccb1c9b61 | 257 | CMD_r101_1101_xaaa_aaaa_dddd_dddd_UC_35 = 0x5d, //!< 8'b01011101 |
whismanoid | 20:97dccb1c9b61 | 258 | CMD_r101_1110_xaaa_aaaa_dddd_dddd_UC_36 = 0x5e, //!< 8'b01011110 |
whismanoid | 20:97dccb1c9b61 | 259 | CMD_r101_1111_xaaa_aaaa_dddd_dddd_UC_37 = 0x5f, //!< 8'b01011111 |
whismanoid | 20:97dccb1c9b61 | 260 | CMD_r110_0000_xaaa_aaaa_dddd_dddd_UC_38 = 0x60, //!< 8'b01100000 |
whismanoid | 20:97dccb1c9b61 | 261 | CMD_r110_0001_xaaa_aaaa_dddd_dddd_UC_39 = 0x61, //!< 8'b01100001 |
whismanoid | 20:97dccb1c9b61 | 262 | CMD_r110_0010_xaaa_aaaa_dddd_dddd_UC_40 = 0x62, //!< 8'b01100010 |
whismanoid | 20:97dccb1c9b61 | 263 | CMD_r110_0011_xaaa_aaaa_dddd_dddd_UC_41 = 0x63, //!< 8'b01100011 |
whismanoid | 20:97dccb1c9b61 | 264 | CMD_r110_0100_xaaa_aaaa_dddd_dddd_UC_42 = 0x64, //!< 8'b01100100 |
whismanoid | 20:97dccb1c9b61 | 265 | CMD_r110_0101_xaaa_aaaa_dddd_dddd_UC_43 = 0x65, //!< 8'b01100101 |
whismanoid | 20:97dccb1c9b61 | 266 | CMD_r110_0110_xaaa_aaaa_dddd_dddd_UC_44 = 0x66, //!< 8'b01100110 |
whismanoid | 20:97dccb1c9b61 | 267 | CMD_r110_0111_xaaa_aaaa_dddd_dddd_UC_45 = 0x67, //!< 8'b01100111 |
whismanoid | 20:97dccb1c9b61 | 268 | CMD_r110_1000_xaaa_aaaa_dddd_dddd_UC_46 = 0x68, //!< 8'b01101000 |
whismanoid | 20:97dccb1c9b61 | 269 | CMD_r110_1001_xaaa_aaaa_dddd_dddd_UC_47 = 0x69, //!< 8'b01101001 |
whismanoid | 20:97dccb1c9b61 | 270 | CMD_r110_1010_xaaa_aaaa_dddd_dddd_UC_48 = 0x6a, //!< 8'b01101010 |
whismanoid | 20:97dccb1c9b61 | 271 | CMD_r110_1011_xaaa_aaaa_dddd_dddd_UC_49 = 0x6b, //!< 8'b01101011 |
whismanoid | 20:97dccb1c9b61 | 272 | CMD_r110_1100_xaaa_aaaa_dddd_dddd_UC_50 = 0x6c, //!< 8'b01101100 |
whismanoid | 20:97dccb1c9b61 | 273 | CMD_r110_1101_xaaa_aaaa_dddd_dddd_UC_51 = 0x6d, //!< 8'b01101101 |
whismanoid | 20:97dccb1c9b61 | 274 | CMD_r110_1110_xaaa_aaaa_dddd_dddd_UC_52 = 0x6e, //!< 8'b01101110 |
whismanoid | 20:97dccb1c9b61 | 275 | CMD_r110_1111_xxxx_xxxx_xaaa_aaaa_UCADDR = 0x6f, //!< 8'b01101111 |
whismanoid | 20:97dccb1c9b61 | 276 | CMD_1aaa_aaaa_REGISTER_READ = 0x80, //!< 8'b10000000 |
whismanoid | 20:97dccb1c9b61 | 277 | } MAX11410_CMD_enum_t; |
whismanoid | 20:97dccb1c9b61 | 278 | |
whismanoid | 20:97dccb1c9b61 | 279 | // CODE GENERATOR: TypedefEnum MAX11410_SEQ_ADDR_enum_t |
whismanoid | 20:97dccb1c9b61 | 280 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 281 | /// Microcode Sequencer Addresses. |
whismanoid | 20:97dccb1c9b61 | 282 | /// CMD_r000_0010_xddd_dddd_SEQ_START |
whismanoid | 20:97dccb1c9b61 | 283 | /// CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR |
whismanoid | 20:97dccb1c9b61 | 284 | /// |
whismanoid | 20:97dccb1c9b61 | 285 | /// Naming convention is CMD_bitstream_FUNCTION_NAME |
whismanoid | 20:97dccb1c9b61 | 286 | /// - xaaa_aaaa = 7-bit register address field |
whismanoid | 20:97dccb1c9b61 | 287 | /// - dddd_dddd = 8-bit register data field |
whismanoid | 20:97dccb1c9b61 | 288 | /// - xxxx = don't care |
whismanoid | 20:97dccb1c9b61 | 289 | typedef enum MAX11410_SEQ_ADDR_enum_t { |
whismanoid | 20:97dccb1c9b61 | 290 | SEQ_ADDR_r011_1010_xaaa_aaaa_dddd_dddd_UC_0 = 0x3a, //!< 8'b00111010 |
whismanoid | 20:97dccb1c9b61 | 291 | SEQ_ADDR_r011_1011_xaaa_aaaa_dddd_dddd_UC_1 = 0x3b, //!< 8'b00111011 |
whismanoid | 20:97dccb1c9b61 | 292 | SEQ_ADDR_r011_1100_xaaa_aaaa_dddd_dddd_UC_2 = 0x3c, //!< 8'b00111100 |
whismanoid | 20:97dccb1c9b61 | 293 | SEQ_ADDR_r011_1101_xaaa_aaaa_dddd_dddd_UC_3 = 0x3d, //!< 8'b00111101 |
whismanoid | 20:97dccb1c9b61 | 294 | SEQ_ADDR_r011_1110_xaaa_aaaa_dddd_dddd_UC_4 = 0x3e, //!< 8'b00111110 |
whismanoid | 20:97dccb1c9b61 | 295 | SEQ_ADDR_r011_1111_xaaa_aaaa_dddd_dddd_UC_5 = 0x3f, //!< 8'b00111111 |
whismanoid | 20:97dccb1c9b61 | 296 | SEQ_ADDR_r100_0000_xaaa_aaaa_dddd_dddd_UC_6 = 0x40, //!< 8'b01000000 |
whismanoid | 20:97dccb1c9b61 | 297 | SEQ_ADDR_r100_0001_xaaa_aaaa_dddd_dddd_UC_7 = 0x41, //!< 8'b01000001 |
whismanoid | 20:97dccb1c9b61 | 298 | SEQ_ADDR_r100_0010_xaaa_aaaa_dddd_dddd_UC_8 = 0x42, //!< 8'b01000010 |
whismanoid | 20:97dccb1c9b61 | 299 | SEQ_ADDR_r100_0011_xaaa_aaaa_dddd_dddd_UC_9 = 0x43, //!< 8'b01000011 |
whismanoid | 20:97dccb1c9b61 | 300 | SEQ_ADDR_r100_0100_xaaa_aaaa_dddd_dddd_UC_10 = 0x44, //!< 8'b01000100 |
whismanoid | 20:97dccb1c9b61 | 301 | SEQ_ADDR_r100_0101_xaaa_aaaa_dddd_dddd_UC_11 = 0x45, //!< 8'b01000101 |
whismanoid | 20:97dccb1c9b61 | 302 | SEQ_ADDR_r100_0110_xaaa_aaaa_dddd_dddd_UC_12 = 0x46, //!< 8'b01000110 |
whismanoid | 20:97dccb1c9b61 | 303 | SEQ_ADDR_r100_0111_xaaa_aaaa_dddd_dddd_UC_13 = 0x47, //!< 8'b01000111 |
whismanoid | 20:97dccb1c9b61 | 304 | SEQ_ADDR_r100_1000_xaaa_aaaa_dddd_dddd_UC_14 = 0x48, //!< 8'b01001000 |
whismanoid | 20:97dccb1c9b61 | 305 | SEQ_ADDR_r100_1001_xaaa_aaaa_dddd_dddd_UC_15 = 0x49, //!< 8'b01001001 |
whismanoid | 20:97dccb1c9b61 | 306 | SEQ_ADDR_r100_1010_xaaa_aaaa_dddd_dddd_UC_16 = 0x4a, //!< 8'b01001010 |
whismanoid | 20:97dccb1c9b61 | 307 | SEQ_ADDR_r100_1011_xaaa_aaaa_dddd_dddd_UC_17 = 0x4b, //!< 8'b01001011 |
whismanoid | 20:97dccb1c9b61 | 308 | SEQ_ADDR_r100_1100_xaaa_aaaa_dddd_dddd_UC_18 = 0x4c, //!< 8'b01001100 |
whismanoid | 20:97dccb1c9b61 | 309 | SEQ_ADDR_r100_1101_xaaa_aaaa_dddd_dddd_UC_19 = 0x4d, //!< 8'b01001101 |
whismanoid | 20:97dccb1c9b61 | 310 | SEQ_ADDR_r100_1110_xaaa_aaaa_dddd_dddd_UC_20 = 0x4e, //!< 8'b01001110 |
whismanoid | 20:97dccb1c9b61 | 311 | SEQ_ADDR_r100_1111_xaaa_aaaa_dddd_dddd_UC_21 = 0x4f, //!< 8'b01001111 |
whismanoid | 20:97dccb1c9b61 | 312 | SEQ_ADDR_r101_0000_xaaa_aaaa_dddd_dddd_UC_22 = 0x50, //!< 8'b01010000 |
whismanoid | 20:97dccb1c9b61 | 313 | SEQ_ADDR_r101_0001_xaaa_aaaa_dddd_dddd_UC_23 = 0x51, //!< 8'b01010001 |
whismanoid | 20:97dccb1c9b61 | 314 | SEQ_ADDR_r101_0010_xaaa_aaaa_dddd_dddd_UC_24 = 0x52, //!< 8'b01010010 |
whismanoid | 20:97dccb1c9b61 | 315 | SEQ_ADDR_r101_0011_xaaa_aaaa_dddd_dddd_UC_25 = 0x53, //!< 8'b01010011 |
whismanoid | 20:97dccb1c9b61 | 316 | SEQ_ADDR_r101_0100_xaaa_aaaa_dddd_dddd_UC_26 = 0x54, //!< 8'b01010100 |
whismanoid | 20:97dccb1c9b61 | 317 | SEQ_ADDR_r101_0101_xaaa_aaaa_dddd_dddd_UC_27 = 0x55, //!< 8'b01010101 |
whismanoid | 20:97dccb1c9b61 | 318 | SEQ_ADDR_r101_0110_xaaa_aaaa_dddd_dddd_UC_28 = 0x56, //!< 8'b01010110 |
whismanoid | 20:97dccb1c9b61 | 319 | SEQ_ADDR_r101_0111_xaaa_aaaa_dddd_dddd_UC_29 = 0x57, //!< 8'b01010111 |
whismanoid | 20:97dccb1c9b61 | 320 | SEQ_ADDR_r101_1000_xaaa_aaaa_dddd_dddd_UC_30 = 0x58, //!< 8'b01011000 |
whismanoid | 20:97dccb1c9b61 | 321 | SEQ_ADDR_r101_1001_xaaa_aaaa_dddd_dddd_UC_31 = 0x59, //!< 8'b01011001 |
whismanoid | 20:97dccb1c9b61 | 322 | SEQ_ADDR_r101_1010_xaaa_aaaa_dddd_dddd_UC_32 = 0x5a, //!< 8'b01011010 |
whismanoid | 20:97dccb1c9b61 | 323 | SEQ_ADDR_r101_1011_xaaa_aaaa_dddd_dddd_UC_33 = 0x5b, //!< 8'b01011011 |
whismanoid | 20:97dccb1c9b61 | 324 | SEQ_ADDR_r101_1100_xaaa_aaaa_dddd_dddd_UC_34 = 0x5c, //!< 8'b01011100 |
whismanoid | 20:97dccb1c9b61 | 325 | SEQ_ADDR_r101_1101_xaaa_aaaa_dddd_dddd_UC_35 = 0x5d, //!< 8'b01011101 |
whismanoid | 20:97dccb1c9b61 | 326 | SEQ_ADDR_r101_1110_xaaa_aaaa_dddd_dddd_UC_36 = 0x5e, //!< 8'b01011110 |
whismanoid | 20:97dccb1c9b61 | 327 | SEQ_ADDR_r101_1111_xaaa_aaaa_dddd_dddd_UC_37 = 0x5f, //!< 8'b01011111 |
whismanoid | 20:97dccb1c9b61 | 328 | SEQ_ADDR_r110_0000_xaaa_aaaa_dddd_dddd_UC_38 = 0x60, //!< 8'b01100000 |
whismanoid | 20:97dccb1c9b61 | 329 | SEQ_ADDR_r110_0001_xaaa_aaaa_dddd_dddd_UC_39 = 0x61, //!< 8'b01100001 |
whismanoid | 20:97dccb1c9b61 | 330 | SEQ_ADDR_r110_0010_xaaa_aaaa_dddd_dddd_UC_40 = 0x62, //!< 8'b01100010 |
whismanoid | 20:97dccb1c9b61 | 331 | SEQ_ADDR_r110_0011_xaaa_aaaa_dddd_dddd_UC_41 = 0x63, //!< 8'b01100011 |
whismanoid | 20:97dccb1c9b61 | 332 | SEQ_ADDR_r110_0100_xaaa_aaaa_dddd_dddd_UC_42 = 0x64, //!< 8'b01100100 |
whismanoid | 20:97dccb1c9b61 | 333 | SEQ_ADDR_r110_0101_xaaa_aaaa_dddd_dddd_UC_43 = 0x65, //!< 8'b01100101 |
whismanoid | 20:97dccb1c9b61 | 334 | SEQ_ADDR_r110_0110_xaaa_aaaa_dddd_dddd_UC_44 = 0x66, //!< 8'b01100110 |
whismanoid | 20:97dccb1c9b61 | 335 | SEQ_ADDR_r110_0111_xaaa_aaaa_dddd_dddd_UC_45 = 0x67, //!< 8'b01100111 |
whismanoid | 20:97dccb1c9b61 | 336 | SEQ_ADDR_r110_1000_xaaa_aaaa_dddd_dddd_UC_46 = 0x68, //!< 8'b01101000 |
whismanoid | 20:97dccb1c9b61 | 337 | SEQ_ADDR_r110_1001_xaaa_aaaa_dddd_dddd_UC_47 = 0x69, //!< 8'b01101001 |
whismanoid | 20:97dccb1c9b61 | 338 | SEQ_ADDR_r110_1010_xaaa_aaaa_dddd_dddd_UC_48 = 0x6a, //!< 8'b01101010 |
whismanoid | 20:97dccb1c9b61 | 339 | SEQ_ADDR_r110_1011_xaaa_aaaa_dddd_dddd_UC_49 = 0x6b, //!< 8'b01101011 |
whismanoid | 20:97dccb1c9b61 | 340 | SEQ_ADDR_r110_1100_xaaa_aaaa_dddd_dddd_UC_50 = 0x6c, //!< 8'b01101100 |
whismanoid | 20:97dccb1c9b61 | 341 | SEQ_ADDR_r110_1101_xaaa_aaaa_dddd_dddd_UC_51 = 0x6d, //!< 8'b01101101 |
whismanoid | 20:97dccb1c9b61 | 342 | SEQ_ADDR_r110_1110_xaaa_aaaa_dddd_dddd_UC_52 = 0x6e, //!< 8'b01101110 |
whismanoid | 20:97dccb1c9b61 | 343 | } MAX11410_SEQ_ADDR_enum_t; |
whismanoid | 20:97dccb1c9b61 | 344 | |
whismanoid | 20:97dccb1c9b61 | 345 | // CODE GENERATOR: TypedefEnum MAX11410_PD_enum_t |
whismanoid | 20:97dccb1c9b61 | 346 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 347 | /// Power-down state command |
whismanoid | 20:97dccb1c9b61 | 348 | /// CMD_r000_0000_xxxx_xxdd_PD PD[1:0] field |
whismanoid | 20:97dccb1c9b61 | 349 | /// |
whismanoid | 20:97dccb1c9b61 | 350 | /// - 00: Normal mode |
whismanoid | 20:97dccb1c9b61 | 351 | /// - 01: Standby mode -- Powers down all analog circuity, but not the internal voltage regulator |
whismanoid | 20:97dccb1c9b61 | 352 | /// - 10: Sleep mode -- Powers down all analog circuitry including the internal voltage regulator |
whismanoid | 20:97dccb1c9b61 | 353 | /// - 11: Reset -- all registers reset to POR state (Self Clearing to 01 Standby mode) |
whismanoid | 20:97dccb1c9b61 | 354 | typedef enum MAX11410_PD_enum_t { |
whismanoid | 20:97dccb1c9b61 | 355 | PD_00_Normal = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 356 | PD_01_Standby = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 357 | PD_10_Sleep = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 358 | PD_11_Reset = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 359 | } MAX11410_PD_enum_t; |
whismanoid | 20:97dccb1c9b61 | 360 | |
whismanoid | 20:97dccb1c9b61 | 361 | // CODE GENERATOR: TypedefEnum MAX11410_DEST_enum_t |
whismanoid | 20:97dccb1c9b61 | 362 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 363 | /// Conversion / seqeuncer start command |
whismanoid | 20:97dccb1c9b61 | 364 | /// CMD_r000_0001_xddd_xxdd_CONV_START DEST[2:0] field. |
whismanoid | 20:97dccb1c9b61 | 365 | /// CMD_r000_0110_xddd_xxdd_GP_CONV GP_DEST[2:0] field. |
whismanoid | 20:97dccb1c9b61 | 366 | /// |
whismanoid | 20:97dccb1c9b61 | 367 | /// - 000: Store result in DATA0 |
whismanoid | 20:97dccb1c9b61 | 368 | /// - 001: Store result in DATA1 |
whismanoid | 20:97dccb1c9b61 | 369 | /// - 010: Store result in DATA2 |
whismanoid | 20:97dccb1c9b61 | 370 | /// - 011: Store result in DATA3 |
whismanoid | 20:97dccb1c9b61 | 371 | /// - 100: Store result in DATA4 |
whismanoid | 20:97dccb1c9b61 | 372 | /// - 101: Store result in DATA5 |
whismanoid | 20:97dccb1c9b61 | 373 | /// - 110: Store result in DATA6 |
whismanoid | 20:97dccb1c9b61 | 374 | /// - 111: Store result in DATA7 |
whismanoid | 20:97dccb1c9b61 | 375 | typedef enum MAX11410_DEST_enum_t { |
whismanoid | 20:97dccb1c9b61 | 376 | DEST_000_DATA0 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 377 | DEST_001_DATA1 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 378 | DEST_010_DATA2 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 379 | DEST_011_DATA3 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 380 | DEST_100_DATA4 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 381 | DEST_101_DATA5 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 382 | DEST_110_DATA6 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 383 | DEST_111_DATA7 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 384 | } MAX11410_DEST_enum_t; |
whismanoid | 20:97dccb1c9b61 | 385 | |
whismanoid | 20:97dccb1c9b61 | 386 | // CODE GENERATOR: TypedefEnum MAX11410_CONV_TYPE_enum_t |
whismanoid | 20:97dccb1c9b61 | 387 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 388 | /// Conversion / seqeuncer start command |
whismanoid | 20:97dccb1c9b61 | 389 | /// CMD_r000_0001_xddd_xxdd_CONV_START CONV_TYPE[1:0] field. |
whismanoid | 20:97dccb1c9b61 | 390 | /// CMD_r000_0110_xddd_xxdd_GP_CONV GP_CONV_TYPE[2:0] field. |
whismanoid | 20:97dccb1c9b61 | 391 | /// |
whismanoid | 20:97dccb1c9b61 | 392 | /// - 00: Single conversion |
whismanoid | 20:97dccb1c9b61 | 393 | /// - 01: Continuous conversions |
whismanoid | 20:97dccb1c9b61 | 394 | /// - 10, 11: 1:4 Duty cycled conversions (modulator low-power mode) |
whismanoid | 20:97dccb1c9b61 | 395 | typedef enum MAX11410_CONV_TYPE_enum_t { |
whismanoid | 20:97dccb1c9b61 | 396 | CONV_TYPE_00_Single = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 397 | CONV_TYPE_01_Continuous = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 398 | CONV_TYPE_10_DutyCycle_1_4 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 399 | CONV_TYPE_11_DutyCycle_1_4 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 400 | } MAX11410_CONV_TYPE_enum_t; |
whismanoid | 20:97dccb1c9b61 | 401 | |
whismanoid | 20:97dccb1c9b61 | 402 | // CODE GENERATOR: TypedefEnum MAX11410_CAL_TYPE_enum_t |
whismanoid | 20:97dccb1c9b61 | 403 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 404 | /// Calbration command |
whismanoid | 20:97dccb1c9b61 | 405 | /// CMD_r000_0011_xxxx_xddd_CAL_START CAL_TYPE[2:0] field |
whismanoid | 20:97dccb1c9b61 | 406 | /// |
whismanoid | 20:97dccb1c9b61 | 407 | /// - 000: Performs a self-calibration. Resulting offset calibration value is stored in the SELF_OFF register, and the 1x gain calibration value is stored in the SELF_GAIN_1 register. |
whismanoid | 20:97dccb1c9b61 | 408 | /// - 001: Performs a PGA gain calibration at the currently programmed PGA gain. A 'No Op' will result if PGA Gain calibration is executed with the PGA disabled via the SIG_PATH register, or with the GAIN register set to 1x.The resulting gain calibration value is stored in the SELF_GAIN_[2-128] register corresponding to the currently programmed PGA GAIN setting. |
whismanoid | 20:97dccb1c9b61 | 409 | /// - 010: Reserved |
whismanoid | 20:97dccb1c9b61 | 410 | /// - 011: Reserved |
whismanoid | 20:97dccb1c9b61 | 411 | /// - 100: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_A register. |
whismanoid | 20:97dccb1c9b61 | 412 | /// - 101: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_A register. |
whismanoid | 20:97dccb1c9b61 | 413 | /// - 110: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_B register. |
whismanoid | 20:97dccb1c9b61 | 414 | /// - 111: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_B register. |
whismanoid | 20:97dccb1c9b61 | 415 | typedef enum MAX11410_CAL_TYPE_enum_t { |
whismanoid | 20:97dccb1c9b61 | 416 | CAL_TYPE_000_SELF_CAL = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 417 | CAL_TYPE_001_PGA_GAIN = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 418 | CAL_TYPE_010_reserved = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 419 | CAL_TYPE_011_reserved = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 420 | CAL_TYPE_100_SYS_OFF_A = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 421 | CAL_TYPE_101_SYS_GAIN_A = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 422 | CAL_TYPE_110_SYS_OFF_B = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 423 | CAL_TYPE_111_SYS_GAIN_B = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 424 | } MAX11410_CAL_TYPE_enum_t; |
whismanoid | 20:97dccb1c9b61 | 425 | |
whismanoid | 20:97dccb1c9b61 | 426 | // CODE GENERATOR: TypedefEnum MAX11410_GP0_DIR_enum_t |
whismanoid | 20:97dccb1c9b61 | 427 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 428 | /// GPIO0 pin command |
whismanoid | 20:97dccb1c9b61 | 429 | /// CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_DIR[1:0] field |
whismanoid | 20:97dccb1c9b61 | 430 | /// |
whismanoid | 20:97dccb1c9b61 | 431 | /// - 00: Input mode, reference to VDDIO (default) |
whismanoid | 20:97dccb1c9b61 | 432 | /// - 01: Reserved |
whismanoid | 20:97dccb1c9b61 | 433 | /// - 10: Output mode, open-drain output |
whismanoid | 20:97dccb1c9b61 | 434 | /// - 11: Output mode, CMOS output |
whismanoid | 20:97dccb1c9b61 | 435 | typedef enum MAX11410_GP0_DIR_enum_t { |
whismanoid | 20:97dccb1c9b61 | 436 | GP0_DIR_000_Input = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 437 | GP0_DIR_001_reserved = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 438 | GP0_DIR_010_OutputOpenDrain = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 439 | GP0_DIR_011_Output = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 440 | } MAX11410_GP0_DIR_enum_t; |
whismanoid | 20:97dccb1c9b61 | 441 | |
whismanoid | 20:97dccb1c9b61 | 442 | // CODE GENERATOR: TypedefEnum MAX11410_GP0_ISEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 443 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 444 | /// GPIO0 pin command |
whismanoid | 20:97dccb1c9b61 | 445 | /// CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_ISEL[1:0] field |
whismanoid | 20:97dccb1c9b61 | 446 | /// |
whismanoid | 20:97dccb1c9b61 | 447 | /// - 00: GPIO_0 input disabled (default) |
whismanoid | 20:97dccb1c9b61 | 448 | /// - 01: GPIO_0 input configured as rising-edge-triggered conversion start |
whismanoid | 20:97dccb1c9b61 | 449 | /// - 10: GPIO_0 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR |
whismanoid | 20:97dccb1c9b61 | 450 | /// - 11: Reserved |
whismanoid | 20:97dccb1c9b61 | 451 | typedef enum MAX11410_GP0_ISEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 452 | GP0_ISEL_000_disabled = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 453 | GP0_ISEL_001_TRIGGER_CONV_START = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 454 | GP0_ISEL_010_TRIGGER_SEQ_START = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 455 | GP0_ISEL_011_reserved = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 456 | } MAX11410_GP0_ISEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 457 | |
whismanoid | 20:97dccb1c9b61 | 458 | // CODE GENERATOR: TypedefEnum MAX11410_GP0_OSEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 459 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 460 | /// GPIO0 pin command |
whismanoid | 20:97dccb1c9b61 | 461 | /// CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_OSEL[2:0] field |
whismanoid | 20:97dccb1c9b61 | 462 | /// |
whismanoid | 20:97dccb1c9b61 | 463 | /// - 000: GPIO_0 output disabled, high Z (default) |
whismanoid | 20:97dccb1c9b61 | 464 | /// - 001: GPIO_0 output is configured as INTRB (active low) |
whismanoid | 20:97dccb1c9b61 | 465 | /// - 010: GPIO_0 output is configured as INTR (active high) |
whismanoid | 20:97dccb1c9b61 | 466 | /// - 011: GPIO_0 output is configured as state Logic 0 |
whismanoid | 20:97dccb1c9b61 | 467 | /// - 100: GPIO_0 output is configured as state Logic 1 |
whismanoid | 20:97dccb1c9b61 | 468 | /// - 101: GPIO_0 output is configured as automatic low-side switch operation (CMOS output mode overridden) |
whismanoid | 20:97dccb1c9b61 | 469 | /// - 110: GPIO_0 output is configured as modulator active status |
whismanoid | 20:97dccb1c9b61 | 470 | /// - 111: GPIO_0 output is configured as system clock (2.456Mhz Nominal) |
whismanoid | 20:97dccb1c9b61 | 471 | typedef enum MAX11410_GP0_OSEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 472 | GP0_OSEL_000_disabled = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 473 | GP0_OSEL_001_INTRB = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 474 | GP0_OSEL_010_INTR = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 475 | GP0_OSEL_011_LOGIC_0 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 476 | GP0_OSEL_100_LOGIC_1 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 477 | GP0_OSEL_101_AUTO_LOWSIDE_SWITCH = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 478 | GP0_OSEL_110_MODULATOR_ACTIVE_STATUS = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 479 | GP0_OSEL_111_CLOCK_2M456 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 480 | } MAX11410_GP0_OSEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 481 | |
whismanoid | 20:97dccb1c9b61 | 482 | // CODE GENERATOR: TypedefEnum MAX11410_GP1_DIR_enum_t |
whismanoid | 20:97dccb1c9b61 | 483 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 484 | /// GPIO1 pin command |
whismanoid | 20:97dccb1c9b61 | 485 | /// CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_DIR[1:0] field |
whismanoid | 20:97dccb1c9b61 | 486 | /// |
whismanoid | 20:97dccb1c9b61 | 487 | /// - 00: Input mode, reference to VDDIO (default) |
whismanoid | 20:97dccb1c9b61 | 488 | /// - 01: Reserved |
whismanoid | 20:97dccb1c9b61 | 489 | /// - 10: Output mode, open-drain output |
whismanoid | 20:97dccb1c9b61 | 490 | /// - 11: Output mode, CMOS output |
whismanoid | 20:97dccb1c9b61 | 491 | typedef enum MAX11410_GP1_DIR_enum_t { |
whismanoid | 20:97dccb1c9b61 | 492 | GP1_DIR_000_Input = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 493 | GP1_DIR_001_reserved = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 494 | GP1_DIR_010_OutputOpenDrain = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 495 | GP1_DIR_011_Output = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 496 | } MAX11410_GP1_DIR_enum_t; |
whismanoid | 20:97dccb1c9b61 | 497 | |
whismanoid | 20:97dccb1c9b61 | 498 | // CODE GENERATOR: TypedefEnum MAX11410_GP1_ISEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 499 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 500 | /// GPIO1 pin command |
whismanoid | 20:97dccb1c9b61 | 501 | /// CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_ISEL[1:0] field |
whismanoid | 20:97dccb1c9b61 | 502 | /// |
whismanoid | 20:97dccb1c9b61 | 503 | /// - 00: GPIO_1 input disabled (default) |
whismanoid | 20:97dccb1c9b61 | 504 | /// - 01: GPIO_1 input configured as rising-edge-triggered conversion start |
whismanoid | 20:97dccb1c9b61 | 505 | /// - 10: GPIO_1 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR |
whismanoid | 20:97dccb1c9b61 | 506 | /// - 11: Reserved |
whismanoid | 20:97dccb1c9b61 | 507 | typedef enum MAX11410_GP1_ISEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 508 | GP1_ISEL_000_disabled = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 509 | GP1_ISEL_001_TRIGGER_CONV_START = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 510 | GP1_ISEL_010_TRIGGER_SEQ_START = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 511 | GP1_ISEL_011_reserved = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 512 | } MAX11410_GP1_ISEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 513 | |
whismanoid | 20:97dccb1c9b61 | 514 | // CODE GENERATOR: TypedefEnum MAX11410_GP1_OSEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 515 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 516 | /// GPIO1 pin command |
whismanoid | 20:97dccb1c9b61 | 517 | /// CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_OSEL[2:0] field |
whismanoid | 20:97dccb1c9b61 | 518 | /// |
whismanoid | 20:97dccb1c9b61 | 519 | /// - 000: GPIO_1 output disabled, high Z (default) |
whismanoid | 20:97dccb1c9b61 | 520 | /// - 001: GPIO_1 output is configured as INTRB (active low) |
whismanoid | 20:97dccb1c9b61 | 521 | /// - 010: GPIO_1 output is configured as INTR (active high) |
whismanoid | 20:97dccb1c9b61 | 522 | /// - 011: GPIO_1 output is configured as state Logic 0 |
whismanoid | 20:97dccb1c9b61 | 523 | /// - 100: GPIO_1 output is configured as state Logic 1 |
whismanoid | 20:97dccb1c9b61 | 524 | /// - 101: GPIO_1 output is configured as system clock (2.456Mhz Nominal) |
whismanoid | 20:97dccb1c9b61 | 525 | /// - 110: GPIO_1 output is configured as modulator active status |
whismanoid | 20:97dccb1c9b61 | 526 | /// - 111: GPIO_1 output is configured as automatic low-side switch operation (CMOS output mode overridden) |
whismanoid | 20:97dccb1c9b61 | 527 | typedef enum MAX11410_GP1_OSEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 528 | GP1_OSEL_000_disabled = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 529 | GP1_OSEL_001_INTRB = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 530 | GP1_OSEL_010_INTR = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 531 | GP1_OSEL_011_LOGIC_0 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 532 | GP1_OSEL_100_LOGIC_1 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 533 | GP1_OSEL_101_AUTO_LOWSIDE_SWITCH = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 534 | GP1_OSEL_110_MODULATOR_ACTIVE_STATUS = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 535 | GP1_OSEL_111_CLOCK_2M456 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 536 | } MAX11410_GP1_OSEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 537 | |
whismanoid | 20:97dccb1c9b61 | 538 | // CODE GENERATOR: TypedefEnum MAX11410_LINEF_enum_t |
whismanoid | 20:97dccb1c9b61 | 539 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 540 | /// Filter command |
whismanoid | 20:97dccb1c9b61 | 541 | /// CMD_r000_1000_x0dd_dddd_FILTER LINEF[1:0] field |
whismanoid | 20:97dccb1c9b61 | 542 | /// |
whismanoid | 20:97dccb1c9b61 | 543 | /// - 00: Simultaneous 50/60Hz FIR rejection (default) |
whismanoid | 20:97dccb1c9b61 | 544 | /// - 01: 50Hz FIR rejection |
whismanoid | 20:97dccb1c9b61 | 545 | /// - 10: 60Hz FIR rejection |
whismanoid | 20:97dccb1c9b61 | 546 | /// - 11: SINC4 |
whismanoid | 20:97dccb1c9b61 | 547 | typedef enum MAX11410_LINEF_enum_t { |
whismanoid | 20:97dccb1c9b61 | 548 | LINEF_00_50Hz_60Hz_FIR = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 549 | LINEF_01_50Hz_FIR = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 550 | LINEF_10_60Hz_FIR = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 551 | LINEF_11_SINC4 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 552 | } MAX11410_LINEF_enum_t; |
whismanoid | 20:97dccb1c9b61 | 553 | |
whismanoid | 20:97dccb1c9b61 | 554 | // CODE GENERATOR: TypedefEnum MAX11410_RATE_enum_t |
whismanoid | 20:97dccb1c9b61 | 555 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 556 | /// Filter command |
whismanoid | 20:97dccb1c9b61 | 557 | /// CMD_r000_1000_x0dd_dddd_FILTER RATE[3:0] field |
whismanoid | 20:97dccb1c9b61 | 558 | /// |
whismanoid | 20:97dccb1c9b61 | 559 | /// Sets conversion rate based on LINEF value. See Table 9a through Table 9d for details. |
whismanoid | 20:97dccb1c9b61 | 560 | /// |
whismanoid | 20:97dccb1c9b61 | 561 | /// Table 9a. LINEF = 00 Data Rate and Filter Rejection Settings |
whismanoid | 20:97dccb1c9b61 | 562 | /// |
whismanoid | 20:97dccb1c9b61 | 563 | /// Rate | LINEF | CONV_TYPE | Rate |
whismanoid | 20:97dccb1c9b61 | 564 | /// -----------|------------------------|----------------------------|---------- |
whismanoid | 20:97dccb1c9b61 | 565 | /// RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 1.0SPS |
whismanoid | 20:97dccb1c9b61 | 566 | /// RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 2.0SPS |
whismanoid | 20:97dccb1c9b61 | 567 | /// RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 4.0SPS |
whismanoid | 20:97dccb1c9b61 | 568 | /// RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 8.0SPS |
whismanoid | 20:97dccb1c9b61 | 569 | /// RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 16.0SPS |
whismanoid | 20:97dccb1c9b61 | 570 | /// RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 1.1SPS |
whismanoid | 20:97dccb1c9b61 | 571 | /// RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 2.1SPS |
whismanoid | 20:97dccb1c9b61 | 572 | /// RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 4.2SPS |
whismanoid | 20:97dccb1c9b61 | 573 | /// RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 8.4SPS |
whismanoid | 20:97dccb1c9b61 | 574 | /// RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 16.8SPS |
whismanoid | 20:97dccb1c9b61 | 575 | /// RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS |
whismanoid | 20:97dccb1c9b61 | 576 | /// RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.5SPS |
whismanoid | 20:97dccb1c9b61 | 577 | /// RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.1SPS |
whismanoid | 20:97dccb1c9b61 | 578 | /// RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.1SPS |
whismanoid | 20:97dccb1c9b61 | 579 | /// RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 4.2SPS |
whismanoid | 20:97dccb1c9b61 | 580 | /// |
whismanoid | 20:97dccb1c9b61 | 581 | /// Table 9b. LINEF = 01 Data Rate and Filter Rejection Settings |
whismanoid | 20:97dccb1c9b61 | 582 | /// |
whismanoid | 20:97dccb1c9b61 | 583 | /// Rate | LINEF | CONV_TYPE | Rate |
whismanoid | 20:97dccb1c9b61 | 584 | /// ----------|------------------------|----------------------------|---------- |
whismanoid | 20:97dccb1c9b61 | 585 | /// RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 1.3SPS |
whismanoid | 20:97dccb1c9b61 | 586 | /// RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 2.5SPS |
whismanoid | 20:97dccb1c9b61 | 587 | /// RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 5.0SPS |
whismanoid | 20:97dccb1c9b61 | 588 | /// RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 10.0SPS |
whismanoid | 20:97dccb1c9b61 | 589 | /// RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 20.0SPS |
whismanoid | 20:97dccb1c9b61 | 590 | /// RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 35.6SPS |
whismanoid | 20:97dccb1c9b61 | 591 | /// RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 1.3SPS |
whismanoid | 20:97dccb1c9b61 | 592 | /// RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 2.7SPS |
whismanoid | 20:97dccb1c9b61 | 593 | /// RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 5.3SPS |
whismanoid | 20:97dccb1c9b61 | 594 | /// RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 10.7SPS |
whismanoid | 20:97dccb1c9b61 | 595 | /// RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 21.3SPS |
whismanoid | 20:97dccb1c9b61 | 596 | /// RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 40.0SPS |
whismanoid | 20:97dccb1c9b61 | 597 | /// RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS |
whismanoid | 20:97dccb1c9b61 | 598 | /// RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.7SPS |
whismanoid | 20:97dccb1c9b61 | 599 | /// RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.3SPS |
whismanoid | 20:97dccb1c9b61 | 600 | /// RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.7SPS |
whismanoid | 20:97dccb1c9b61 | 601 | /// RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 5.3SPS |
whismanoid | 20:97dccb1c9b61 | 602 | /// RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 10.0SPS |
whismanoid | 20:97dccb1c9b61 | 603 | /// |
whismanoid | 20:97dccb1c9b61 | 604 | /// Table 9c. LINEF = 10 Data Rate and Filter Rejection Settings |
whismanoid | 20:97dccb1c9b61 | 605 | /// |
whismanoid | 20:97dccb1c9b61 | 606 | /// Rate | LINEF | CONV_TYPE | Rate |
whismanoid | 20:97dccb1c9b61 | 607 | /// ----------|------------------------|----------------------------|---------- |
whismanoid | 20:97dccb1c9b61 | 608 | /// RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 1.3SPS |
whismanoid | 20:97dccb1c9b61 | 609 | /// RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 2.5SPS |
whismanoid | 20:97dccb1c9b61 | 610 | /// RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 5.0SPS |
whismanoid | 20:97dccb1c9b61 | 611 | /// RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 10.0SPS |
whismanoid | 20:97dccb1c9b61 | 612 | /// RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 20.0SPS |
whismanoid | 20:97dccb1c9b61 | 613 | /// RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 35.6SPS |
whismanoid | 20:97dccb1c9b61 | 614 | /// RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 1.3SPS |
whismanoid | 20:97dccb1c9b61 | 615 | /// RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 2.7SPS |
whismanoid | 20:97dccb1c9b61 | 616 | /// RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 5.3SPS |
whismanoid | 20:97dccb1c9b61 | 617 | /// RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 10.7SPS |
whismanoid | 20:97dccb1c9b61 | 618 | /// RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 21.3SPS |
whismanoid | 20:97dccb1c9b61 | 619 | /// RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 40.0SPS |
whismanoid | 20:97dccb1c9b61 | 620 | /// RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS |
whismanoid | 20:97dccb1c9b61 | 621 | /// RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.7SPS |
whismanoid | 20:97dccb1c9b61 | 622 | /// RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.3SPS |
whismanoid | 20:97dccb1c9b61 | 623 | /// RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.7SPS |
whismanoid | 20:97dccb1c9b61 | 624 | /// RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 5.3SPS |
whismanoid | 20:97dccb1c9b61 | 625 | /// RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 10.0SPS |
whismanoid | 20:97dccb1c9b61 | 626 | /// |
whismanoid | 20:97dccb1c9b61 | 627 | /// Table 9d. LINEF = 11 Data Rate and Filter Rejection Settings |
whismanoid | 20:97dccb1c9b61 | 628 | /// |
whismanoid | 20:97dccb1c9b61 | 629 | /// Rate | LINEF | CONV_TYPE | Rate |
whismanoid | 20:97dccb1c9b61 | 630 | /// ----------|------------------------|----------------------------|---------- |
whismanoid | 20:97dccb1c9b61 | 631 | /// RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 1SPS |
whismanoid | 20:97dccb1c9b61 | 632 | /// RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 2.5SPS |
whismanoid | 20:97dccb1c9b61 | 633 | /// RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 5SPS |
whismanoid | 20:97dccb1c9b61 | 634 | /// RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 10SPS |
whismanoid | 20:97dccb1c9b61 | 635 | /// RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 15SPS |
whismanoid | 20:97dccb1c9b61 | 636 | /// RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 30SPS |
whismanoid | 20:97dccb1c9b61 | 637 | /// RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 60SPS |
whismanoid | 20:97dccb1c9b61 | 638 | /// RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 120SPS |
whismanoid | 20:97dccb1c9b61 | 639 | /// RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 240SPS |
whismanoid | 20:97dccb1c9b61 | 640 | /// RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 480SPS |
whismanoid | 20:97dccb1c9b61 | 641 | /// RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 4SPS |
whismanoid | 20:97dccb1c9b61 | 642 | /// RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 10SPS |
whismanoid | 20:97dccb1c9b61 | 643 | /// RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 20SPS |
whismanoid | 20:97dccb1c9b61 | 644 | /// RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 40SPS |
whismanoid | 20:97dccb1c9b61 | 645 | /// RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 60SPS |
whismanoid | 20:97dccb1c9b61 | 646 | /// RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 120SPS |
whismanoid | 20:97dccb1c9b61 | 647 | /// RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 240SPS |
whismanoid | 20:97dccb1c9b61 | 648 | /// RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 480SPS |
whismanoid | 20:97dccb1c9b61 | 649 | /// RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 960SPS |
whismanoid | 20:97dccb1c9b61 | 650 | /// RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 1920SPS |
whismanoid | 20:97dccb1c9b61 | 651 | /// RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 1SPS |
whismanoid | 20:97dccb1c9b61 | 652 | /// RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 2.5SPS |
whismanoid | 20:97dccb1c9b61 | 653 | /// RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 5SPS |
whismanoid | 20:97dccb1c9b61 | 654 | /// RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 10SPS |
whismanoid | 20:97dccb1c9b61 | 655 | /// RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 15SPS |
whismanoid | 20:97dccb1c9b61 | 656 | /// RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 30SPS |
whismanoid | 20:97dccb1c9b61 | 657 | /// RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 60SPS |
whismanoid | 20:97dccb1c9b61 | 658 | /// RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 120SPS |
whismanoid | 20:97dccb1c9b61 | 659 | /// RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 240SPS |
whismanoid | 20:97dccb1c9b61 | 660 | /// RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 480SPS |
whismanoid | 20:97dccb1c9b61 | 661 | /// |
whismanoid | 20:97dccb1c9b61 | 662 | typedef enum MAX11410_RATE_enum_t { |
whismanoid | 20:97dccb1c9b61 | 663 | RATE_0000 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 664 | RATE_0001 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 665 | RATE_0010 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 666 | RATE_0011 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 667 | RATE_0100 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 668 | RATE_0101 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 669 | RATE_0110 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 670 | RATE_0111 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 671 | RATE_1000 = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 672 | RATE_1001 = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 673 | RATE_1010 = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 674 | RATE_1011 = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 675 | RATE_1100 = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 676 | RATE_1101 = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 677 | RATE_1110 = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 678 | RATE_1111 = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 679 | } MAX11410_RATE_enum_t; |
whismanoid | 20:97dccb1c9b61 | 680 | |
whismanoid | 20:97dccb1c9b61 | 681 | // CODE GENERATOR: TypedefEnum MAX11410_REF_SEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 682 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 683 | /// Filter command |
whismanoid | 20:97dccb1c9b61 | 684 | /// CMD_r000_1001_dddd_dddd_CTRL REF_SEL[2:0] field |
whismanoid | 20:97dccb1c9b61 | 685 | /// |
whismanoid | 20:97dccb1c9b61 | 686 | /// - 000: AIN0(REF0P)/AIN1(REF0N) |
whismanoid | 20:97dccb1c9b61 | 687 | /// - 001: REF1P/REF1N (default) |
whismanoid | 20:97dccb1c9b61 | 688 | /// - 010: REF2P/REF2N |
whismanoid | 20:97dccb1c9b61 | 689 | /// - 011: AVDD/AGND |
whismanoid | 20:97dccb1c9b61 | 690 | /// - 100: AIN0(REF0P)/AGND (single-ended mode) |
whismanoid | 20:97dccb1c9b61 | 691 | /// - 101: REF1P/AGND (single-ended mode) |
whismanoid | 20:97dccb1c9b61 | 692 | /// - 110: REF2P/AGND (single-ended mode) |
whismanoid | 20:97dccb1c9b61 | 693 | /// - 111: AVDD/AGND |
whismanoid | 20:97dccb1c9b61 | 694 | typedef enum MAX11410_REF_SEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 695 | REF_SEL_000_AIN0_AIN1 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 696 | REF_SEL_001_REF1P_REF1N = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 697 | REF_SEL_010_REF2P_REF2N = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 698 | REF_SEL_011_AVDD_AGND = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 699 | REF_SEL_100_AIN0_AGND = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 700 | REF_SEL_101_REF1P_AGND = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 701 | REF_SEL_110_REF2P_AGND = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 702 | REF_SEL_111_AVDD_AGND = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 703 | } MAX11410_REF_SEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 704 | |
whismanoid | 20:97dccb1c9b61 | 705 | // CODE GENERATOR: TypedefEnum MAX11410_VBIAS_MODE_enum_t |
whismanoid | 20:97dccb1c9b61 | 706 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 707 | /// Source command |
whismanoid | 20:97dccb1c9b61 | 708 | /// CMD_r000_1010_dddd_dddd_SOURCE VBIAS_MODE[1:0] field |
whismanoid | 20:97dccb1c9b61 | 709 | /// |
whismanoid | 20:97dccb1c9b61 | 710 | /// - 00: Active mode (default) |
whismanoid | 20:97dccb1c9b61 | 711 | /// - 01: High impedance; 125kOhm output impedance |
whismanoid | 20:97dccb1c9b61 | 712 | /// - 10: Low impedance; 20kOhm output impedance |
whismanoid | 20:97dccb1c9b61 | 713 | /// - 11: Low impedance; 20kOhm output impedance |
whismanoid | 20:97dccb1c9b61 | 714 | typedef enum MAX11410_VBIAS_MODE_enum_t { |
whismanoid | 20:97dccb1c9b61 | 715 | VBIAS_MODE_00_Active = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 716 | VBIAS_MODE_01_125kOhm = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 717 | VBIAS_MODE_10_20kOhm = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 718 | VBIAS_MODE_11_20kOhm = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 719 | } MAX11410_VBIAS_MODE_enum_t; |
whismanoid | 20:97dccb1c9b61 | 720 | |
whismanoid | 20:97dccb1c9b61 | 721 | // CODE GENERATOR: TypedefEnum MAX11410_BRN_MODE_enum_t |
whismanoid | 20:97dccb1c9b61 | 722 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 723 | /// Source command |
whismanoid | 20:97dccb1c9b61 | 724 | /// CMD_r000_1010_dddd_dddd_SOURCE BRN_MODE[1:0] field |
whismanoid | 20:97dccb1c9b61 | 725 | /// |
whismanoid | 20:97dccb1c9b61 | 726 | /// - 00: Powered down, burnout sources disabled (default) |
whismanoid | 20:97dccb1c9b61 | 727 | /// - 01: 0.5uA burnout current sources enabled |
whismanoid | 20:97dccb1c9b61 | 728 | /// - 10: 1uA burnout current sources enabled |
whismanoid | 20:97dccb1c9b61 | 729 | /// - 11: 10uA burnout current sources enabled |
whismanoid | 20:97dccb1c9b61 | 730 | typedef enum MAX11410_BRN_MODE_enum_t { |
whismanoid | 20:97dccb1c9b61 | 731 | BRN_MODE_00_disabled = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 732 | BRN_MODE_01_0u5A = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 733 | BRN_MODE_10_1uA = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 734 | BRN_MODE_11_10uA = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 735 | } MAX11410_BRN_MODE_enum_t; |
whismanoid | 20:97dccb1c9b61 | 736 | |
whismanoid | 20:97dccb1c9b61 | 737 | // CODE GENERATOR: TypedefEnum MAX11410_IDAC_MODE_enum_t |
whismanoid | 20:97dccb1c9b61 | 738 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 739 | /// Source command |
whismanoid | 20:97dccb1c9b61 | 740 | /// CMD_r000_1010_dddd_dddd_SOURCE IDAC_MODE[3:0] field |
whismanoid | 20:97dccb1c9b61 | 741 | /// |
whismanoid | 20:97dccb1c9b61 | 742 | /// - 0000: 10uA (default) |
whismanoid | 20:97dccb1c9b61 | 743 | /// - 0001: 50uA |
whismanoid | 20:97dccb1c9b61 | 744 | /// - 0010: 75uA |
whismanoid | 20:97dccb1c9b61 | 745 | /// - 0011: 100uA |
whismanoid | 20:97dccb1c9b61 | 746 | /// - 0100: 125uA |
whismanoid | 20:97dccb1c9b61 | 747 | /// - 0101: 150uA |
whismanoid | 20:97dccb1c9b61 | 748 | /// - 0110: 175uA |
whismanoid | 20:97dccb1c9b61 | 749 | /// - 0111: 200uA |
whismanoid | 20:97dccb1c9b61 | 750 | /// - 1000: 225uA |
whismanoid | 20:97dccb1c9b61 | 751 | /// - 1001: 250uA |
whismanoid | 20:97dccb1c9b61 | 752 | /// - 1010: 300uA |
whismanoid | 20:97dccb1c9b61 | 753 | /// - 1011: 400uA |
whismanoid | 20:97dccb1c9b61 | 754 | /// - 1100: 600uA |
whismanoid | 20:97dccb1c9b61 | 755 | /// - 1101: 800uA |
whismanoid | 20:97dccb1c9b61 | 756 | /// - 1110: 1200uA |
whismanoid | 20:97dccb1c9b61 | 757 | /// - 1111: 1600uA |
whismanoid | 20:97dccb1c9b61 | 758 | typedef enum MAX11410_IDAC_MODE_enum_t { |
whismanoid | 20:97dccb1c9b61 | 759 | IDAC_MODE_0000_10uA = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 760 | IDAC_MODE_0001_50uA = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 761 | IDAC_MODE_0010_75uA = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 762 | IDAC_MODE_0011_100uA = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 763 | IDAC_MODE_0100_125uA = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 764 | IDAC_MODE_0101_150uA = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 765 | IDAC_MODE_0110_175uA = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 766 | IDAC_MODE_0111_200uA = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 767 | IDAC_MODE_1000_225uA = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 768 | IDAC_MODE_1001_250uA = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 769 | IDAC_MODE_1010_300uA = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 770 | IDAC_MODE_1011_400uA = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 771 | IDAC_MODE_1100_600uA = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 772 | IDAC_MODE_1101_800uA = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 773 | IDAC_MODE_1110_1200uA = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 774 | IDAC_MODE_1111_1600uA = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 775 | } MAX11410_IDAC_MODE_enum_t; |
whismanoid | 20:97dccb1c9b61 | 776 | |
whismanoid | 20:97dccb1c9b61 | 777 | // CODE GENERATOR: TypedefEnum MAX11410_AINP_SEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 778 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 779 | /// Input multiplexer channel selection |
whismanoid | 20:97dccb1c9b61 | 780 | /// CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0] |
whismanoid | 20:97dccb1c9b61 | 781 | /// |
whismanoid | 20:97dccb1c9b61 | 782 | /// - 0000: AINP = AIN0 |
whismanoid | 20:97dccb1c9b61 | 783 | /// - 0001: AINP = AIN1 |
whismanoid | 20:97dccb1c9b61 | 784 | /// - 0010: AINP = AIN2 |
whismanoid | 20:97dccb1c9b61 | 785 | /// - 0011: AINP = AIN3 |
whismanoid | 20:97dccb1c9b61 | 786 | /// - 0100: AINP = AIN4 |
whismanoid | 20:97dccb1c9b61 | 787 | /// - 0101: AINP = AIN5 |
whismanoid | 20:97dccb1c9b61 | 788 | /// - 0110: AINP = AIN6 |
whismanoid | 20:97dccb1c9b61 | 789 | /// - 0111: AINP = AIN7 |
whismanoid | 20:97dccb1c9b61 | 790 | /// - 1000: AINP = AIN8 |
whismanoid | 20:97dccb1c9b61 | 791 | /// - 1001: AINP = AIN9 |
whismanoid | 20:97dccb1c9b61 | 792 | /// - 1010: AINP = AVDD |
whismanoid | 20:97dccb1c9b61 | 793 | /// - 1011: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 794 | /// - 1100: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 795 | /// - 1101: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 796 | /// - 1110: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 797 | /// - 1111: AINN = Unconnected (default) |
whismanoid | 20:97dccb1c9b61 | 798 | typedef enum MAX11410_AINP_SEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 799 | AINP_SEL_0000_AIN0 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 800 | AINP_SEL_0001_AIN1 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 801 | AINP_SEL_0010_AIN2 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 802 | AINP_SEL_0011_AIN3 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 803 | AINP_SEL_0100_AIN4 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 804 | AINP_SEL_0101_AIN5 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 805 | AINP_SEL_0110_AIN6 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 806 | AINP_SEL_0111_AIN7 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 807 | AINP_SEL_1000_AIN8 = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 808 | AINP_SEL_1001_AIN9 = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 809 | AINP_SEL_1010_AVDD = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 810 | AINP_SEL_1011_unconnected = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 811 | AINP_SEL_1100_unconnected = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 812 | AINP_SEL_1101_unconnected = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 813 | AINP_SEL_1110_unconnected = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 814 | AINP_SEL_1111_unconnected = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 815 | } MAX11410_AINP_SEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 816 | |
whismanoid | 20:97dccb1c9b61 | 817 | // CODE GENERATOR: TypedefEnum MAX11410_AINN_SEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 818 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 819 | /// Input multiplexer channel selection |
whismanoid | 20:97dccb1c9b61 | 820 | /// CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0] |
whismanoid | 20:97dccb1c9b61 | 821 | /// |
whismanoid | 20:97dccb1c9b61 | 822 | /// - 0000: AINN = AIN0 |
whismanoid | 20:97dccb1c9b61 | 823 | /// - 0001: AINN = AIN1 |
whismanoid | 20:97dccb1c9b61 | 824 | /// - 0010: AINN = AIN2 |
whismanoid | 20:97dccb1c9b61 | 825 | /// - 0011: AINN = AIN3 |
whismanoid | 20:97dccb1c9b61 | 826 | /// - 0100: AINN = AIN4 |
whismanoid | 20:97dccb1c9b61 | 827 | /// - 0101: AINN = AIN5 |
whismanoid | 20:97dccb1c9b61 | 828 | /// - 0110: AINN = AIN6 |
whismanoid | 20:97dccb1c9b61 | 829 | /// - 0111: AINN = AIN7 |
whismanoid | 20:97dccb1c9b61 | 830 | /// - 1000: AINN = AIN8 |
whismanoid | 20:97dccb1c9b61 | 831 | /// - 1001: AINN = AIN9 |
whismanoid | 20:97dccb1c9b61 | 832 | /// - 1010: AINN = GND |
whismanoid | 20:97dccb1c9b61 | 833 | /// - 1011: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 834 | /// - 1100: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 835 | /// - 1101: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 836 | /// - 1110: AINN = Unconnected |
whismanoid | 20:97dccb1c9b61 | 837 | /// - 1111: AINN = Unconnected (default) |
whismanoid | 20:97dccb1c9b61 | 838 | typedef enum MAX11410_AINN_SEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 839 | AINN_SEL_0000_AIN0 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 840 | AINN_SEL_0001_AIN1 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 841 | AINN_SEL_0010_AIN2 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 842 | AINN_SEL_0011_AIN3 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 843 | AINN_SEL_0100_AIN4 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 844 | AINN_SEL_0101_AIN5 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 845 | AINN_SEL_0110_AIN6 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 846 | AINN_SEL_0111_AIN7 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 847 | AINN_SEL_1000_AIN8 = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 848 | AINN_SEL_1001_AIN9 = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 849 | AINN_SEL_1010_GND = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 850 | AINN_SEL_1011_unconnected = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 851 | AINN_SEL_1100_unconnected = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 852 | AINN_SEL_1101_unconnected = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 853 | AINN_SEL_1110_unconnected = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 854 | AINN_SEL_1111_unconnected = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 855 | } MAX11410_AINN_SEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 856 | |
whismanoid | 20:97dccb1c9b61 | 857 | // CODE GENERATOR: TypedefEnum MAX11410_IDAC1_SEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 858 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 859 | /// Input multiplexer channel selection |
whismanoid | 20:97dccb1c9b61 | 860 | /// CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC1_SEL[3:0] |
whismanoid | 20:97dccb1c9b61 | 861 | /// |
whismanoid | 20:97dccb1c9b61 | 862 | /// - 0000: AIN0 |
whismanoid | 20:97dccb1c9b61 | 863 | /// - 0001: AIN1 |
whismanoid | 20:97dccb1c9b61 | 864 | /// - 0010: AIN2 |
whismanoid | 20:97dccb1c9b61 | 865 | /// - 0011: AIN3 |
whismanoid | 20:97dccb1c9b61 | 866 | /// - 0100: AIN4 |
whismanoid | 20:97dccb1c9b61 | 867 | /// - 0101: AIN5 |
whismanoid | 20:97dccb1c9b61 | 868 | /// - 0110: AIN6 |
whismanoid | 20:97dccb1c9b61 | 869 | /// - 0111: AIN7 |
whismanoid | 20:97dccb1c9b61 | 870 | /// - 1000: AIN8 |
whismanoid | 20:97dccb1c9b61 | 871 | /// - 1001: AIN9 |
whismanoid | 20:97dccb1c9b61 | 872 | /// - 1010: Unconnected; IDAC1 powered down. |
whismanoid | 20:97dccb1c9b61 | 873 | /// - 1011: Unconnected; IDAC1 powered down. |
whismanoid | 20:97dccb1c9b61 | 874 | /// - 1100: Unconnected; IDAC1 powered down. |
whismanoid | 20:97dccb1c9b61 | 875 | /// - 1101: Unconnected; IDAC1 powered down. |
whismanoid | 20:97dccb1c9b61 | 876 | /// - 1110: Unconnected; IDAC1 powered down. |
whismanoid | 20:97dccb1c9b61 | 877 | /// - 1111: Unconnected; IDAC1 powered down.(Default) |
whismanoid | 20:97dccb1c9b61 | 878 | typedef enum MAX11410_IDAC1_SEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 879 | IDAC1_SEL_0000_AIN0 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 880 | IDAC1_SEL_0001_AIN1 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 881 | IDAC1_SEL_0010_AIN2 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 882 | IDAC1_SEL_0011_AIN3 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 883 | IDAC1_SEL_0100_AIN4 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 884 | IDAC1_SEL_0101_AIN5 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 885 | IDAC1_SEL_0110_AIN6 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 886 | IDAC1_SEL_0111_AIN7 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 887 | IDAC1_SEL_1000_AIN8 = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 888 | IDAC1_SEL_1001_AIN9 = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 889 | IDAC1_SEL_1010_unconnected = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 890 | IDAC1_SEL_1011_unconnected = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 891 | IDAC1_SEL_1100_unconnected = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 892 | IDAC1_SEL_1101_unconnected = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 893 | IDAC1_SEL_1110_unconnected = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 894 | IDAC1_SEL_1111_unconnected = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 895 | } MAX11410_IDAC1_SEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 896 | |
whismanoid | 20:97dccb1c9b61 | 897 | // CODE GENERATOR: TypedefEnum MAX11410_IDAC0_SEL_enum_t |
whismanoid | 20:97dccb1c9b61 | 898 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 899 | /// Input multiplexer channel selection |
whismanoid | 20:97dccb1c9b61 | 900 | /// CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC0_SEL[3:0] |
whismanoid | 20:97dccb1c9b61 | 901 | /// |
whismanoid | 20:97dccb1c9b61 | 902 | /// - 0000: AIN0 |
whismanoid | 20:97dccb1c9b61 | 903 | /// - 0001: AIN1 |
whismanoid | 20:97dccb1c9b61 | 904 | /// - 0010: AIN2 |
whismanoid | 20:97dccb1c9b61 | 905 | /// - 0011: AIN3 |
whismanoid | 20:97dccb1c9b61 | 906 | /// - 0100: AIN4 |
whismanoid | 20:97dccb1c9b61 | 907 | /// - 0101: AIN5 |
whismanoid | 20:97dccb1c9b61 | 908 | /// - 0110: AIN6 |
whismanoid | 20:97dccb1c9b61 | 909 | /// - 0111: AIN7 |
whismanoid | 20:97dccb1c9b61 | 910 | /// - 1000: AIN8 |
whismanoid | 20:97dccb1c9b61 | 911 | /// - 1001: AIN9 |
whismanoid | 20:97dccb1c9b61 | 912 | /// - 1010: Unconnected; IDAC0 powered down. |
whismanoid | 20:97dccb1c9b61 | 913 | /// - 1011: Unconnected; IDAC0 powered down. |
whismanoid | 20:97dccb1c9b61 | 914 | /// - 1100: Unconnected; IDAC0 powered down. |
whismanoid | 20:97dccb1c9b61 | 915 | /// - 1101: Unconnected; IDAC0 powered down. |
whismanoid | 20:97dccb1c9b61 | 916 | /// - 1110: Unconnected; IDAC0 powered down. |
whismanoid | 20:97dccb1c9b61 | 917 | /// - 1111: Unconnected; IDAC0 powered down.(Default) |
whismanoid | 20:97dccb1c9b61 | 918 | typedef enum MAX11410_IDAC0_SEL_enum_t { |
whismanoid | 20:97dccb1c9b61 | 919 | IDAC0_SEL_0000_AIN0 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 920 | IDAC0_SEL_0001_AIN1 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 921 | IDAC0_SEL_0010_AIN2 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 922 | IDAC0_SEL_0011_AIN3 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 923 | IDAC0_SEL_0100_AIN4 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 924 | IDAC0_SEL_0101_AIN5 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 925 | IDAC0_SEL_0110_AIN6 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 926 | IDAC0_SEL_0111_AIN7 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 927 | IDAC0_SEL_1000_AIN8 = 0x08, //!< 8'b00001000 |
whismanoid | 20:97dccb1c9b61 | 928 | IDAC0_SEL_1001_AIN9 = 0x09, //!< 8'b00001001 |
whismanoid | 20:97dccb1c9b61 | 929 | IDAC0_SEL_1010_unconnected = 0x0a, //!< 8'b00001010 |
whismanoid | 20:97dccb1c9b61 | 930 | IDAC0_SEL_1011_unconnected = 0x0b, //!< 8'b00001011 |
whismanoid | 20:97dccb1c9b61 | 931 | IDAC0_SEL_1100_unconnected = 0x0c, //!< 8'b00001100 |
whismanoid | 20:97dccb1c9b61 | 932 | IDAC0_SEL_1101_unconnected = 0x0d, //!< 8'b00001101 |
whismanoid | 20:97dccb1c9b61 | 933 | IDAC0_SEL_1110_unconnected = 0x0e, //!< 8'b00001110 |
whismanoid | 20:97dccb1c9b61 | 934 | IDAC0_SEL_1111_unconnected = 0x0f, //!< 8'b00001111 |
whismanoid | 20:97dccb1c9b61 | 935 | } MAX11410_IDAC0_SEL_enum_t; |
whismanoid | 20:97dccb1c9b61 | 936 | |
whismanoid | 20:97dccb1c9b61 | 937 | // CODE GENERATOR: TypedefEnum MAX11410_SIG_PATH_enum_t |
whismanoid | 20:97dccb1c9b61 | 938 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 939 | /// Input multiplexer channel selection |
whismanoid | 20:97dccb1c9b61 | 940 | /// CMD_r000_1110_xxdd_xddd_PGA field SIG_PATH[1:0] |
whismanoid | 20:97dccb1c9b61 | 941 | /// |
whismanoid | 20:97dccb1c9b61 | 942 | /// - 00: Buffered, low-power, unity-gain path (PGA disabled, digital gain) [default] |
whismanoid | 20:97dccb1c9b61 | 943 | /// - 01: Bypass path (signal buffer disabled,PGA disabled, digital gain) |
whismanoid | 20:97dccb1c9b61 | 944 | /// - 10: PGA path (signal buffer disabled, analog gain) |
whismanoid | 20:97dccb1c9b61 | 945 | /// - 11: Reserved |
whismanoid | 20:97dccb1c9b61 | 946 | typedef enum MAX11410_SIG_PATH_enum_t { |
whismanoid | 20:97dccb1c9b61 | 947 | SIG_PATH_00_BUFFERED = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 948 | SIG_PATH_01_BYPASS = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 949 | SIG_PATH_10_PGA = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 950 | SIG_PATH_11_reserved = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 951 | } MAX11410_SIG_PATH_enum_t; |
whismanoid | 20:97dccb1c9b61 | 952 | |
whismanoid | 20:97dccb1c9b61 | 953 | // CODE GENERATOR: TypedefEnum MAX11410_GAIN_enum_t |
whismanoid | 20:97dccb1c9b61 | 954 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 955 | /// Input multiplexer channel selection |
whismanoid | 20:97dccb1c9b61 | 956 | /// CMD_r000_1110_xxdd_xddd_PGA field GAIN[2:0] |
whismanoid | 20:97dccb1c9b61 | 957 | /// |
whismanoid | 20:97dccb1c9b61 | 958 | /// - 000: 1 (default) |
whismanoid | 20:97dccb1c9b61 | 959 | /// - 001: 2 |
whismanoid | 20:97dccb1c9b61 | 960 | /// - 010: 4 |
whismanoid | 20:97dccb1c9b61 | 961 | /// - 011: 8 |
whismanoid | 20:97dccb1c9b61 | 962 | /// - 100: 16 |
whismanoid | 20:97dccb1c9b61 | 963 | /// - 101: 32 |
whismanoid | 20:97dccb1c9b61 | 964 | /// - 110: 64 |
whismanoid | 20:97dccb1c9b61 | 965 | /// - 111: 128 |
whismanoid | 20:97dccb1c9b61 | 966 | typedef enum MAX11410_GAIN_enum_t { |
whismanoid | 20:97dccb1c9b61 | 967 | GAIN_000_1 = 0x00, //!< 8'b00000000 |
whismanoid | 20:97dccb1c9b61 | 968 | GAIN_001_2 = 0x01, //!< 8'b00000001 |
whismanoid | 20:97dccb1c9b61 | 969 | GAIN_010_4 = 0x02, //!< 8'b00000010 |
whismanoid | 20:97dccb1c9b61 | 970 | GAIN_011_8 = 0x03, //!< 8'b00000011 |
whismanoid | 20:97dccb1c9b61 | 971 | GAIN_100_16 = 0x04, //!< 8'b00000100 |
whismanoid | 20:97dccb1c9b61 | 972 | GAIN_101_32 = 0x05, //!< 8'b00000101 |
whismanoid | 20:97dccb1c9b61 | 973 | GAIN_110_64 = 0x06, //!< 8'b00000110 |
whismanoid | 20:97dccb1c9b61 | 974 | GAIN_111_128 = 0x07, //!< 8'b00000111 |
whismanoid | 20:97dccb1c9b61 | 975 | } MAX11410_GAIN_enum_t; |
whismanoid | 20:97dccb1c9b61 | 976 | |
whismanoid | 20:97dccb1c9b61 | 977 | // TODO1: CODE GENERATOR: ic_variant -- IC's supported with this driver |
whismanoid | 20:97dccb1c9b61 | 978 | /** |
whismanoid | 20:97dccb1c9b61 | 979 | * @brief IC's supported with this driver |
whismanoid | 20:97dccb1c9b61 | 980 | * @details MAX11410 |
whismanoid | 20:97dccb1c9b61 | 981 | */ |
whismanoid | 20:97dccb1c9b61 | 982 | typedef enum |
whismanoid | 20:97dccb1c9b61 | 983 | { |
whismanoid | 20:97dccb1c9b61 | 984 | MAX11410_IC = 0, |
whismanoid | 20:97dccb1c9b61 | 985 | //MAX11410_IC = 1 |
whismanoid | 20:97dccb1c9b61 | 986 | } MAX11410_ic_t; |
whismanoid | 20:97dccb1c9b61 | 987 | |
whismanoid | 20:97dccb1c9b61 | 988 | // TODO1: CODE GENERATOR: class constructor declaration |
whismanoid | 20:97dccb1c9b61 | 989 | /**********************************************************//** |
whismanoid | 20:97dccb1c9b61 | 990 | * @brief Constructor for MAX11410 Class. |
whismanoid | 20:97dccb1c9b61 | 991 | * |
whismanoid | 20:97dccb1c9b61 | 992 | * @details Requires an existing SPI object as well as a DigitalOut object. |
whismanoid | 20:97dccb1c9b61 | 993 | * The DigitalOut object is used for a chip enable signal |
whismanoid | 20:97dccb1c9b61 | 994 | * |
whismanoid | 20:97dccb1c9b61 | 995 | * On Entry: |
whismanoid | 20:97dccb1c9b61 | 996 | * @param[in] spi - pointer to existing SPI object |
whismanoid | 20:97dccb1c9b61 | 997 | * @param[in] cs_pin - pointer to a DigitalOut pin object |
whismanoid | 20:97dccb1c9b61 | 998 | * CODE GENERATOR: class constructor docstrings gpio InputPin pins |
whismanoid | 20:97dccb1c9b61 | 999 | * CODE GENERATOR: class constructor docstrings gpio OutputPin pins |
whismanoid | 20:97dccb1c9b61 | 1000 | * @param[in] ic_variant - which type of MAX11410 is used |
whismanoid | 20:97dccb1c9b61 | 1001 | * |
whismanoid | 20:97dccb1c9b61 | 1002 | * On Exit: |
whismanoid | 20:97dccb1c9b61 | 1003 | * |
whismanoid | 20:97dccb1c9b61 | 1004 | * @return None |
whismanoid | 20:97dccb1c9b61 | 1005 | **************************************************************/ |
whismanoid | 20:97dccb1c9b61 | 1006 | MAX11410(SPI &spi, DigitalOut &cs_pin, // SPI interface |
whismanoid | 20:97dccb1c9b61 | 1007 | // CODE GENERATOR: class constructor declaration gpio InputPin pins |
whismanoid | 20:97dccb1c9b61 | 1008 | // CODE GENERATOR: class constructor declaration gpio OutputPin pins |
whismanoid | 20:97dccb1c9b61 | 1009 | MAX11410_ic_t ic_variant); |
whismanoid | 20:97dccb1c9b61 | 1010 | |
whismanoid | 20:97dccb1c9b61 | 1011 | // CODE GENERATOR: class destructor declaration |
whismanoid | 20:97dccb1c9b61 | 1012 | /************************************************************ |
whismanoid | 20:97dccb1c9b61 | 1013 | * @brief Default destructor for MAX11410 Class. |
whismanoid | 20:97dccb1c9b61 | 1014 | * |
whismanoid | 20:97dccb1c9b61 | 1015 | * @details Destroys SPI object if owner |
whismanoid | 20:97dccb1c9b61 | 1016 | * |
whismanoid | 20:97dccb1c9b61 | 1017 | * On Entry: |
whismanoid | 20:97dccb1c9b61 | 1018 | * |
whismanoid | 20:97dccb1c9b61 | 1019 | * On Exit: |
whismanoid | 20:97dccb1c9b61 | 1020 | * |
whismanoid | 20:97dccb1c9b61 | 1021 | * @return None |
whismanoid | 20:97dccb1c9b61 | 1022 | **************************************************************/ |
whismanoid | 20:97dccb1c9b61 | 1023 | ~MAX11410(); |
whismanoid | 20:97dccb1c9b61 | 1024 | |
whismanoid | 20:97dccb1c9b61 | 1025 | // CODE GENERATOR: spi_frequency setter declaration |
whismanoid | 20:97dccb1c9b61 | 1026 | /// set SPI SCLK frequency |
whismanoid | 20:97dccb1c9b61 | 1027 | void spi_frequency(int spi_sclk_Hz); |
whismanoid | 20:97dccb1c9b61 | 1028 | |
whismanoid | 20:97dccb1c9b61 | 1029 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1030 | // CODE GENERATOR: omit typedef enum MAX11410_device_t, class members instead of global device object |
whismanoid | 20:97dccb1c9b61 | 1031 | public: |
whismanoid | 20:97dccb1c9b61 | 1032 | |
whismanoid | 20:97dccb1c9b61 | 1033 | /// reference voltage, in Volts |
whismanoid | 20:97dccb1c9b61 | 1034 | double VRef; |
whismanoid | 20:97dccb1c9b61 | 1035 | |
whismanoid | 21:498357e216b0 | 1036 | /// shadow of register CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS |
whismanoid | 21:498357e216b0 | 1037 | uint32_t status; |
whismanoid | 21:498357e216b0 | 1038 | |
whismanoid | 21:498357e216b0 | 1039 | /// shadow of register CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0 |
whismanoid | 21:498357e216b0 | 1040 | uint32_t data0; |
whismanoid | 21:498357e216b0 | 1041 | |
whismanoid | 20:97dccb1c9b61 | 1042 | // CODE GENERATOR: omit global g_MAX11410_device |
whismanoid | 20:97dccb1c9b61 | 1043 | |
whismanoid | 20:97dccb1c9b61 | 1044 | // CODE GENERATOR: extern function declarations |
whismanoid | 20:97dccb1c9b61 | 1045 | // CODE GENERATOR: extern function declaration SPIoutputCS |
whismanoid | 20:97dccb1c9b61 | 1046 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1047 | // Assert SPI Chip Select |
whismanoid | 20:97dccb1c9b61 | 1048 | // SPI chip-select for MAX11410 |
whismanoid | 20:97dccb1c9b61 | 1049 | // |
whismanoid | 20:97dccb1c9b61 | 1050 | void SPIoutputCS(int isLogicHigh); |
whismanoid | 20:97dccb1c9b61 | 1051 | |
whismanoid | 20:97dccb1c9b61 | 1052 | // CODE GENERATOR: extern function declaration SPIwrite16bits |
whismanoid | 20:97dccb1c9b61 | 1053 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1054 | // SPI write 16 bits |
whismanoid | 20:97dccb1c9b61 | 1055 | // SPI interface to MAX11410 shift 16 bits mosiData into MAX11410 DIN |
whismanoid | 20:97dccb1c9b61 | 1056 | // |
whismanoid | 20:97dccb1c9b61 | 1057 | void SPIwrite16bits(int16_t mosiData16); |
whismanoid | 20:97dccb1c9b61 | 1058 | |
whismanoid | 20:97dccb1c9b61 | 1059 | // CODE GENERATOR: class member data |
whismanoid | 20:97dccb1c9b61 | 1060 | private: |
whismanoid | 20:97dccb1c9b61 | 1061 | // CODE GENERATOR: class member data for SPI interface |
whismanoid | 20:97dccb1c9b61 | 1062 | // SPI object |
whismanoid | 20:97dccb1c9b61 | 1063 | SPI &m_spi; |
whismanoid | 20:97dccb1c9b61 | 1064 | int m_SPI_SCLK_Hz; |
whismanoid | 20:97dccb1c9b61 | 1065 | int m_SPI_dataMode; |
whismanoid | 20:97dccb1c9b61 | 1066 | int m_SPI_cs_state; |
whismanoid | 20:97dccb1c9b61 | 1067 | |
whismanoid | 20:97dccb1c9b61 | 1068 | // Selector pin object |
whismanoid | 20:97dccb1c9b61 | 1069 | DigitalOut &m_cs_pin; |
whismanoid | 20:97dccb1c9b61 | 1070 | |
whismanoid | 20:97dccb1c9b61 | 1071 | // CODE GENERATOR: class member data for gpio InputPin pins |
whismanoid | 20:97dccb1c9b61 | 1072 | // CODE GENERATOR: class member data for gpio OutputPin pins |
whismanoid | 20:97dccb1c9b61 | 1073 | |
whismanoid | 20:97dccb1c9b61 | 1074 | // Identifies which IC variant is being used |
whismanoid | 20:97dccb1c9b61 | 1075 | MAX11410_ic_t m_ic_variant; |
whismanoid | 20:97dccb1c9b61 | 1076 | |
whismanoid | 20:97dccb1c9b61 | 1077 | public: |
whismanoid | 20:97dccb1c9b61 | 1078 | |
whismanoid | 20:97dccb1c9b61 | 1079 | // CODE GENERATOR: class member function declarations |
whismanoid | 20:97dccb1c9b61 | 1080 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1081 | /// Initialize device |
whismanoid | 20:97dccb1c9b61 | 1082 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1083 | uint8_t Init(void); |
whismanoid | 20:97dccb1c9b61 | 1084 | |
whismanoid | 20:97dccb1c9b61 | 1085 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1086 | /// Return the physical voltage corresponding to DAC register. |
whismanoid | 20:97dccb1c9b61 | 1087 | /// Does not perform any offset or gain correction. |
whismanoid | 20:97dccb1c9b61 | 1088 | /// |
whismanoid | 20:97dccb1c9b61 | 1089 | /// @pre g_MAX11410_device.VRef = Voltage of REF input, in Volts |
whismanoid | 20:97dccb1c9b61 | 1090 | /// @param[in] value_u24: raw 24-bit MAX11410 code (right justified). |
whismanoid | 20:97dccb1c9b61 | 1091 | /// @return physical voltage corresponding to MAX11410 code. |
whismanoid | 20:97dccb1c9b61 | 1092 | double VoltageOfCode(uint16_t value_u24); |
whismanoid | 20:97dccb1c9b61 | 1093 | |
whismanoid | 20:97dccb1c9b61 | 1094 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1095 | /// Write an 8-bit MAX11410 register |
whismanoid | 20:97dccb1c9b61 | 1096 | /// |
whismanoid | 22:3e03687b7e95 | 1097 | /// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0. |
whismanoid | 20:97dccb1c9b61 | 1098 | /// |
whismanoid | 20:97dccb1c9b61 | 1099 | /// SPI 16-bit transfer |
whismanoid | 20:97dccb1c9b61 | 1100 | /// |
whismanoid | 20:97dccb1c9b61 | 1101 | /// SPI MOSI = 0aaa_aaaa_dddd_dddd |
whismanoid | 20:97dccb1c9b61 | 1102 | /// |
whismanoid | 20:97dccb1c9b61 | 1103 | /// SPI MISO = xxxx_xxxx_xxxx_xxxx |
whismanoid | 20:97dccb1c9b61 | 1104 | /// |
whismanoid | 20:97dccb1c9b61 | 1105 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1106 | uint8_t Write_8bit(MAX11410_CMD_enum_t regAddress, uint8_t regData); |
whismanoid | 20:97dccb1c9b61 | 1107 | |
whismanoid | 20:97dccb1c9b61 | 1108 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1109 | /// Read an 8-bit MAX11410 register |
whismanoid | 20:97dccb1c9b61 | 1110 | /// |
whismanoid | 22:3e03687b7e95 | 1111 | /// CMD_1aaa_aaaa_REGISTER_READ bit is set 1. |
whismanoid | 20:97dccb1c9b61 | 1112 | /// |
whismanoid | 20:97dccb1c9b61 | 1113 | /// SPI 16-bit transfer |
whismanoid | 20:97dccb1c9b61 | 1114 | /// |
whismanoid | 20:97dccb1c9b61 | 1115 | /// SPI MOSI = 1aaa_aaaa_0000_0000 |
whismanoid | 20:97dccb1c9b61 | 1116 | /// |
whismanoid | 20:97dccb1c9b61 | 1117 | /// SPI MISO = xxxx_xxxx_dddd_dddd |
whismanoid | 20:97dccb1c9b61 | 1118 | /// |
whismanoid | 20:97dccb1c9b61 | 1119 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1120 | uint8_t Read_8bit(MAX11410_CMD_enum_t regAddress, uint8_t* ptrRegData); |
whismanoid | 20:97dccb1c9b61 | 1121 | |
whismanoid | 20:97dccb1c9b61 | 1122 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1123 | /// Write a 16-bit MAX11410 register |
whismanoid | 20:97dccb1c9b61 | 1124 | /// |
whismanoid | 22:3e03687b7e95 | 1125 | /// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0. |
whismanoid | 20:97dccb1c9b61 | 1126 | /// |
whismanoid | 20:97dccb1c9b61 | 1127 | /// SPI 24-bit transfer |
whismanoid | 20:97dccb1c9b61 | 1128 | /// |
whismanoid | 20:97dccb1c9b61 | 1129 | /// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd |
whismanoid | 20:97dccb1c9b61 | 1130 | /// |
whismanoid | 20:97dccb1c9b61 | 1131 | /// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx |
whismanoid | 20:97dccb1c9b61 | 1132 | /// |
whismanoid | 20:97dccb1c9b61 | 1133 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1134 | uint8_t Write_16bit(MAX11410_CMD_enum_t regAddress, uint16_t regData); |
whismanoid | 20:97dccb1c9b61 | 1135 | |
whismanoid | 20:97dccb1c9b61 | 1136 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1137 | /// Read a 16-bit MAX11410 register |
whismanoid | 20:97dccb1c9b61 | 1138 | /// |
whismanoid | 22:3e03687b7e95 | 1139 | /// CMD_1aaa_aaaa_REGISTER_READ bit is set 1. |
whismanoid | 20:97dccb1c9b61 | 1140 | /// |
whismanoid | 20:97dccb1c9b61 | 1141 | /// SPI 24-bit transfer |
whismanoid | 20:97dccb1c9b61 | 1142 | /// |
whismanoid | 20:97dccb1c9b61 | 1143 | /// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 |
whismanoid | 20:97dccb1c9b61 | 1144 | /// |
whismanoid | 20:97dccb1c9b61 | 1145 | /// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd |
whismanoid | 20:97dccb1c9b61 | 1146 | /// |
whismanoid | 20:97dccb1c9b61 | 1147 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1148 | uint8_t Read_16bit(MAX11410_CMD_enum_t regAddress, uint16_t* ptrRegData); |
whismanoid | 20:97dccb1c9b61 | 1149 | |
whismanoid | 20:97dccb1c9b61 | 1150 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1151 | /// Write a 24-bit MAX11410 register |
whismanoid | 20:97dccb1c9b61 | 1152 | /// |
whismanoid | 22:3e03687b7e95 | 1153 | /// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0. |
whismanoid | 20:97dccb1c9b61 | 1154 | /// |
whismanoid | 20:97dccb1c9b61 | 1155 | /// SPI 32-bit transfer |
whismanoid | 20:97dccb1c9b61 | 1156 | /// |
whismanoid | 20:97dccb1c9b61 | 1157 | /// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd |
whismanoid | 20:97dccb1c9b61 | 1158 | /// |
whismanoid | 20:97dccb1c9b61 | 1159 | /// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx |
whismanoid | 20:97dccb1c9b61 | 1160 | /// |
whismanoid | 20:97dccb1c9b61 | 1161 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1162 | uint8_t Write_24bit(MAX11410_CMD_enum_t regAddress, uint32_t regData); |
whismanoid | 20:97dccb1c9b61 | 1163 | |
whismanoid | 20:97dccb1c9b61 | 1164 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1165 | /// Read a 24-bit MAX11410 register |
whismanoid | 20:97dccb1c9b61 | 1166 | /// |
whismanoid | 22:3e03687b7e95 | 1167 | /// CMD_1aaa_aaaa_REGISTER_READ bit is set 1. |
whismanoid | 20:97dccb1c9b61 | 1168 | /// |
whismanoid | 20:97dccb1c9b61 | 1169 | /// SPI 32-bit transfer |
whismanoid | 20:97dccb1c9b61 | 1170 | /// |
whismanoid | 20:97dccb1c9b61 | 1171 | /// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 |
whismanoid | 20:97dccb1c9b61 | 1172 | /// |
whismanoid | 20:97dccb1c9b61 | 1173 | /// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd |
whismanoid | 20:97dccb1c9b61 | 1174 | /// |
whismanoid | 20:97dccb1c9b61 | 1175 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1176 | uint8_t Read_24bit(MAX11410_CMD_enum_t regAddress, uint32_t* ptrRegData); |
whismanoid | 20:97dccb1c9b61 | 1177 | |
whismanoid | 20:97dccb1c9b61 | 1178 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1179 | /// Configure Measurement for voltage input. |
whismanoid | 20:97dccb1c9b61 | 1180 | /// |
whismanoid | 20:97dccb1c9b61 | 1181 | /// Example code for typical voltage measurement. |
whismanoid | 20:97dccb1c9b61 | 1182 | /// |
whismanoid | 20:97dccb1c9b61 | 1183 | /// SPI register write sequence test AIN0-AGND voltage input using REF2=2.5V |
whismanoid | 20:97dccb1c9b61 | 1184 | /// write8 0x00 PD = 0x03 (Reset Registers; enter Standby mode) |
whismanoid | 20:97dccb1c9b61 | 1185 | /// write8 0x00 PD = 0x00 (NOP) |
whismanoid | 20:97dccb1c9b61 | 1186 | /// write8 0x08 FILTER = 0x34 to select RATE_0100, LINEF_11_SINC4 60SPS (given CONV_TYPE_01_Continuous ) |
whismanoid | 20:97dccb1c9b61 | 1187 | /// write8 0x0B MUX_CTRL0 = 0x0A to select AINP=AIN0 and AINN=GND |
whismanoid | 20:97dccb1c9b61 | 1188 | /// write8 0x09 CTRL = 0x02 to select reference REF2P/REF2N; or CTRL = 0x1A to select reference REF2P/REF2N with reference input buffers enabled; Data Format = Bipolar 2's Complement |
whismanoid | 20:97dccb1c9b61 | 1189 | /// write8 0x0E PGA = 0x00 to select input path = Buffers, digital gain = 1V/V |
whismanoid | 20:97dccb1c9b61 | 1190 | /// write8 0x01 CONV_START = 0x01 to set Conversion Mode = Continuous |
whismanoid | 20:97dccb1c9b61 | 1191 | /// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0) |
whismanoid | 20:97dccb1c9b61 | 1192 | /// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0) |
whismanoid | 20:97dccb1c9b61 | 1193 | /// |
whismanoid | 20:97dccb1c9b61 | 1194 | /// @param[in] channel_hi = channel high side |
whismanoid | 20:97dccb1c9b61 | 1195 | /// @param[in] channel_lo = channel low side |
whismanoid | 20:97dccb1c9b61 | 1196 | /// |
whismanoid | 20:97dccb1c9b61 | 1197 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1198 | uint8_t Configure_Voltage(MAX11410_AINP_SEL_enum_t channel_hi, MAX11410_AINN_SEL_enum_t channel_lo); |
whismanoid | 20:97dccb1c9b61 | 1199 | |
whismanoid | 20:97dccb1c9b61 | 1200 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1201 | /// Trigger Measurement for voltage input. |
whismanoid | 20:97dccb1c9b61 | 1202 | /// |
whismanoid | 20:97dccb1c9b61 | 1203 | /// Example code for typical voltage measurement. |
whismanoid | 20:97dccb1c9b61 | 1204 | /// |
whismanoid | 20:97dccb1c9b61 | 1205 | /// @param[in] channel_hi = channel high side |
whismanoid | 20:97dccb1c9b61 | 1206 | /// @param[in] channel_lo = channel low side |
whismanoid | 20:97dccb1c9b61 | 1207 | /// @post TODO: where does the measurement go? struct member? |
whismanoid | 20:97dccb1c9b61 | 1208 | /// |
whismanoid | 20:97dccb1c9b61 | 1209 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1210 | uint8_t Measure_Voltage(MAX11410_AINP_SEL_enum_t channel_hi, MAX11410_AINN_SEL_enum_t channel_lo); |
whismanoid | 20:97dccb1c9b61 | 1211 | |
whismanoid | 20:97dccb1c9b61 | 1212 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1213 | /// Configure Measurement for Resistive Temperature Device (RTD). |
whismanoid | 20:97dccb1c9b61 | 1214 | /// |
whismanoid | 20:97dccb1c9b61 | 1215 | /// Example code for typical RTD measurement. |
whismanoid | 20:97dccb1c9b61 | 1216 | /// |
whismanoid | 20:97dccb1c9b61 | 1217 | /// @param[in] channel_RTD_Force = channel RTD high side force |
whismanoid | 20:97dccb1c9b61 | 1218 | /// @param[in] channel_RTD_Hi = channel RTD high side sense |
whismanoid | 20:97dccb1c9b61 | 1219 | /// @param[in] channel_RTD_Lo = channel RTD low side |
whismanoid | 20:97dccb1c9b61 | 1220 | /// |
whismanoid | 20:97dccb1c9b61 | 1221 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1222 | uint8_t Configure_RTD(MAX11410_AINP_SEL_enum_t channel_RTD_Force, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINN_SEL_enum_t channel_RTD_Lo); |
whismanoid | 20:97dccb1c9b61 | 1223 | |
whismanoid | 20:97dccb1c9b61 | 1224 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1225 | /// Trigger Measurement for Resistive Temperature Device (RTD). |
whismanoid | 20:97dccb1c9b61 | 1226 | /// |
whismanoid | 20:97dccb1c9b61 | 1227 | /// Example code for typical RTD measurement. |
whismanoid | 20:97dccb1c9b61 | 1228 | /// |
whismanoid | 20:97dccb1c9b61 | 1229 | /// @param[in] channel_RTD_Force = channel RTD high side force |
whismanoid | 20:97dccb1c9b61 | 1230 | /// @param[in] channel_RTD_Hi = channel RTD high side sense |
whismanoid | 20:97dccb1c9b61 | 1231 | /// @param[in] channel_RTD_Lo = channel RTD low side |
whismanoid | 20:97dccb1c9b61 | 1232 | /// @post TODO: where does the measurement go? struct member? |
whismanoid | 20:97dccb1c9b61 | 1233 | /// |
whismanoid | 20:97dccb1c9b61 | 1234 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1235 | uint8_t Measure_RTD(MAX11410_AINP_SEL_enum_t channel_RTD_Force, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINN_SEL_enum_t channel_RTD_Lo); |
whismanoid | 20:97dccb1c9b61 | 1236 | |
whismanoid | 20:97dccb1c9b61 | 1237 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1238 | /// Configure Measurement for Thermocouple |
whismanoid | 20:97dccb1c9b61 | 1239 | /// |
whismanoid | 20:97dccb1c9b61 | 1240 | /// Example code for typical Thermocouple measurement. |
whismanoid | 20:97dccb1c9b61 | 1241 | /// |
whismanoid | 20:97dccb1c9b61 | 1242 | /// @param[in] channel_TC_Hi = channel of Thermocouple high side |
whismanoid | 20:97dccb1c9b61 | 1243 | /// @param[in] channel_TC_Lo = channel of Thermocouple low side |
whismanoid | 20:97dccb1c9b61 | 1244 | /// @param[in] channel_RTD_Hi = channel of cold junction RTD high side |
whismanoid | 20:97dccb1c9b61 | 1245 | /// @param[in] channel_RTD_Lo = channel of cold junction RTD low side |
whismanoid | 20:97dccb1c9b61 | 1246 | /// |
whismanoid | 20:97dccb1c9b61 | 1247 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1248 | uint8_t Configure_Thermocouple(MAX11410_AINP_SEL_enum_t channel_TC_Hi, MAX11410_AINN_SEL_enum_t channel_TC_Lo, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINP_SEL_enum_t channel_RTD_Lo); |
whismanoid | 20:97dccb1c9b61 | 1249 | |
whismanoid | 20:97dccb1c9b61 | 1250 | //---------------------------------------- |
whismanoid | 20:97dccb1c9b61 | 1251 | /// Trigger Measurement for Thermocouple |
whismanoid | 20:97dccb1c9b61 | 1252 | /// |
whismanoid | 20:97dccb1c9b61 | 1253 | /// Example code for typical Thermocouple measurement. |
whismanoid | 20:97dccb1c9b61 | 1254 | /// |
whismanoid | 20:97dccb1c9b61 | 1255 | /// @param[in] channel_TC_Hi = channel of Thermocouple high side |
whismanoid | 20:97dccb1c9b61 | 1256 | /// @param[in] channel_TC_Lo = channel of Thermocouple low side |
whismanoid | 20:97dccb1c9b61 | 1257 | /// @param[in] channel_RTD_Hi = channel of cold junction RTD high side |
whismanoid | 20:97dccb1c9b61 | 1258 | /// @param[in] channel_RTD_Lo = channel of cold junction RTD low side |
whismanoid | 20:97dccb1c9b61 | 1259 | /// @post TODO: where does the measurement go? struct member? |
whismanoid | 20:97dccb1c9b61 | 1260 | /// |
whismanoid | 20:97dccb1c9b61 | 1261 | /// @return 1 on success; 0 on failure |
whismanoid | 20:97dccb1c9b61 | 1262 | uint8_t Measure_Thermocouple(MAX11410_AINP_SEL_enum_t channel_TC_Hi, MAX11410_AINN_SEL_enum_t channel_TC_Lo, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINP_SEL_enum_t channel_RTD_Lo); |
whismanoid | 20:97dccb1c9b61 | 1263 | |
whismanoid | 20:97dccb1c9b61 | 1264 | }; // end of class MAX11410 |
whismanoid | 20:97dccb1c9b61 | 1265 | |
whismanoid | 20:97dccb1c9b61 | 1266 | #endif // __MAX11410_H__ |
whismanoid | 20:97dccb1c9b61 | 1267 | |
whismanoid | 20:97dccb1c9b61 | 1268 | // End of file |