Maxim Integrated / MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents:   MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.cpp@5:6ef046dbe77e, 2019-08-04 (annotated)

Committer:
whismanoid
Date:
Sun Aug 04 01:16:46 2019 -0700
Revision:
5:6ef046dbe77e
Parent:
4:8a0ae95546fa
Child:
6:cb7bdeb185d0
CodeGenerator MAX11131 ifndef guards sorted

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 1:77f1ee332e4a 1 // /*******************************************************************************
whismanoid 1:77f1ee332e4a 2 // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 1:77f1ee332e4a 3 // *
whismanoid 1:77f1ee332e4a 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 1:77f1ee332e4a 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 1:77f1ee332e4a 6 // * to deal in the Software without restriction, including without limitation
whismanoid 1:77f1ee332e4a 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 1:77f1ee332e4a 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 1:77f1ee332e4a 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 1:77f1ee332e4a 10 // *
whismanoid 1:77f1ee332e4a 11 // * The above copyright notice and this permission notice shall be included
whismanoid 1:77f1ee332e4a 12 // * in all copies or substantial portions of the Software.
whismanoid 1:77f1ee332e4a 13 // *
whismanoid 1:77f1ee332e4a 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 1:77f1ee332e4a 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 1:77f1ee332e4a 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 1:77f1ee332e4a 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 1:77f1ee332e4a 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 1:77f1ee332e4a 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 1:77f1ee332e4a 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 1:77f1ee332e4a 21 // *
whismanoid 1:77f1ee332e4a 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 1:77f1ee332e4a 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 1:77f1ee332e4a 24 // * Products, Inc. Branding Policy.
whismanoid 1:77f1ee332e4a 25 // *
whismanoid 1:77f1ee332e4a 26 // * The mere transfer of this software does not imply any licenses
whismanoid 1:77f1ee332e4a 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 1:77f1ee332e4a 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 1:77f1ee332e4a 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 1:77f1ee332e4a 30 // * ownership rights.
whismanoid 1:77f1ee332e4a 31 // *******************************************************************************
whismanoid 1:77f1ee332e4a 32 // */
whismanoid 1:77f1ee332e4a 33 // *********************************************************************
whismanoid 1:77f1ee332e4a 34 // @file MAX11131.cpp
whismanoid 1:77f1ee332e4a 35 // *********************************************************************
whismanoid 1:77f1ee332e4a 36 // Device Driver file
whismanoid 1:77f1ee332e4a 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 1:77f1ee332e4a 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 1:77f1ee332e4a 39 // System Name = ExampleSystem
whismanoid 1:77f1ee332e4a 40 // System Description = Device driver example
whismanoid 1:77f1ee332e4a 41
whismanoid 1:77f1ee332e4a 42 #include "MAX11131.h"
whismanoid 1:77f1ee332e4a 43
whismanoid 1:77f1ee332e4a 44 // Device Name = MAX11131
whismanoid 1:77f1ee332e4a 45 // Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 1:77f1ee332e4a 46 // Device Manufacturer = Maxim Integrated
whismanoid 1:77f1ee332e4a 47 // Device PartNumber = MAX11131ATI+
whismanoid 1:77f1ee332e4a 48 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 1:77f1ee332e4a 49 //
whismanoid 1:77f1ee332e4a 50 // ADC MaxOutputDataRate = 3Msps
whismanoid 1:77f1ee332e4a 51 // ADC NumChannels = 16
whismanoid 1:77f1ee332e4a 52 // ADC ResolutionBits = 12
whismanoid 1:77f1ee332e4a 53 //
whismanoid 1:77f1ee332e4a 54 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 55 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 56 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 57 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 58 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 59 // SPI SCLK Idle High
whismanoid 1:77f1ee332e4a 60 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 61 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 62 //
whismanoid 1:77f1ee332e4a 63 // InputPin Name = CNVST
whismanoid 1:77f1ee332e4a 64 // InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid 1:77f1ee332e4a 65 // InputPin Function = Trigger
whismanoid 1:77f1ee332e4a 66 //
whismanoid 1:77f1ee332e4a 67 // InputPin Name = REF+
whismanoid 1:77f1ee332e4a 68 // InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid 1:77f1ee332e4a 69 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 70 //
whismanoid 1:77f1ee332e4a 71 // InputPin Name = REF-/AIN15
whismanoid 1:77f1ee332e4a 72 // InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid 1:77f1ee332e4a 73 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 74 //
whismanoid 1:77f1ee332e4a 75 // OutputPin Name = EOC
whismanoid 1:77f1ee332e4a 76 // OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid 1:77f1ee332e4a 77 // OutputPin Function = Event
whismanoid 1:77f1ee332e4a 78 //
whismanoid 1:77f1ee332e4a 79 // SupplyPin Name = VDD
whismanoid 1:77f1ee332e4a 80 // SupplyPin Description = Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 81 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 82 // SupplyPin VinMin = 2.35
whismanoid 1:77f1ee332e4a 83 // SupplyPin Function = Analog
whismanoid 1:77f1ee332e4a 84 //
whismanoid 1:77f1ee332e4a 85 // SupplyPin Name = OVDD
whismanoid 1:77f1ee332e4a 86 // SupplyPin Description = Interface Digital Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 87 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 88 // SupplyPin VinMin = 1.5
whismanoid 1:77f1ee332e4a 89 // SupplyPin Function = Digital
whismanoid 1:77f1ee332e4a 90 //
whismanoid 1:77f1ee332e4a 91
whismanoid 1:77f1ee332e4a 92 // CODE GENERATOR: class constructor definition
whismanoid 1:77f1ee332e4a 93 MAX11131::MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 1:77f1ee332e4a 94 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 1:77f1ee332e4a 95 DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid 1:77f1ee332e4a 96 // AnalogOut &REF__pin, // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 97 // AnalogOut &REF__AIN15_pin, // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 98 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 1:77f1ee332e4a 99 DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 100 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 1:77f1ee332e4a 101 MAX11131_ic_t ic_variant)
whismanoid 1:77f1ee332e4a 102 // CODE GENERATOR: class constructor initializer list
whismanoid 1:77f1ee332e4a 103 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 1:77f1ee332e4a 104 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 1:77f1ee332e4a 105 m_CNVST_pin(CNVST_pin), // Digital Trigger Input to MAX11131 device
whismanoid 1:77f1ee332e4a 106 // m_REF__pin(REF__pin), // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 107 // m_REF__AIN15_pin(REF__AIN15_pin), // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 108 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 1:77f1ee332e4a 109 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 110 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 1:77f1ee332e4a 111 m_ic_variant(ic_variant)
whismanoid 1:77f1ee332e4a 112 {
whismanoid 1:77f1ee332e4a 113 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 1:77f1ee332e4a 114 //
whismanoid 1:77f1ee332e4a 115 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 116 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 117 m_SPI_cs_state = 1;
whismanoid 1:77f1ee332e4a 118 m_cs_pin = m_SPI_cs_state;
whismanoid 1:77f1ee332e4a 119
whismanoid 1:77f1ee332e4a 120 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 121 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 122 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 123 // SPI SCLK Idle High
whismanoid 1:77f1ee332e4a 124 m_SPI_dataMode = 3; //SPI_MODE3 // CPOL=1,CPHA=1: Rising Edge stable; SCLK idle High
whismanoid 1:77f1ee332e4a 125 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 1:77f1ee332e4a 126
whismanoid 1:77f1ee332e4a 127 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 128 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 129 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 1:77f1ee332e4a 130 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 1:77f1ee332e4a 131 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 3:621191a7e3fd 132 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 1:77f1ee332e4a 133 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 1:77f1ee332e4a 134 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 1:77f1ee332e4a 135 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 3:621191a7e3fd 136 #if defined(TARGET_MAX32600)
whismanoid 3:621191a7e3fd 137 // MAX11131BOB_Serial_Tester on MAX32600MBED limit SCLK=6MHz
whismanoid 3:621191a7e3fd 138 m_SPI_SCLK_Hz = 6000000; // 6MHz; MAX11131 limit is 48MHz
whismanoid 3:621191a7e3fd 139 #else
whismanoid 3:621191a7e3fd 140 // all other platforms
whismanoid 1:77f1ee332e4a 141 m_SPI_SCLK_Hz = 12000000; // 12MHz; MAX11131 limit is 48MHz
whismanoid 3:621191a7e3fd 142 #endif
whismanoid 1:77f1ee332e4a 143 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 144
whismanoid 1:77f1ee332e4a 145 // TODO1: CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 1:77f1ee332e4a 146 //
whismanoid 1:77f1ee332e4a 147 m_CNVST_pin = 1; // output logic high -- initial value in constructor
whismanoid 1:77f1ee332e4a 148 }
whismanoid 1:77f1ee332e4a 149
whismanoid 1:77f1ee332e4a 150 // CODE GENERATOR: class destructor definition
whismanoid 1:77f1ee332e4a 151 MAX11131::~MAX11131()
whismanoid 1:77f1ee332e4a 152 {
whismanoid 1:77f1ee332e4a 153 // do nothing
whismanoid 1:77f1ee332e4a 154 }
whismanoid 1:77f1ee332e4a 155
whismanoid 1:77f1ee332e4a 156 // CODE GENERATOR: spi_frequency setter definition
whismanoid 5:6ef046dbe77e 157 /// set SPI SCLK frequency
whismanoid 1:77f1ee332e4a 158 void MAX11131::spi_frequency(int spi_sclk_Hz)
whismanoid 1:77f1ee332e4a 159 {
whismanoid 1:77f1ee332e4a 160 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 1:77f1ee332e4a 161 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 162 }
whismanoid 1:77f1ee332e4a 163
whismanoid 1:77f1ee332e4a 164 // CODE GENERATOR: omit global g_MAX11131_device
whismanoid 1:77f1ee332e4a 165 // CODE GENERATOR: extern function declarations
whismanoid 1:77f1ee332e4a 166 // CODE GENERATOR: extern function requirement MAX11131::SPIoutputCS
whismanoid 1:77f1ee332e4a 167 // Assert SPI Chip Select
whismanoid 1:77f1ee332e4a 168 // SPI chip-select for MAX11131
whismanoid 1:77f1ee332e4a 169 //
whismanoid 1:77f1ee332e4a 170 void MAX11131::SPIoutputCS(int isLogicHigh)
whismanoid 1:77f1ee332e4a 171 {
whismanoid 1:77f1ee332e4a 172 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 1:77f1ee332e4a 173 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 1:77f1ee332e4a 174 m_SPI_cs_state = isLogicHigh;
whismanoid 1:77f1ee332e4a 175 m_cs_pin = m_SPI_cs_state;
whismanoid 1:77f1ee332e4a 176 }
whismanoid 1:77f1ee332e4a 177
whismanoid 1:77f1ee332e4a 178 // CODE GENERATOR: extern function requirement MAX11131::SPIwrite16bits
whismanoid 1:77f1ee332e4a 179 // SPI write 16 bits
whismanoid 1:77f1ee332e4a 180 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 181 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 182 //
whismanoid 1:77f1ee332e4a 183 void MAX11131::SPIwrite16bits(int16_t mosiData16)
whismanoid 1:77f1ee332e4a 184 {
whismanoid 1:77f1ee332e4a 185 // CODE GENERATOR: extern function definition for function SPIwrite16bits
whismanoid 1:77f1ee332e4a 186 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite16bits(int16_t mosiData16)
whismanoid 1:77f1ee332e4a 187 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 188 static char mosiData[2];
whismanoid 1:77f1ee332e4a 189 static char misoData[2];
whismanoid 1:77f1ee332e4a 190 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 191 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 192 //
whismanoid 1:77f1ee332e4a 193 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 194 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 195 //
whismanoid 1:77f1ee332e4a 196 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 197 //
whismanoid 1:77f1ee332e4a 198 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 199 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 200 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 201 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 202 //
whismanoid 1:77f1ee332e4a 203 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 204 //
whismanoid 1:77f1ee332e4a 205 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 206 //~ interrupts();
whismanoid 1:77f1ee332e4a 207 //
whismanoid 1:77f1ee332e4a 208 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 209 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 210 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 211 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 212 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 213 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 214 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 215 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 216 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 217 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 218 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 219 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 220 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 221 }
whismanoid 1:77f1ee332e4a 222 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 223 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 224 {
whismanoid 1:77f1ee332e4a 225 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 226 }
whismanoid 1:77f1ee332e4a 227 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 228 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 229 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 230 {
whismanoid 1:77f1ee332e4a 231 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 232 }
whismanoid 1:77f1ee332e4a 233 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 234 #endif
whismanoid 1:77f1ee332e4a 235 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 236 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 237 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 238 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 239 }
whismanoid 1:77f1ee332e4a 240 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 241 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 242 {
whismanoid 1:77f1ee332e4a 243 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 244 }
whismanoid 1:77f1ee332e4a 245 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 246 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 247 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 248 {
whismanoid 1:77f1ee332e4a 249 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 250 }
whismanoid 1:77f1ee332e4a 251 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 252 #endif
whismanoid 1:77f1ee332e4a 253 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 254 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 255 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 256 //
whismanoid 1:77f1ee332e4a 257 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 258 // return misoData16;
whismanoid 1:77f1ee332e4a 259 }
whismanoid 1:77f1ee332e4a 260
whismanoid 1:77f1ee332e4a 261 // CODE GENERATOR: extern function requirement MAX11131::SPIwrite24bits
whismanoid 1:77f1ee332e4a 262 // SPI write 17-24 bits
whismanoid 1:77f1ee332e4a 263 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 264 // followed by one additional SCLK byte.
whismanoid 1:77f1ee332e4a 265 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 266 //
whismanoid 1:77f1ee332e4a 267 void MAX11131::SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 268 {
whismanoid 1:77f1ee332e4a 269 // CODE GENERATOR: extern function definition for function SPIwrite24bits
whismanoid 1:77f1ee332e4a 270 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 271 // TODO: implement SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 272 size_t byteCount = 3;
whismanoid 1:77f1ee332e4a 273 static char mosiData[3];
whismanoid 1:77f1ee332e4a 274 static char misoData[3];
whismanoid 1:77f1ee332e4a 275 mosiData[0] = (char)((mosiData16_FFFF00 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 276 mosiData[1] = (char)((mosiData16_FFFF00 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 277 mosiData[2] = mosiData8_0000FF;
whismanoid 1:77f1ee332e4a 278 //
whismanoid 1:77f1ee332e4a 279 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 280 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 281 //
whismanoid 1:77f1ee332e4a 282 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 283 //
whismanoid 1:77f1ee332e4a 284 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 285 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 286 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 287 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 288 //
whismanoid 1:77f1ee332e4a 289 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 290 //
whismanoid 1:77f1ee332e4a 291 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 292 //~ interrupts();
whismanoid 1:77f1ee332e4a 293 //
whismanoid 1:77f1ee332e4a 294 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 295 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 296 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 297 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 298 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 299 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 300 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 301 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 302 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 303 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 304 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 305 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 306 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 307 }
whismanoid 1:77f1ee332e4a 308 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 309 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 310 {
whismanoid 1:77f1ee332e4a 311 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 312 }
whismanoid 1:77f1ee332e4a 313 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 314 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 315 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 316 {
whismanoid 1:77f1ee332e4a 317 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 318 }
whismanoid 1:77f1ee332e4a 319 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 320 #endif
whismanoid 1:77f1ee332e4a 321 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 322 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 323 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 324 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 325 }
whismanoid 1:77f1ee332e4a 326 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 327 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 328 {
whismanoid 1:77f1ee332e4a 329 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 330 }
whismanoid 1:77f1ee332e4a 331 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 332 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 333 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 334 {
whismanoid 1:77f1ee332e4a 335 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 336 }
whismanoid 1:77f1ee332e4a 337 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 338 #endif
whismanoid 1:77f1ee332e4a 339 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 340 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 341 //
whismanoid 1:77f1ee332e4a 342 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 343 // return misoData16;
whismanoid 1:77f1ee332e4a 344 }
whismanoid 1:77f1ee332e4a 345
whismanoid 1:77f1ee332e4a 346 // CODE GENERATOR: extern function requirement MAX11131::SPIread16bits
whismanoid 1:77f1ee332e4a 347 // SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid 1:77f1ee332e4a 348 // SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid 1:77f1ee332e4a 349 //
whismanoid 1:77f1ee332e4a 350 int16_t MAX11131::SPIread16bits()
whismanoid 1:77f1ee332e4a 351 {
whismanoid 1:77f1ee332e4a 352 // CODE GENERATOR: extern function definition for function SPIread16bits
whismanoid 1:77f1ee332e4a 353 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function int16_t SPIread16bits()
whismanoid 1:77f1ee332e4a 354 int mosiData16 = 0;
whismanoid 1:77f1ee332e4a 355 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 356 static char mosiData[2];
whismanoid 1:77f1ee332e4a 357 static char misoData[2];
whismanoid 1:77f1ee332e4a 358 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 359 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 360 //
whismanoid 1:77f1ee332e4a 361 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 362 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 363 //
whismanoid 1:77f1ee332e4a 364 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 365 //
whismanoid 1:77f1ee332e4a 366 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 367 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 368 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 369 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 370 //
whismanoid 1:77f1ee332e4a 371 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 372 //
whismanoid 1:77f1ee332e4a 373 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 374 //~ interrupts();
whismanoid 1:77f1ee332e4a 375 //
whismanoid 1:77f1ee332e4a 376 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 377 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 378 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 379 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 380 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 381 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 382 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 383 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 384 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 385 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 386 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 387 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 388 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 389 }
whismanoid 1:77f1ee332e4a 390 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 391 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 392 {
whismanoid 1:77f1ee332e4a 393 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 394 }
whismanoid 1:77f1ee332e4a 395 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 396 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 397 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 398 {
whismanoid 1:77f1ee332e4a 399 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 400 }
whismanoid 1:77f1ee332e4a 401 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 402 #endif
whismanoid 1:77f1ee332e4a 403 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 404 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 405 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 406 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 407 }
whismanoid 1:77f1ee332e4a 408 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 409 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 410 {
whismanoid 1:77f1ee332e4a 411 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 412 }
whismanoid 1:77f1ee332e4a 413 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 414 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 415 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 416 {
whismanoid 1:77f1ee332e4a 417 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 418 }
whismanoid 1:77f1ee332e4a 419 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 420 #endif
whismanoid 1:77f1ee332e4a 421 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 422 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 423 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 424 //
whismanoid 1:77f1ee332e4a 425 int misoData16 = (misoData[0] << 8) | misoData[1];
whismanoid 1:77f1ee332e4a 426 return misoData16;
whismanoid 1:77f1ee332e4a 427 }
whismanoid 1:77f1ee332e4a 428
whismanoid 1:77f1ee332e4a 429 // CODE GENERATOR: extern function requirement MAX11131::CNVSToutputPulseLow
whismanoid 1:77f1ee332e4a 430 // Assert MAX11131 CNVST convert start.
whismanoid 1:77f1ee332e4a 431 // Required when using any of the InternalClock modes with SWCNV 0.
whismanoid 1:77f1ee332e4a 432 // Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 433 //
whismanoid 1:77f1ee332e4a 434 void MAX11131::CNVSToutputPulseLow()
whismanoid 1:77f1ee332e4a 435 {
whismanoid 1:77f1ee332e4a 436 // CODE GENERATOR: extern function definition for function CNVSToutputPulseLow
whismanoid 1:77f1ee332e4a 437 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CNVSToutputPulseLow
whismanoid 1:77f1ee332e4a 438 // TODO1: CODE GENERATOR: gpio pin CNVST assuming member function m_CNVST_pin
whismanoid 1:77f1ee332e4a 439 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 1:77f1ee332e4a 440 // m_CNVST_pin.output(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 441 // TODO1: CODE GENERATOR: gpio function PulseLow
whismanoid 1:77f1ee332e4a 442 m_CNVST_pin = 0; // output logic low
whismanoid 1:77f1ee332e4a 443 wait(0.01); // pulse low delay time
whismanoid 1:77f1ee332e4a 444 m_CNVST_pin = 1; // output logic high
whismanoid 1:77f1ee332e4a 445 }
whismanoid 1:77f1ee332e4a 446
whismanoid 1:77f1ee332e4a 447 // CODE GENERATOR: extern function requirement MAX11131::EOCinputWaitUntilLow
whismanoid 1:77f1ee332e4a 448 // Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid 1:77f1ee332e4a 449 // Required when using any of the InternalClock modes.
whismanoid 1:77f1ee332e4a 450 //
whismanoid 1:77f1ee332e4a 451 void MAX11131::EOCinputWaitUntilLow()
whismanoid 1:77f1ee332e4a 452 {
whismanoid 1:77f1ee332e4a 453 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 1:77f1ee332e4a 454 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 1:77f1ee332e4a 455 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 1:77f1ee332e4a 456 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 1:77f1ee332e4a 457 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 458 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 1:77f1ee332e4a 459 while (m_EOC_pin != 0)
whismanoid 1:77f1ee332e4a 460 {
whismanoid 1:77f1ee332e4a 461 // spinlock waiting for logic low pin state
whismanoid 1:77f1ee332e4a 462 }
whismanoid 1:77f1ee332e4a 463 }
whismanoid 1:77f1ee332e4a 464
whismanoid 1:77f1ee332e4a 465 // CODE GENERATOR: extern function requirement MAX11131::EOCinputValue
whismanoid 1:77f1ee332e4a 466 // Return the status of the MAX11131 EOC pin.
whismanoid 1:77f1ee332e4a 467 //
whismanoid 1:77f1ee332e4a 468 int MAX11131::EOCinputValue()
whismanoid 1:77f1ee332e4a 469 {
whismanoid 1:77f1ee332e4a 470 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 1:77f1ee332e4a 471 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 1:77f1ee332e4a 472 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 1:77f1ee332e4a 473 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 1:77f1ee332e4a 474 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 475 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 1:77f1ee332e4a 476 return m_EOC_pin.read();
whismanoid 1:77f1ee332e4a 477 }
whismanoid 1:77f1ee332e4a 478
whismanoid 1:77f1ee332e4a 479 // CODE GENERATOR: class member function definitions
whismanoid 1:77f1ee332e4a 480 //----------------------------------------
whismanoid 1:77f1ee332e4a 481 // Initialize device
whismanoid 1:77f1ee332e4a 482 void MAX11131::Init(void)
whismanoid 1:77f1ee332e4a 483 {
whismanoid 1:77f1ee332e4a 484
whismanoid 1:77f1ee332e4a 485 //----------------------------------------
whismanoid 1:77f1ee332e4a 486 // Nominal Full-Scale Voltage Reference
whismanoid 1:77f1ee332e4a 487 VRef = 2.500;
whismanoid 1:77f1ee332e4a 488
whismanoid 1:77f1ee332e4a 489 //----------------------------------------
whismanoid 1:77f1ee332e4a 490 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 491 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 492 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 493 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 494 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 495 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 496 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 497 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 498
whismanoid 1:77f1ee332e4a 499 //----------------------------------------
whismanoid 1:77f1ee332e4a 500 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 501 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 502 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 503 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 504 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 505 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 506 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 507 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 508
whismanoid 1:77f1ee332e4a 509 //----------------------------------------
whismanoid 1:77f1ee332e4a 510 // define write-only registers UNIPOLAR,BIPOLAR,RANGE
whismanoid 1:77f1ee332e4a 511 UNIPOLAR = 0x8800; //!< mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 512 BIPOLAR = 0x9000; //!< mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid 1:77f1ee332e4a 513 RANGE = 0x9800; //!< mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid 1:77f1ee332e4a 514 const int AIN_0_1_LSB = 10; // UNIPOLAR.UCH0/1 BIPOLAR.BCH0/1 RANGE.RANGE0/1
whismanoid 1:77f1ee332e4a 515 const int AIN_2_3_LSB = 9; // UNIPOLAR.UCH2/3 BIPOLAR.BCH2/3 RANGE.RANGE2/3
whismanoid 1:77f1ee332e4a 516 const int AIN_4_5_LSB = 8; // UNIPOLAR.UCH4/5 BIPOLAR.BCH4/5 RANGE.RANGE4/5
whismanoid 1:77f1ee332e4a 517 const int AIN_6_7_LSB = 7; // UNIPOLAR.UCH6/7 BIPOLAR.BCH6/7 RANGE.RANGE6/7
whismanoid 1:77f1ee332e4a 518 const int AIN_8_9_LSB = 6; // UNIPOLAR.UCH8/9 BIPOLAR.BCH8/9 RANGE.RANGE8/9
whismanoid 1:77f1ee332e4a 519 const int AIN_10_11_LSB = 5; // UNIPOLAR.UCH10/11 BIPOLAR.BCH10/11 RANGE.RANGE10/11
whismanoid 1:77f1ee332e4a 520 const int AIN_12_13_LSB = 4; // UNIPOLAR.UCH12/13 BIPOLAR.BCH12/13 RANGE.RANGE12/13
whismanoid 1:77f1ee332e4a 521 const int AIN_14_15_LSB = 3; // UNIPOLAR.UCH14/15 BIPOLAR.BCH14/15 RANGE.RANGE14/15
whismanoid 1:77f1ee332e4a 522 const int PDIFF_COMM_LSB = 2; const int PDIFF_COMM_BITS = 0x01; // UNIPOLAR.PDIFF_COM
whismanoid 1:77f1ee332e4a 523 // Summary of Table 8:
whismanoid 1:77f1ee332e4a 524 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 525 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 4:8a0ae95546fa 526 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 527 // UCH0/1=1, BCH0/1=1, RANGE0/1=0: reserved do not use
whismanoid 1:77f1ee332e4a 528 // UCH0/1=0, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 529 // UCH0/1=1, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 4:8a0ae95546fa 530 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 531 // UCH0/1=1, BCH0/1=1, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 532 // Both channels of a differential pair must be within Input Voltage Range (dynamic signal range) 0..VREF.
whismanoid 1:77f1ee332e4a 533
whismanoid 1:77f1ee332e4a 534 //----------------------------------------
whismanoid 1:77f1ee332e4a 535 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 536 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 537 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 538 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 539 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 540 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 541 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 542 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 543 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 544 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 545 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 546 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 547 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 548 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 549 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 550 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 551 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 552 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 553 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 554
whismanoid 1:77f1ee332e4a 555 //----------------------------------------
whismanoid 1:77f1ee332e4a 556 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 557 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 558 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 559 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 560 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 561 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 562
whismanoid 1:77f1ee332e4a 563 //----------------------------------------
whismanoid 1:77f1ee332e4a 564 // Reset all registers: ADC_MODE_CONTROL.RESET[1:0] = 2
whismanoid 1:77f1ee332e4a 565 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 566 ADC_MODE_CONTROL |= ((2 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 567
whismanoid 1:77f1ee332e4a 568 //----------------------------------------
whismanoid 1:77f1ee332e4a 569 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 570 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 571 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 572 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 573 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 574 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 575
whismanoid 1:77f1ee332e4a 576 #if REFSEL_0
whismanoid 1:77f1ee332e4a 577
whismanoid 1:77f1ee332e4a 578 //----------------------------------------
whismanoid 1:77f1ee332e4a 579 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=0: external single-ended reference
whismanoid 1:77f1ee332e4a 580 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 581 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL SINGLE-ENDED
whismanoid 1:77f1ee332e4a 582 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 0
whismanoid 1:77f1ee332e4a 583 ADC_CONFIGURATION &= ~ (( REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=0: external single-ended reference. (For the 16-channel chips: channel AIN15 is available.)
whismanoid 1:77f1ee332e4a 584 #endif // REFSEL_0
whismanoid 1:77f1ee332e4a 585
whismanoid 1:77f1ee332e4a 586 #if REFSEL_1
whismanoid 1:77f1ee332e4a 587
whismanoid 1:77f1ee332e4a 588 //----------------------------------------
whismanoid 1:77f1ee332e4a 589 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 590 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 591 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL DIFFERENTIAL
whismanoid 1:77f1ee332e4a 592 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 1
whismanoid 1:77f1ee332e4a 593 ADC_CONFIGURATION |= ((1 & REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=1: external differential reference. (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 594 #endif // REFSEL_1
whismanoid 1:77f1ee332e4a 595
whismanoid 1:77f1ee332e4a 596 #if PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 597
whismanoid 1:77f1ee332e4a 598 //----------------------------------------
whismanoid 1:77f1ee332e4a 599 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 600 UNIPOLAR &= ~ (( PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=0: all single-ended channels use GND as common
whismanoid 1:77f1ee332e4a 601 #endif // PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 602
whismanoid 1:77f1ee332e4a 603 #if PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 604
whismanoid 1:77f1ee332e4a 605 //----------------------------------------
whismanoid 1:77f1ee332e4a 606 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 607 // SELECT UNIPOLAR AND register set BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION
whismanoid 1:77f1ee332e4a 608 UNIPOLAR |= ((1 & PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=1: all single-ended channels are pseudo-differential with REF- as common
whismanoid 1:77f1ee332e4a 609 #endif // PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 610
whismanoid 1:77f1ee332e4a 611 #if AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 612
whismanoid 1:77f1ee332e4a 613 //----------------------------------------
whismanoid 1:77f1ee332e4a 614 // ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 615 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 616 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 617 // AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 618 // AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 619 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 620 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 621 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 622 //
whismanoid 1:77f1ee332e4a 623 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 624 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 625 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 626 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 627 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 628 #endif // AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 629
whismanoid 1:77f1ee332e4a 630 #if AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 631
whismanoid 1:77f1ee332e4a 632 //----------------------------------------
whismanoid 1:77f1ee332e4a 633 // ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid 1:77f1ee332e4a 634 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 635 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 636 // AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 637 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 638 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 639 //
whismanoid 1:77f1ee332e4a 640 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 641 UNIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 642 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 643 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 644 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 645 #endif // AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 646
whismanoid 1:77f1ee332e4a 647 #if AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 648
whismanoid 1:77f1ee332e4a 649 //----------------------------------------
whismanoid 1:77f1ee332e4a 650 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 651 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 652 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 653 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 654 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 655 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 656 //
whismanoid 1:77f1ee332e4a 657 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 658 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 659 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 660 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 661 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 4:8a0ae95546fa 662 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 663 #endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 664
whismanoid 1:77f1ee332e4a 665 #if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 666
whismanoid 1:77f1ee332e4a 667 //----------------------------------------
whismanoid 1:77f1ee332e4a 668 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 669 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 670 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 671 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 672 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 673 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 674 //
whismanoid 1:77f1ee332e4a 675 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 676 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 677 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 678 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 679 RANGE |= (1 << AIN_0_1_LSB);
whismanoid 4:8a0ae95546fa 680 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 681 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 682
whismanoid 1:77f1ee332e4a 683 #if AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 684
whismanoid 1:77f1ee332e4a 685 //----------------------------------------
whismanoid 1:77f1ee332e4a 686 // ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 687 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 688 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 689 // AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 690 // AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 691 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 692 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 693 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 694 //
whismanoid 1:77f1ee332e4a 695 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 696 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 697 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 698 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 699 // UCH2/3=0, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 700 #endif // AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 701
whismanoid 1:77f1ee332e4a 702 #if AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 703
whismanoid 1:77f1ee332e4a 704 //----------------------------------------
whismanoid 1:77f1ee332e4a 705 // ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid 1:77f1ee332e4a 706 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 707 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 708 // AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 709 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 710 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 711 //
whismanoid 1:77f1ee332e4a 712 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 713 UNIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 714 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 715 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 716 // UCH2/3=1, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 717 #endif // AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 718
whismanoid 1:77f1ee332e4a 719 #if AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 720
whismanoid 1:77f1ee332e4a 721 //----------------------------------------
whismanoid 1:77f1ee332e4a 722 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 723 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 724 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 725 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 726 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 727 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 728 //
whismanoid 1:77f1ee332e4a 729 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 730 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 731 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 732 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 733 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 4:8a0ae95546fa 734 // UCH2/3=0, BCH2/3=1, RANGE2/3=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 735 #endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 736
whismanoid 1:77f1ee332e4a 737 #if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 738
whismanoid 1:77f1ee332e4a 739 //----------------------------------------
whismanoid 1:77f1ee332e4a 740 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 741 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 742 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 743 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 744 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 745 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 746 //
whismanoid 1:77f1ee332e4a 747 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 748 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 749 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 750 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 751 RANGE |= (1 << AIN_2_3_LSB);
whismanoid 4:8a0ae95546fa 752 // UCH2/3=0, BCH2/3=1, RANGE2/3=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 753 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 754
whismanoid 1:77f1ee332e4a 755 #if AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 756
whismanoid 1:77f1ee332e4a 757 //----------------------------------------
whismanoid 1:77f1ee332e4a 758 // ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 759 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 760 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 761 // AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 762 // AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 763 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 764 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 765 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 766 //
whismanoid 1:77f1ee332e4a 767 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 768 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 769 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 770 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 771 // UCH4/5=0, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 772 #endif // AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 773
whismanoid 1:77f1ee332e4a 774 #if AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 775
whismanoid 1:77f1ee332e4a 776 //----------------------------------------
whismanoid 1:77f1ee332e4a 777 // ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid 1:77f1ee332e4a 778 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 779 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 780 // AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 781 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 782 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 783 //
whismanoid 1:77f1ee332e4a 784 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 785 UNIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 786 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 787 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 788 // UCH4/5=1, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 789 #endif // AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 790
whismanoid 1:77f1ee332e4a 791 #if AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 792
whismanoid 1:77f1ee332e4a 793 //----------------------------------------
whismanoid 1:77f1ee332e4a 794 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 795 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 796 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 797 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 798 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 799 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 800 //
whismanoid 1:77f1ee332e4a 801 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 802 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 803 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 804 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 805 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 4:8a0ae95546fa 806 // UCH4/5=0, BCH4/5=1, RANGE4/5=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 807 #endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 808
whismanoid 1:77f1ee332e4a 809 #if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 810
whismanoid 1:77f1ee332e4a 811 //----------------------------------------
whismanoid 1:77f1ee332e4a 812 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 813 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 814 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 815 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 816 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 817 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 818 //
whismanoid 1:77f1ee332e4a 819 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 820 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 821 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 822 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 823 RANGE |= (1 << AIN_4_5_LSB);
whismanoid 4:8a0ae95546fa 824 // UCH4/5=0, BCH4/5=1, RANGE4/5=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 825 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 826
whismanoid 1:77f1ee332e4a 827 #if AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 828
whismanoid 1:77f1ee332e4a 829 //----------------------------------------
whismanoid 1:77f1ee332e4a 830 // ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 831 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 832 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 833 // AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 834 // AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 835 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 836 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 837 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 838 //
whismanoid 1:77f1ee332e4a 839 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 840 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 841 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 842 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 843 // UCH6/7=0, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 844 #endif // AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 845
whismanoid 1:77f1ee332e4a 846 #if AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 847
whismanoid 1:77f1ee332e4a 848 //----------------------------------------
whismanoid 1:77f1ee332e4a 849 // ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid 1:77f1ee332e4a 850 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 851 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 852 // AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 853 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 854 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 855 //
whismanoid 1:77f1ee332e4a 856 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 857 UNIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 858 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 859 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 860 // UCH6/7=1, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 861 #endif // AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 862
whismanoid 1:77f1ee332e4a 863 #if AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 864
whismanoid 1:77f1ee332e4a 865 //----------------------------------------
whismanoid 1:77f1ee332e4a 866 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 867 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 868 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 869 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 870 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 871 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 872 //
whismanoid 1:77f1ee332e4a 873 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 874 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 875 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 876 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 877 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 4:8a0ae95546fa 878 // UCH6/7=0, BCH6/7=1, RANGE6/7=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 879 #endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 880
whismanoid 1:77f1ee332e4a 881 #if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 882
whismanoid 1:77f1ee332e4a 883 //----------------------------------------
whismanoid 1:77f1ee332e4a 884 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 885 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 886 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 887 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 888 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 889 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 890 //
whismanoid 1:77f1ee332e4a 891 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 892 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 893 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 894 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 895 RANGE |= (1 << AIN_6_7_LSB);
whismanoid 4:8a0ae95546fa 896 // UCH6/7=0, BCH6/7=1, RANGE6/7=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 897 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 898
whismanoid 1:77f1ee332e4a 899 #if AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 900
whismanoid 1:77f1ee332e4a 901 //----------------------------------------
whismanoid 1:77f1ee332e4a 902 // ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 903 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 904 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 905 // AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 906 // AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 907 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 908 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 909 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 910 //
whismanoid 1:77f1ee332e4a 911 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 912 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 913 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 914 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 915 // UCH8/9=0, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 916 #endif // AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 917
whismanoid 1:77f1ee332e4a 918 #if AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 919
whismanoid 1:77f1ee332e4a 920 //----------------------------------------
whismanoid 1:77f1ee332e4a 921 // ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid 1:77f1ee332e4a 922 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 923 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 924 // AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 925 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 926 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 927 //
whismanoid 1:77f1ee332e4a 928 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 929 UNIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 930 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 931 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 932 // UCH8/9=1, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 933 #endif // AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 934
whismanoid 1:77f1ee332e4a 935 #if AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 936
whismanoid 1:77f1ee332e4a 937 //----------------------------------------
whismanoid 1:77f1ee332e4a 938 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 939 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 940 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 941 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 942 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 943 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 944 //
whismanoid 1:77f1ee332e4a 945 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 946 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 947 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 948 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 949 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 4:8a0ae95546fa 950 // UCH8/9=0, BCH8/9=1, RANGE8/9=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 951 #endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 952
whismanoid 1:77f1ee332e4a 953 #if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 954
whismanoid 1:77f1ee332e4a 955 //----------------------------------------
whismanoid 1:77f1ee332e4a 956 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 957 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 958 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 959 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 960 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 961 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 962 //
whismanoid 1:77f1ee332e4a 963 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 964 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 965 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 966 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 967 RANGE |= (1 << AIN_8_9_LSB);
whismanoid 4:8a0ae95546fa 968 // UCH8/9=0, BCH8/9=1, RANGE8/9=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 969 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 970
whismanoid 1:77f1ee332e4a 971 #if AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 972
whismanoid 1:77f1ee332e4a 973 //----------------------------------------
whismanoid 1:77f1ee332e4a 974 // ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 975 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 976 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 977 // AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 978 // AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 979 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 980 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 981 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 982 //
whismanoid 1:77f1ee332e4a 983 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 984 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 985 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 986 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 987 // UCH10/11=0, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 988 #endif // AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 989
whismanoid 1:77f1ee332e4a 990 #if AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 991
whismanoid 1:77f1ee332e4a 992 //----------------------------------------
whismanoid 1:77f1ee332e4a 993 // ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid 1:77f1ee332e4a 994 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 995 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 996 // AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 997 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 998 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 999 //
whismanoid 1:77f1ee332e4a 1000 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1001 UNIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1002 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1003 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1004 // UCH10/11=1, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1005 #endif // AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1006
whismanoid 1:77f1ee332e4a 1007 #if AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1008
whismanoid 1:77f1ee332e4a 1009 //----------------------------------------
whismanoid 1:77f1ee332e4a 1010 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1011 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1012 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1013 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1014 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1015 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1016 //
whismanoid 1:77f1ee332e4a 1017 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1018 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1019 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1020 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1021 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 4:8a0ae95546fa 1022 // UCH10/11=0, BCH10/11=1, RANGE10/11=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1023 #endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1024
whismanoid 1:77f1ee332e4a 1025 #if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1026
whismanoid 1:77f1ee332e4a 1027 //----------------------------------------
whismanoid 1:77f1ee332e4a 1028 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1029 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1030 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1031 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1032 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1033 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1034 //
whismanoid 1:77f1ee332e4a 1035 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1036 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1037 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1038 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1039 RANGE |= (1 << AIN_10_11_LSB);
whismanoid 4:8a0ae95546fa 1040 // UCH10/11=0, BCH10/11=1, RANGE10/11=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1041 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1042
whismanoid 1:77f1ee332e4a 1043 #if AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1044
whismanoid 1:77f1ee332e4a 1045 //----------------------------------------
whismanoid 1:77f1ee332e4a 1046 // ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1047 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1048 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1049 // AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1050 // AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1051 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1052 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1053 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1054 //
whismanoid 1:77f1ee332e4a 1055 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1056 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1057 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1058 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1059 // UCH12/13=0, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1060 #endif // AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1061
whismanoid 1:77f1ee332e4a 1062 #if AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1063
whismanoid 1:77f1ee332e4a 1064 //----------------------------------------
whismanoid 1:77f1ee332e4a 1065 // ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid 1:77f1ee332e4a 1066 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1067 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1068 // AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1069 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1070 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1071 //
whismanoid 1:77f1ee332e4a 1072 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1073 UNIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1074 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1075 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1076 // UCH12/13=1, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1077 #endif // AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1078
whismanoid 1:77f1ee332e4a 1079 #if AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1080
whismanoid 1:77f1ee332e4a 1081 //----------------------------------------
whismanoid 1:77f1ee332e4a 1082 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1083 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1084 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1085 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1086 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1087 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1088 //
whismanoid 1:77f1ee332e4a 1089 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1090 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1091 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1092 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1093 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 4:8a0ae95546fa 1094 // UCH12/13=0, BCH12/13=1, RANGE12/13=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1095 #endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1096
whismanoid 1:77f1ee332e4a 1097 #if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1098
whismanoid 1:77f1ee332e4a 1099 //----------------------------------------
whismanoid 1:77f1ee332e4a 1100 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1101 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1102 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1103 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1104 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1105 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1106 //
whismanoid 1:77f1ee332e4a 1107 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1108 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1109 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1110 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1111 RANGE |= (1 << AIN_12_13_LSB);
whismanoid 4:8a0ae95546fa 1112 // UCH12/13=0, BCH12/13=1, RANGE12/13=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1113 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1114
whismanoid 1:77f1ee332e4a 1115 #if AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1116
whismanoid 1:77f1ee332e4a 1117 //----------------------------------------
whismanoid 1:77f1ee332e4a 1118 // ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1119 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1120 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1121 // AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1122 // AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1123 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1124 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1125 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1126 //
whismanoid 1:77f1ee332e4a 1127 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1128 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1129 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1130 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1131 // UCH14/15=0, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1132 #endif // AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1133
whismanoid 1:77f1ee332e4a 1134 #if AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1135
whismanoid 1:77f1ee332e4a 1136 //----------------------------------------
whismanoid 1:77f1ee332e4a 1137 // ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid 1:77f1ee332e4a 1138 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1139 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1140 // AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1141 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1142 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1143 //
whismanoid 1:77f1ee332e4a 1144 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1145 UNIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1146 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1147 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1148 // UCH14/15=1, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1149 #endif // AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1150
whismanoid 1:77f1ee332e4a 1151 #if AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1152
whismanoid 1:77f1ee332e4a 1153 //----------------------------------------
whismanoid 1:77f1ee332e4a 1154 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1155 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1156 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1157 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1158 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1159 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1160 //
whismanoid 1:77f1ee332e4a 1161 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1162 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1163 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1164 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1165 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 4:8a0ae95546fa 1166 // UCH14/15=0, BCH14/15=1, RANGE14/15=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1167 #endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1168
whismanoid 1:77f1ee332e4a 1169 #if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1170
whismanoid 1:77f1ee332e4a 1171 //----------------------------------------
whismanoid 1:77f1ee332e4a 1172 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1173 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1174 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1175 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1176 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1177 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1178 //
whismanoid 1:77f1ee332e4a 1179 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1180 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1181 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1182 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1183 RANGE |= (1 << AIN_14_15_LSB);
whismanoid 4:8a0ae95546fa 1184 // UCH14/15=0, BCH14/15=1, RANGE14/15=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1185 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1186
whismanoid 1:77f1ee332e4a 1187 //----------------------------------------
whismanoid 1:77f1ee332e4a 1188 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1189 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1190 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1191 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1192 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1193 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1194
whismanoid 1:77f1ee332e4a 1195 //----------------------------------------
whismanoid 1:77f1ee332e4a 1196 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1197 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1198 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1199 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1200 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1201 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1202 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1203 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1204 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1205 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1206 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1207
whismanoid 1:77f1ee332e4a 1208 //----------------------------------------
whismanoid 1:77f1ee332e4a 1209 // SPI write CSCAN0 CSCAN1 registers
whismanoid 1:77f1ee332e4a 1210 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1211 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1212 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 1213 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1214 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1215 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 1216 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1217 }
whismanoid 1:77f1ee332e4a 1218
whismanoid 1:77f1ee332e4a 1219 //----------------------------------------
whismanoid 1:77f1ee332e4a 1220 // ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1221 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1222 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1223 // AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1224 // AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1225 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1226 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1227 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1228 //
whismanoid 1:77f1ee332e4a 1229 void MAX11131::Reconfigure_SingleEnded(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1230 {
whismanoid 1:77f1ee332e4a 1231
whismanoid 1:77f1ee332e4a 1232 //----------------------------------------
whismanoid 1:77f1ee332e4a 1233 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1234 // AIN(ch)/AIN(ch+1) two independent single-ended inputs,
whismanoid 1:77f1ee332e4a 1235 // unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1236 //
whismanoid 1:77f1ee332e4a 1237 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1238 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1239 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1240 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1241 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1242
whismanoid 1:77f1ee332e4a 1243 //----------------------------------------
whismanoid 1:77f1ee332e4a 1244 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1245 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1246 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1247 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1248 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1249 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1250 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1251 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1252 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1253 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1254 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1255 }
whismanoid 1:77f1ee332e4a 1256
whismanoid 1:77f1ee332e4a 1257 //----------------------------------------
whismanoid 1:77f1ee332e4a 1258 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid 1:77f1ee332e4a 1259 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1260 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1261 // AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1262 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1263 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1264 //
whismanoid 1:77f1ee332e4a 1265 void MAX11131::Reconfigure_DifferentialUnipolar(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1266 {
whismanoid 1:77f1ee332e4a 1267
whismanoid 1:77f1ee332e4a 1268 //----------------------------------------
whismanoid 1:77f1ee332e4a 1269 // UCH(ch)/(ch+1)=1, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1270 // AIN(ch)/AIN(ch+1) differential input pair,
whismanoid 1:77f1ee332e4a 1271 // unipolar code (AIN(ch)>AIN(ch+1)) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1272 //
whismanoid 1:77f1ee332e4a 1273 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1274 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1275 UNIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1276 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1277 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1278 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1279
whismanoid 1:77f1ee332e4a 1280 //----------------------------------------
whismanoid 1:77f1ee332e4a 1281 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1282 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1283 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1284 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1285 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1286 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1287 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1288 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1289 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1290 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1291 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1292 }
whismanoid 1:77f1ee332e4a 1293
whismanoid 1:77f1ee332e4a 1294 //----------------------------------------
whismanoid 1:77f1ee332e4a 1295 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1296 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1297 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1298 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1299 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1300 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1301 //
whismanoid 1:77f1ee332e4a 1302 void MAX11131::Reconfigure_DifferentialBipolarFSVref(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1303 {
whismanoid 1:77f1ee332e4a 1304
whismanoid 1:77f1ee332e4a 1305 //----------------------------------------
whismanoid 1:77f1ee332e4a 1306 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=0:
whismanoid 4:8a0ae95546fa 1307 // AIN(ch)/AIN(ch+1) differential input pair (+/-)(1/2)Vref,
whismanoid 1:77f1ee332e4a 1308 // bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1309 //
whismanoid 1:77f1ee332e4a 1310 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1311 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1312 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1313 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1314 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1315
whismanoid 1:77f1ee332e4a 1316 //----------------------------------------
whismanoid 1:77f1ee332e4a 1317 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1318 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1319 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1320 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1321 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1322 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1323 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1324 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1325 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1326 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1327 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1328 }
whismanoid 1:77f1ee332e4a 1329
whismanoid 1:77f1ee332e4a 1330 //----------------------------------------
whismanoid 1:77f1ee332e4a 1331 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1332 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1333 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1334 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1335 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1336 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1337 //
whismanoid 1:77f1ee332e4a 1338 void MAX11131::Reconfigure_DifferentialBipolarFS2Vref(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1339 {
whismanoid 1:77f1ee332e4a 1340
whismanoid 1:77f1ee332e4a 1341 //----------------------------------------
whismanoid 1:77f1ee332e4a 1342 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=1:
whismanoid 4:8a0ae95546fa 1343 // AIN(ch)/AIN(ch+1) differential input pair (+/-)Vref,
whismanoid 1:77f1ee332e4a 1344 // bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1345 //
whismanoid 1:77f1ee332e4a 1346 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1347 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1348 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1349 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1350 RANGE |= bitmask;
whismanoid 4:8a0ae95546fa 1351 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1352
whismanoid 1:77f1ee332e4a 1353 //----------------------------------------
whismanoid 1:77f1ee332e4a 1354 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1355 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1356 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1357 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1358 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1359 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1360 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1361 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1362 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1363 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1364 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1365 }
whismanoid 1:77f1ee332e4a 1366
whismanoid 1:77f1ee332e4a 1367 //----------------------------------------
whismanoid 1:77f1ee332e4a 1368 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1369 //
whismanoid 1:77f1ee332e4a 1370 // Shift 16 bits out of ADC, without changing configuration.
whismanoid 1:77f1ee332e4a 1371 // Note: @return data format depends on CHAN_ID bit:
whismanoid 1:77f1ee332e4a 1372 // "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid 1:77f1ee332e4a 1373 // "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid 1:77f1ee332e4a 1374 int16_t MAX11131::ScanRead(void)
whismanoid 1:77f1ee332e4a 1375 {
whismanoid 1:77f1ee332e4a 1376
whismanoid 1:77f1ee332e4a 1377 //----------------------------------------
whismanoid 1:77f1ee332e4a 1378 // Read SPI data from device while MOSI (Maxim DIN) is 0. Effectively ADC_MODE_CONTROL SCAN[3:0] = SCAN_0000_NOP = 0
whismanoid 1:77f1ee332e4a 1379 SPI_MOSI_Semantic = 0; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1380 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1381 int16_t misoData16 = SPIread16bits();
whismanoid 1:77f1ee332e4a 1382 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1383 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1384 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1385 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1386 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1387 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1388 return misoData16;
whismanoid 1:77f1ee332e4a 1389 }
whismanoid 0:f7d706d2904d 1390
whismanoid 1:77f1ee332e4a 1391 //----------------------------------------
whismanoid 1:77f1ee332e4a 1392 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1393 //
whismanoid 1:77f1ee332e4a 1394 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 1395 // If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid 1:77f1ee332e4a 1396 //
whismanoid 1:77f1ee332e4a 1397 // @pre one of the Scan functions was called, setting NumWords
whismanoid 1:77f1ee332e4a 1398 // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 1:77f1ee332e4a 1399 // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 1:77f1ee332e4a 1400 //
whismanoid 1:77f1ee332e4a 1401 void MAX11131::ReadAINcode(void)
whismanoid 1:77f1ee332e4a 1402 {
whismanoid 1:77f1ee332e4a 1403
whismanoid 1:77f1ee332e4a 1404 //----------------------------------------
whismanoid 1:77f1ee332e4a 1405 // loop index for RAW_misoData16[SAMPLESET_MAX_ENTRIES];
whismanoid 1:77f1ee332e4a 1406 int index;
whismanoid 1:77f1ee332e4a 1407
whismanoid 1:77f1ee332e4a 1408 //----------------------------------------
whismanoid 1:77f1ee332e4a 1409 // If internal clock mode with SWCNV=0, trigger measurement using CNVST pin and wait for EOC pin.
whismanoid 1:77f1ee332e4a 1410 if (isExternalClock == 0)
whismanoid 1:77f1ee332e4a 1411 {
whismanoid 1:77f1ee332e4a 1412 if (swcnv_0_1 == 0)
whismanoid 1:77f1ee332e4a 1413 {
whismanoid 1:77f1ee332e4a 1414 // SWCNV=0: trigger measurement by driving CNVST/AIN14 pin low
whismanoid 1:77f1ee332e4a 1415 // for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1416 // One CNVST pulse scans all requested channels and stores the results in the FIFO.
whismanoid 1:77f1ee332e4a 1417 CNVSToutputPulseLow();
whismanoid 1:77f1ee332e4a 1418 }
whismanoid 1:77f1ee332e4a 1419 // wait for EOC low (internal clock mode end of conversion)
whismanoid 1:77f1ee332e4a 1420 EOCinputWaitUntilLow();
whismanoid 1:77f1ee332e4a 1421 }
whismanoid 1:77f1ee332e4a 1422
whismanoid 1:77f1ee332e4a 1423 //----------------------------------------
whismanoid 1:77f1ee332e4a 1424 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 1425 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1426 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1427 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1428 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1429 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1430 switch(ScanMode)
whismanoid 1:77f1ee332e4a 1431 {
whismanoid 1:77f1ee332e4a 1432 //----------------------------------------
whismanoid 1:77f1ee332e4a 1433 // read data words
whismanoid 1:77f1ee332e4a 1434 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1435 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1436 case SCAN_0000_NOP:
whismanoid 1:77f1ee332e4a 1437 case SCAN_0011_StandardInternalClock:
whismanoid 1:77f1ee332e4a 1438 case SCAN_0101_UpperInternalClock:
whismanoid 1:77f1ee332e4a 1439 case SCAN_0111_CustomInternalClock:
whismanoid 1:77f1ee332e4a 1440 default:
whismanoid 1:77f1ee332e4a 1441 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1442 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1443 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1444 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1445 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 1446 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 1447 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1448 }
whismanoid 1:77f1ee332e4a 1449 break;
whismanoid 1:77f1ee332e4a 1450 //----------------------------------------
whismanoid 1:77f1ee332e4a 1451 // read data words
whismanoid 1:77f1ee332e4a 1452 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1453 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1454 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1455 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1456 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1457 case SCAN_0001_Manual:
whismanoid 1:77f1ee332e4a 1458 case SCAN_0100_StandardExternalClock:
whismanoid 1:77f1ee332e4a 1459 case SCAN_0110_UpperExternalClock:
whismanoid 1:77f1ee332e4a 1460 case SCAN_1000_CustomExternalClock:
whismanoid 1:77f1ee332e4a 1461 case SCAN_1001_SampleSetExternalClock:
whismanoid 1:77f1ee332e4a 1462 if (chan_id_0_1 != 0) {
whismanoid 1:77f1ee332e4a 1463 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1464 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1465 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1466 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1467 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 1468 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 1469 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1470 }
whismanoid 1:77f1ee332e4a 1471 } else {
whismanoid 1:77f1ee332e4a 1472 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1473 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1474 int16_t value_u12 = ((RAW_misoData16[index] >> 3) & 0x0FFF);
whismanoid 1:77f1ee332e4a 1475 int channelId = channelNumber_0_15;
whismanoid 1:77f1ee332e4a 1476 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1477 }
whismanoid 1:77f1ee332e4a 1478 }
whismanoid 1:77f1ee332e4a 1479 break;
whismanoid 1:77f1ee332e4a 1480 //----------------------------------------
whismanoid 1:77f1ee332e4a 1481 // read data words and calculate mean, stddev
whismanoid 1:77f1ee332e4a 1482 case SCAN_0010_Repeat:
whismanoid 1:77f1ee332e4a 1483 // ScanRead_nWords_chanID_mean(NumWords); // TODO1: missing function
whismanoid 1:77f1ee332e4a 1484 // was this function AINcode_print_value_chanID_mean(int nWords) in main?
whismanoid 1:77f1ee332e4a 1485 // But this function prints to standard output so can't be inside the driver.
whismanoid 1:77f1ee332e4a 1486 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1487 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1488 }
whismanoid 1:77f1ee332e4a 1489 break;
whismanoid 1:77f1ee332e4a 1490 }
whismanoid 1:77f1ee332e4a 1491 }
whismanoid 1:77f1ee332e4a 1492
whismanoid 1:77f1ee332e4a 1493 //----------------------------------------
whismanoid 1:77f1ee332e4a 1494 // Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid 1:77f1ee332e4a 1495 // Supports the bipolar transfer functions.
whismanoid 1:77f1ee332e4a 1496 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 1497 // @return sign-extended 2's complement value.
whismanoid 1:77f1ee332e4a 1498 //
whismanoid 1:77f1ee332e4a 1499 int32_t MAX11131::TwosComplementValue(uint32_t regValue)
whismanoid 1:77f1ee332e4a 1500 {
whismanoid 1:77f1ee332e4a 1501 const uint16_t SIGN_BIT_12BIT = 0x0800;
whismanoid 1:77f1ee332e4a 1502 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 1:77f1ee332e4a 1503 if (((regValue & SIGN_BIT_12BIT) != 0) && !((regValue & (SIGN_BIT_12BIT << 1)) != 0))
whismanoid 1:77f1ee332e4a 1504 {
whismanoid 1:77f1ee332e4a 1505 // (bSignBitNegative && !bExtendedSignBitNegative)
whismanoid 1:77f1ee332e4a 1506 // Twos_Complement negative value
whismanoid 1:77f1ee332e4a 1507 int32_t Offset_regValue = (int32_t)(regValue - (FULL_SCALE_CODE_12BIT + 1));
whismanoid 1:77f1ee332e4a 1508 return Offset_regValue;
whismanoid 1:77f1ee332e4a 1509 }
whismanoid 1:77f1ee332e4a 1510 // Twos_Complement positive value or zero
whismanoid 1:77f1ee332e4a 1511 return (int32_t)regValue;
whismanoid 1:77f1ee332e4a 1512 }
whismanoid 1:77f1ee332e4a 1513
whismanoid 1:77f1ee332e4a 1514 //----------------------------------------
whismanoid 1:77f1ee332e4a 1515 // Return the physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 1516 // Does not perform any offset or gain correction.
whismanoid 1:77f1ee332e4a 1517 // @pre VRef = Voltage of REF input, in Volts
whismanoid 1:77f1ee332e4a 1518 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 1519 // @param[in] channelId: AIN channel number.
whismanoid 1:77f1ee332e4a 1520 // @return physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 1521 //
whismanoid 1:77f1ee332e4a 1522 double MAX11131::VoltageOfCode(int16_t value_u12, int channelId)
whismanoid 1:77f1ee332e4a 1523 {
whismanoid 1:77f1ee332e4a 1524 int channelPairIndex = channelId / 2;
whismanoid 1:77f1ee332e4a 1525 // format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 1526 int UCHn = (UNIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1527 int BCHn = (BIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1528 int RANGEn = (RANGE >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1529 if (UCHn)
whismanoid 1:77f1ee332e4a 1530 {
whismanoid 1:77f1ee332e4a 1531 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1532 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 1533 }
whismanoid 1:77f1ee332e4a 1534 else
whismanoid 1:77f1ee332e4a 1535 {
whismanoid 1:77f1ee332e4a 1536 if (BCHn)
whismanoid 1:77f1ee332e4a 1537 {
whismanoid 1:77f1ee332e4a 1538 if (RANGEn)
whismanoid 1:77f1ee332e4a 1539 {
whismanoid 4:8a0ae95546fa 1540 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1541 return (TwosComplementValue(value_u12) * VRef / 2048);
whismanoid 1:77f1ee332e4a 1542 }
whismanoid 1:77f1ee332e4a 1543 else
whismanoid 1:77f1ee332e4a 1544 {
whismanoid 4:8a0ae95546fa 1545 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1546 return (TwosComplementValue(value_u12) * VRef / 4096);
whismanoid 1:77f1ee332e4a 1547 }
whismanoid 1:77f1ee332e4a 1548 }
whismanoid 1:77f1ee332e4a 1549 else
whismanoid 1:77f1ee332e4a 1550 {
whismanoid 1:77f1ee332e4a 1551 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1552 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 1553 }
whismanoid 1:77f1ee332e4a 1554 }
whismanoid 1:77f1ee332e4a 1555 }
whismanoid 1:77f1ee332e4a 1556
whismanoid 1:77f1ee332e4a 1557 //----------------------------------------
whismanoid 1:77f1ee332e4a 1558 // SCAN_0001_Manual
whismanoid 1:77f1ee332e4a 1559 //
whismanoid 1:77f1ee332e4a 1560 // Measure ADC channel channelNumber_0_15 once.
whismanoid 1:77f1ee332e4a 1561 // External clock mode.
whismanoid 1:77f1ee332e4a 1562 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1563 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1564 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1565 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1566 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 1567 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1568 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1569 //
whismanoid 1:77f1ee332e4a 1570 int MAX11131::ScanManual(void)
whismanoid 1:77f1ee332e4a 1571 {
whismanoid 1:77f1ee332e4a 1572
whismanoid 1:77f1ee332e4a 1573 //----------------------------------------
whismanoid 2:50a0cf017492 1574 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 1575 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 1576 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 1577 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 1578 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 1579 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 1580 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 1581 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 1582
whismanoid 2:50a0cf017492 1583 //----------------------------------------
whismanoid 2:50a0cf017492 1584 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 1585 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 1586 if (needFIFOreset) {
whismanoid 2:50a0cf017492 1587 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 1588 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 1589 // Send SPI configuration to device
whismanoid 2:50a0cf017492 1590 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 1591 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 1592 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 1593 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 1594 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 1595 }
whismanoid 2:50a0cf017492 1596
whismanoid 2:50a0cf017492 1597 //----------------------------------------
whismanoid 1:77f1ee332e4a 1598 // number of words to read
whismanoid 1:77f1ee332e4a 1599 NumWords = 1;
whismanoid 1:77f1ee332e4a 1600
whismanoid 1:77f1ee332e4a 1601 //----------------------------------------
whismanoid 1:77f1ee332e4a 1602 // External Clock Mode
whismanoid 1:77f1ee332e4a 1603 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 1604
whismanoid 1:77f1ee332e4a 1605 //----------------------------------------
whismanoid 1:77f1ee332e4a 1606 // update device driver global variable
whismanoid 1:77f1ee332e4a 1607 ScanMode = SCAN_0001_Manual;
whismanoid 1:77f1ee332e4a 1608
whismanoid 1:77f1ee332e4a 1609 //----------------------------------------
whismanoid 1:77f1ee332e4a 1610 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0001_Manual = 1
whismanoid 1:77f1ee332e4a 1611 //~ const int SCAN_0001_Manual = 1; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1612 ADC_MODE_CONTROL |= ((SCAN_0001_Manual & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1613
whismanoid 1:77f1ee332e4a 1614 //----------------------------------------
whismanoid 1:77f1ee332e4a 1615 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1616 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1617
whismanoid 1:77f1ee332e4a 1618 //----------------------------------------
whismanoid 1:77f1ee332e4a 1619 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1620 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1621
whismanoid 1:77f1ee332e4a 1622 //----------------------------------------
whismanoid 1:77f1ee332e4a 1623 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 1624 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 1625 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1626 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1627 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1628 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1629 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1630 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 1631
whismanoid 1:77f1ee332e4a 1632 //----------------------------------------
whismanoid 1:77f1ee332e4a 1633 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1634 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1635 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1636 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1637 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1638 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1639
whismanoid 1:77f1ee332e4a 1640 //----------------------------------------
whismanoid 1:77f1ee332e4a 1641 // return number of words to read
whismanoid 1:77f1ee332e4a 1642 return NumWords;
whismanoid 1:77f1ee332e4a 1643 }
whismanoid 1:77f1ee332e4a 1644
whismanoid 1:77f1ee332e4a 1645 //----------------------------------------
whismanoid 1:77f1ee332e4a 1646 // SCAN_0010_Repeat
whismanoid 1:77f1ee332e4a 1647 //
whismanoid 1:77f1ee332e4a 1648 // Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid 1:77f1ee332e4a 1649 // Internal clock mode.
whismanoid 1:77f1ee332e4a 1650 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1651 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 1652 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 1653 // @param[in] nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid 1:77f1ee332e4a 1654 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1655 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 1656 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1657 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 1658 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1659 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1660 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1661 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1662 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1663 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1664 //
whismanoid 1:77f1ee332e4a 1665 int MAX11131::ScanRepeat(void)
whismanoid 1:77f1ee332e4a 1666 {
whismanoid 1:77f1ee332e4a 1667
whismanoid 1:77f1ee332e4a 1668 //----------------------------------------
whismanoid 1:77f1ee332e4a 1669 // number of words to read
whismanoid 1:77f1ee332e4a 1670 NumWords = (nscan_4_8_12_16);
whismanoid 1:77f1ee332e4a 1671
whismanoid 1:77f1ee332e4a 1672 //----------------------------------------
whismanoid 1:77f1ee332e4a 1673 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 1674 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 1675
whismanoid 1:77f1ee332e4a 1676 //----------------------------------------
whismanoid 1:77f1ee332e4a 1677 // update device driver global variable
whismanoid 1:77f1ee332e4a 1678 ScanMode = SCAN_0010_Repeat;
whismanoid 1:77f1ee332e4a 1679
whismanoid 1:77f1ee332e4a 1680 //----------------------------------------
whismanoid 1:77f1ee332e4a 1681 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1682 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1683 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1684 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1685 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1686 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1687 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1688 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1689
whismanoid 1:77f1ee332e4a 1690 //----------------------------------------
whismanoid 1:77f1ee332e4a 1691 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 1692 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 1693 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 1694 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 1695 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 1696 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 1697 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 1698 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 1699
whismanoid 1:77f1ee332e4a 1700 //----------------------------------------
whismanoid 1:77f1ee332e4a 1701 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 1702 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1703 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 1704 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 1705 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 1706 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1707 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1708 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1709 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1710 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 1711 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 1712 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1713 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1714 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1715 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 1716 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 1717 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1718 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1719 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1720 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 1721 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 1722 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1723 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1724 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1725 } else {
whismanoid 1:77f1ee332e4a 1726 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1727 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1728 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1729 }
whismanoid 1:77f1ee332e4a 1730
whismanoid 1:77f1ee332e4a 1731 //----------------------------------------
whismanoid 1:77f1ee332e4a 1732 // ADC CONFIGURATION register set NSCAN[1:0] for scan count
whismanoid 1:77f1ee332e4a 1733 // (applicable to SCAN_0010_Repeat only)
whismanoid 1:77f1ee332e4a 1734 if (nscan_4_8_12_16 == 4) {
whismanoid 1:77f1ee332e4a 1735 // Set scan count 4
whismanoid 1:77f1ee332e4a 1736 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1737 ADC_CONFIGURATION |= ((0 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1738 } else if (nscan_4_8_12_16 == 8) {
whismanoid 1:77f1ee332e4a 1739 // Set scan count 8
whismanoid 1:77f1ee332e4a 1740 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1741 ADC_CONFIGURATION |= ((1 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1742 } else if (nscan_4_8_12_16 == 12) {
whismanoid 1:77f1ee332e4a 1743 // Set scan count 12
whismanoid 1:77f1ee332e4a 1744 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1745 ADC_CONFIGURATION |= ((2 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1746 } else if (nscan_4_8_12_16 == 16) {
whismanoid 1:77f1ee332e4a 1747 // Set scan count 16
whismanoid 1:77f1ee332e4a 1748 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1749 ADC_CONFIGURATION |= ((3 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1750 }
whismanoid 1:77f1ee332e4a 1751
whismanoid 1:77f1ee332e4a 1752 //----------------------------------------
whismanoid 1:77f1ee332e4a 1753 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1754 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1755 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1756 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1757 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1758 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1759
whismanoid 1:77f1ee332e4a 1760 //----------------------------------------
whismanoid 1:77f1ee332e4a 1761 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 1762 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1763 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1764
whismanoid 1:77f1ee332e4a 1765 //----------------------------------------
whismanoid 1:77f1ee332e4a 1766 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0010_Repeat = 2
whismanoid 1:77f1ee332e4a 1767 //~ const int SCAN_0010_Repeat = 2; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1768 ADC_MODE_CONTROL |= ((SCAN_0010_Repeat & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1769
whismanoid 1:77f1ee332e4a 1770 //----------------------------------------
whismanoid 1:77f1ee332e4a 1771 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1772 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1773
whismanoid 1:77f1ee332e4a 1774 //----------------------------------------
whismanoid 1:77f1ee332e4a 1775 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1776 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1777
whismanoid 1:77f1ee332e4a 1778 //----------------------------------------
whismanoid 1:77f1ee332e4a 1779 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 1780 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 1781 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1782 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1783 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1784 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1785 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1786 } else {
whismanoid 1:77f1ee332e4a 1787 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1788 }
whismanoid 1:77f1ee332e4a 1789
whismanoid 1:77f1ee332e4a 1790 //----------------------------------------
whismanoid 1:77f1ee332e4a 1791 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1792 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1793 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1794 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1795 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1796 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1797 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1798 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 1799 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 1800 } else {
whismanoid 1:77f1ee332e4a 1801 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1802 }
whismanoid 1:77f1ee332e4a 1803 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1804
whismanoid 1:77f1ee332e4a 1805 //----------------------------------------
whismanoid 1:77f1ee332e4a 1806 // return number of words to read
whismanoid 1:77f1ee332e4a 1807 return NumWords;
whismanoid 1:77f1ee332e4a 1808 }
whismanoid 1:77f1ee332e4a 1809
whismanoid 1:77f1ee332e4a 1810 //----------------------------------------
whismanoid 1:77f1ee332e4a 1811 // SCAN_0011_StandardInternalClock
whismanoid 1:77f1ee332e4a 1812 //
whismanoid 1:77f1ee332e4a 1813 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 1814 // Internal clock mode.
whismanoid 1:77f1ee332e4a 1815 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1816 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 1817 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 1818 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1819 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1820 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 1821 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1822 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 1823 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1824 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1825 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1826 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1827 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1828 //
whismanoid 1:77f1ee332e4a 1829 int MAX11131::ScanStandardInternalClock(void)
whismanoid 1:77f1ee332e4a 1830 {
whismanoid 1:77f1ee332e4a 1831
whismanoid 1:77f1ee332e4a 1832 //----------------------------------------
whismanoid 1:77f1ee332e4a 1833 // number of words to read
whismanoid 1:77f1ee332e4a 1834 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 1835
whismanoid 1:77f1ee332e4a 1836 //----------------------------------------
whismanoid 1:77f1ee332e4a 1837 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 1838 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 1839
whismanoid 1:77f1ee332e4a 1840 //----------------------------------------
whismanoid 1:77f1ee332e4a 1841 // update device driver global variable
whismanoid 1:77f1ee332e4a 1842 ScanMode = SCAN_0011_StandardInternalClock;
whismanoid 1:77f1ee332e4a 1843
whismanoid 1:77f1ee332e4a 1844 //----------------------------------------
whismanoid 1:77f1ee332e4a 1845 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1846 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1847 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1848 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1849 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1850 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1851 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1852 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1853
whismanoid 1:77f1ee332e4a 1854 //----------------------------------------
whismanoid 1:77f1ee332e4a 1855 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 1856 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 1857 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 1858 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 1859 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 1860 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 1861 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 1862 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 1863
whismanoid 1:77f1ee332e4a 1864 //----------------------------------------
whismanoid 1:77f1ee332e4a 1865 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 1866 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1867 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 1868 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 1869 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 1870 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1871 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1872 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1873 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1874 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 1875 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 1876 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1877 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1878 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1879 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 1880 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 1881 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1882 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1883 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1884 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 1885 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 1886 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1887 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1888 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1889 } else {
whismanoid 1:77f1ee332e4a 1890 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1891 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1892 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1893 }
whismanoid 1:77f1ee332e4a 1894
whismanoid 1:77f1ee332e4a 1895 //----------------------------------------
whismanoid 1:77f1ee332e4a 1896 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1897 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1898 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1899 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1900 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1901 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1902
whismanoid 1:77f1ee332e4a 1903 //----------------------------------------
whismanoid 1:77f1ee332e4a 1904 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 1905 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1906 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1907
whismanoid 1:77f1ee332e4a 1908 //----------------------------------------
whismanoid 1:77f1ee332e4a 1909 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0011_StandardInternalClock = 3
whismanoid 1:77f1ee332e4a 1910 //~ const int SCAN_0011_StandardInternalClock = 3; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1911 ADC_MODE_CONTROL |= ((SCAN_0011_StandardInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1912
whismanoid 1:77f1ee332e4a 1913 //----------------------------------------
whismanoid 1:77f1ee332e4a 1914 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1915 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1916
whismanoid 1:77f1ee332e4a 1917 //----------------------------------------
whismanoid 1:77f1ee332e4a 1918 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1919 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1920
whismanoid 1:77f1ee332e4a 1921 //----------------------------------------
whismanoid 1:77f1ee332e4a 1922 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 1923 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 1924 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1925 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1926 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1927 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1928 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1929 } else {
whismanoid 1:77f1ee332e4a 1930 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1931 }
whismanoid 1:77f1ee332e4a 1932
whismanoid 1:77f1ee332e4a 1933 //----------------------------------------
whismanoid 1:77f1ee332e4a 1934 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1935 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1936 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1937 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1938 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1939 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1940 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1941 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 1942 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 1943 } else {
whismanoid 1:77f1ee332e4a 1944 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1945 }
whismanoid 1:77f1ee332e4a 1946 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1947
whismanoid 1:77f1ee332e4a 1948 //----------------------------------------
whismanoid 1:77f1ee332e4a 1949 // return number of words to read
whismanoid 1:77f1ee332e4a 1950 return NumWords;
whismanoid 1:77f1ee332e4a 1951 }
whismanoid 1:77f1ee332e4a 1952
whismanoid 1:77f1ee332e4a 1953 //----------------------------------------
whismanoid 1:77f1ee332e4a 1954 // SCAN_0100_StandardExternalClock
whismanoid 1:77f1ee332e4a 1955 //
whismanoid 1:77f1ee332e4a 1956 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 1957 // External clock mode.
whismanoid 1:77f1ee332e4a 1958 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1959 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1960 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1961 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1962 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 1963 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1964 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1965 //
whismanoid 1:77f1ee332e4a 1966 int MAX11131::ScanStandardExternalClock(void)
whismanoid 1:77f1ee332e4a 1967 {
whismanoid 1:77f1ee332e4a 1968
whismanoid 1:77f1ee332e4a 1969 //----------------------------------------
whismanoid 2:50a0cf017492 1970 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 1971 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 1972 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 1973 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 1974 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 1975 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 1976 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 1977 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 1978
whismanoid 2:50a0cf017492 1979 //----------------------------------------
whismanoid 2:50a0cf017492 1980 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 1981 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 1982 if (needFIFOreset) {
whismanoid 2:50a0cf017492 1983 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 1984 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 1985 // Send SPI configuration to device
whismanoid 2:50a0cf017492 1986 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 1987 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 1988 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 1989 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 1990 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 1991 }
whismanoid 2:50a0cf017492 1992
whismanoid 2:50a0cf017492 1993 //----------------------------------------
whismanoid 1:77f1ee332e4a 1994 // number of words to read
whismanoid 1:77f1ee332e4a 1995 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 1996
whismanoid 1:77f1ee332e4a 1997 //----------------------------------------
whismanoid 1:77f1ee332e4a 1998 // External Clock Mode
whismanoid 1:77f1ee332e4a 1999 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2000
whismanoid 1:77f1ee332e4a 2001 //----------------------------------------
whismanoid 1:77f1ee332e4a 2002 // update device driver global variable
whismanoid 1:77f1ee332e4a 2003 ScanMode = SCAN_0100_StandardExternalClock;
whismanoid 1:77f1ee332e4a 2004
whismanoid 1:77f1ee332e4a 2005 //----------------------------------------
whismanoid 1:77f1ee332e4a 2006 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0100_StandardExternalClock = 4
whismanoid 1:77f1ee332e4a 2007 //~ const int SCAN_0100_StandardExternalClock = 4; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2008 ADC_MODE_CONTROL |= ((SCAN_0100_StandardExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2009
whismanoid 1:77f1ee332e4a 2010 //----------------------------------------
whismanoid 1:77f1ee332e4a 2011 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2012 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2013
whismanoid 1:77f1ee332e4a 2014 //----------------------------------------
whismanoid 1:77f1ee332e4a 2015 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2016 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2017
whismanoid 1:77f1ee332e4a 2018 //----------------------------------------
whismanoid 1:77f1ee332e4a 2019 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2020 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2021 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2022 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2023 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2024 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2025 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2026 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2027
whismanoid 1:77f1ee332e4a 2028 //----------------------------------------
whismanoid 1:77f1ee332e4a 2029 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2030 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2031 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2032 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2033 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2034 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2035
whismanoid 1:77f1ee332e4a 2036 //----------------------------------------
whismanoid 1:77f1ee332e4a 2037 // return number of words to read
whismanoid 1:77f1ee332e4a 2038 return NumWords;
whismanoid 1:77f1ee332e4a 2039 }
whismanoid 1:77f1ee332e4a 2040
whismanoid 1:77f1ee332e4a 2041 //----------------------------------------
whismanoid 1:77f1ee332e4a 2042 // SCAN_0101_UpperInternalClock
whismanoid 1:77f1ee332e4a 2043 //
whismanoid 1:77f1ee332e4a 2044 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2045 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2046 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2047 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2048 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2049 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2050 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2051 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2052 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2053 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2054 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2055 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2056 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2057 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2058 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2059 //
whismanoid 1:77f1ee332e4a 2060 int MAX11131::ScanUpperInternalClock(void)
whismanoid 1:77f1ee332e4a 2061 {
whismanoid 1:77f1ee332e4a 2062
whismanoid 1:77f1ee332e4a 2063 //----------------------------------------
whismanoid 1:77f1ee332e4a 2064 // number of words to read
whismanoid 1:77f1ee332e4a 2065 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2066
whismanoid 1:77f1ee332e4a 2067 //----------------------------------------
whismanoid 1:77f1ee332e4a 2068 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2069 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2070
whismanoid 1:77f1ee332e4a 2071 //----------------------------------------
whismanoid 1:77f1ee332e4a 2072 // update device driver global variable
whismanoid 1:77f1ee332e4a 2073 ScanMode = SCAN_0101_UpperInternalClock;
whismanoid 1:77f1ee332e4a 2074
whismanoid 1:77f1ee332e4a 2075 //----------------------------------------
whismanoid 1:77f1ee332e4a 2076 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2077 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2078 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2079 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2080 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2081 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2082 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2083 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2084
whismanoid 1:77f1ee332e4a 2085 //----------------------------------------
whismanoid 1:77f1ee332e4a 2086 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2087 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2088 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2089 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2090 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2091 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2092 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2093 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2094
whismanoid 1:77f1ee332e4a 2095 //----------------------------------------
whismanoid 1:77f1ee332e4a 2096 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2097 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2098 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2099 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2100 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2101 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2102 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2103 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2104 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2105 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2106 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2107 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2108 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2109 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2110 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2111 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2112 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2113 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2114 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2115 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2116 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2117 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2118 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2119 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2120 } else {
whismanoid 1:77f1ee332e4a 2121 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2122 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2123 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2124 }
whismanoid 1:77f1ee332e4a 2125
whismanoid 1:77f1ee332e4a 2126 //----------------------------------------
whismanoid 1:77f1ee332e4a 2127 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2128 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2129 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2130 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2131 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2132 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2133
whismanoid 1:77f1ee332e4a 2134 //----------------------------------------
whismanoid 1:77f1ee332e4a 2135 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2136 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2137 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2138
whismanoid 1:77f1ee332e4a 2139 //----------------------------------------
whismanoid 1:77f1ee332e4a 2140 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0101_UpperInternalClock = 5
whismanoid 1:77f1ee332e4a 2141 //~ const int SCAN_0101_UpperInternalClock = 5; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2142 ADC_MODE_CONTROL |= ((SCAN_0101_UpperInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2143
whismanoid 1:77f1ee332e4a 2144 //----------------------------------------
whismanoid 1:77f1ee332e4a 2145 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2146 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2147
whismanoid 1:77f1ee332e4a 2148 //----------------------------------------
whismanoid 1:77f1ee332e4a 2149 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2150 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2151
whismanoid 1:77f1ee332e4a 2152 //----------------------------------------
whismanoid 1:77f1ee332e4a 2153 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2154 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2155 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2156 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2157 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2158 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2159 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2160 } else {
whismanoid 1:77f1ee332e4a 2161 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2162 }
whismanoid 1:77f1ee332e4a 2163
whismanoid 1:77f1ee332e4a 2164 //----------------------------------------
whismanoid 1:77f1ee332e4a 2165 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2166 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2167 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2168 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2169 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2170 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2171 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2172 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2173 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2174 } else {
whismanoid 1:77f1ee332e4a 2175 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2176 }
whismanoid 1:77f1ee332e4a 2177 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2178
whismanoid 1:77f1ee332e4a 2179 //----------------------------------------
whismanoid 1:77f1ee332e4a 2180 // return number of words to read
whismanoid 1:77f1ee332e4a 2181 return NumWords;
whismanoid 1:77f1ee332e4a 2182 }
whismanoid 1:77f1ee332e4a 2183
whismanoid 1:77f1ee332e4a 2184 //----------------------------------------
whismanoid 1:77f1ee332e4a 2185 // SCAN_0110_UpperExternalClock
whismanoid 1:77f1ee332e4a 2186 //
whismanoid 1:77f1ee332e4a 2187 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2188 // External clock mode.
whismanoid 1:77f1ee332e4a 2189 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2190 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2191 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2192 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2193 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2194 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2195 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2196 //
whismanoid 1:77f1ee332e4a 2197 int MAX11131::ScanUpperExternalClock(void)
whismanoid 1:77f1ee332e4a 2198 {
whismanoid 1:77f1ee332e4a 2199
whismanoid 1:77f1ee332e4a 2200 //----------------------------------------
whismanoid 2:50a0cf017492 2201 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2202 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2203 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2204 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2205 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2206 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2207 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2208 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2209
whismanoid 2:50a0cf017492 2210 //----------------------------------------
whismanoid 2:50a0cf017492 2211 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2212 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2213 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2214 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2215 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2216 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2217 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2218 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2219 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2220 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2221 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2222 }
whismanoid 2:50a0cf017492 2223
whismanoid 2:50a0cf017492 2224 //----------------------------------------
whismanoid 1:77f1ee332e4a 2225 // number of words to read
whismanoid 1:77f1ee332e4a 2226 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2227
whismanoid 1:77f1ee332e4a 2228 //----------------------------------------
whismanoid 1:77f1ee332e4a 2229 // External Clock Mode
whismanoid 1:77f1ee332e4a 2230 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2231
whismanoid 1:77f1ee332e4a 2232 //----------------------------------------
whismanoid 1:77f1ee332e4a 2233 // update device driver global variable
whismanoid 1:77f1ee332e4a 2234 ScanMode = SCAN_0110_UpperExternalClock;
whismanoid 1:77f1ee332e4a 2235
whismanoid 1:77f1ee332e4a 2236 //----------------------------------------
whismanoid 1:77f1ee332e4a 2237 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0110_UpperExternalClock = 6
whismanoid 1:77f1ee332e4a 2238 //~ const int SCAN_0110_UpperExternalClock = 6; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2239 ADC_MODE_CONTROL |= ((SCAN_0110_UpperExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2240
whismanoid 1:77f1ee332e4a 2241 //----------------------------------------
whismanoid 1:77f1ee332e4a 2242 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2243 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2244
whismanoid 1:77f1ee332e4a 2245 //----------------------------------------
whismanoid 1:77f1ee332e4a 2246 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2247 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2248
whismanoid 1:77f1ee332e4a 2249 //----------------------------------------
whismanoid 1:77f1ee332e4a 2250 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2251 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2252 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2253 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2254 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2255 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2256 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2257 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2258
whismanoid 1:77f1ee332e4a 2259 //----------------------------------------
whismanoid 1:77f1ee332e4a 2260 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2261 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2262 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2263 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2264 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2265 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2266
whismanoid 1:77f1ee332e4a 2267 //----------------------------------------
whismanoid 1:77f1ee332e4a 2268 // return number of words to read
whismanoid 1:77f1ee332e4a 2269 return NumWords;
whismanoid 1:77f1ee332e4a 2270 }
whismanoid 1:77f1ee332e4a 2271
whismanoid 1:77f1ee332e4a 2272 //----------------------------------------
whismanoid 1:77f1ee332e4a 2273 // SCAN_0111_CustomInternalClock
whismanoid 1:77f1ee332e4a 2274 //
whismanoid 1:77f1ee332e4a 2275 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2276 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2277 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2278 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2279 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2280 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2281 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2282 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2283 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2284 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2285 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2286 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2287 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2288 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2289 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2290 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2291 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2292 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2293 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2294 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2295 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2296 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2297 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2298 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2299 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2300 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2301 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2302 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2303 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2304 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2305 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2306 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2307 //
whismanoid 1:77f1ee332e4a 2308 int MAX11131::ScanCustomInternalClock(void)
whismanoid 1:77f1ee332e4a 2309 {
whismanoid 1:77f1ee332e4a 2310
whismanoid 1:77f1ee332e4a 2311 //----------------------------------------
whismanoid 1:77f1ee332e4a 2312 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2313 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2314 int nWords = 0;
whismanoid 1:77f1ee332e4a 2315 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2316 {
whismanoid 1:77f1ee332e4a 2317 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2318 {
whismanoid 1:77f1ee332e4a 2319 nWords++;
whismanoid 1:77f1ee332e4a 2320 }
whismanoid 1:77f1ee332e4a 2321 }
whismanoid 1:77f1ee332e4a 2322
whismanoid 1:77f1ee332e4a 2323 //----------------------------------------
whismanoid 1:77f1ee332e4a 2324 // number of words to read
whismanoid 1:77f1ee332e4a 2325 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2326
whismanoid 1:77f1ee332e4a 2327 //----------------------------------------
whismanoid 1:77f1ee332e4a 2328 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2329 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2330
whismanoid 1:77f1ee332e4a 2331 //----------------------------------------
whismanoid 1:77f1ee332e4a 2332 // update device driver global variable
whismanoid 1:77f1ee332e4a 2333 ScanMode = SCAN_0111_CustomInternalClock;
whismanoid 1:77f1ee332e4a 2334
whismanoid 1:77f1ee332e4a 2335 //----------------------------------------
whismanoid 1:77f1ee332e4a 2336 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2337 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2338 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2339 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2340 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2341 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2342 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2343 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2344
whismanoid 1:77f1ee332e4a 2345 //----------------------------------------
whismanoid 1:77f1ee332e4a 2346 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2347 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2348 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2349 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2350 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2351 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2352 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2353 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2354
whismanoid 1:77f1ee332e4a 2355 //----------------------------------------
whismanoid 1:77f1ee332e4a 2356 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2357 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2358 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2359 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2360 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2361 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2362 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2363 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2364 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2365 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2366 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2367 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2368 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2369 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 2370 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 2371 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 2372 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 2373 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 2374 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 2375
whismanoid 1:77f1ee332e4a 2376 //----------------------------------------
whismanoid 1:77f1ee332e4a 2377 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2378 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2379 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2380 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2381 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2382 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2383 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2384 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2385 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2386 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2387 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2388 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2389 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2390 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2391 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2392 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2393 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2394 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2395 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2396 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2397 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2398 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2399 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2400 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2401 } else {
whismanoid 1:77f1ee332e4a 2402 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2403 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2404 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2405 }
whismanoid 1:77f1ee332e4a 2406
whismanoid 1:77f1ee332e4a 2407 //----------------------------------------
whismanoid 1:77f1ee332e4a 2408 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2409 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2410 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2411 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2412 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2413 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2414
whismanoid 1:77f1ee332e4a 2415 //----------------------------------------
whismanoid 1:77f1ee332e4a 2416 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 2417 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 2418 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 2419 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2420 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2421 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 2422 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2423 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2424 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 2425 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2426
whismanoid 1:77f1ee332e4a 2427 //----------------------------------------
whismanoid 1:77f1ee332e4a 2428 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2429 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2430 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2431
whismanoid 1:77f1ee332e4a 2432 //----------------------------------------
whismanoid 1:77f1ee332e4a 2433 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0111_CustomInternalClock = 7
whismanoid 1:77f1ee332e4a 2434 //~ const int SCAN_0111_CustomInternalClock = 7; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2435 ADC_MODE_CONTROL |= ((SCAN_0111_CustomInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2436
whismanoid 1:77f1ee332e4a 2437 //----------------------------------------
whismanoid 1:77f1ee332e4a 2438 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2439 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2440
whismanoid 1:77f1ee332e4a 2441 //----------------------------------------
whismanoid 1:77f1ee332e4a 2442 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2443 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2444 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2445 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2446 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2447 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2448 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2449 } else {
whismanoid 1:77f1ee332e4a 2450 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2451 }
whismanoid 1:77f1ee332e4a 2452
whismanoid 1:77f1ee332e4a 2453 //----------------------------------------
whismanoid 1:77f1ee332e4a 2454 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2455 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2456 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2457 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2458 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2459 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2460 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2461 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2462 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2463 } else {
whismanoid 1:77f1ee332e4a 2464 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2465 }
whismanoid 1:77f1ee332e4a 2466 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2467
whismanoid 1:77f1ee332e4a 2468 //----------------------------------------
whismanoid 1:77f1ee332e4a 2469 // return number of words to read
whismanoid 1:77f1ee332e4a 2470 return NumWords;
whismanoid 1:77f1ee332e4a 2471 }
whismanoid 1:77f1ee332e4a 2472
whismanoid 1:77f1ee332e4a 2473 //----------------------------------------
whismanoid 1:77f1ee332e4a 2474 // SCAN_1000_CustomExternalClock
whismanoid 1:77f1ee332e4a 2475 //
whismanoid 1:77f1ee332e4a 2476 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2477 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2478 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2479 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2480 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2481 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2482 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2483 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2484 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2485 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2486 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2487 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2488 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2489 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2490 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2491 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2492 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2493 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2494 // External clock mode.
whismanoid 1:77f1ee332e4a 2495 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2496 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2497 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2498 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2499 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2500 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2501 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2502 //
whismanoid 1:77f1ee332e4a 2503 int MAX11131::ScanCustomExternalClock(void)
whismanoid 1:77f1ee332e4a 2504 {
whismanoid 1:77f1ee332e4a 2505
whismanoid 1:77f1ee332e4a 2506 //----------------------------------------
whismanoid 1:77f1ee332e4a 2507 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2508 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2509 int nWords = 0;
whismanoid 1:77f1ee332e4a 2510 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2511 {
whismanoid 1:77f1ee332e4a 2512 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2513 {
whismanoid 1:77f1ee332e4a 2514 nWords++;
whismanoid 1:77f1ee332e4a 2515 }
whismanoid 1:77f1ee332e4a 2516 }
whismanoid 1:77f1ee332e4a 2517
whismanoid 1:77f1ee332e4a 2518 //----------------------------------------
whismanoid 2:50a0cf017492 2519 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2520 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2521 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2522 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2523 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2524 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2525 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2526 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2527
whismanoid 2:50a0cf017492 2528 //----------------------------------------
whismanoid 2:50a0cf017492 2529 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2530 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2531 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2532 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2533 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2534 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2535 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2536 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2537 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2538 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2539 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2540 }
whismanoid 2:50a0cf017492 2541
whismanoid 2:50a0cf017492 2542 //----------------------------------------
whismanoid 1:77f1ee332e4a 2543 // number of words to read
whismanoid 1:77f1ee332e4a 2544 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2545
whismanoid 1:77f1ee332e4a 2546 //----------------------------------------
whismanoid 1:77f1ee332e4a 2547 // External Clock Mode
whismanoid 1:77f1ee332e4a 2548 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2549
whismanoid 1:77f1ee332e4a 2550 //----------------------------------------
whismanoid 1:77f1ee332e4a 2551 // update device driver global variable
whismanoid 1:77f1ee332e4a 2552 ScanMode = SCAN_1000_CustomExternalClock;
whismanoid 1:77f1ee332e4a 2553
whismanoid 1:77f1ee332e4a 2554 //----------------------------------------
whismanoid 1:77f1ee332e4a 2555 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2556 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2557 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2558 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2559 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2560 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2561 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2562 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2563 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2564 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2565 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2566 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2567 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2568 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 2569 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 2570 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 2571 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 2572 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 2573 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 2574
whismanoid 1:77f1ee332e4a 2575 //----------------------------------------
whismanoid 1:77f1ee332e4a 2576 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 2577 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 2578 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 2579 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2580 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2581 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 2582 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2583 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2584 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 2585 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2586
whismanoid 1:77f1ee332e4a 2587 //----------------------------------------
whismanoid 1:77f1ee332e4a 2588 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1000_CustomExternalClock = 8
whismanoid 1:77f1ee332e4a 2589 //~ const int SCAN_1000_CustomExternalClock = 8; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2590 ADC_MODE_CONTROL |= ((SCAN_1000_CustomExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2591
whismanoid 1:77f1ee332e4a 2592 //----------------------------------------
whismanoid 1:77f1ee332e4a 2593 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2594 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2595
whismanoid 1:77f1ee332e4a 2596 //----------------------------------------
whismanoid 1:77f1ee332e4a 2597 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2598 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2599 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2600 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2601 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2602 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2603 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2604 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2605
whismanoid 1:77f1ee332e4a 2606 //----------------------------------------
whismanoid 1:77f1ee332e4a 2607 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2608 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2609 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2610 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2611 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2612 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2613
whismanoid 1:77f1ee332e4a 2614 //----------------------------------------
whismanoid 1:77f1ee332e4a 2615 // return number of words to read
whismanoid 1:77f1ee332e4a 2616 return NumWords;
whismanoid 1:77f1ee332e4a 2617 }
whismanoid 1:77f1ee332e4a 2618
whismanoid 1:77f1ee332e4a 2619 //----------------------------------------
whismanoid 1:77f1ee332e4a 2620 // SCAN_1001_SampleSetExternalClock
whismanoid 1:77f1ee332e4a 2621 //
whismanoid 1:77f1ee332e4a 2622 // Measure ADC channels in an arbitrary pattern.
whismanoid 1:77f1ee332e4a 2623 // Channels can be visited in any order, with repetition allowed.
whismanoid 1:77f1ee332e4a 2624 // External clock mode.
whismanoid 1:77f1ee332e4a 2625 // @pre enabledChannelsPatternLength_1_256: number of channel selections
whismanoid 1:77f1ee332e4a 2626 // @pre enabledChannelsPattern: array containing channel selection pattern
whismanoid 1:77f1ee332e4a 2627 // In the array, one channel select per byte.
whismanoid 1:77f1ee332e4a 2628 // In the SPI interface, immediately after SAMPLESET register is written,
whismanoid 1:77f1ee332e4a 2629 // each byte encodes two channelNumber selections.
whismanoid 1:77f1ee332e4a 2630 // The high 4 bits encode the first channelNumber.
whismanoid 1:77f1ee332e4a 2631 // (((enabledChannelsPattern[0]) & 0x0F) << 4) | ((enabledChannelsPattern[1]) & 0x0F)
whismanoid 1:77f1ee332e4a 2632 // If it is an odd number of channels, additional nybbles will be ignored.
whismanoid 1:77f1ee332e4a 2633 // CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid 1:77f1ee332e4a 2634 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2635 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2636 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2637 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2638 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2639 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2640 //
whismanoid 1:77f1ee332e4a 2641 int MAX11131::ScanSampleSetExternalClock(void)
whismanoid 1:77f1ee332e4a 2642 {
whismanoid 1:77f1ee332e4a 2643
whismanoid 1:77f1ee332e4a 2644 //----------------------------------------
whismanoid 2:50a0cf017492 2645 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2646 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2647 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2648 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2649 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2650 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2651 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2652 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2653
whismanoid 2:50a0cf017492 2654 //----------------------------------------
whismanoid 2:50a0cf017492 2655 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2656 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2657 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2658 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2659 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2660 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2661 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2662 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2663 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2664 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2665 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2666 }
whismanoid 2:50a0cf017492 2667
whismanoid 2:50a0cf017492 2668 //----------------------------------------
whismanoid 1:77f1ee332e4a 2669 // number of words to read
whismanoid 1:77f1ee332e4a 2670 NumWords = ((enabledChannelsPatternLength_1_256 != 0) ? enabledChannelsPatternLength_1_256 : 256 );
whismanoid 1:77f1ee332e4a 2671
whismanoid 1:77f1ee332e4a 2672 //----------------------------------------
whismanoid 1:77f1ee332e4a 2673 // External Clock Mode
whismanoid 1:77f1ee332e4a 2674 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2675
whismanoid 1:77f1ee332e4a 2676 //----------------------------------------
whismanoid 1:77f1ee332e4a 2677 // update device driver global variable
whismanoid 1:77f1ee332e4a 2678 ScanMode = SCAN_1001_SampleSetExternalClock;
whismanoid 1:77f1ee332e4a 2679
whismanoid 1:77f1ee332e4a 2680 //----------------------------------------
whismanoid 1:77f1ee332e4a 2681 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 2682 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 2683 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 2684 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 2685 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 2686 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 2687
whismanoid 1:77f1ee332e4a 2688 //----------------------------------------
whismanoid 1:77f1ee332e4a 2689 // SampleSet register set SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH; FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH
whismanoid 1:77f1ee332e4a 2690 // NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid 1:77f1ee332e4a 2691 // NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid 1:77f1ee332e4a 2692 // NOTE: Channels can be repeated in any arbitrary order.
whismanoid 1:77f1ee332e4a 2693 // NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid 1:77f1ee332e4a 2694 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 2695 const int seq_length_minus_one_0_255 = enabledChannelsPatternLength_1_256 - 1;
whismanoid 1:77f1ee332e4a 2696 SAMPLESET = 0xB000;
whismanoid 1:77f1ee332e4a 2697 //SAMPLESET &= ~ (( SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 2698 SAMPLESET |= ((seq_length_minus_one_0_255 & SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 2699 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2700 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2701 SPIwrite16bits(SAMPLESET); // SAMPLESET must be followed by several more bytes, length specified by SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 2702 // pack enabledChannelsPattern[index] into nybbles
whismanoid 1:77f1ee332e4a 2703 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2704 // NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid 1:77f1ee332e4a 2705 SPI_MOSI_Semantic = 2; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2706 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2707 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 2708 int entryIndex;
whismanoid 1:77f1ee332e4a 2709 for (entryIndex = 0; entryIndex < enabledChannelsPatternLength_1_256; entryIndex += 4)
whismanoid 1:77f1ee332e4a 2710 {
whismanoid 1:77f1ee332e4a 2711 uint16_t pack4channels = 0;
whismanoid 1:77f1ee332e4a 2712 pack4channels |= (((enabledChannelsPattern[entryIndex + 0]) & 0x0F) << 12);
whismanoid 1:77f1ee332e4a 2713 if ((entryIndex + 1) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 2714 pack4channels |= (((enabledChannelsPattern[entryIndex + 1]) & 0x0F) << 8);
whismanoid 1:77f1ee332e4a 2715 }
whismanoid 1:77f1ee332e4a 2716 if ((entryIndex + 2) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 2717 pack4channels |= (((enabledChannelsPattern[entryIndex + 2]) & 0x0F) << 4);
whismanoid 1:77f1ee332e4a 2718 }
whismanoid 1:77f1ee332e4a 2719 if ((entryIndex + 3) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 2720 pack4channels |= ((enabledChannelsPattern[entryIndex + 3]) & 0x0F);
whismanoid 1:77f1ee332e4a 2721 }
whismanoid 1:77f1ee332e4a 2722 SPIwrite16bits(pack4channels);
whismanoid 1:77f1ee332e4a 2723 }
whismanoid 1:77f1ee332e4a 2724 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2725
whismanoid 1:77f1ee332e4a 2726 //----------------------------------------
whismanoid 1:77f1ee332e4a 2727 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1001_SampleSetExternalClock = 9
whismanoid 1:77f1ee332e4a 2728 //~ const int SCAN_1001_SampleSetExternalClock = 9; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2729 ADC_MODE_CONTROL |= ((SCAN_1001_SampleSetExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2730
whismanoid 1:77f1ee332e4a 2731 //----------------------------------------
whismanoid 1:77f1ee332e4a 2732 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2733 ADC_MODE_CONTROL |= ((0 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2734
whismanoid 1:77f1ee332e4a 2735 //----------------------------------------
whismanoid 1:77f1ee332e4a 2736 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2737 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2738
whismanoid 1:77f1ee332e4a 2739 //----------------------------------------
whismanoid 1:77f1ee332e4a 2740 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2741 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2742 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2743 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2744 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2745 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2746 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2747 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2748
whismanoid 1:77f1ee332e4a 2749 //----------------------------------------
whismanoid 1:77f1ee332e4a 2750 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2751 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2752 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2753 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2754 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2755 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2756
whismanoid 1:77f1ee332e4a 2757 //----------------------------------------
whismanoid 1:77f1ee332e4a 2758 // return number of words to read
whismanoid 1:77f1ee332e4a 2759 return NumWords;
whismanoid 1:77f1ee332e4a 2760 }
whismanoid 1:77f1ee332e4a 2761
whismanoid 1:77f1ee332e4a 2762 //----------------------------------------
whismanoid 1:77f1ee332e4a 2763 // Example configure and perform some measurements in ScanManual mode.
whismanoid 1:77f1ee332e4a 2764 // @param[out] pd_mean = address for double mean (avearge)
whismanoid 1:77f1ee332e4a 2765 // @param[out] pd_variance = address for double variance (variance)
whismanoid 1:77f1ee332e4a 2766 // @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid 1:77f1ee332e4a 2767 // @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid 1:77f1ee332e4a 2768 // @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid 1:77f1ee332e4a 2769 void MAX11131::Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid 1:77f1ee332e4a 2770 double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid 1:77f1ee332e4a 2771 double* pd_Sx, double* pd_Sxx)
whismanoid 1:77f1ee332e4a 2772 {
whismanoid 1:77f1ee332e4a 2773
whismanoid 1:77f1ee332e4a 2774 //----------------------------------------
whismanoid 1:77f1ee332e4a 2775 // configure and perform some measurements in ScanManual mode
whismanoid 1:77f1ee332e4a 2776 Init();
whismanoid 1:77f1ee332e4a 2777 channelNumber_0_15 = channelNumber_0_15; // Analog Input Channel Select AIN0..
whismanoid 1:77f1ee332e4a 2778 PowerManagement_0_2 = 0; // Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2779 chan_id_0_1 = 1; // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2780 // const int nWords = 100;
whismanoid 1:77f1ee332e4a 2781 double Sx = 0;
whismanoid 1:77f1ee332e4a 2782 double Sxx = 0;
whismanoid 1:77f1ee332e4a 2783 int index;
whismanoid 1:77f1ee332e4a 2784 ScanManual();
whismanoid 1:77f1ee332e4a 2785 for (index = 0; index < nWords; index++)
whismanoid 1:77f1ee332e4a 2786 {
whismanoid 1:77f1ee332e4a 2787 int16_t misoData16 = ScanRead();
whismanoid 1:77f1ee332e4a 2788 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2789 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2790 int16_t value_u12 = (misoData16 & 0x0FFF);
whismanoid 1:77f1ee332e4a 2791 int channelId = ((misoData16 >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 2792 Sx = Sx + value_u12;
whismanoid 1:77f1ee332e4a 2793 Sxx = Sxx + ((double)value_u12 * value_u12);
whismanoid 1:77f1ee332e4a 2794 }
whismanoid 1:77f1ee332e4a 2795 if (pd_Sx != 0) {
whismanoid 1:77f1ee332e4a 2796 *(pd_Sx) = Sx;
whismanoid 1:77f1ee332e4a 2797 }
whismanoid 1:77f1ee332e4a 2798 if (pd_Sxx != 0) {
whismanoid 1:77f1ee332e4a 2799 *(pd_Sxx) = Sxx;
whismanoid 1:77f1ee332e4a 2800 }
whismanoid 1:77f1ee332e4a 2801 if (pd_mean != 0) {
whismanoid 1:77f1ee332e4a 2802 *(pd_mean) = Sx / nWords;
whismanoid 1:77f1ee332e4a 2803 }
whismanoid 1:77f1ee332e4a 2804 if (nWords >= 2)
whismanoid 1:77f1ee332e4a 2805 {
whismanoid 1:77f1ee332e4a 2806 if (pd_variance != 0) {
whismanoid 1:77f1ee332e4a 2807 // TODO1: is this variance calculation too naive to work reliably?
whismanoid 1:77f1ee332e4a 2808 // see https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance
whismanoid 1:77f1ee332e4a 2809 *(pd_variance) = (Sxx - ( Sx * Sx / nWords) ) / (nWords - 1);
whismanoid 1:77f1ee332e4a 2810 }
whismanoid 1:77f1ee332e4a 2811 if (pd_stddev != 0) {
whismanoid 1:77f1ee332e4a 2812 *(pd_stddev) = sqrt( *(pd_variance) );
whismanoid 1:77f1ee332e4a 2813 }
whismanoid 1:77f1ee332e4a 2814 }
whismanoid 1:77f1ee332e4a 2815 }
whismanoid 1:77f1ee332e4a 2816
whismanoid 1:77f1ee332e4a 2817
whismanoid 1:77f1ee332e4a 2818 // End of file