Maxim Integrated / Mbed OS HSP_RPC_GUI

MAX32620HSP (MAXREFDES100) RPC Example for Graphical User Interface

Dependencies:   USBDevice

Fork of HSP_Release by Jerry Bradshaw

This is an example program for the MAX32620HSP (MAXREFDES100 Health Sensor Platform). It demonstrates all the features of the platform and works with a companion graphical user interface (GUI) to help evaluate/configure/monitor the board. Go to the MAXREFDES100 product page and click on "design resources" to download the companion software. The GUI connects to the board through an RPC interface on a virtual serial port over the USB interface.

The RPC interface provides access to all the features of the board and is available to interface with other development environments such Matlab. This firmware provides realtime data streaming through the RPC interface over USB, and also provides the ability to log the data to flash for untethered battery operation. The data logging settings are configured through the GUI, and the GUI also provides the interface to download logged data.

Details on the RPC interface can be found here: HSP RPC Interface Documentation

Windows

With this program loaded, the MAX32620HSP will appear on your computer as a serial port. On Mac and Linux, this will happen by default. For Windows, you need to install a driver: HSP serial port windows driver

For more details about this platform and how to use it, see the MAXREFDES100 product page.

HSP/Devices/MAX30001/MAX30001/MAX30001.h@3:8e9b9f5818aa, 2017-04-25 (annotated)

Committer:
jbradshaw
Date:
Tue Apr 25 10:47:10 2017 -0500
Revision:
3:8e9b9f5818aa
Parent:
1:9490836294ea 
Removed Bulk Erasing, instead a small number of bytes are sampled from each and every page to determine if sector is "dirty", if so sector is erased

Prevents device from sleeping when the firmware detects a series of binary flash page RPC transfers, this increases flash page transfers by %450

  when 200mS elapse with the last flash page transfer, normal sleep behaviour is resumed

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jbradshaw 0:e4a10ed6eb92 1 /*******************************************************************************
jbradshaw 1:9490836294ea 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
jbradshaw 1:9490836294ea 3 *
jbradshaw 1:9490836294ea 4 * Permission is hereby granted, free of charge, to any person obtaining a
jbradshaw 1:9490836294ea 5 * copy of this software and associated documentation files (the "Software"),
jbradshaw 1:9490836294ea 6 * to deal in the Software without restriction, including without limitation
jbradshaw 1:9490836294ea 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
jbradshaw 1:9490836294ea 8 * and/or sell copies of the Software, and to permit persons to whom the
jbradshaw 1:9490836294ea 9 * Software is furnished to do so, subject to the following conditions:
jbradshaw 1:9490836294ea 10 *
jbradshaw 1:9490836294ea 11 * The above copyright notice and this permission notice shall be included
jbradshaw 1:9490836294ea 12 * in all copies or substantial portions of the Software.
jbradshaw 1:9490836294ea 13 *
jbradshaw 1:9490836294ea 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
jbradshaw 1:9490836294ea 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
jbradshaw 1:9490836294ea 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
jbradshaw 1:9490836294ea 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
jbradshaw 1:9490836294ea 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
jbradshaw 1:9490836294ea 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
jbradshaw 1:9490836294ea 20 * OTHER DEALINGS IN THE SOFTWARE.
jbradshaw 1:9490836294ea 21 *
jbradshaw 1:9490836294ea 22 * Except as contained in this notice, the name of Maxim Integrated
jbradshaw 1:9490836294ea 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
jbradshaw 1:9490836294ea 24 * Products, Inc. Branding Policy.
jbradshaw 1:9490836294ea 25 *
jbradshaw 1:9490836294ea 26 * The mere transfer of this software does not imply any licenses
jbradshaw 1:9490836294ea 27 * of trade secrets, proprietary technology, copyrights, patents,
jbradshaw 1:9490836294ea 28 * trademarks, maskwork rights, or any other form of intellectual
jbradshaw 1:9490836294ea 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
jbradshaw 1:9490836294ea 30 * ownership rights.
jbradshaw 1:9490836294ea 31 *******************************************************************************/
jbradshaw 1:9490836294ea 32 /**
jbradshaw 1:9490836294ea 33 *
jbradshaw 1:9490836294ea 34 * Maxim Integrated MAX30001 ECG/BIOZ chip
jbradshaw 0:e4a10ed6eb92 35 *
jbradshaw 1:9490836294ea 36 * @code
jbradshaw 1:9490836294ea 37 * #include "mbed.h"
jbradshaw 1:9490836294ea 38 * #include "MAX30001.h"
jbradshaw 1:9490836294ea 39 *
jbradshaw 1:9490836294ea 40 * /// Initialization values for ECG_InitStart()
jbradshaw 1:9490836294ea 41 * #define EN_ECG 0b1
jbradshaw 1:9490836294ea 42 * #define OPENP 0b1
jbradshaw 1:9490836294ea 43 * #define OPENN 0b1
jbradshaw 1:9490836294ea 44 * #define POL 0b0
jbradshaw 1:9490836294ea 45 * #define CALP_SEL 0b10
jbradshaw 1:9490836294ea 46 * #define CALN_SEL 0b11
jbradshaw 1:9490836294ea 47 * #define E_FIT 31
jbradshaw 1:9490836294ea 48 * #define RATE 0b00
jbradshaw 1:9490836294ea 49 * #define GAIN 0b00
jbradshaw 1:9490836294ea 50 * #define DHPF 0b0
jbradshaw 1:9490836294ea 51 * #define DLPF 0b01
jbradshaw 1:9490836294ea 52 *
jbradshaw 1:9490836294ea 53 * /// Initialization values for CAL_InitStart()
jbradshaw 1:9490836294ea 54 * #define EN_VCAL 0b1
jbradshaw 1:9490836294ea 55 * #define VMODE 0b1
jbradshaw 1:9490836294ea 56 * #define VMAG 0b1
jbradshaw 1:9490836294ea 57 * #define FCAL 0b011
jbradshaw 1:9490836294ea 58 * #define THIGH 0x7FF
jbradshaw 1:9490836294ea 59 * #define FIFTY 0b0
jbradshaw 1:9490836294ea 60 *
jbradshaw 1:9490836294ea 61 * /// Initializaton values for Rbias_FMSTR_Init()
jbradshaw 1:9490836294ea 62 * #define EN_RBIAS 0b01
jbradshaw 1:9490836294ea 63 * #define RBIASV 0b10
jbradshaw 1:9490836294ea 64 * #define RBIASP 0b1
jbradshaw 1:9490836294ea 65 * #define RBIASN 0b1
jbradshaw 1:9490836294ea 66 * #define FMSTR 0b00
jbradshaw 1:9490836294ea 67 *
jbradshaw 1:9490836294ea 68 * #define BUFFER_LENGTH 50
jbradshaw 1:9490836294ea 69 *
jbradshaw 1:9490836294ea 70 * // @brief SPI Master 0 with SPI0_SS for use with MAX30001
jbradshaw 1:9490836294ea 71 * SPI spi(SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SS); // used by MAX30001
jbradshaw 1:9490836294ea 72 *
jbradshaw 1:9490836294ea 73 * //@brief ECG device
jbradshaw 1:9490836294ea 74 * MAX30001 max30001(&spi);
jbradshaw 1:9490836294ea 75 * InterruptIn max30001_InterruptB(P3_6);
jbradshaw 1:9490836294ea 76 * InterruptIn max30001_Interrupt2B(P4_5);
jbradshaw 1:9490836294ea 77 * //@brief PWM used as fclk for the MAX30001
jbradshaw 1:9490836294ea 78 * PwmOut pwmout(P1_7);
jbradshaw 1:9490836294ea 79 *
jbradshaw 1:9490836294ea 80 * //@brief Creating a buffer to hold the data
jbradshaw 1:9490836294ea 81 * uint32_t ecgBuffer[BUFFER_LENGTH];
jbradshaw 1:9490836294ea 82 * int ecgIndex = 0;
jbradshaw 1:9490836294ea 83 * char data_trigger = 0;
jbradshaw 1:9490836294ea 84 *
jbradshaw 1:9490836294ea 85 *
jbradshaw 1:9490836294ea 86 * //
jbradshaw 1:9490836294ea 87 * // @brief Creates a packet that will be streamed via USB Serial
jbradshaw 1:9490836294ea 88 * // the packet created will be inserted into a fifo to be streamed at a later time
jbradshaw 1:9490836294ea 89 * // @param id Streaming ID
jbradshaw 1:9490836294ea 90 * // @param buffer Pointer to a uint32 array that contains the data to include in the packet
jbradshaw 1:9490836294ea 91 * // @param number Number of elements in the buffer
jbradshaw 1:9490836294ea 92 * //
jbradshaw 1:9490836294ea 93 * void StreamPacketUint32_ecg(uint32_t id, uint32_t *buffer, uint32_t number) {
jbradshaw 1:9490836294ea 94 * int i;
jbradshaw 1:9490836294ea 95 * if (id == MAX30001_DATA_ECG) {
jbradshaw 1:9490836294ea 96 * for (i = 0; i < number; i++) {
jbradshaw 1:9490836294ea 97 * ecgBuffer[ecgIndex] = buffer[i];
jbradshaw 1:9490836294ea 98 * ecgIndex++;
jbradshaw 1:9490836294ea 99 * if (ecgIndex > BUFFER_LENGTH)
jbradshaw 1:9490836294ea 100 * {
jbradshaw 1:9490836294ea 101 * data_trigger = 1;
jbradshaw 1:9490836294ea 102 * ecgIndex = 0;
jbradshaw 1:9490836294ea 103 * }
jbradshaw 1:9490836294ea 104 * }
jbradshaw 1:9490836294ea 105 * }
jbradshaw 1:9490836294ea 106 * if (id == MAX30001_DATA_BIOZ) {
jbradshaw 1:9490836294ea 107 * /// Add code for reading BIOZ data
jbradshaw 1:9490836294ea 108 * }
jbradshaw 1:9490836294ea 109 * if (id == MAX30001_DATA_PACE) {
jbradshaw 1:9490836294ea 110 * /// Add code for reading Pace data
jbradshaw 1:9490836294ea 111 * }
jbradshaw 1:9490836294ea 112 * if (id == MAX30001_DATA_RTOR) {
jbradshaw 1:9490836294ea 113 * /// Add code for reading RtoR data
jbradshaw 1:9490836294ea 114 * }
jbradshaw 1:9490836294ea 115 * }
jbradshaw 1:9490836294ea 116 *
jbradshaw 1:9490836294ea 117 *
jbradshaw 1:9490836294ea 118 * int main() {
jbradshaw 1:9490836294ea 119 *
jbradshaw 1:9490836294ea 120 * uint32_t all;
jbradshaw 1:9490836294ea 121 *
jbradshaw 1:9490836294ea 122 * /// set NVIC priorities for GPIO to prevent priority inversion
jbradshaw 1:9490836294ea 123 * NVIC_SetPriority(GPIO_P0_IRQn, 5);
jbradshaw 1:9490836294ea 124 * NVIC_SetPriority(GPIO_P1_IRQn, 5);
jbradshaw 1:9490836294ea 125 * NVIC_SetPriority(GPIO_P2_IRQn, 5);
jbradshaw 1:9490836294ea 126 * NVIC_SetPriority(GPIO_P3_IRQn, 5);
jbradshaw 1:9490836294ea 127 * NVIC_SetPriority(GPIO_P4_IRQn, 5);
jbradshaw 1:9490836294ea 128 * NVIC_SetPriority(GPIO_P5_IRQn, 5);
jbradshaw 1:9490836294ea 129 * NVIC_SetPriority(GPIO_P6_IRQn, 5);
jbradshaw 1:9490836294ea 130 * // used by the MAX30001
jbradshaw 1:9490836294ea 131 * NVIC_SetPriority(SPI1_IRQn, 0);
jbradshaw 1:9490836294ea 132 *
jbradshaw 1:9490836294ea 133 *
jbradshaw 1:9490836294ea 134 * /// Setup interrupts and callback functions
jbradshaw 1:9490836294ea 135 * max30001_InterruptB.disable_irq();
jbradshaw 1:9490836294ea 136 * max30001_Interrupt2B.disable_irq();
jbradshaw 1:9490836294ea 137 *
jbradshaw 1:9490836294ea 138 * max30001_InterruptB.mode(PullUp);
jbradshaw 1:9490836294ea 139 * max30001_InterruptB.fall(&MAX30001::Mid_IntB_Handler);
jbradshaw 1:9490836294ea 140 *
jbradshaw 1:9490836294ea 141 * max30001_Interrupt2B.mode(PullUp);
jbradshaw 1:9490836294ea 142 * max30001_Interrupt2B.fall(&MAX30001::Mid_Int2B_Handler);
jbradshaw 1:9490836294ea 143 *
jbradshaw 1:9490836294ea 144 * max30001_InterruptB.enable_irq();
jbradshaw 1:9490836294ea 145 * max30001_Interrupt2B.enable_irq();
jbradshaw 1:9490836294ea 146 *
jbradshaw 1:9490836294ea 147 * max30001.AllowInterrupts(1);
jbradshaw 1:9490836294ea 148 *
jbradshaw 1:9490836294ea 149 * // Configuring the FCLK for the ECG, set to 32.768KHZ
jbradshaw 1:9490836294ea 150 * pwmout.period_us(31);
jbradshaw 1:9490836294ea 151 * pwmout.write(0.5); // 0-1 is 0-100%, 0.5 = 50% duty cycle.
jbradshaw 1:9490836294ea 152 * max30001.sw_rst(); // Do a software reset of the MAX30001
jbradshaw 1:9490836294ea 153 *
jbradshaw 1:9490836294ea 154 * max30001.INT_assignment(MAX30001::MAX30001_INT_B, MAX30001::MAX30001_NO_INT, MAX30001::MAX30001_NO_INT, // en_enint_loc, en_eovf_loc, en_fstint_loc,
jbradshaw 1:9490836294ea 155 * MAX30001::MAX30001_INT_2B, MAX30001::MAX30001_INT_2B, MAX30001::MAX30001_NO_INT, // en_dcloffint_loc, en_bint_loc, en_bovf_loc,
jbradshaw 1:9490836294ea 156 * MAX30001::MAX30001_INT_2B, MAX30001::MAX30001_INT_2B, MAX30001::MAX30001_NO_INT, // en_bover_loc, en_bundr_loc, en_bcgmon_loc,
jbradshaw 1:9490836294ea 157 * MAX30001::MAX30001_INT_B, MAX30001::MAX30001_NO_INT, MAX30001::MAX30001_NO_INT, // en_pint_loc, en_povf_loc, en_pedge_loc,
jbradshaw 1:9490836294ea 158 * MAX30001::MAX30001_INT_2B, MAX30001::MAX30001_INT_B, MAX30001::MAX30001_NO_INT, // en_lonint_loc, en_rrint_loc, en_samp_loc,
jbradshaw 1:9490836294ea 159 * MAX30001::MAX30001_INT_ODNR, MAX30001::MAX30001_INT_ODNR); // intb_Type, int2b_Type)
jbradshaw 1:9490836294ea 160 *
jbradshaw 1:9490836294ea 161 * max30001.onDataAvailable(&StreamPacketUint32_ecg);
jbradshaw 1:9490836294ea 162 *
jbradshaw 1:9490836294ea 163 * /// Set and Start the VCAL input
jbradshaw 1:9490836294ea 164 * /// @brief NOTE VCAL must be set first if VCAL is to be used
jbradshaw 1:9490836294ea 165 * max30001.CAL_InitStart(EN_VCAL , VMODE, VMAG, FCAL, THIGH, FIFTY);
jbradshaw 1:9490836294ea 166 *
jbradshaw 1:9490836294ea 167 * /// ECG Initialization
jbradshaw 1:9490836294ea 168 * max30001.ECG_InitStart(EN_ECG, OPENP, OPENN, POL, CALP_SEL, CALN_SEL, E_FIT, RATE, GAIN, DHPF, DLPF);
jbradshaw 1:9490836294ea 169 *
jbradshaw 1:9490836294ea 170 * /// @details The user can call any of the InitStart functions for Pace, BIOZ and RtoR
jbradshaw 1:9490836294ea 171 *
jbradshaw 1:9490836294ea 172 *
jbradshaw 1:9490836294ea 173 * /// @brief Set Rbias & FMSTR over here
jbradshaw 1:9490836294ea 174 * max30001.Rbias_FMSTR_Init(EN_RBIAS, RBIASV, RBIASP, RBIASN,FMSTR);
jbradshaw 1:9490836294ea 175 *
jbradshaw 1:9490836294ea 176 * max30001.synch();
jbradshaw 1:9490836294ea 177 *
jbradshaw 1:9490836294ea 178 * /// clear the status register for a clean start
jbradshaw 1:9490836294ea 179 * max30001.reg_read(MAX30001::STATUS, &all);
jbradshaw 1:9490836294ea 180 *
jbradshaw 1:9490836294ea 181 * printf("Please wait for data to start streaming\n");
jbradshaw 1:9490836294ea 182 * fflush(stdout);
jbradshaw 1:9490836294ea 183 *
jbradshaw 1:9490836294ea 184 * while (1) {
jbradshaw 1:9490836294ea 185 * if(data_trigger == 1){
jbradshaw 1:9490836294ea 186 * printf("%ld ", ecgBuffer[ecgIndex]); // Print the ECG data on a serial port terminal software
jbradshaw 1:9490836294ea 187 * fflush(stdout);
jbradshaw 1:9490836294ea 188 * }
jbradshaw 1:9490836294ea 189 * }
jbradshaw 1:9490836294ea 190 * }
jbradshaw 1:9490836294ea 191 * @endcode
jbradshaw 1:9490836294ea 192 *
jbradshaw 0:e4a10ed6eb92 193 */
jbradshaw 0:e4a10ed6eb92 194
jbradshaw 1:9490836294ea 195
jbradshaw 0:e4a10ed6eb92 196 #ifndef MAX30001_H_
jbradshaw 0:e4a10ed6eb92 197 #define MAX30001_H_
jbradshaw 0:e4a10ed6eb92 198
jbradshaw 0:e4a10ed6eb92 199 #include "mbed.h"
jbradshaw 0:e4a10ed6eb92 200
jbradshaw 1:9490836294ea 201 #define mbed_COMPLIANT ///< Uncomment to Use timer for MAX30001 FCLK (for mbed)
jbradshaw 1:9490836294ea 202 ///< Comment to use the RTC clock
jbradshaw 0:e4a10ed6eb92 203
jbradshaw 1:9490836294ea 204 #define ASYNC_SPI_BUFFER_SIZE (32 * 3) ///< Maximimum buffer size for async byte transfers
jbradshaw 0:e4a10ed6eb92 205
jbradshaw 1:9490836294ea 206 ///< Defines for data callbacks
jbradshaw 0:e4a10ed6eb92 207 #define MAX30001_DATA_ECG 0x30
jbradshaw 0:e4a10ed6eb92 208 #define MAX30001_DATA_PACE 0x31
jbradshaw 0:e4a10ed6eb92 209 #define MAX30001_DATA_RTOR 0x32
jbradshaw 0:e4a10ed6eb92 210 #define MAX30001_DATA_BIOZ 0x33
jbradshaw 0:e4a10ed6eb92 211 #define MAX30001_DATA_LEADOFF_DC 0x34
jbradshaw 0:e4a10ed6eb92 212 #define MAX30001_DATA_LEADOFF_AC 0x35
jbradshaw 0:e4a10ed6eb92 213 #define MAX30001_DATA_BCGMON 0x36
jbradshaw 0:e4a10ed6eb92 214 #define MAX30001_DATA_ACLEADON 0x37
jbradshaw 0:e4a10ed6eb92 215
jbradshaw 0:e4a10ed6eb92 216 #define MAX30001_SPI_MASTER_PORT 0
jbradshaw 0:e4a10ed6eb92 217 #define MAX30001_SPI_SS_INDEX 0
jbradshaw 0:e4a10ed6eb92 218
jbradshaw 0:e4a10ed6eb92 219 #define MAX30001_INT_PORT_B 3
jbradshaw 0:e4a10ed6eb92 220 #define MAX30001_INT_PIN_B 6
jbradshaw 0:e4a10ed6eb92 221
jbradshaw 0:e4a10ed6eb92 222 #define MAX30001_INT_PORT_2B 4
jbradshaw 0:e4a10ed6eb92 223 #define MAX30001_INT_PIN_2B 5
jbradshaw 0:e4a10ed6eb92 224
jbradshaw 0:e4a10ed6eb92 225 #define MAX30001_INT_PORT_FCLK 1
jbradshaw 0:e4a10ed6eb92 226 #define MAX30001_INT_PIN_FCLK 7
jbradshaw 0:e4a10ed6eb92 227
jbradshaw 1:9490836294ea 228 #define MAX30001_FUNC_SEL_TMR 2 ///< 0=FW Control, 1= Pulse Train, 2=Timer
jbradshaw 0:e4a10ed6eb92 229
jbradshaw 0:e4a10ed6eb92 230 #define MAX30001_INDEX 3
jbradshaw 0:e4a10ed6eb92 231 #define MAX30001_POLARITY 0
jbradshaw 0:e4a10ed6eb92 232 #define MAX30001_PERIOD 30518
jbradshaw 0:e4a10ed6eb92 233 #define MAX30001_CYCLE 50
jbradshaw 0:e4a10ed6eb92 234
jbradshaw 0:e4a10ed6eb92 235 #define MAX30001_IOMUX_IO_ENABLE 1
jbradshaw 0:e4a10ed6eb92 236
jbradshaw 0:e4a10ed6eb92 237 #define MAX30001_SPI_PORT 0
jbradshaw 0:e4a10ed6eb92 238 #define MAX30001_CS_PIN 0
jbradshaw 0:e4a10ed6eb92 239 #define MAX30001_CS_POLARITY 0
jbradshaw 0:e4a10ed6eb92 240 #define MAX30001_CS_ACTIVITY_DELAY 0
jbradshaw 0:e4a10ed6eb92 241 #define MAX30001_CS_INACTIVITY_DELAY 0
jbradshaw 0:e4a10ed6eb92 242 #define MAX30001_CLK_HI 1
jbradshaw 0:e4a10ed6eb92 243 #define MAX30001_CLK_LOW 1
jbradshaw 0:e4a10ed6eb92 244 #define MAX30001_ALT_CLK 0
jbradshaw 0:e4a10ed6eb92 245 #define MAX30001_CLK_POLARITY 0
jbradshaw 0:e4a10ed6eb92 246 #define MAX30001_CLK_PHASE 0
jbradshaw 0:e4a10ed6eb92 247 #define MAX30001_WRITE 1
jbradshaw 0:e4a10ed6eb92 248 #define MAX30001_READ 0
jbradshaw 0:e4a10ed6eb92 249
jbradshaw 0:e4a10ed6eb92 250 #define MAX30001_INT_PORT_B 3
jbradshaw 0:e4a10ed6eb92 251 #define MAX30001INT_PIN_B 6
jbradshaw 0:e4a10ed6eb92 252
jbradshaw 0:e4a10ed6eb92 253 void MAX30001_AllowInterrupts(int state);
jbradshaw 0:e4a10ed6eb92 254
jbradshaw 0:e4a10ed6eb92 255 /**
jbradshaw 1:9490836294ea 256 * @brief Maxim Integrated MAX30001 ECG/BIOZ chip
jbradshaw 0:e4a10ed6eb92 257 */
jbradshaw 0:e4a10ed6eb92 258 class MAX30001 {
jbradshaw 0:e4a10ed6eb92 259
jbradshaw 0:e4a10ed6eb92 260 public:
jbradshaw 1:9490836294ea 261 typedef enum { ///< MAX30001 Register addresses
jbradshaw 0:e4a10ed6eb92 262 STATUS = 0x01,
jbradshaw 0:e4a10ed6eb92 263 EN_INT = 0x02,
jbradshaw 0:e4a10ed6eb92 264 EN_INT2 = 0x03,
jbradshaw 0:e4a10ed6eb92 265 MNGR_INT = 0x04,
jbradshaw 0:e4a10ed6eb92 266 MNGR_DYN = 0x05,
jbradshaw 0:e4a10ed6eb92 267 SW_RST = 0x08,
jbradshaw 0:e4a10ed6eb92 268 SYNCH = 0x09,
jbradshaw 0:e4a10ed6eb92 269 FIFO_RST = 0x0A,
jbradshaw 0:e4a10ed6eb92 270 INFO = 0x0F,
jbradshaw 0:e4a10ed6eb92 271 CNFG_GEN = 0x10,
jbradshaw 0:e4a10ed6eb92 272 CNFG_CAL = 0x12,
jbradshaw 0:e4a10ed6eb92 273 CNFG_EMUX = 0x14,
jbradshaw 0:e4a10ed6eb92 274 CNFG_ECG = 0x15,
jbradshaw 0:e4a10ed6eb92 275 CNFG_BMUX = 0x17,
jbradshaw 0:e4a10ed6eb92 276 CNFG_BIOZ = 0x18,
jbradshaw 0:e4a10ed6eb92 277 CNFG_PACE = 0x1A,
jbradshaw 0:e4a10ed6eb92 278 CNFG_RTOR1 = 0x1D,
jbradshaw 0:e4a10ed6eb92 279 CNFG_RTOR2 = 0x1E,
jbradshaw 0:e4a10ed6eb92 280
jbradshaw 0:e4a10ed6eb92 281 // Data locations
jbradshaw 0:e4a10ed6eb92 282 ECG_FIFO_BURST = 0x20,
jbradshaw 0:e4a10ed6eb92 283 ECG_FIFO = 0x21,
jbradshaw 0:e4a10ed6eb92 284 FIFO_BURST = 0x22,
jbradshaw 0:e4a10ed6eb92 285 BIOZ_FIFO = 0x23,
jbradshaw 0:e4a10ed6eb92 286 RTOR = 0x25,
jbradshaw 0:e4a10ed6eb92 287
jbradshaw 0:e4a10ed6eb92 288 PACE0_FIFO_BURST = 0x30,
jbradshaw 0:e4a10ed6eb92 289 PACE0_A = 0x31,
jbradshaw 0:e4a10ed6eb92 290 PACE0_B = 0x32,
jbradshaw 0:e4a10ed6eb92 291 PACE0_C = 0x33,
jbradshaw 0:e4a10ed6eb92 292
jbradshaw 0:e4a10ed6eb92 293 PACE1_FIFO_BURST = 0x34,
jbradshaw 0:e4a10ed6eb92 294 PACE1_A = 0x35,
jbradshaw 0:e4a10ed6eb92 295 PACE1_B = 0x36,
jbradshaw 0:e4a10ed6eb92 296 PACE1_C = 0x37,
jbradshaw 0:e4a10ed6eb92 297
jbradshaw 0:e4a10ed6eb92 298 PACE2_FIFO_BURST = 0x38,
jbradshaw 0:e4a10ed6eb92 299 PACE2_A = 0x39,
jbradshaw 0:e4a10ed6eb92 300 PACE2_B = 0x3A,
jbradshaw 0:e4a10ed6eb92 301 PACE2_C = 0x3B,
jbradshaw 0:e4a10ed6eb92 302
jbradshaw 0:e4a10ed6eb92 303 PACE3_FIFO_BURST = 0x3C,
jbradshaw 0:e4a10ed6eb92 304 PACE3_A = 0x3D,
jbradshaw 0:e4a10ed6eb92 305 PACE3_B = 0x3E,
jbradshaw 0:e4a10ed6eb92 306 PACE3_C = 0x3F,
jbradshaw 0:e4a10ed6eb92 307
jbradshaw 0:e4a10ed6eb92 308 PACE4_FIFO_BURST = 0x40,
jbradshaw 0:e4a10ed6eb92 309 PACE4_A = 0x41,
jbradshaw 0:e4a10ed6eb92 310 PACE4_B = 0x42,
jbradshaw 0:e4a10ed6eb92 311 PACE4_C = 0x43,
jbradshaw 0:e4a10ed6eb92 312
jbradshaw 0:e4a10ed6eb92 313 PACE5_FIFO_BURST = 0x44,
jbradshaw 0:e4a10ed6eb92 314 PACE5_A = 0x45,
jbradshaw 0:e4a10ed6eb92 315 PACE5_B = 0x46,
jbradshaw 0:e4a10ed6eb92 316 PACE5_C = 0x47,
jbradshaw 0:e4a10ed6eb92 317
jbradshaw 0:e4a10ed6eb92 318 } MAX30001_REG_map_t;
jbradshaw 0:e4a10ed6eb92 319
jbradshaw 0:e4a10ed6eb92 320 /**
jbradshaw 0:e4a10ed6eb92 321 * @brief STATUS (0x01)
jbradshaw 0:e4a10ed6eb92 322 */
jbradshaw 1:9490836294ea 323 typedef union max30001_status_reg {
jbradshaw 0:e4a10ed6eb92 324 uint32_t all;
jbradshaw 0:e4a10ed6eb92 325
jbradshaw 0:e4a10ed6eb92 326 struct {
jbradshaw 0:e4a10ed6eb92 327 uint32_t loff_nl : 1;
jbradshaw 0:e4a10ed6eb92 328 uint32_t loff_nh : 1;
jbradshaw 0:e4a10ed6eb92 329 uint32_t loff_pl : 1;
jbradshaw 0:e4a10ed6eb92 330 uint32_t loff_ph : 1;
jbradshaw 0:e4a10ed6eb92 331
jbradshaw 0:e4a10ed6eb92 332 uint32_t bcgmn : 1;
jbradshaw 0:e4a10ed6eb92 333 uint32_t bcgmp : 1;
jbradshaw 0:e4a10ed6eb92 334 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 335 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 336
jbradshaw 0:e4a10ed6eb92 337 uint32_t pllint : 1;
jbradshaw 0:e4a10ed6eb92 338 uint32_t samp : 1;
jbradshaw 0:e4a10ed6eb92 339 uint32_t rrint : 1;
jbradshaw 0:e4a10ed6eb92 340 uint32_t lonint : 1;
jbradshaw 0:e4a10ed6eb92 341
jbradshaw 0:e4a10ed6eb92 342 uint32_t pedge : 1;
jbradshaw 0:e4a10ed6eb92 343 uint32_t povf : 1;
jbradshaw 0:e4a10ed6eb92 344 uint32_t pint : 1;
jbradshaw 0:e4a10ed6eb92 345 uint32_t bcgmon : 1;
jbradshaw 0:e4a10ed6eb92 346
jbradshaw 0:e4a10ed6eb92 347 uint32_t bundr : 1;
jbradshaw 0:e4a10ed6eb92 348 uint32_t bover : 1;
jbradshaw 0:e4a10ed6eb92 349 uint32_t bovf : 1;
jbradshaw 0:e4a10ed6eb92 350 uint32_t bint : 1;
jbradshaw 0:e4a10ed6eb92 351
jbradshaw 0:e4a10ed6eb92 352 uint32_t dcloffint : 1;
jbradshaw 0:e4a10ed6eb92 353 uint32_t fstint : 1;
jbradshaw 0:e4a10ed6eb92 354 uint32_t eovf : 1;
jbradshaw 0:e4a10ed6eb92 355 uint32_t eint : 1;
jbradshaw 0:e4a10ed6eb92 356
jbradshaw 0:e4a10ed6eb92 357 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 358
jbradshaw 0:e4a10ed6eb92 359 } bit;
jbradshaw 0:e4a10ed6eb92 360
jbradshaw 1:9490836294ea 361 } max30001_status_t;
jbradshaw 0:e4a10ed6eb92 362
jbradshaw 0:e4a10ed6eb92 363
jbradshaw 0:e4a10ed6eb92 364 /**
jbradshaw 0:e4a10ed6eb92 365 * @brief EN_INT (0x02)
jbradshaw 0:e4a10ed6eb92 366 */
jbradshaw 0:e4a10ed6eb92 367
jbradshaw 1:9490836294ea 368 typedef union max30001_en_int_reg {
jbradshaw 0:e4a10ed6eb92 369 uint32_t all;
jbradshaw 0:e4a10ed6eb92 370
jbradshaw 0:e4a10ed6eb92 371 struct {
jbradshaw 0:e4a10ed6eb92 372 uint32_t intb_type : 2;
jbradshaw 0:e4a10ed6eb92 373 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 374 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 375
jbradshaw 0:e4a10ed6eb92 376 uint32_t reserved3 : 1;
jbradshaw 0:e4a10ed6eb92 377 uint32_t reserved4 : 1;
jbradshaw 0:e4a10ed6eb92 378 uint32_t reserved5 : 1;
jbradshaw 0:e4a10ed6eb92 379 uint32_t reserved6 : 1;
jbradshaw 0:e4a10ed6eb92 380
jbradshaw 0:e4a10ed6eb92 381 uint32_t en_pllint : 1;
jbradshaw 0:e4a10ed6eb92 382 uint32_t en_samp : 1;
jbradshaw 0:e4a10ed6eb92 383 uint32_t en_rrint : 1;
jbradshaw 0:e4a10ed6eb92 384 uint32_t en_lonint : 1;
jbradshaw 0:e4a10ed6eb92 385
jbradshaw 0:e4a10ed6eb92 386 uint32_t en_pedge : 1;
jbradshaw 0:e4a10ed6eb92 387 uint32_t en_povf : 1;
jbradshaw 0:e4a10ed6eb92 388 uint32_t en_pint : 1;
jbradshaw 0:e4a10ed6eb92 389 uint32_t en_bcgmon : 1;
jbradshaw 0:e4a10ed6eb92 390
jbradshaw 0:e4a10ed6eb92 391 uint32_t en_bundr : 1;
jbradshaw 0:e4a10ed6eb92 392 uint32_t en_bover : 1;
jbradshaw 0:e4a10ed6eb92 393 uint32_t en_bovf : 1;
jbradshaw 0:e4a10ed6eb92 394 uint32_t en_bint : 1;
jbradshaw 0:e4a10ed6eb92 395
jbradshaw 0:e4a10ed6eb92 396 uint32_t en_dcloffint : 1;
jbradshaw 0:e4a10ed6eb92 397 uint32_t en_fstint : 1;
jbradshaw 0:e4a10ed6eb92 398 uint32_t en_eovf : 1;
jbradshaw 0:e4a10ed6eb92 399 uint32_t en_eint : 1;
jbradshaw 0:e4a10ed6eb92 400
jbradshaw 0:e4a10ed6eb92 401 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 402
jbradshaw 0:e4a10ed6eb92 403 } bit;
jbradshaw 0:e4a10ed6eb92 404
jbradshaw 1:9490836294ea 405 } max30001_en_int_t;
jbradshaw 0:e4a10ed6eb92 406
jbradshaw 0:e4a10ed6eb92 407
jbradshaw 0:e4a10ed6eb92 408 /**
jbradshaw 0:e4a10ed6eb92 409 * @brief EN_INT2 (0x03)
jbradshaw 0:e4a10ed6eb92 410 */
jbradshaw 1:9490836294ea 411 typedef union max30001_en_int2_reg {
jbradshaw 0:e4a10ed6eb92 412 uint32_t all;
jbradshaw 0:e4a10ed6eb92 413
jbradshaw 0:e4a10ed6eb92 414 struct {
jbradshaw 0:e4a10ed6eb92 415 uint32_t intb_type : 2;
jbradshaw 0:e4a10ed6eb92 416 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 417 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 418
jbradshaw 0:e4a10ed6eb92 419 uint32_t reserved3 : 1;
jbradshaw 0:e4a10ed6eb92 420 uint32_t reserved4 : 1;
jbradshaw 0:e4a10ed6eb92 421 uint32_t reserved5 : 1;
jbradshaw 0:e4a10ed6eb92 422 uint32_t reserved6 : 1;
jbradshaw 0:e4a10ed6eb92 423
jbradshaw 0:e4a10ed6eb92 424 uint32_t en_pllint : 1;
jbradshaw 0:e4a10ed6eb92 425 uint32_t en_samp : 1;
jbradshaw 0:e4a10ed6eb92 426 uint32_t en_rrint : 1;
jbradshaw 0:e4a10ed6eb92 427 uint32_t en_lonint : 1;
jbradshaw 0:e4a10ed6eb92 428
jbradshaw 0:e4a10ed6eb92 429 uint32_t en_pedge : 1;
jbradshaw 0:e4a10ed6eb92 430 uint32_t en_povf : 1;
jbradshaw 0:e4a10ed6eb92 431 uint32_t en_pint : 1;
jbradshaw 0:e4a10ed6eb92 432 uint32_t en_bcgmon : 1;
jbradshaw 0:e4a10ed6eb92 433
jbradshaw 0:e4a10ed6eb92 434 uint32_t en_bundr : 1;
jbradshaw 0:e4a10ed6eb92 435 uint32_t en_bover : 1;
jbradshaw 0:e4a10ed6eb92 436 uint32_t en_bovf : 1;
jbradshaw 0:e4a10ed6eb92 437 uint32_t en_bint : 1;
jbradshaw 0:e4a10ed6eb92 438
jbradshaw 0:e4a10ed6eb92 439 uint32_t en_dcloffint : 1;
jbradshaw 0:e4a10ed6eb92 440 uint32_t en_fstint : 1;
jbradshaw 0:e4a10ed6eb92 441 uint32_t en_eovf : 1;
jbradshaw 0:e4a10ed6eb92 442 uint32_t en_eint : 1;
jbradshaw 0:e4a10ed6eb92 443
jbradshaw 0:e4a10ed6eb92 444 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 445
jbradshaw 0:e4a10ed6eb92 446 } bit;
jbradshaw 0:e4a10ed6eb92 447
jbradshaw 1:9490836294ea 448 } max30001_en_int2_t;
jbradshaw 0:e4a10ed6eb92 449
jbradshaw 0:e4a10ed6eb92 450 /**
jbradshaw 0:e4a10ed6eb92 451 * @brief MNGR_INT (0x04)
jbradshaw 0:e4a10ed6eb92 452 */
jbradshaw 1:9490836294ea 453 typedef union max30001_mngr_int_reg {
jbradshaw 0:e4a10ed6eb92 454 uint32_t all;
jbradshaw 0:e4a10ed6eb92 455
jbradshaw 0:e4a10ed6eb92 456 struct {
jbradshaw 0:e4a10ed6eb92 457 uint32_t samp_it : 2;
jbradshaw 0:e4a10ed6eb92 458 uint32_t clr_samp : 1;
jbradshaw 0:e4a10ed6eb92 459 uint32_t clr_pedge : 1;
jbradshaw 0:e4a10ed6eb92 460 uint32_t clr_rrint : 2;
jbradshaw 0:e4a10ed6eb92 461 uint32_t clr_fast : 1;
jbradshaw 0:e4a10ed6eb92 462 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 463 uint32_t reserved2 : 4;
jbradshaw 0:e4a10ed6eb92 464 uint32_t reserved3 : 4;
jbradshaw 0:e4a10ed6eb92 465
jbradshaw 0:e4a10ed6eb92 466 uint32_t b_fit : 3;
jbradshaw 0:e4a10ed6eb92 467 uint32_t e_fit : 5;
jbradshaw 0:e4a10ed6eb92 468
jbradshaw 0:e4a10ed6eb92 469 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 470
jbradshaw 0:e4a10ed6eb92 471 } bit;
jbradshaw 0:e4a10ed6eb92 472
jbradshaw 1:9490836294ea 473 } max30001_mngr_int_t;
jbradshaw 0:e4a10ed6eb92 474
jbradshaw 0:e4a10ed6eb92 475 /**
jbradshaw 0:e4a10ed6eb92 476 * @brief MNGR_DYN (0x05)
jbradshaw 0:e4a10ed6eb92 477 */
jbradshaw 1:9490836294ea 478 typedef union max30001_mngr_dyn_reg {
jbradshaw 0:e4a10ed6eb92 479 uint32_t all;
jbradshaw 0:e4a10ed6eb92 480
jbradshaw 0:e4a10ed6eb92 481 struct {
jbradshaw 0:e4a10ed6eb92 482 uint32_t bloff_lo_it : 8;
jbradshaw 0:e4a10ed6eb92 483 uint32_t bloff_hi_it : 8;
jbradshaw 0:e4a10ed6eb92 484 uint32_t fast_th : 6;
jbradshaw 0:e4a10ed6eb92 485 uint32_t fast : 2;
jbradshaw 0:e4a10ed6eb92 486 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 487 } bit;
jbradshaw 0:e4a10ed6eb92 488
jbradshaw 1:9490836294ea 489 } max30001_mngr_dyn_t;
jbradshaw 0:e4a10ed6eb92 490
jbradshaw 0:e4a10ed6eb92 491
jbradshaw 0:e4a10ed6eb92 492 /**
jbradshaw 0:e4a10ed6eb92 493 * @brief INFO (0x0F)
jbradshaw 0:e4a10ed6eb92 494 */
jbradshaw 1:9490836294ea 495 typedef union max30001_info_reg {
jbradshaw 0:e4a10ed6eb92 496 uint32_t all;
jbradshaw 0:e4a10ed6eb92 497 struct {
jbradshaw 0:e4a10ed6eb92 498 uint32_t serial : 12;
jbradshaw 0:e4a10ed6eb92 499 uint32_t part_id : 2;
jbradshaw 0:e4a10ed6eb92 500 uint32_t sample : 1;
jbradshaw 0:e4a10ed6eb92 501 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 502 uint32_t rev_id : 4;
jbradshaw 0:e4a10ed6eb92 503 uint32_t pattern : 4;
jbradshaw 0:e4a10ed6eb92 504 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 505 } bit;
jbradshaw 0:e4a10ed6eb92 506
jbradshaw 1:9490836294ea 507 } max30001_info_t;
jbradshaw 0:e4a10ed6eb92 508
jbradshaw 0:e4a10ed6eb92 509 /**
jbradshaw 0:e4a10ed6eb92 510 * @brief CNFG_GEN (0x10)
jbradshaw 0:e4a10ed6eb92 511 */
jbradshaw 1:9490836294ea 512 typedef union max30001_cnfg_gen_reg {
jbradshaw 0:e4a10ed6eb92 513 uint32_t all;
jbradshaw 0:e4a10ed6eb92 514 struct {
jbradshaw 0:e4a10ed6eb92 515 uint32_t rbiasn : 1;
jbradshaw 0:e4a10ed6eb92 516 uint32_t rbiasp : 1;
jbradshaw 0:e4a10ed6eb92 517 uint32_t rbiasv : 2;
jbradshaw 0:e4a10ed6eb92 518 uint32_t en_rbias : 2;
jbradshaw 0:e4a10ed6eb92 519 uint32_t vth : 2;
jbradshaw 0:e4a10ed6eb92 520 uint32_t imag : 3;
jbradshaw 0:e4a10ed6eb92 521 uint32_t ipol : 1;
jbradshaw 0:e4a10ed6eb92 522 uint32_t en_dcloff : 2;
jbradshaw 0:e4a10ed6eb92 523 uint32_t en_bloff : 2;
jbradshaw 0:e4a10ed6eb92 524 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 525 uint32_t en_pace : 1;
jbradshaw 0:e4a10ed6eb92 526 uint32_t en_bioz : 1;
jbradshaw 0:e4a10ed6eb92 527 uint32_t en_ecg : 1;
jbradshaw 0:e4a10ed6eb92 528 uint32_t fmstr : 2;
jbradshaw 0:e4a10ed6eb92 529 uint32_t en_ulp_lon : 2;
jbradshaw 0:e4a10ed6eb92 530 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 531 } bit;
jbradshaw 0:e4a10ed6eb92 532
jbradshaw 1:9490836294ea 533 } max30001_cnfg_gen_t;
jbradshaw 0:e4a10ed6eb92 534
jbradshaw 0:e4a10ed6eb92 535
jbradshaw 0:e4a10ed6eb92 536 /**
jbradshaw 0:e4a10ed6eb92 537 * @brief CNFG_CAL (0x12)
jbradshaw 0:e4a10ed6eb92 538 */
jbradshaw 1:9490836294ea 539 typedef union max30001_cnfg_cal_reg {
jbradshaw 0:e4a10ed6eb92 540 uint32_t all;
jbradshaw 0:e4a10ed6eb92 541 struct {
jbradshaw 0:e4a10ed6eb92 542 uint32_t thigh : 11;
jbradshaw 0:e4a10ed6eb92 543 uint32_t fifty : 1;
jbradshaw 0:e4a10ed6eb92 544 uint32_t fcal : 3;
jbradshaw 0:e4a10ed6eb92 545 uint32_t reserved1 : 5;
jbradshaw 0:e4a10ed6eb92 546 uint32_t vmag : 1;
jbradshaw 0:e4a10ed6eb92 547 uint32_t vmode : 1;
jbradshaw 0:e4a10ed6eb92 548 uint32_t en_vcal : 1;
jbradshaw 0:e4a10ed6eb92 549 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 550 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 551 } bit;
jbradshaw 0:e4a10ed6eb92 552
jbradshaw 1:9490836294ea 553 } max30001_cnfg_cal_t;
jbradshaw 0:e4a10ed6eb92 554
jbradshaw 0:e4a10ed6eb92 555 /**
jbradshaw 0:e4a10ed6eb92 556 * @brief CNFG_EMUX (0x14)
jbradshaw 0:e4a10ed6eb92 557 */
jbradshaw 1:9490836294ea 558 typedef union max30001_cnfg_emux_reg {
jbradshaw 0:e4a10ed6eb92 559 uint32_t all;
jbradshaw 0:e4a10ed6eb92 560 struct {
jbradshaw 0:e4a10ed6eb92 561 uint32_t reserved1 : 16;
jbradshaw 0:e4a10ed6eb92 562 uint32_t caln_sel : 2;
jbradshaw 0:e4a10ed6eb92 563 uint32_t calp_sel : 2;
jbradshaw 0:e4a10ed6eb92 564 uint32_t openn : 1;
jbradshaw 0:e4a10ed6eb92 565 uint32_t openp : 1;
jbradshaw 0:e4a10ed6eb92 566 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 567 uint32_t pol : 1;
jbradshaw 0:e4a10ed6eb92 568 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 569 } bit;
jbradshaw 0:e4a10ed6eb92 570
jbradshaw 1:9490836294ea 571 } max30001_cnfg_emux_t;
jbradshaw 0:e4a10ed6eb92 572
jbradshaw 0:e4a10ed6eb92 573
jbradshaw 0:e4a10ed6eb92 574 /**
jbradshaw 0:e4a10ed6eb92 575 * @brief CNFG_ECG (0x15)
jbradshaw 0:e4a10ed6eb92 576 */
jbradshaw 1:9490836294ea 577 typedef union max30001_cnfg_ecg_reg {
jbradshaw 0:e4a10ed6eb92 578 uint32_t all;
jbradshaw 0:e4a10ed6eb92 579 struct {
jbradshaw 0:e4a10ed6eb92 580 uint32_t reserved1 : 12;
jbradshaw 0:e4a10ed6eb92 581 uint32_t dlpf : 2;
jbradshaw 0:e4a10ed6eb92 582 uint32_t dhpf : 1;
jbradshaw 0:e4a10ed6eb92 583 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 584 uint32_t gain : 2;
jbradshaw 0:e4a10ed6eb92 585 uint32_t reserved3 : 4;
jbradshaw 0:e4a10ed6eb92 586 uint32_t rate : 2;
jbradshaw 0:e4a10ed6eb92 587
jbradshaw 0:e4a10ed6eb92 588 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 589 } bit;
jbradshaw 0:e4a10ed6eb92 590
jbradshaw 1:9490836294ea 591 } max30001_cnfg_ecg_t;
jbradshaw 0:e4a10ed6eb92 592
jbradshaw 0:e4a10ed6eb92 593 /**
jbradshaw 0:e4a10ed6eb92 594 * @brief CNFG_BMUX (0x17)
jbradshaw 0:e4a10ed6eb92 595 */
jbradshaw 1:9490836294ea 596 typedef union max30001_cnfg_bmux_reg {
jbradshaw 0:e4a10ed6eb92 597 uint32_t all;
jbradshaw 0:e4a10ed6eb92 598 struct {
jbradshaw 0:e4a10ed6eb92 599 uint32_t fbist : 2;
jbradshaw 0:e4a10ed6eb92 600 uint32_t reserved1 : 2;
jbradshaw 0:e4a10ed6eb92 601 uint32_t rmod : 3;
jbradshaw 0:e4a10ed6eb92 602 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 603 uint32_t rnom : 3;
jbradshaw 0:e4a10ed6eb92 604 uint32_t en_bist : 1;
jbradshaw 0:e4a10ed6eb92 605 uint32_t cg_mode : 2;
jbradshaw 0:e4a10ed6eb92 606 uint32_t reserved3 : 2;
jbradshaw 0:e4a10ed6eb92 607 uint32_t caln_sel : 2;
jbradshaw 0:e4a10ed6eb92 608 uint32_t calp_sel : 2;
jbradshaw 0:e4a10ed6eb92 609 uint32_t openn : 1;
jbradshaw 0:e4a10ed6eb92 610 uint32_t openp : 1;
jbradshaw 0:e4a10ed6eb92 611 uint32_t reserved4 : 2;
jbradshaw 1:9490836294ea 612 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 613 } bit;
jbradshaw 0:e4a10ed6eb92 614
jbradshaw 1:9490836294ea 615 } max30001_cnfg_bmux_t;
jbradshaw 0:e4a10ed6eb92 616
jbradshaw 0:e4a10ed6eb92 617 /**
jbradshaw 0:e4a10ed6eb92 618 * @brief CNFG_BIOZ (0x18)
jbradshaw 0:e4a10ed6eb92 619 */
jbradshaw 1:9490836294ea 620 typedef union max30001_bioz_reg {
jbradshaw 0:e4a10ed6eb92 621 uint32_t all;
jbradshaw 0:e4a10ed6eb92 622 struct {
jbradshaw 0:e4a10ed6eb92 623 uint32_t phoff : 4;
jbradshaw 0:e4a10ed6eb92 624 uint32_t cgmag : 3;
jbradshaw 0:e4a10ed6eb92 625 uint32_t cgmon : 1;
jbradshaw 0:e4a10ed6eb92 626 uint32_t fcgen : 4;
jbradshaw 0:e4a10ed6eb92 627 uint32_t dlpf : 2;
jbradshaw 0:e4a10ed6eb92 628 uint32_t dhpf : 2;
jbradshaw 0:e4a10ed6eb92 629 uint32_t gain : 2;
jbradshaw 0:e4a10ed6eb92 630 uint32_t reserved1 : 1;
jbradshaw 0:e4a10ed6eb92 631 uint32_t ext_rbias : 1;
jbradshaw 0:e4a10ed6eb92 632 uint32_t ahpf : 3;
jbradshaw 0:e4a10ed6eb92 633 uint32_t rate : 1;
jbradshaw 1:9490836294ea 634 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 635 } bit;
jbradshaw 0:e4a10ed6eb92 636
jbradshaw 1:9490836294ea 637 } max30001_cnfg_bioz_t;
jbradshaw 0:e4a10ed6eb92 638
jbradshaw 0:e4a10ed6eb92 639
jbradshaw 0:e4a10ed6eb92 640 /**
jbradshaw 0:e4a10ed6eb92 641 * @brief CNFG_PACE (0x1A)
jbradshaw 0:e4a10ed6eb92 642 */
jbradshaw 1:9490836294ea 643 typedef union max30001_cnfg_pace_reg {
jbradshaw 0:e4a10ed6eb92 644 uint32_t all;
jbradshaw 0:e4a10ed6eb92 645
jbradshaw 0:e4a10ed6eb92 646 struct {
jbradshaw 0:e4a10ed6eb92 647 uint32_t dacn : 4;
jbradshaw 0:e4a10ed6eb92 648 uint32_t dacp : 4;
jbradshaw 0:e4a10ed6eb92 649 uint32_t reserved1 : 4;
jbradshaw 0:e4a10ed6eb92 650 uint32_t aout : 2;
jbradshaw 0:e4a10ed6eb92 651 uint32_t aout_lbw : 1;
jbradshaw 0:e4a10ed6eb92 652 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 653 uint32_t gain : 3;
jbradshaw 0:e4a10ed6eb92 654 uint32_t gn_diff_off : 1;
jbradshaw 0:e4a10ed6eb92 655 uint32_t reserved3 : 3;
jbradshaw 0:e4a10ed6eb92 656 uint32_t pol : 1;
jbradshaw 0:e4a10ed6eb92 657 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 658 } bit;
jbradshaw 0:e4a10ed6eb92 659
jbradshaw 1:9490836294ea 660 } max30001_cnfg_pace_t;
jbradshaw 0:e4a10ed6eb92 661
jbradshaw 0:e4a10ed6eb92 662 /**
jbradshaw 0:e4a10ed6eb92 663 * @brief CNFG_RTOR1 (0x1D)
jbradshaw 0:e4a10ed6eb92 664 */
jbradshaw 1:9490836294ea 665 typedef union max30001_cnfg_rtor1_reg {
jbradshaw 0:e4a10ed6eb92 666 uint32_t all;
jbradshaw 0:e4a10ed6eb92 667 struct {
jbradshaw 0:e4a10ed6eb92 668 uint32_t reserved1 : 8;
jbradshaw 0:e4a10ed6eb92 669 uint32_t ptsf : 4;
jbradshaw 0:e4a10ed6eb92 670 uint32_t pavg : 2;
jbradshaw 0:e4a10ed6eb92 671 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 672 uint32_t en_rtor : 1;
jbradshaw 0:e4a10ed6eb92 673 uint32_t gain : 4;
jbradshaw 0:e4a10ed6eb92 674 uint32_t wndw : 4;
jbradshaw 1:9490836294ea 675 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 676 } bit;
jbradshaw 0:e4a10ed6eb92 677
jbradshaw 1:9490836294ea 678 } max30001_cnfg_rtor1_t;
jbradshaw 0:e4a10ed6eb92 679
jbradshaw 0:e4a10ed6eb92 680 /**
jbradshaw 0:e4a10ed6eb92 681 * @brief CNFG_RTOR2 (0x1E)
jbradshaw 0:e4a10ed6eb92 682 */
jbradshaw 1:9490836294ea 683 typedef union max30001_cnfg_rtor2_reg {
jbradshaw 0:e4a10ed6eb92 684 uint32_t all;
jbradshaw 0:e4a10ed6eb92 685 struct {
jbradshaw 0:e4a10ed6eb92 686 uint32_t reserved1 : 8;
jbradshaw 0:e4a10ed6eb92 687 uint32_t rhsf : 3;
jbradshaw 0:e4a10ed6eb92 688 uint32_t reserved2 : 1;
jbradshaw 0:e4a10ed6eb92 689 uint32_t ravg : 2;
jbradshaw 0:e4a10ed6eb92 690 uint32_t reserved3 : 2;
jbradshaw 0:e4a10ed6eb92 691 uint32_t hoff : 6;
jbradshaw 0:e4a10ed6eb92 692 uint32_t reserved4 : 2;
jbradshaw 0:e4a10ed6eb92 693 uint32_t reserved : 8;
jbradshaw 0:e4a10ed6eb92 694 } bit;
jbradshaw 0:e4a10ed6eb92 695
jbradshaw 1:9490836294ea 696 } max30001_cnfg_rtor2_t;
jbradshaw 0:e4a10ed6eb92 697
jbradshaw 0:e4a10ed6eb92 698 /*********************************************************************************/
jbradshaw 0:e4a10ed6eb92 699
jbradshaw 0:e4a10ed6eb92 700 typedef enum {
jbradshaw 1:9490836294ea 701 MAX30001_NO_INT = 0, ///< No interrupt
jbradshaw 1:9490836294ea 702 MAX30001_INT_B = 1, ///< INTB selected for interrupt
jbradshaw 1:9490836294ea 703 MAX30001_INT_2B = 2 ///< INT2B selected for interrupt
jbradshaw 0:e4a10ed6eb92 704 } max30001_intrpt_Location_t;
jbradshaw 0:e4a10ed6eb92 705
jbradshaw 0:e4a10ed6eb92 706 typedef enum {
jbradshaw 0:e4a10ed6eb92 707 MAX30001_INT_DISABLED = 0b00,
jbradshaw 0:e4a10ed6eb92 708 MAX30001_INT_CMOS = 0b01,
jbradshaw 0:e4a10ed6eb92 709 MAX30001_INT_ODN = 0b10,
jbradshaw 0:e4a10ed6eb92 710 MAX30001_INT_ODNR = 0b11
jbradshaw 0:e4a10ed6eb92 711 } max30001_intrpt_type_t;
jbradshaw 0:e4a10ed6eb92 712
jbradshaw 1:9490836294ea 713 typedef enum { ///< Input Polarity selection
jbradshaw 1:9490836294ea 714 MAX30001_NON_INV = 0, ///< Non-Inverted
jbradshaw 1:9490836294ea 715 MAX30001_INV = 1 ///< Inverted
jbradshaw 1:9490836294ea 716 } max30001_emux_pol_t;
jbradshaw 0:e4a10ed6eb92 717
jbradshaw 1:9490836294ea 718 typedef enum { ///< OPENP and OPENN setting
jbradshaw 1:9490836294ea 719 MAX30001_ECG_CON_AFE = 0, ///< ECGx is connected to AFE channel
jbradshaw 1:9490836294ea 720 MAX30001_ECG_ISO_AFE = 1 ///< ECGx is isolated from AFE channel
jbradshaw 1:9490836294ea 721 } max30001_emux_openx_t;
jbradshaw 0:e4a10ed6eb92 722
jbradshaw 1:9490836294ea 723 typedef enum { ///< EMUX_CALP_SEL & EMUX_CALN_SEL
jbradshaw 1:9490836294ea 724 MAX30001_NO_CAL_SIG = 0b00, ///< No calibration signal is applied
jbradshaw 1:9490836294ea 725 MAX30001_INPT_VMID = 0b01, ///< Input is connected to VMID
jbradshaw 1:9490836294ea 726 MAX30001_INPT_VCALP = 0b10, ///< Input is connected to VCALP
jbradshaw 1:9490836294ea 727 MAX30001_INPT_VCALN = 0b11 ///< Input is connected to VCALN
jbradshaw 1:9490836294ea 728 } max30001_emux_calx_sel_t;
jbradshaw 0:e4a10ed6eb92 729
jbradshaw 1:9490836294ea 730 typedef enum { ///< EN_ECG, EN_BIOZ, EN_PACE
jbradshaw 1:9490836294ea 731 MAX30001_CHANNEL_DISABLED = 0b0,
jbradshaw 0:e4a10ed6eb92 732 MAX30001_CHANNEL_ENABLED = 0b1
jbradshaw 1:9490836294ea 733 } max30001_en_feature_t;
jbradshaw 0:e4a10ed6eb92 734
jbradshaw 0:e4a10ed6eb92 735 /*********************************************************************************/
jbradshaw 0:e4a10ed6eb92 736 // Data
jbradshaw 1:9490836294ea 737 uint32_t max30001_ECG_FIFO_buffer[32]; ///< (303 for internal test)
jbradshaw 1:9490836294ea 738 uint32_t max30001_BIOZ_FIFO_buffer[8]; ///< (303 for internal test)
jbradshaw 0:e4a10ed6eb92 739
jbradshaw 1:9490836294ea 740 uint32_t max30001_PACE[18]; ///< Pace Data 0-5
jbradshaw 0:e4a10ed6eb92 741
jbradshaw 1:9490836294ea 742 uint32_t max30001_RtoR_data; ///< This holds the RtoR data
jbradshaw 0:e4a10ed6eb92 743
jbradshaw 1:9490836294ea 744 uint32_t max30001_DCLeadOff; ///< This holds the LeadOff data, Last 4 bits give
jbradshaw 1:9490836294ea 745 ///< the status, BIT3=LOFF_PH, BIT2=LOFF_PL,
jbradshaw 1:9490836294ea 746 ///< BIT1=LOFF_NH, BIT0=LOFF_NL
jbradshaw 1:9490836294ea 747 ///< 8th and 9th bits tell Lead off is due to ECG or BIOZ.
jbradshaw 1:9490836294ea 748 ///< 0b01 = ECG Lead Off and 0b10 = BIOZ Lead off
jbradshaw 0:e4a10ed6eb92 749
jbradshaw 1:9490836294ea 750 uint32_t max30001_ACLeadOff; ///< This gives the state of the BIOZ AC Lead Off
jbradshaw 1:9490836294ea 751 ///< state. BIT 1 = BOVER, BIT 0 = BUNDR
jbradshaw 0:e4a10ed6eb92 752
jbradshaw 1:9490836294ea 753 uint32_t max30001_bcgmon; ///< This holds the BCGMON data, BIT 1 = BCGMP, BIT0 =
jbradshaw 1:9490836294ea 754 ///< BCGMN
jbradshaw 0:e4a10ed6eb92 755
jbradshaw 1:9490836294ea 756 uint32_t max30001_LeadOn; ///< This holds the LeadOn data, BIT1 = BIOZ Lead ON,
jbradshaw 1:9490836294ea 757 ///< BIT0 = ECG Lead ON, BIT8= Lead On Status Bit
jbradshaw 0:e4a10ed6eb92 758
jbradshaw 1:9490836294ea 759 uint32_t max30001_timeout; ///< If the PLL does not respond, timeout and get out.
jbradshaw 0:e4a10ed6eb92 760
jbradshaw 1:9490836294ea 761 typedef struct { ///< Creating a structure for BLE data
jbradshaw 0:e4a10ed6eb92 762 int16_t R2R;
jbradshaw 0:e4a10ed6eb92 763 int16_t fmstr;
jbradshaw 1:9490836294ea 764 } max30001_bledata_t;
jbradshaw 0:e4a10ed6eb92 765
jbradshaw 1:9490836294ea 766 max30001_bledata_t hspValMax30001; // R2R, FMSTR
jbradshaw 1:9490836294ea 767
jbradshaw 1:9490836294ea 768 max30001_status_t global_status;
jbradshaw 0:e4a10ed6eb92 769
jbradshaw 0:e4a10ed6eb92 770 /**
jbradshaw 0:e4a10ed6eb92 771 * @brief Constructor that accepts pin names for the SPI interface
jbradshaw 0:e4a10ed6eb92 772 * @param spi pointer to the mbed SPI object
jbradshaw 0:e4a10ed6eb92 773 */
jbradshaw 0:e4a10ed6eb92 774 MAX30001(SPI *spi);
jbradshaw 0:e4a10ed6eb92 775
jbradshaw 0:e4a10ed6eb92 776 /**
jbradshaw 0:e4a10ed6eb92 777 * @brief Constructor that accepts pin names for the SPI interface
jbradshaw 0:e4a10ed6eb92 778 * @param mosi master out slave in pin name
jbradshaw 0:e4a10ed6eb92 779 * @param miso master in slave out pin name
jbradshaw 0:e4a10ed6eb92 780 * @param sclk serial clock pin name
jbradshaw 0:e4a10ed6eb92 781 * @param cs chip select pin name
jbradshaw 0:e4a10ed6eb92 782 */
jbradshaw 0:e4a10ed6eb92 783 MAX30001(PinName mosi, PinName miso, PinName sclk, PinName cs);
jbradshaw 0:e4a10ed6eb92 784
jbradshaw 0:e4a10ed6eb92 785 /**
jbradshaw 0:e4a10ed6eb92 786 * MAX30001 destructor
jbradshaw 0:e4a10ed6eb92 787 */
jbradshaw 0:e4a10ed6eb92 788 ~MAX30001(void);
jbradshaw 1:9490836294ea 789
jbradshaw 1:9490836294ea 790 /**
jbradshaw 1:9490836294ea 791 * @brief This function is MAXIM Proprietary. It channels the RTC crystal
jbradshaw 1:9490836294ea 792 * @brief clock to P1.7. Thus providing 32768Hz on FCLK pin of the MAX30001-3
jbradshaw 1:9490836294ea 793 */
jbradshaw 1:9490836294ea 794 void FCLK_MaximOnly(void);
jbradshaw 1:9490836294ea 795
jbradshaw 0:e4a10ed6eb92 796 /**
jbradshaw 0:e4a10ed6eb92 797 * @brief This function sets up the Resistive Bias mode and also selects the master clock frequency.
jbradshaw 0:e4a10ed6eb92 798 * @brief Uses Register: CNFG_GEN-0x10
jbradshaw 0:e4a10ed6eb92 799 * @param En_rbias: Enable and Select Resitive Lead Bias Mode
jbradshaw 0:e4a10ed6eb92 800 * @param Rbiasv: Resistive Bias Mode Value Selection
jbradshaw 0:e4a10ed6eb92 801 * @param Rbiasp: Enables Resistive Bias on Positive Input
jbradshaw 0:e4a10ed6eb92 802 * @param Rbiasn: Enables Resistive Bias on Negative Input
jbradshaw 0:e4a10ed6eb92 803 * @param Fmstr: Selects Master Clock Frequency
jbradshaw 0:e4a10ed6eb92 804 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 805 *
jbradshaw 0:e4a10ed6eb92 806 */
jbradshaw 1:9490836294ea 807 int Rbias_FMSTR_Init(uint8_t En_rbias, uint8_t Rbiasv,
jbradshaw 0:e4a10ed6eb92 808 uint8_t Rbiasp, uint8_t Rbiasn, uint8_t Fmstr);
jbradshaw 0:e4a10ed6eb92 809
jbradshaw 0:e4a10ed6eb92 810 /**
jbradshaw 0:e4a10ed6eb92 811 * @brief This function uses sets up the calibration signal internally. If it is desired to use the internal signal, then
jbradshaw 0:e4a10ed6eb92 812 * @brief this function must be called and the registers set, prior to setting the CALP_SEL and CALN_SEL in the ECG_InitStart
jbradshaw 0:e4a10ed6eb92 813 * @brief and BIOZ_InitStart functions.
jbradshaw 0:e4a10ed6eb92 814 * @brief Uses Register: CNFG_CAL-0x12
jbradshaw 0:e4a10ed6eb92 815 * @param En_Vcal: Calibration Source (VCALP and VCALN) Enable
jbradshaw 0:e4a10ed6eb92 816 * @param Vmode: Calibration Source Mode Selection
jbradshaw 0:e4a10ed6eb92 817 * @param Vmag: Calibration Source Magnitude Selection (VMAG)
jbradshaw 0:e4a10ed6eb92 818 * @param Fcal: Calibration Source Frequency Selection (FCAL)
jbradshaw 0:e4a10ed6eb92 819 * @param Thigh: Calibration Source Time High Selection
jbradshaw 0:e4a10ed6eb92 820 * @param Fifty: Calibration Source Duty Cycle Mode Selection
jbradshaw 0:e4a10ed6eb92 821 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 822 *
jbradshaw 0:e4a10ed6eb92 823 */
jbradshaw 1:9490836294ea 824 int CAL_InitStart(uint8_t En_Vcal, uint8_t Vmode, uint8_t Vmag,
jbradshaw 0:e4a10ed6eb92 825 uint8_t Fcal, uint16_t Thigh, uint8_t Fifty);
jbradshaw 0:e4a10ed6eb92 826
jbradshaw 0:e4a10ed6eb92 827 /**
jbradshaw 0:e4a10ed6eb92 828 * @brief This function disables the VCAL signal
jbradshaw 0:e4a10ed6eb92 829 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 830 */
jbradshaw 1:9490836294ea 831 int CAL_Stop(void);
jbradshaw 0:e4a10ed6eb92 832
jbradshaw 0:e4a10ed6eb92 833 /**
jbradshaw 0:e4a10ed6eb92 834 * @brief This function handles the assignment of the two interrupt pins (INTB & INT2B) with various
jbradshaw 0:e4a10ed6eb92 835 * @brief functions/behaviors of the MAX30001. Also, each pin can be configured for different drive capability.
jbradshaw 0:e4a10ed6eb92 836 * @brief Uses Registers: EN_INT-0x02 and EN_INT2-0x03.
jbradshaw 0:e4a10ed6eb92 837 * @param max30001_intrpt_Locatio_t <argument>: All the arguments with the aforementioned enumeration essentially
jbradshaw 0:e4a10ed6eb92 838 * can be configured to generate an interrupt on either INTB or INT2B or NONE.
jbradshaw 0:e4a10ed6eb92 839 * @param max30001_intrpt_type_t intb_Type: INTB Port Type (EN_INT Selections).
jbradshaw 0:e4a10ed6eb92 840 * @param max30001_intrpt_type _t int2b_Type: INT2B Port Type (EN_INT2 Selections)
jbradshaw 0:e4a10ed6eb92 841 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 842 *
jbradshaw 0:e4a10ed6eb92 843 */
jbradshaw 1:9490836294ea 844 int INT_assignment(max30001_intrpt_Location_t en_enint_loc, max30001_intrpt_Location_t en_eovf_loc, max30001_intrpt_Location_t en_fstint_loc,
jbradshaw 0:e4a10ed6eb92 845 max30001_intrpt_Location_t en_dcloffint_loc, max30001_intrpt_Location_t en_bint_loc, max30001_intrpt_Location_t en_bovf_loc,
jbradshaw 0:e4a10ed6eb92 846 max30001_intrpt_Location_t en_bover_loc, max30001_intrpt_Location_t en_bundr_loc, max30001_intrpt_Location_t en_bcgmon_loc,
jbradshaw 0:e4a10ed6eb92 847 max30001_intrpt_Location_t en_pint_loc, max30001_intrpt_Location_t en_povf_loc, max30001_intrpt_Location_t en_pedge_loc,
jbradshaw 0:e4a10ed6eb92 848 max30001_intrpt_Location_t en_lonint_loc, max30001_intrpt_Location_t en_rrint_loc, max30001_intrpt_Location_t en_samp_loc,
jbradshaw 0:e4a10ed6eb92 849 max30001_intrpt_type_t intb_Type, max30001_intrpt_type_t int2b_Type);
jbradshaw 0:e4a10ed6eb92 850
jbradshaw 0:e4a10ed6eb92 851
jbradshaw 0:e4a10ed6eb92 852
jbradshaw 0:e4a10ed6eb92 853 /**
jbradshaw 0:e4a10ed6eb92 854 * @brief For MAX30001/3 ONLY
jbradshaw 0:e4a10ed6eb92 855 * @brief This function sets up the MAX30001 for the ECG measurements.
jbradshaw 0:e4a10ed6eb92 856 * @brief Registers used: CNFG_EMUX, CNFG_GEN, MNGR_INT, CNFG_ECG.
jbradshaw 0:e4a10ed6eb92 857 * @param En_ecg: ECG Channel Enable <CNFG_GEN register bits>
jbradshaw 0:e4a10ed6eb92 858 * @param Openp: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits>
jbradshaw 0:e4a10ed6eb92 859 * @param Openn: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits>
jbradshaw 0:e4a10ed6eb92 860 * @param Calp_sel: ECGP Calibration Selection <CNFG_EMUX register bits>
jbradshaw 0:e4a10ed6eb92 861 * @param Caln_sel: ECGN Calibration Selection <CNFG_EMUX register bits>
jbradshaw 0:e4a10ed6eb92 862 * @param E_fit: ECG FIFO Interrupt Threshold (issues EINT based on number of unread FIFO records) <CNFG_GEN register bits>
jbradshaw 0:e4a10ed6eb92 863 * @param Clr_rrint: RTOR R Detect Interrupt (RRINT) Clear Behavior <CNFG_GEN register bits>
jbradshaw 0:e4a10ed6eb92 864 * @param Rate: ECG Data Rate
jbradshaw 0:e4a10ed6eb92 865 * @param Gain: ECG Channel Gain Setting
jbradshaw 0:e4a10ed6eb92 866 * @param Dhpf: ECG Channel Digital High Pass Filter Cutoff Frequency
jbradshaw 0:e4a10ed6eb92 867 * @param Dlpf: ECG Channel Digital Low Pass Filter Cutoff Frequency
jbradshaw 0:e4a10ed6eb92 868 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 869 *
jbradshaw 0:e4a10ed6eb92 870 */
jbradshaw 1:9490836294ea 871 int ECG_InitStart(uint8_t En_ecg, uint8_t Openp, uint8_t Openn,
jbradshaw 1:9490836294ea 872 uint8_t Pol, uint8_t Calp_sel, uint8_t Caln_sel,
jbradshaw 1:9490836294ea 873 uint8_t E_fit, uint8_t Rate, uint8_t Gain,
jbradshaw 1:9490836294ea 874 uint8_t Dhpf, uint8_t Dlpf);
jbradshaw 0:e4a10ed6eb92 875
jbradshaw 0:e4a10ed6eb92 876 /**
jbradshaw 0:e4a10ed6eb92 877 * @brief For MAX30001/3 ONLY
jbradshaw 0:e4a10ed6eb92 878 * @brief This function enables the Fast mode feature of the ECG.
jbradshaw 0:e4a10ed6eb92 879 * @brief Registers used: MNGR_INT-0x04, MNGR_DYN-0x05
jbradshaw 0:e4a10ed6eb92 880 * @param Clr_Fast: FAST MODE Interrupt Clear Behavior <MNGR_INT Register>
jbradshaw 0:e4a10ed6eb92 881 * @param Fast: ECG Channel Fast Recovery Mode Selection (ECG High Pass Filter Bypass) <MNGR_DYN Register>
jbradshaw 0:e4a10ed6eb92 882 * @param Fast_Th: Automatic Fast Recovery Threshold
jbradshaw 0:e4a10ed6eb92 883 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 884 *
jbradshaw 0:e4a10ed6eb92 885 */
jbradshaw 1:9490836294ea 886 int ECGFast_Init(uint8_t Clr_Fast, uint8_t Fast, uint8_t Fast_Th);
jbradshaw 0:e4a10ed6eb92 887
jbradshaw 0:e4a10ed6eb92 888 /**
jbradshaw 0:e4a10ed6eb92 889 * @brief For MAX30001/3 ONLY
jbradshaw 0:e4a10ed6eb92 890 * @brief This function disables the ECG.
jbradshaw 0:e4a10ed6eb92 891 * @brief Uses Register CNFG_GEN-0x10.
jbradshaw 0:e4a10ed6eb92 892 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 893 *
jbradshaw 0:e4a10ed6eb92 894 */
jbradshaw 1:9490836294ea 895 int Stop_ECG(void);
jbradshaw 0:e4a10ed6eb92 896
jbradshaw 0:e4a10ed6eb92 897 /**
jbradshaw 0:e4a10ed6eb92 898 * @brief For MAX30001 ONLY
jbradshaw 0:e4a10ed6eb92 899 * @brief This function sets up the MAX30001 for pace signal detection.
jbradshaw 0:e4a10ed6eb92 900 * @brief If both PACE and BIOZ are turned ON, then make sure Fcgen is set for 80K or 40K in the
jbradshaw 0:e4a10ed6eb92 901 * @brief max30001_BIOZ_InitStart() function. However, if Only PACE is on but BIOZ off, then Fcgen can be set
jbradshaw 0:e4a10ed6eb92 902 * @brief for 80K only, in the max30001_BIOZ_InitStart() function
jbradshaw 0:e4a10ed6eb92 903 * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0x37, CNFG_PACE-0x1A.
jbradshaw 0:e4a10ed6eb92 904 * @param En_pace : PACE Channel Enable <CNFG_GEN Register>
jbradshaw 0:e4a10ed6eb92 905 * @param Clr_pedge : PACE Edge Detect Interrupt (PEDGE) Clear Behavior <MNGR_INT Register>
jbradshaw 0:e4a10ed6eb92 906 * @param Pol: PACE Input Polarity Selection <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 907 * @param Gn_diff_off: PACE Differentiator Mode <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 908 * @param Gain: PACE Channel Gain Selection <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 909 * @param Aout_lbw: PACE Analog Output Buffer Bandwidth Mode <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 910 * @param Aout: PACE Single Ended Analog Output Buffer Signal Monitoring Selection <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 911 * @param Dacp (4bits): PACE Detector Positive Comparator Threshold <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 912 * @param Dacn(4bits): PACE Detector Negative Comparator Threshold <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 913 * @returns 0-if no error. A non-zero value indicates an error <CNFG_PACE Register>
jbradshaw 0:e4a10ed6eb92 914 *
jbradshaw 0:e4a10ed6eb92 915 */
jbradshaw 1:9490836294ea 916 int PACE_InitStart(uint8_t En_pace, uint8_t Clr_pedge, uint8_t Pol,
jbradshaw 0:e4a10ed6eb92 917 uint8_t Gn_diff_off, uint8_t Gain,
jbradshaw 0:e4a10ed6eb92 918 uint8_t Aout_lbw, uint8_t Aout, uint8_t Dacp,
jbradshaw 0:e4a10ed6eb92 919 uint8_t Dacn);
jbradshaw 0:e4a10ed6eb92 920
jbradshaw 0:e4a10ed6eb92 921 /**
jbradshaw 0:e4a10ed6eb92 922 *@brief For MAX30001 ONLY
jbradshaw 0:e4a10ed6eb92 923 *@param This function disables the PACE. Uses Register CNFG_GEN-0x10.
jbradshaw 0:e4a10ed6eb92 924 *@returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 925 *
jbradshaw 0:e4a10ed6eb92 926 */
jbradshaw 1:9490836294ea 927 int Stop_PACE(void);
jbradshaw 0:e4a10ed6eb92 928
jbradshaw 0:e4a10ed6eb92 929 /**
jbradshaw 0:e4a10ed6eb92 930 * @brief For MAX30001/2 ONLY
jbradshaw 0:e4a10ed6eb92 931 * @brief This function sets up the MAX30001 for BIOZ measurement.
jbradshaw 0:e4a10ed6eb92 932 * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0X10, CNFG_BMUX-0x17,CNFG_BIOZ-0x18.
jbradshaw 0:e4a10ed6eb92 933 * @param En_bioz: BIOZ Channel Enable <CNFG_GEN Register>
jbradshaw 0:e4a10ed6eb92 934 * @param Openp: Open the BIP Input Switch <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 935 * @param Openn: Open the BIN Input Switch <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 936 * @param Calp_sel: BIP Calibration Selection <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 937 * @param Caln_sel: BIN Calibration Selection <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 938 * @param CG_mode: BIOZ Current Generator Mode Selection <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 939 * @param B_fit: BIOZ FIFO Interrupt Threshold (issues BINT based on number of unread FIFO records) <MNGR_INT Register>
jbradshaw 0:e4a10ed6eb92 940 * @param Rate: BIOZ Data Rate <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 941 * @param Ahpf: BIOZ/PACE Channel Analog High Pass Filter Cutoff Frequency and Bypass <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 942 * @param Ext_rbias: External Resistor Bias Enable <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 943 * @param Gain: BIOZ Channel Gain Setting <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 944 * @param Dhpf: BIOZ Channel Digital High Pass Filter Cutoff Frequency <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 945 * @param Dlpf: BIOZ Channel Digital Low Pass Filter Cutoff Frequency <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 946 * @param Fcgen: BIOZ Current Generator Modulation Frequency <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 947 * @param Cgmon: BIOZ Current Generator Monitor <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 948 * @param Cgmag: BIOZ Current Generator Magnitude <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 949 * @param Phoff: BIOZ Current Generator Modulation Phase Offset <CNFG_BIOZ Register>
jbradshaw 0:e4a10ed6eb92 950 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 951 *
jbradshaw 0:e4a10ed6eb92 952 */
jbradshaw 1:9490836294ea 953 int BIOZ_InitStart(uint8_t En_bioz, uint8_t Openp, uint8_t Openn,
jbradshaw 0:e4a10ed6eb92 954 uint8_t Calp_sel, uint8_t Caln_sel,
jbradshaw 0:e4a10ed6eb92 955 uint8_t CG_mode,
jbradshaw 0:e4a10ed6eb92 956 /* uint8_t En_bioz,*/ uint8_t B_fit, uint8_t Rate,
jbradshaw 0:e4a10ed6eb92 957 uint8_t Ahpf, uint8_t Ext_rbias, uint8_t Gain,
jbradshaw 0:e4a10ed6eb92 958 uint8_t Dhpf, uint8_t Dlpf, uint8_t Fcgen,
jbradshaw 0:e4a10ed6eb92 959 uint8_t Cgmon, uint8_t Cgmag, uint8_t Phoff);
jbradshaw 0:e4a10ed6eb92 960
jbradshaw 0:e4a10ed6eb92 961 /**
jbradshaw 0:e4a10ed6eb92 962 * @brief For MAX30001/2 ONLY
jbradshaw 0:e4a10ed6eb92 963 * @brief This function disables the BIOZ. Uses Register CNFG_GEN-0x10.
jbradshaw 0:e4a10ed6eb92 964 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 965 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 966 *
jbradshaw 0:e4a10ed6eb92 967 */
jbradshaw 1:9490836294ea 968 int Stop_BIOZ(void);
jbradshaw 0:e4a10ed6eb92 969
jbradshaw 0:e4a10ed6eb92 970 /**
jbradshaw 0:e4a10ed6eb92 971 * @brief For MAX30001/2 ONLY
jbradshaw 0:e4a10ed6eb92 972 * @brief BIOZ modulated Resistance Built-in-Self-Test, Registers used: CNFG_BMUX-0x17
jbradshaw 0:e4a10ed6eb92 973 * @param En_bist: Enable Modulated Resistance Built-in-Self-test <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 974 * @param Rnom: BIOZ RMOD BIST Nominal Resistance Selection <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 975 * @param Rmod: BIOZ RMOD BIST Modulated Resistance Selection <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 976 * @param Fbist: BIOZ RMOD BIST Frequency Selection <CNFG_BMUX Register>
jbradshaw 0:e4a10ed6eb92 977 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 978 *
jbradshaw 0:e4a10ed6eb92 979 */
jbradshaw 1:9490836294ea 980 int BIOZ_InitBist(uint8_t En_bist, uint8_t Rnom, uint8_t Rmod,
jbradshaw 0:e4a10ed6eb92 981 uint8_t Fbist);
jbradshaw 0:e4a10ed6eb92 982
jbradshaw 0:e4a10ed6eb92 983 /**
jbradshaw 0:e4a10ed6eb92 984 * @brief For MAX30001/3/4 ONLY
jbradshaw 0:e4a10ed6eb92 985 * @brief Sets up the device for RtoR measurement
jbradshaw 0:e4a10ed6eb92 986 * @param EN_rtor: ECG RTOR Detection Enable <RTOR1 Register>
jbradshaw 0:e4a10ed6eb92 987 * @param Wndw: R to R Window Averaging (Window Width = RTOR_WNDW[3:0]*8mS) <RTOR1 Register>
jbradshaw 0:e4a10ed6eb92 988 * @param Gain: R to R Gain (where Gain = 2^RTOR_GAIN[3:0], plus an auto-scale option) <RTOR1 Register>
jbradshaw 0:e4a10ed6eb92 989 * @param Pavg: R to R Peak Averaging Weight Factor <RTOR1 Register>
jbradshaw 0:e4a10ed6eb92 990 * @param Ptsf: R to R Peak Threshold Scaling Factor <RTOR1 Register>
jbradshaw 0:e4a10ed6eb92 991 * @param Hoff: R to R minimum Hold Off <RTOR2 Register>
jbradshaw 0:e4a10ed6eb92 992 * @param Ravg: R to R Interval Averaging Weight Factor <RTOR2 Register>
jbradshaw 0:e4a10ed6eb92 993 * @param Rhsf: R to R Interval Hold Off Scaling Factor <RTOR2 Register>
jbradshaw 0:e4a10ed6eb92 994 * @param Clr_rrint: RTOR Detect Interrupt Clear behaviour <MNGR_INT Register>
jbradshaw 0:e4a10ed6eb92 995 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 996 *
jbradshaw 0:e4a10ed6eb92 997 */
jbradshaw 1:9490836294ea 998 int RtoR_InitStart(uint8_t En_rtor, uint8_t Wndw, uint8_t Gain,
jbradshaw 0:e4a10ed6eb92 999 uint8_t Pavg, uint8_t Ptsf, uint8_t Hoff,
jbradshaw 0:e4a10ed6eb92 1000 uint8_t Ravg, uint8_t Rhsf, uint8_t Clr_rrint);
jbradshaw 0:e4a10ed6eb92 1001
jbradshaw 0:e4a10ed6eb92 1002 /**
jbradshaw 0:e4a10ed6eb92 1003 * @brief For MAX30001/3/4 ONLY
jbradshaw 0:e4a10ed6eb92 1004 * @brief This function disables the RtoR. Uses Register CNFG_RTOR1-0x1D
jbradshaw 0:e4a10ed6eb92 1005 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1006 *
jbradshaw 0:e4a10ed6eb92 1007 */
jbradshaw 1:9490836294ea 1008 int Stop_RtoR(void);
jbradshaw 0:e4a10ed6eb92 1009
jbradshaw 0:e4a10ed6eb92 1010 /**
jbradshaw 0:e4a10ed6eb92 1011 * @brief This is a function that waits for the PLL to lock; once a lock is achieved it exits out. (For convenience only)
jbradshaw 0:e4a10ed6eb92 1012 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1013 *
jbradshaw 0:e4a10ed6eb92 1014 */
jbradshaw 1:9490836294ea 1015 int PLL_lock(void);
jbradshaw 0:e4a10ed6eb92 1016
jbradshaw 0:e4a10ed6eb92 1017 /**
jbradshaw 0:e4a10ed6eb92 1018 * @brief This function causes the MAX30001 to reset. Uses Register SW_RST-0x08
jbradshaw 0:e4a10ed6eb92 1019 * @return 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1020 *
jbradshaw 0:e4a10ed6eb92 1021 */
jbradshaw 1:9490836294ea 1022 int sw_rst(void);
jbradshaw 0:e4a10ed6eb92 1023
jbradshaw 0:e4a10ed6eb92 1024 /**
jbradshaw 0:e4a10ed6eb92 1025 * @brief This function provides a SYNCH operation. Uses Register SYCNH-0x09. Please refer to the data sheet for
jbradshaw 0:e4a10ed6eb92 1026 * @brief the details on how to use this.
jbradshaw 0:e4a10ed6eb92 1027 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1028 *
jbradshaw 0:e4a10ed6eb92 1029 */
jbradshaw 1:9490836294ea 1030 int synch(void);
jbradshaw 0:e4a10ed6eb92 1031
jbradshaw 0:e4a10ed6eb92 1032 /**
jbradshaw 0:e4a10ed6eb92 1033 * @brief This function performs a FIFO Reset. Uses Register FIFO_RST-0x0A. Please refer to the data sheet
jbradshaw 0:e4a10ed6eb92 1034 * @brief for the details on how to use this.
jbradshaw 0:e4a10ed6eb92 1035 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1036 */
jbradshaw 1:9490836294ea 1037 int fifo_rst(void);
jbradshaw 0:e4a10ed6eb92 1038
jbradshaw 0:e4a10ed6eb92 1039 /**
jbradshaw 0:e4a10ed6eb92 1040 *
jbradshaw 0:e4a10ed6eb92 1041 * @brief This is a callback function which collects all the data from the ECG, BIOZ, PACE and RtoR. It also handles
jbradshaw 0:e4a10ed6eb92 1042 * @brief Lead On/Off. This function is passed through the argument of max30001_COMMinit().
jbradshaw 0:e4a10ed6eb92 1043 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1044 *
jbradshaw 0:e4a10ed6eb92 1045 */
jbradshaw 1:9490836294ea 1046 int int_handler(void);
jbradshaw 0:e4a10ed6eb92 1047
jbradshaw 0:e4a10ed6eb92 1048 /**
jbradshaw 0:e4a10ed6eb92 1049 * @brief This is function called from the max30001_int_handler() function and processes all the ECG, BIOZ, PACE
jbradshaw 0:e4a10ed6eb92 1050 * @brief and the RtoR data and sticks them in appropriate arrays and variables each unsigned 32 bits.
jbradshaw 0:e4a10ed6eb92 1051 * @param ECG data will be in the array (input): max30001_ECG_FIFO_buffer[]
jbradshaw 0:e4a10ed6eb92 1052 * @param Pace data will be in the array (input): max30001_PACE[]
jbradshaw 0:e4a10ed6eb92 1053 * @param RtoRdata will be in the variable (input): max30001_RtoR_data
jbradshaw 0:e4a10ed6eb92 1054 * @param BIOZ data will be in the array (input): max30001_BIOZ_FIFO_buffer[]
jbradshaw 0:e4a10ed6eb92 1055 * @param global max30001_ECG_FIFO_buffer[]
jbradshaw 0:e4a10ed6eb92 1056 * @param global max30001_PACE[]
jbradshaw 0:e4a10ed6eb92 1057 * @param global max30001_BIOZ_FIFO_buffer[]
jbradshaw 0:e4a10ed6eb92 1058 * @param global max30001_RtoR_data
jbradshaw 0:e4a10ed6eb92 1059 * @param global max30001_DCLeadOff
jbradshaw 0:e4a10ed6eb92 1060 * @param global max30001_ACLeadOff
jbradshaw 0:e4a10ed6eb92 1061 * @param global max30001_LeadON
jbradshaw 0:e4a10ed6eb92 1062 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1063 *
jbradshaw 0:e4a10ed6eb92 1064 */
jbradshaw 1:9490836294ea 1065 int FIFO_LeadONOff_Read(void);
jbradshaw 0:e4a10ed6eb92 1066
jbradshaw 0:e4a10ed6eb92 1067 /**
jbradshaw 0:e4a10ed6eb92 1068 * @brief This function allows writing to a register.
jbradshaw 0:e4a10ed6eb92 1069 * @param addr: Address of the register to write to
jbradshaw 0:e4a10ed6eb92 1070 * @param data: 24-bit data read from the register.
jbradshaw 0:e4a10ed6eb92 1071 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1072 *
jbradshaw 0:e4a10ed6eb92 1073 */
jbradshaw 1:9490836294ea 1074 int reg_write(MAX30001_REG_map_t addr, uint32_t data);
jbradshaw 0:e4a10ed6eb92 1075
jbradshaw 0:e4a10ed6eb92 1076 /**
jbradshaw 0:e4a10ed6eb92 1077 * @brief This function allows reading from a register
jbradshaw 0:e4a10ed6eb92 1078 * @param addr: Address of the register to read from.
jbradshaw 0:e4a10ed6eb92 1079 * @param *return_data: pointer to the value read from the register.
jbradshaw 0:e4a10ed6eb92 1080 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1081 *
jbradshaw 0:e4a10ed6eb92 1082 */
jbradshaw 1:9490836294ea 1083 int reg_read(MAX30001_REG_map_t addr, uint32_t *return_data);
jbradshaw 0:e4a10ed6eb92 1084
jbradshaw 0:e4a10ed6eb92 1085 /**
jbradshaw 0:e4a10ed6eb92 1086 * @brief This function enables the DC Lead Off detection. Either ECG or BIOZ can be detected, one at a time.
jbradshaw 0:e4a10ed6eb92 1087 * @brief Registers Used: CNFG_GEN-0x10
jbradshaw 0:e4a10ed6eb92 1088 * @param En_dcloff: BIOZ Digital Lead Off Detection Enable
jbradshaw 0:e4a10ed6eb92 1089 * @param Ipol: DC Lead Off Current Polarity (if current sources are enabled/connected)
jbradshaw 0:e4a10ed6eb92 1090 * @param Imag: DC Lead off current Magnitude Selection
jbradshaw 0:e4a10ed6eb92 1091 * @param Vth: DC Lead Off Voltage Threshold Selection
jbradshaw 0:e4a10ed6eb92 1092 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1093 *
jbradshaw 0:e4a10ed6eb92 1094 */
jbradshaw 1:9490836294ea 1095 int Enable_DcLeadOFF_Init(int8_t En_dcloff, int8_t Ipol, int8_t Imag,
jbradshaw 0:e4a10ed6eb92 1096 int8_t Vth);
jbradshaw 0:e4a10ed6eb92 1097
jbradshaw 0:e4a10ed6eb92 1098 /**
jbradshaw 0:e4a10ed6eb92 1099 * @brief This function disables the DC Lead OFF feature, whichever is active.
jbradshaw 0:e4a10ed6eb92 1100 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1101 *
jbradshaw 0:e4a10ed6eb92 1102 */
jbradshaw 1:9490836294ea 1103 int Disable_DcLeadOFF(void);
jbradshaw 0:e4a10ed6eb92 1104
jbradshaw 0:e4a10ed6eb92 1105 /**
jbradshaw 0:e4a10ed6eb92 1106 * @brief This function sets up the BIOZ for AC Lead Off test.
jbradshaw 0:e4a10ed6eb92 1107 * @brief Registers Used: CNFG_GEN-0x10, MNGR_DYN-0x05
jbradshaw 0:e4a10ed6eb92 1108 * @param En_bloff: BIOZ Digital Lead Off Detection Enable <CNFG_GEN register>
jbradshaw 0:e4a10ed6eb92 1109 * @param Bloff_hi_it: DC Lead Off Current Polarity (if current sources are enabled/connected) <MNGR_DYN register>
jbradshaw 0:e4a10ed6eb92 1110 * @param Bloff_lo_it: DC Lead off current Magnitude Selection <MNGR_DYN register>
jbradshaw 0:e4a10ed6eb92 1111 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1112 *
jbradshaw 0:e4a10ed6eb92 1113 */
jbradshaw 1:9490836294ea 1114 int BIOZ_Enable_ACLeadOFF_Init(uint8_t En_bloff, uint8_t Bloff_hi_it,
jbradshaw 0:e4a10ed6eb92 1115 uint8_t Bloff_lo_it);
jbradshaw 0:e4a10ed6eb92 1116
jbradshaw 0:e4a10ed6eb92 1117 /**
jbradshaw 0:e4a10ed6eb92 1118 * @brief This function Turns of the BIOZ AC Lead OFF feature
jbradshaw 0:e4a10ed6eb92 1119 * @brief Registers Used: CNFG_GEN-0x10
jbradshaw 0:e4a10ed6eb92 1120 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1121 *
jbradshaw 0:e4a10ed6eb92 1122 */
jbradshaw 1:9490836294ea 1123 int BIOZ_Disable_ACleadOFF(void);
jbradshaw 0:e4a10ed6eb92 1124
jbradshaw 0:e4a10ed6eb92 1125 /**
jbradshaw 0:e4a10ed6eb92 1126 * @brief This function enables the Current Gnerator Monitor
jbradshaw 0:e4a10ed6eb92 1127 * @brief Registers Used: CNFG_BIOZ-0x18
jbradshaw 0:e4a10ed6eb92 1128 * @returns 0-if no error. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1129 *
jbradshaw 0:e4a10ed6eb92 1130 */
jbradshaw 1:9490836294ea 1131 int BIOZ_Enable_BCGMON(void);
jbradshaw 0:e4a10ed6eb92 1132
jbradshaw 0:e4a10ed6eb92 1133 /**
jbradshaw 0:e4a10ed6eb92 1134 *
jbradshaw 0:e4a10ed6eb92 1135 * @brief This function enables the Lead ON detection. Either ECG or BIOZ can be detected, one at a time.
jbradshaw 0:e4a10ed6eb92 1136 * @brief Also, the en_bioz, en_ecg, en_pace setting is saved so that when this feature is disabled through the
jbradshaw 0:e4a10ed6eb92 1137 * @brief max30001_Disable_LeadON() function (or otherwise) the enable/disable state of those features can be retrieved.
jbradshaw 0:e4a10ed6eb92 1138 * @param Channel: ECG or BIOZ detection
jbradshaw 0:e4a10ed6eb92 1139 * @returns 0-if everything is good. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1140 *
jbradshaw 0:e4a10ed6eb92 1141 */
jbradshaw 1:9490836294ea 1142 int Enable_LeadON(int8_t Channel);
jbradshaw 0:e4a10ed6eb92 1143
jbradshaw 0:e4a10ed6eb92 1144 /**
jbradshaw 0:e4a10ed6eb92 1145 * @brief This function turns off the Lead ON feature, whichever one is active. Also, retrieves the en_bioz,
jbradshaw 0:e4a10ed6eb92 1146 * @brief en_ecg, en_pace and sets it back to as it was.
jbradshaw 0:e4a10ed6eb92 1147 * @param 0-if everything is good. A non-zero value indicates an error.
jbradshaw 0:e4a10ed6eb92 1148 *
jbradshaw 0:e4a10ed6eb92 1149 */
jbradshaw 1:9490836294ea 1150 int Disable_LeadON(void);
jbradshaw 0:e4a10ed6eb92 1151
jbradshaw 0:e4a10ed6eb92 1152 /**
jbradshaw 0:e4a10ed6eb92 1153 *
jbradshaw 0:e4a10ed6eb92 1154 * @brief This function is toggled every 2 seconds to switch between ECG Lead ON and BIOZ Lead ON detect
jbradshaw 0:e4a10ed6eb92 1155 * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles.
jbradshaw 0:e4a10ed6eb92 1156 * @param CurrentTime - This gets fed the time by RTC_GetValue function
jbradshaw 0:e4a10ed6eb92 1157 *
jbradshaw 0:e4a10ed6eb92 1158 */
jbradshaw 1:9490836294ea 1159 void ServiceLeadON(uint32_t currentTime);
jbradshaw 0:e4a10ed6eb92 1160
jbradshaw 0:e4a10ed6eb92 1161 /**
jbradshaw 0:e4a10ed6eb92 1162 *
jbradshaw 0:e4a10ed6eb92 1163 * @brief This function is toggled every 2 seconds to switch between ECG DC Lead Off and BIOZ DC Lead Off
jbradshaw 0:e4a10ed6eb92 1164 * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles.
jbradshaw 0:e4a10ed6eb92 1165 * @param CurrentTime - This gets fed the time by RTC_GetValue function
jbradshaw 0:e4a10ed6eb92 1166 *
jbradshaw 0:e4a10ed6eb92 1167 */
jbradshaw 1:9490836294ea 1168 void ServiceLeadoff(uint32_t currentTime);
jbradshaw 0:e4a10ed6eb92 1169
jbradshaw 0:e4a10ed6eb92 1170 /**
jbradshaw 0:e4a10ed6eb92 1171 *
jbradshaw 0:e4a10ed6eb92 1172 * @brief This function sets current RtoR values and fmstr values in a pointer structure
jbradshaw 0:e4a10ed6eb92 1173 * @param hspValMax30001 - Pointer to a structure where to store the values
jbradshaw 0:e4a10ed6eb92 1174 *
jbradshaw 0:e4a10ed6eb92 1175 */
jbradshaw 1:9490836294ea 1176 void ReadHeartrateData(max30001_bledata_t *_hspValMax30001);
jbradshaw 0:e4a10ed6eb92 1177
jbradshaw 0:e4a10ed6eb92 1178 /**
jbradshaw 0:e4a10ed6eb92 1179 * @brief type definition for data interrupt
jbradshaw 0:e4a10ed6eb92 1180 */
jbradshaw 0:e4a10ed6eb92 1181 typedef void (*PtrFunction)(uint32_t id, uint32_t *buffer, uint32_t length);
jbradshaw 0:e4a10ed6eb92 1182
jbradshaw 0:e4a10ed6eb92 1183 /**
jbradshaw 0:e4a10ed6eb92 1184 * @brief Used to connect a callback for when interrupt data is available
jbradshaw 0:e4a10ed6eb92 1185 */
jbradshaw 0:e4a10ed6eb92 1186 void onDataAvailable(PtrFunction _onDataAvailable);
jbradshaw 0:e4a10ed6eb92 1187
jbradshaw 1:9490836294ea 1188
jbradshaw 1:9490836294ea 1189
jbradshaw 1:9490836294ea 1190 /**
jbradshaw 1:9490836294ea 1191 * @brief Preventive measure used to dismiss interrupts that fire too early during
jbradshaw 1:9490836294ea 1192 * @brief initialization on INTB line
jbradshaw 1:9490836294ea 1193 *
jbradshaw 1:9490836294ea 1194 */
jbradshaw 1:9490836294ea 1195 static void Mid_IntB_Handler(void);
jbradshaw 1:9490836294ea 1196
jbradshaw 1:9490836294ea 1197 /**
jbradshaw 1:9490836294ea 1198 * @brief Preventive measure used to dismiss interrupts that fire too early during
jbradshaw 1:9490836294ea 1199 * @brief initialization on INT2B line
jbradshaw 1:9490836294ea 1200 *
jbradshaw 1:9490836294ea 1201 */
jbradshaw 1:9490836294ea 1202 static void Mid_Int2B_Handler(void);
jbradshaw 1:9490836294ea 1203
jbradshaw 1:9490836294ea 1204 /**
jbradshaw 1:9490836294ea 1205 * @brief Allows Interrupts to be accepted as valid.
jbradshaw 1:9490836294ea 1206 * @param state: 1-Allow interrupts, Any-Don't allow interrupts.
jbradshaw 1:9490836294ea 1207 *
jbradshaw 1:9490836294ea 1208 */
jbradshaw 1:9490836294ea 1209 void AllowInterrupts(int state);
jbradshaw 1:9490836294ea 1210
jbradshaw 1:9490836294ea 1211
jbradshaw 1:9490836294ea 1212 /// @brief function pointer to the async callback
jbradshaw 1:9490836294ea 1213 static event_callback_t functionpointer;
jbradshaw 1:9490836294ea 1214
jbradshaw 1:9490836294ea 1215 /// @brief flag used to indicate an async xfer has taken place
jbradshaw 1:9490836294ea 1216 static volatile int xferFlag;
jbradshaw 1:9490836294ea 1217
jbradshaw 1:9490836294ea 1218 /**
jbradshaw 1:9490836294ea 1219 * @brief Callback handler for SPI async events
jbradshaw 1:9490836294ea 1220 * @param events description of event that occurred
jbradshaw 1:9490836294ea 1221 */
jbradshaw 1:9490836294ea 1222 static void spiHandler(int events);
jbradshaw 1:9490836294ea 1223
jbradshaw 1:9490836294ea 1224
jbradshaw 0:e4a10ed6eb92 1225 static MAX30001 *instance;
jbradshaw 0:e4a10ed6eb92 1226
jbradshaw 0:e4a10ed6eb92 1227 private:
jbradshaw 1:9490836294ea 1228
jbradshaw 1:9490836294ea 1229 /**
jbradshaw 1:9490836294ea 1230 * @brief Used to notify an external function that interrupt data is available
jbradshaw 1:9490836294ea 1231 * @param id type of data available
jbradshaw 1:9490836294ea 1232 * @param buffer 32-bit buffer that points to the data
jbradshaw 1:9490836294ea 1233 * @param length length of 32-bit elements available
jbradshaw 1:9490836294ea 1234 */
jbradshaw 0:e4a10ed6eb92 1235 void dataAvailable(uint32_t id, uint32_t *buffer, uint32_t length);
jbradshaw 1:9490836294ea 1236
jbradshaw 1:9490836294ea 1237 /**
jbradshaw 1:9490836294ea 1238 * @brief Transmit and recieve QUAD SPI data
jbradshaw 1:9490836294ea 1239 * @param tx_buf pointer to transmit byte buffer
jbradshaw 1:9490836294ea 1240 * @param tx_size number of bytes to transmit
jbradshaw 1:9490836294ea 1241 * @param rx_buf pointer to the recieve buffer
jbradshaw 1:9490836294ea 1242 * @param rx_size number of bytes to recieve
jbradshaw 1:9490836294ea 1243 */
jbradshaw 0:e4a10ed6eb92 1244 int SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size, uint8_t *rx_buf,
jbradshaw 0:e4a10ed6eb92 1245 uint32_t rx_size);
jbradshaw 0:e4a10ed6eb92 1246
jbradshaw 0:e4a10ed6eb92 1247 /// pointer to mbed SPI object
jbradshaw 0:e4a10ed6eb92 1248 SPI *spi;
jbradshaw 0:e4a10ed6eb92 1249 /// is this object the owner of the spi object
jbradshaw 0:e4a10ed6eb92 1250 bool spi_owner;
jbradshaw 0:e4a10ed6eb92 1251 /// buffer to use for async transfers
jbradshaw 0:e4a10ed6eb92 1252 uint8_t buffer[ASYNC_SPI_BUFFER_SIZE];
jbradshaw 0:e4a10ed6eb92 1253 /// function pointer to the async callback
jbradshaw 1:9490836294ea 1254 // event_callback_t functionpointer;
jbradshaw 0:e4a10ed6eb92 1255 /// callback function when interrupt data is available
jbradshaw 0:e4a10ed6eb92 1256 PtrFunction onDataAvailableCallback;
jbradshaw 0:e4a10ed6eb92 1257
jbradshaw 0:e4a10ed6eb92 1258 }; // End of MAX30001 Class
jbradshaw 0:e4a10ed6eb92 1259
jbradshaw 0:e4a10ed6eb92 1260
jbradshaw 0:e4a10ed6eb92 1261 #endif /* MAX30001_H_ */