Maxim Integrated
MAX32620HSP (MAXREFDES100) RPC Example for Graphical User Interface
Dependencies: USBDevice
Fork of
HSP_Release
by 
Jerry Bradshaw
This is an example program for the MAX32620HSP (MAXREFDES100 Health Sensor Platform). It demonstrates all the features of the platform and works with a companion graphical user interface (GUI) to help evaluate/configure/monitor the board. Go to the MAXREFDES100 product page and click on "design resources" to download the companion software. The GUI connects to the board through an RPC interface on a virtual serial port over the USB interface.
The RPC interface provides access to all the features of the board and is available to interface with other development environments such Matlab. This firmware provides realtime data streaming through the RPC interface over USB, and also provides the ability to log the data to flash for untethered battery operation. The data logging settings are configured through the GUI, and the GUI also provides the interface to download logged data.
Details on the RPC interface can be found here: HSP RPC Interface Documentation
Windows
With this program loaded, the MAX32620HSP will appear on your computer as a serial port. On Mac and Linux, this will happen by default. For Windows, you need to install a driver: HSP serial port windows driver
For more details about this platform and how to use it, see the MAXREFDES100 product page.
HSP/Devices/MAX30001/MAX30001/MAX30001.h@0:e4a10ed6eb92, 2016-10-25 (annotated)
- Committer:
- jbradshaw
- Date:
- Tue Oct 25 15:22:11 2016 +0000
- Revision:
- 0:e4a10ed6eb92
- Child:
- 1:9490836294ea
tewt
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| jbradshaw | 0:e4a10ed6eb92 | 1 | /******************************************************************************* |
| jbradshaw | 0:e4a10ed6eb92 | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
| jbradshaw | 0:e4a10ed6eb92 | 3 | * |
| jbradshaw | 0:e4a10ed6eb92 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| jbradshaw | 0:e4a10ed6eb92 | 5 | * copy of this software and associated documentation files (the "Software"), |
| jbradshaw | 0:e4a10ed6eb92 | 6 | * to deal in the Software without restriction, including without limitation |
| jbradshaw | 0:e4a10ed6eb92 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| jbradshaw | 0:e4a10ed6eb92 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| jbradshaw | 0:e4a10ed6eb92 | 9 | * Software is furnished to do so, subject to the following conditions: |
| jbradshaw | 0:e4a10ed6eb92 | 10 | * |
| jbradshaw | 0:e4a10ed6eb92 | 11 | * The above copyright notice and this permission notice shall be included |
| jbradshaw | 0:e4a10ed6eb92 | 12 | * in all copies or substantial portions of the Software. |
| jbradshaw | 0:e4a10ed6eb92 | 13 | * |
| jbradshaw | 0:e4a10ed6eb92 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| jbradshaw | 0:e4a10ed6eb92 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| jbradshaw | 0:e4a10ed6eb92 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| jbradshaw | 0:e4a10ed6eb92 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| jbradshaw | 0:e4a10ed6eb92 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| jbradshaw | 0:e4a10ed6eb92 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| jbradshaw | 0:e4a10ed6eb92 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| jbradshaw | 0:e4a10ed6eb92 | 21 | * |
| jbradshaw | 0:e4a10ed6eb92 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| jbradshaw | 0:e4a10ed6eb92 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| jbradshaw | 0:e4a10ed6eb92 | 24 | * Products, Inc. Branding Policy. |
| jbradshaw | 0:e4a10ed6eb92 | 25 | * |
| jbradshaw | 0:e4a10ed6eb92 | 26 | * The mere transfer of this software does not imply any licenses |
| jbradshaw | 0:e4a10ed6eb92 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| jbradshaw | 0:e4a10ed6eb92 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| jbradshaw | 0:e4a10ed6eb92 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| jbradshaw | 0:e4a10ed6eb92 | 30 | * ownership rights. |
| jbradshaw | 0:e4a10ed6eb92 | 31 | *******************************************************************************/ |
| jbradshaw | 0:e4a10ed6eb92 | 32 | /* |
| jbradshaw | 0:e4a10ed6eb92 | 33 | * max30001.h |
| jbradshaw | 0:e4a10ed6eb92 | 34 | * |
| jbradshaw | 0:e4a10ed6eb92 | 35 | * Created on: Oct 9, 2015 |
| jbradshaw | 0:e4a10ed6eb92 | 36 | * Author: faisal.tariq |
| jbradshaw | 0:e4a10ed6eb92 | 37 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 38 | |
| jbradshaw | 0:e4a10ed6eb92 | 39 | #ifndef MAX30001_H_ |
| jbradshaw | 0:e4a10ed6eb92 | 40 | #define MAX30001_H_ |
| jbradshaw | 0:e4a10ed6eb92 | 41 | |
| jbradshaw | 0:e4a10ed6eb92 | 42 | #include "mbed.h" |
| jbradshaw | 0:e4a10ed6eb92 | 43 | |
| jbradshaw | 0:e4a10ed6eb92 | 44 | #define mbed_COMPLIANT // Uncomment to Use timer for MAX30001 FCLK (for mbed) |
| jbradshaw | 0:e4a10ed6eb92 | 45 | // Comment to use the RTC clock |
| jbradshaw | 0:e4a10ed6eb92 | 46 | |
| jbradshaw | 0:e4a10ed6eb92 | 47 | #define ASYNC_SPI_BUFFER_SIZE (32 * 3) // Maximimum buffer size for async byte transfers |
| jbradshaw | 0:e4a10ed6eb92 | 48 | |
| jbradshaw | 0:e4a10ed6eb92 | 49 | // Defines for data callbacks |
| jbradshaw | 0:e4a10ed6eb92 | 50 | #define MAX30001_DATA_ECG 0x30 |
| jbradshaw | 0:e4a10ed6eb92 | 51 | #define MAX30001_DATA_PACE 0x31 |
| jbradshaw | 0:e4a10ed6eb92 | 52 | #define MAX30001_DATA_RTOR 0x32 |
| jbradshaw | 0:e4a10ed6eb92 | 53 | #define MAX30001_DATA_BIOZ 0x33 |
| jbradshaw | 0:e4a10ed6eb92 | 54 | #define MAX30001_DATA_LEADOFF_DC 0x34 |
| jbradshaw | 0:e4a10ed6eb92 | 55 | #define MAX30001_DATA_LEADOFF_AC 0x35 |
| jbradshaw | 0:e4a10ed6eb92 | 56 | #define MAX30001_DATA_BCGMON 0x36 |
| jbradshaw | 0:e4a10ed6eb92 | 57 | #define MAX30001_DATA_ACLEADON 0x37 |
| jbradshaw | 0:e4a10ed6eb92 | 58 | |
| jbradshaw | 0:e4a10ed6eb92 | 59 | #define MAX30001_SPI_MASTER_PORT 0 |
| jbradshaw | 0:e4a10ed6eb92 | 60 | #define MAX30001_SPI_SS_INDEX 0 |
| jbradshaw | 0:e4a10ed6eb92 | 61 | |
| jbradshaw | 0:e4a10ed6eb92 | 62 | #define MAX30001_INT_PORT_B 3 |
| jbradshaw | 0:e4a10ed6eb92 | 63 | #define MAX30001_INT_PIN_B 6 |
| jbradshaw | 0:e4a10ed6eb92 | 64 | |
| jbradshaw | 0:e4a10ed6eb92 | 65 | #define MAX30001_INT_PORT_2B 4 |
| jbradshaw | 0:e4a10ed6eb92 | 66 | #define MAX30001_INT_PIN_2B 5 |
| jbradshaw | 0:e4a10ed6eb92 | 67 | |
| jbradshaw | 0:e4a10ed6eb92 | 68 | #define MAX30001_INT_PORT_FCLK 1 |
| jbradshaw | 0:e4a10ed6eb92 | 69 | #define MAX30001_INT_PIN_FCLK 7 |
| jbradshaw | 0:e4a10ed6eb92 | 70 | |
| jbradshaw | 0:e4a10ed6eb92 | 71 | #define MAX30001_FUNC_SEL_TMR 2 // 0=FW Control, 1= Pulse Train, 2=Timer |
| jbradshaw | 0:e4a10ed6eb92 | 72 | |
| jbradshaw | 0:e4a10ed6eb92 | 73 | #define MAX30001_INDEX 3 |
| jbradshaw | 0:e4a10ed6eb92 | 74 | #define MAX30001_POLARITY 0 |
| jbradshaw | 0:e4a10ed6eb92 | 75 | #define MAX30001_PERIOD 30518 |
| jbradshaw | 0:e4a10ed6eb92 | 76 | #define MAX30001_CYCLE 50 |
| jbradshaw | 0:e4a10ed6eb92 | 77 | |
| jbradshaw | 0:e4a10ed6eb92 | 78 | #define MAX30001_IOMUX_IO_ENABLE 1 |
| jbradshaw | 0:e4a10ed6eb92 | 79 | |
| jbradshaw | 0:e4a10ed6eb92 | 80 | #define MAX30001_SPI_PORT 0 |
| jbradshaw | 0:e4a10ed6eb92 | 81 | #define MAX30001_CS_PIN 0 |
| jbradshaw | 0:e4a10ed6eb92 | 82 | #define MAX30001_CS_POLARITY 0 |
| jbradshaw | 0:e4a10ed6eb92 | 83 | #define MAX30001_CS_ACTIVITY_DELAY 0 |
| jbradshaw | 0:e4a10ed6eb92 | 84 | #define MAX30001_CS_INACTIVITY_DELAY 0 |
| jbradshaw | 0:e4a10ed6eb92 | 85 | #define MAX30001_CLK_HI 1 |
| jbradshaw | 0:e4a10ed6eb92 | 86 | #define MAX30001_CLK_LOW 1 |
| jbradshaw | 0:e4a10ed6eb92 | 87 | #define MAX30001_ALT_CLK 0 |
| jbradshaw | 0:e4a10ed6eb92 | 88 | #define MAX30001_CLK_POLARITY 0 |
| jbradshaw | 0:e4a10ed6eb92 | 89 | #define MAX30001_CLK_PHASE 0 |
| jbradshaw | 0:e4a10ed6eb92 | 90 | #define MAX30001_WRITE 1 |
| jbradshaw | 0:e4a10ed6eb92 | 91 | #define MAX30001_READ 0 |
| jbradshaw | 0:e4a10ed6eb92 | 92 | |
| jbradshaw | 0:e4a10ed6eb92 | 93 | #define MAX30001_INT_PORT_B 3 |
| jbradshaw | 0:e4a10ed6eb92 | 94 | #define MAX30001INT_PIN_B 6 |
| jbradshaw | 0:e4a10ed6eb92 | 95 | |
| jbradshaw | 0:e4a10ed6eb92 | 96 | void MAX30001_AllowInterrupts(int state); |
| jbradshaw | 0:e4a10ed6eb92 | 97 | |
| jbradshaw | 0:e4a10ed6eb92 | 98 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 99 | * Maxim Integrated MAX30001 ECG/BIOZ chip |
| jbradshaw | 0:e4a10ed6eb92 | 100 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 101 | class MAX30001 { |
| jbradshaw | 0:e4a10ed6eb92 | 102 | |
| jbradshaw | 0:e4a10ed6eb92 | 103 | public: |
| jbradshaw | 0:e4a10ed6eb92 | 104 | typedef enum { // MAX30001 Register addresses |
| jbradshaw | 0:e4a10ed6eb92 | 105 | STATUS = 0x01, |
| jbradshaw | 0:e4a10ed6eb92 | 106 | EN_INT = 0x02, |
| jbradshaw | 0:e4a10ed6eb92 | 107 | EN_INT2 = 0x03, |
| jbradshaw | 0:e4a10ed6eb92 | 108 | MNGR_INT = 0x04, |
| jbradshaw | 0:e4a10ed6eb92 | 109 | MNGR_DYN = 0x05, |
| jbradshaw | 0:e4a10ed6eb92 | 110 | SW_RST = 0x08, |
| jbradshaw | 0:e4a10ed6eb92 | 111 | SYNCH = 0x09, |
| jbradshaw | 0:e4a10ed6eb92 | 112 | FIFO_RST = 0x0A, |
| jbradshaw | 0:e4a10ed6eb92 | 113 | INFO = 0x0F, |
| jbradshaw | 0:e4a10ed6eb92 | 114 | CNFG_GEN = 0x10, |
| jbradshaw | 0:e4a10ed6eb92 | 115 | CNFG_CAL = 0x12, |
| jbradshaw | 0:e4a10ed6eb92 | 116 | CNFG_EMUX = 0x14, |
| jbradshaw | 0:e4a10ed6eb92 | 117 | CNFG_ECG = 0x15, |
| jbradshaw | 0:e4a10ed6eb92 | 118 | CNFG_BMUX = 0x17, |
| jbradshaw | 0:e4a10ed6eb92 | 119 | CNFG_BIOZ = 0x18, |
| jbradshaw | 0:e4a10ed6eb92 | 120 | CNFG_PACE = 0x1A, |
| jbradshaw | 0:e4a10ed6eb92 | 121 | CNFG_RTOR1 = 0x1D, |
| jbradshaw | 0:e4a10ed6eb92 | 122 | CNFG_RTOR2 = 0x1E, |
| jbradshaw | 0:e4a10ed6eb92 | 123 | |
| jbradshaw | 0:e4a10ed6eb92 | 124 | // Data locations |
| jbradshaw | 0:e4a10ed6eb92 | 125 | ECG_FIFO_BURST = 0x20, |
| jbradshaw | 0:e4a10ed6eb92 | 126 | ECG_FIFO = 0x21, |
| jbradshaw | 0:e4a10ed6eb92 | 127 | FIFO_BURST = 0x22, |
| jbradshaw | 0:e4a10ed6eb92 | 128 | BIOZ_FIFO = 0x23, |
| jbradshaw | 0:e4a10ed6eb92 | 129 | RTOR = 0x25, |
| jbradshaw | 0:e4a10ed6eb92 | 130 | |
| jbradshaw | 0:e4a10ed6eb92 | 131 | PACE0_FIFO_BURST = 0x30, |
| jbradshaw | 0:e4a10ed6eb92 | 132 | PACE0_A = 0x31, |
| jbradshaw | 0:e4a10ed6eb92 | 133 | PACE0_B = 0x32, |
| jbradshaw | 0:e4a10ed6eb92 | 134 | PACE0_C = 0x33, |
| jbradshaw | 0:e4a10ed6eb92 | 135 | |
| jbradshaw | 0:e4a10ed6eb92 | 136 | PACE1_FIFO_BURST = 0x34, |
| jbradshaw | 0:e4a10ed6eb92 | 137 | PACE1_A = 0x35, |
| jbradshaw | 0:e4a10ed6eb92 | 138 | PACE1_B = 0x36, |
| jbradshaw | 0:e4a10ed6eb92 | 139 | PACE1_C = 0x37, |
| jbradshaw | 0:e4a10ed6eb92 | 140 | |
| jbradshaw | 0:e4a10ed6eb92 | 141 | PACE2_FIFO_BURST = 0x38, |
| jbradshaw | 0:e4a10ed6eb92 | 142 | PACE2_A = 0x39, |
| jbradshaw | 0:e4a10ed6eb92 | 143 | PACE2_B = 0x3A, |
| jbradshaw | 0:e4a10ed6eb92 | 144 | PACE2_C = 0x3B, |
| jbradshaw | 0:e4a10ed6eb92 | 145 | |
| jbradshaw | 0:e4a10ed6eb92 | 146 | PACE3_FIFO_BURST = 0x3C, |
| jbradshaw | 0:e4a10ed6eb92 | 147 | PACE3_A = 0x3D, |
| jbradshaw | 0:e4a10ed6eb92 | 148 | PACE3_B = 0x3E, |
| jbradshaw | 0:e4a10ed6eb92 | 149 | PACE3_C = 0x3F, |
| jbradshaw | 0:e4a10ed6eb92 | 150 | |
| jbradshaw | 0:e4a10ed6eb92 | 151 | PACE4_FIFO_BURST = 0x40, |
| jbradshaw | 0:e4a10ed6eb92 | 152 | PACE4_A = 0x41, |
| jbradshaw | 0:e4a10ed6eb92 | 153 | PACE4_B = 0x42, |
| jbradshaw | 0:e4a10ed6eb92 | 154 | PACE4_C = 0x43, |
| jbradshaw | 0:e4a10ed6eb92 | 155 | |
| jbradshaw | 0:e4a10ed6eb92 | 156 | PACE5_FIFO_BURST = 0x44, |
| jbradshaw | 0:e4a10ed6eb92 | 157 | PACE5_A = 0x45, |
| jbradshaw | 0:e4a10ed6eb92 | 158 | PACE5_B = 0x46, |
| jbradshaw | 0:e4a10ed6eb92 | 159 | PACE5_C = 0x47, |
| jbradshaw | 0:e4a10ed6eb92 | 160 | |
| jbradshaw | 0:e4a10ed6eb92 | 161 | } MAX30001_REG_map_t; |
| jbradshaw | 0:e4a10ed6eb92 | 162 | |
| jbradshaw | 0:e4a10ed6eb92 | 163 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 164 | * @brief STATUS (0x01) |
| jbradshaw | 0:e4a10ed6eb92 | 165 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 166 | union max30001_status_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 167 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 168 | |
| jbradshaw | 0:e4a10ed6eb92 | 169 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 170 | uint32_t loff_nl : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 171 | uint32_t loff_nh : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 172 | uint32_t loff_pl : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 173 | uint32_t loff_ph : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 174 | |
| jbradshaw | 0:e4a10ed6eb92 | 175 | uint32_t bcgmn : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 176 | uint32_t bcgmp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 177 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 178 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 179 | |
| jbradshaw | 0:e4a10ed6eb92 | 180 | uint32_t pllint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 181 | uint32_t samp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 182 | uint32_t rrint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 183 | uint32_t lonint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 184 | |
| jbradshaw | 0:e4a10ed6eb92 | 185 | uint32_t pedge : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 186 | uint32_t povf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 187 | uint32_t pint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 188 | uint32_t bcgmon : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 189 | |
| jbradshaw | 0:e4a10ed6eb92 | 190 | uint32_t bundr : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 191 | uint32_t bover : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 192 | uint32_t bovf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 193 | uint32_t bint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 194 | |
| jbradshaw | 0:e4a10ed6eb92 | 195 | uint32_t dcloffint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 196 | uint32_t fstint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 197 | uint32_t eovf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 198 | uint32_t eint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 199 | |
| jbradshaw | 0:e4a10ed6eb92 | 200 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 201 | |
| jbradshaw | 0:e4a10ed6eb92 | 202 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 203 | |
| jbradshaw | 0:e4a10ed6eb92 | 204 | } max30001_status; |
| jbradshaw | 0:e4a10ed6eb92 | 205 | |
| jbradshaw | 0:e4a10ed6eb92 | 206 | |
| jbradshaw | 0:e4a10ed6eb92 | 207 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 208 | * @brief EN_INT (0x02) |
| jbradshaw | 0:e4a10ed6eb92 | 209 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 210 | |
| jbradshaw | 0:e4a10ed6eb92 | 211 | union max30001_en_int_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 212 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 213 | |
| jbradshaw | 0:e4a10ed6eb92 | 214 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 215 | uint32_t intb_type : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 216 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 217 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 218 | |
| jbradshaw | 0:e4a10ed6eb92 | 219 | uint32_t reserved3 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 220 | uint32_t reserved4 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 221 | uint32_t reserved5 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 222 | uint32_t reserved6 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 223 | |
| jbradshaw | 0:e4a10ed6eb92 | 224 | uint32_t en_pllint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 225 | uint32_t en_samp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 226 | uint32_t en_rrint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 227 | uint32_t en_lonint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 228 | |
| jbradshaw | 0:e4a10ed6eb92 | 229 | uint32_t en_pedge : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 230 | uint32_t en_povf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 231 | uint32_t en_pint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 232 | uint32_t en_bcgmon : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 233 | |
| jbradshaw | 0:e4a10ed6eb92 | 234 | uint32_t en_bundr : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 235 | uint32_t en_bover : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 236 | uint32_t en_bovf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 237 | uint32_t en_bint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 238 | |
| jbradshaw | 0:e4a10ed6eb92 | 239 | uint32_t en_dcloffint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 240 | uint32_t en_fstint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 241 | uint32_t en_eovf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 242 | uint32_t en_eint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 243 | |
| jbradshaw | 0:e4a10ed6eb92 | 244 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 245 | |
| jbradshaw | 0:e4a10ed6eb92 | 246 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 247 | |
| jbradshaw | 0:e4a10ed6eb92 | 248 | } max30001_en_int; |
| jbradshaw | 0:e4a10ed6eb92 | 249 | |
| jbradshaw | 0:e4a10ed6eb92 | 250 | |
| jbradshaw | 0:e4a10ed6eb92 | 251 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 252 | * @brief EN_INT2 (0x03) |
| jbradshaw | 0:e4a10ed6eb92 | 253 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 254 | union max30001_en_int2_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 255 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 256 | |
| jbradshaw | 0:e4a10ed6eb92 | 257 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 258 | uint32_t intb_type : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 259 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 260 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 261 | |
| jbradshaw | 0:e4a10ed6eb92 | 262 | uint32_t reserved3 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 263 | uint32_t reserved4 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 264 | uint32_t reserved5 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 265 | uint32_t reserved6 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 266 | |
| jbradshaw | 0:e4a10ed6eb92 | 267 | uint32_t en_pllint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 268 | uint32_t en_samp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 269 | uint32_t en_rrint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 270 | uint32_t en_lonint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 271 | |
| jbradshaw | 0:e4a10ed6eb92 | 272 | uint32_t en_pedge : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 273 | uint32_t en_povf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 274 | uint32_t en_pint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 275 | uint32_t en_bcgmon : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 276 | |
| jbradshaw | 0:e4a10ed6eb92 | 277 | uint32_t en_bundr : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 278 | uint32_t en_bover : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 279 | uint32_t en_bovf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 280 | uint32_t en_bint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 281 | |
| jbradshaw | 0:e4a10ed6eb92 | 282 | uint32_t en_dcloffint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 283 | uint32_t en_fstint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 284 | uint32_t en_eovf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 285 | uint32_t en_eint : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 286 | |
| jbradshaw | 0:e4a10ed6eb92 | 287 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 288 | |
| jbradshaw | 0:e4a10ed6eb92 | 289 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 290 | |
| jbradshaw | 0:e4a10ed6eb92 | 291 | } max30001_en_int2; |
| jbradshaw | 0:e4a10ed6eb92 | 292 | |
| jbradshaw | 0:e4a10ed6eb92 | 293 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 294 | * @brief MNGR_INT (0x04) |
| jbradshaw | 0:e4a10ed6eb92 | 295 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 296 | union max30001_mngr_int_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 297 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 298 | |
| jbradshaw | 0:e4a10ed6eb92 | 299 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 300 | uint32_t samp_it : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 301 | uint32_t clr_samp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 302 | uint32_t clr_pedge : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 303 | uint32_t clr_rrint : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 304 | uint32_t clr_fast : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 305 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 306 | uint32_t reserved2 : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 307 | uint32_t reserved3 : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 308 | |
| jbradshaw | 0:e4a10ed6eb92 | 309 | uint32_t b_fit : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 310 | uint32_t e_fit : 5; |
| jbradshaw | 0:e4a10ed6eb92 | 311 | |
| jbradshaw | 0:e4a10ed6eb92 | 312 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 313 | |
| jbradshaw | 0:e4a10ed6eb92 | 314 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 315 | |
| jbradshaw | 0:e4a10ed6eb92 | 316 | } max30001_mngr_int; |
| jbradshaw | 0:e4a10ed6eb92 | 317 | |
| jbradshaw | 0:e4a10ed6eb92 | 318 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 319 | * @brief MNGR_DYN (0x05) |
| jbradshaw | 0:e4a10ed6eb92 | 320 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 321 | union max30001_mngr_dyn_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 322 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 323 | |
| jbradshaw | 0:e4a10ed6eb92 | 324 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 325 | uint32_t bloff_lo_it : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 326 | uint32_t bloff_hi_it : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 327 | uint32_t fast_th : 6; |
| jbradshaw | 0:e4a10ed6eb92 | 328 | uint32_t fast : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 329 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 330 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 331 | |
| jbradshaw | 0:e4a10ed6eb92 | 332 | } max30001_mngr_dyn; |
| jbradshaw | 0:e4a10ed6eb92 | 333 | |
| jbradshaw | 0:e4a10ed6eb92 | 334 | // 0x08 |
| jbradshaw | 0:e4a10ed6eb92 | 335 | // uint32_t max30001_sw_rst; |
| jbradshaw | 0:e4a10ed6eb92 | 336 | |
| jbradshaw | 0:e4a10ed6eb92 | 337 | // 0x09 |
| jbradshaw | 0:e4a10ed6eb92 | 338 | // uint32_t max30001_synch; |
| jbradshaw | 0:e4a10ed6eb92 | 339 | |
| jbradshaw | 0:e4a10ed6eb92 | 340 | // 0x0A |
| jbradshaw | 0:e4a10ed6eb92 | 341 | // uint32_t max30001_fifo_rst; |
| jbradshaw | 0:e4a10ed6eb92 | 342 | |
| jbradshaw | 0:e4a10ed6eb92 | 343 | |
| jbradshaw | 0:e4a10ed6eb92 | 344 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 345 | * @brief INFO (0x0F) |
| jbradshaw | 0:e4a10ed6eb92 | 346 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 347 | union max30001_info_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 348 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 349 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 350 | uint32_t serial : 12; |
| jbradshaw | 0:e4a10ed6eb92 | 351 | uint32_t part_id : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 352 | uint32_t sample : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 353 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 354 | uint32_t rev_id : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 355 | uint32_t pattern : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 356 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 357 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 358 | |
| jbradshaw | 0:e4a10ed6eb92 | 359 | } max30001_info; |
| jbradshaw | 0:e4a10ed6eb92 | 360 | |
| jbradshaw | 0:e4a10ed6eb92 | 361 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 362 | * @brief CNFG_GEN (0x10) |
| jbradshaw | 0:e4a10ed6eb92 | 363 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 364 | union max30001_cnfg_gen_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 365 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 366 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 367 | uint32_t rbiasn : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 368 | uint32_t rbiasp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 369 | uint32_t rbiasv : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 370 | uint32_t en_rbias : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 371 | uint32_t vth : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 372 | uint32_t imag : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 373 | uint32_t ipol : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 374 | uint32_t en_dcloff : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 375 | uint32_t en_bloff : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 376 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 377 | uint32_t en_pace : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 378 | uint32_t en_bioz : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 379 | uint32_t en_ecg : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 380 | uint32_t fmstr : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 381 | uint32_t en_ulp_lon : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 382 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 383 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 384 | |
| jbradshaw | 0:e4a10ed6eb92 | 385 | } max30001_cnfg_gen; |
| jbradshaw | 0:e4a10ed6eb92 | 386 | |
| jbradshaw | 0:e4a10ed6eb92 | 387 | |
| jbradshaw | 0:e4a10ed6eb92 | 388 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 389 | * @brief CNFG_CAL (0x12) |
| jbradshaw | 0:e4a10ed6eb92 | 390 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 391 | union max30001_cnfg_cal_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 392 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 393 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 394 | uint32_t thigh : 11; |
| jbradshaw | 0:e4a10ed6eb92 | 395 | uint32_t fifty : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 396 | uint32_t fcal : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 397 | uint32_t reserved1 : 5; |
| jbradshaw | 0:e4a10ed6eb92 | 398 | uint32_t vmag : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 399 | uint32_t vmode : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 400 | uint32_t en_vcal : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 401 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 402 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 403 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 404 | |
| jbradshaw | 0:e4a10ed6eb92 | 405 | } max30001_cnfg_cal; |
| jbradshaw | 0:e4a10ed6eb92 | 406 | |
| jbradshaw | 0:e4a10ed6eb92 | 407 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 408 | * @brief CNFG_EMUX (0x14) |
| jbradshaw | 0:e4a10ed6eb92 | 409 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 410 | union max30001_cnfg_emux_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 411 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 412 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 413 | uint32_t reserved1 : 16; |
| jbradshaw | 0:e4a10ed6eb92 | 414 | uint32_t caln_sel : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 415 | uint32_t calp_sel : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 416 | uint32_t openn : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 417 | uint32_t openp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 418 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 419 | uint32_t pol : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 420 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 421 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 422 | |
| jbradshaw | 0:e4a10ed6eb92 | 423 | } max30001_cnfg_emux; |
| jbradshaw | 0:e4a10ed6eb92 | 424 | |
| jbradshaw | 0:e4a10ed6eb92 | 425 | |
| jbradshaw | 0:e4a10ed6eb92 | 426 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 427 | * @brief CNFG_ECG (0x15) |
| jbradshaw | 0:e4a10ed6eb92 | 428 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 429 | union max30001_cnfg_ecg_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 430 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 431 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 432 | uint32_t reserved1 : 12; |
| jbradshaw | 0:e4a10ed6eb92 | 433 | uint32_t dlpf : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 434 | uint32_t dhpf : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 435 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 436 | uint32_t gain : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 437 | uint32_t reserved3 : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 438 | uint32_t rate : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 439 | |
| jbradshaw | 0:e4a10ed6eb92 | 440 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 441 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 442 | |
| jbradshaw | 0:e4a10ed6eb92 | 443 | } max30001_cnfg_ecg; |
| jbradshaw | 0:e4a10ed6eb92 | 444 | |
| jbradshaw | 0:e4a10ed6eb92 | 445 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 446 | * @brief CNFG_BMUX (0x17) |
| jbradshaw | 0:e4a10ed6eb92 | 447 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 448 | union max30001_cnfg_bmux_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 449 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 450 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 451 | uint32_t fbist : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 452 | uint32_t reserved1 : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 453 | uint32_t rmod : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 454 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 455 | uint32_t rnom : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 456 | uint32_t en_bist : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 457 | uint32_t cg_mode : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 458 | uint32_t reserved3 : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 459 | uint32_t caln_sel : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 460 | uint32_t calp_sel : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 461 | uint32_t openn : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 462 | uint32_t openp : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 463 | uint32_t reserved4 : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 464 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 465 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 466 | |
| jbradshaw | 0:e4a10ed6eb92 | 467 | } max30001_cnfg_bmux; |
| jbradshaw | 0:e4a10ed6eb92 | 468 | |
| jbradshaw | 0:e4a10ed6eb92 | 469 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 470 | * @brief CNFG_BIOZ (0x18) |
| jbradshaw | 0:e4a10ed6eb92 | 471 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 472 | union max30001_bioz_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 473 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 474 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 475 | uint32_t phoff : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 476 | uint32_t cgmag : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 477 | uint32_t cgmon : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 478 | uint32_t fcgen : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 479 | uint32_t dlpf : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 480 | uint32_t dhpf : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 481 | uint32_t gain : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 482 | uint32_t reserved1 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 483 | uint32_t ext_rbias : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 484 | uint32_t ahpf : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 485 | uint32_t rate : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 486 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 487 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 488 | |
| jbradshaw | 0:e4a10ed6eb92 | 489 | } max30001_cnfg_bioz; |
| jbradshaw | 0:e4a10ed6eb92 | 490 | |
| jbradshaw | 0:e4a10ed6eb92 | 491 | |
| jbradshaw | 0:e4a10ed6eb92 | 492 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 493 | * @brief CNFG_PACE (0x1A) |
| jbradshaw | 0:e4a10ed6eb92 | 494 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 495 | union max30001_cnfg_pace_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 496 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 497 | |
| jbradshaw | 0:e4a10ed6eb92 | 498 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 499 | uint32_t dacn : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 500 | uint32_t dacp : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 501 | uint32_t reserved1 : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 502 | uint32_t aout : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 503 | uint32_t aout_lbw : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 504 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 505 | uint32_t gain : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 506 | uint32_t gn_diff_off : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 507 | uint32_t reserved3 : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 508 | uint32_t pol : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 509 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 510 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 511 | |
| jbradshaw | 0:e4a10ed6eb92 | 512 | } max30001_cnfg_pace; |
| jbradshaw | 0:e4a10ed6eb92 | 513 | |
| jbradshaw | 0:e4a10ed6eb92 | 514 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 515 | * @brief CNFG_RTOR1 (0x1D) |
| jbradshaw | 0:e4a10ed6eb92 | 516 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 517 | union max30001_cnfg_rtor1_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 518 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 519 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 520 | uint32_t reserved1 : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 521 | uint32_t ptsf : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 522 | uint32_t pavg : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 523 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 524 | uint32_t en_rtor : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 525 | uint32_t gain : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 526 | uint32_t wndw : 4; |
| jbradshaw | 0:e4a10ed6eb92 | 527 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 528 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 529 | |
| jbradshaw | 0:e4a10ed6eb92 | 530 | } max30001_cnfg_rtor1; |
| jbradshaw | 0:e4a10ed6eb92 | 531 | |
| jbradshaw | 0:e4a10ed6eb92 | 532 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 533 | * @brief CNFG_RTOR2 (0x1E) |
| jbradshaw | 0:e4a10ed6eb92 | 534 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 535 | union max30001_cnfg_rtor2_reg { |
| jbradshaw | 0:e4a10ed6eb92 | 536 | uint32_t all; |
| jbradshaw | 0:e4a10ed6eb92 | 537 | struct { |
| jbradshaw | 0:e4a10ed6eb92 | 538 | uint32_t reserved1 : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 539 | uint32_t rhsf : 3; |
| jbradshaw | 0:e4a10ed6eb92 | 540 | uint32_t reserved2 : 1; |
| jbradshaw | 0:e4a10ed6eb92 | 541 | uint32_t ravg : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 542 | uint32_t reserved3 : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 543 | uint32_t hoff : 6; |
| jbradshaw | 0:e4a10ed6eb92 | 544 | uint32_t reserved4 : 2; |
| jbradshaw | 0:e4a10ed6eb92 | 545 | uint32_t reserved : 8; |
| jbradshaw | 0:e4a10ed6eb92 | 546 | } bit; |
| jbradshaw | 0:e4a10ed6eb92 | 547 | |
| jbradshaw | 0:e4a10ed6eb92 | 548 | } max30001_cnfg_rtor2; |
| jbradshaw | 0:e4a10ed6eb92 | 549 | |
| jbradshaw | 0:e4a10ed6eb92 | 550 | /*********************************************************************************/ |
| jbradshaw | 0:e4a10ed6eb92 | 551 | |
| jbradshaw | 0:e4a10ed6eb92 | 552 | typedef enum { |
| jbradshaw | 0:e4a10ed6eb92 | 553 | MAX30001_NO_INT = 0, // No interrupt |
| jbradshaw | 0:e4a10ed6eb92 | 554 | MAX30001_INT_B = 1, // INTB selected for interrupt |
| jbradshaw | 0:e4a10ed6eb92 | 555 | MAX30001_INT_2B = 2 // INT2B selected for interrupt |
| jbradshaw | 0:e4a10ed6eb92 | 556 | } max30001_intrpt_Location_t; |
| jbradshaw | 0:e4a10ed6eb92 | 557 | |
| jbradshaw | 0:e4a10ed6eb92 | 558 | typedef enum { |
| jbradshaw | 0:e4a10ed6eb92 | 559 | MAX30001_INT_DISABLED = 0b00, |
| jbradshaw | 0:e4a10ed6eb92 | 560 | MAX30001_INT_CMOS = 0b01, |
| jbradshaw | 0:e4a10ed6eb92 | 561 | MAX30001_INT_ODN = 0b10, |
| jbradshaw | 0:e4a10ed6eb92 | 562 | MAX30001_INT_ODNR = 0b11 |
| jbradshaw | 0:e4a10ed6eb92 | 563 | } max30001_intrpt_type_t; |
| jbradshaw | 0:e4a10ed6eb92 | 564 | |
| jbradshaw | 0:e4a10ed6eb92 | 565 | typedef enum { // Input Polarity selection |
| jbradshaw | 0:e4a10ed6eb92 | 566 | MAX30001_NON_INV = 0, // Non-Inverted |
| jbradshaw | 0:e4a10ed6eb92 | 567 | MAX30001_INV = 1 // Inverted |
| jbradshaw | 0:e4a10ed6eb92 | 568 | } max30001_emux_pol; |
| jbradshaw | 0:e4a10ed6eb92 | 569 | |
| jbradshaw | 0:e4a10ed6eb92 | 570 | typedef enum { // OPENP and OPENN setting |
| jbradshaw | 0:e4a10ed6eb92 | 571 | MAX30001_ECG_CON_AFE = 0, // ECGx is connected to AFE channel |
| jbradshaw | 0:e4a10ed6eb92 | 572 | MAX30001_ECG_ISO_AFE = 1 // ECGx is isolated from AFE channel |
| jbradshaw | 0:e4a10ed6eb92 | 573 | } max30001_emux_openx; |
| jbradshaw | 0:e4a10ed6eb92 | 574 | |
| jbradshaw | 0:e4a10ed6eb92 | 575 | typedef enum { // EMUX_CALP_SEL & EMUX_CALN_SEL |
| jbradshaw | 0:e4a10ed6eb92 | 576 | MAX30001_NO_CAL_SIG = 0b00, // No calibration signal is applied |
| jbradshaw | 0:e4a10ed6eb92 | 577 | MAX30001_INPT_VMID = 0b01, // Input is connected to VMID |
| jbradshaw | 0:e4a10ed6eb92 | 578 | MAX30001_INPT_VCALP = 0b10, // Input is connected to VCALP |
| jbradshaw | 0:e4a10ed6eb92 | 579 | MAX30001_INPT_VCALN = 0b11 // Input is connected to VCALN |
| jbradshaw | 0:e4a10ed6eb92 | 580 | } max30001_emux_calx_sel; |
| jbradshaw | 0:e4a10ed6eb92 | 581 | |
| jbradshaw | 0:e4a10ed6eb92 | 582 | typedef enum { // EN_ECG, EN_BIOZ, EN_PACE |
| jbradshaw | 0:e4a10ed6eb92 | 583 | MAX30001_CHANNEL_DISABLED = 0b0, // |
| jbradshaw | 0:e4a10ed6eb92 | 584 | MAX30001_CHANNEL_ENABLED = 0b1 |
| jbradshaw | 0:e4a10ed6eb92 | 585 | } max30001_en_feature; |
| jbradshaw | 0:e4a10ed6eb92 | 586 | |
| jbradshaw | 0:e4a10ed6eb92 | 587 | /*********************************************************************************/ |
| jbradshaw | 0:e4a10ed6eb92 | 588 | // Data |
| jbradshaw | 0:e4a10ed6eb92 | 589 | uint32_t max30001_ECG_FIFO_buffer[32]; // (303 for internal test) |
| jbradshaw | 0:e4a10ed6eb92 | 590 | uint32_t max30001_BIOZ_FIFO_buffer[8]; // (303 for internal test) |
| jbradshaw | 0:e4a10ed6eb92 | 591 | |
| jbradshaw | 0:e4a10ed6eb92 | 592 | uint32_t max30001_PACE[18]; // Pace Data 0-5 |
| jbradshaw | 0:e4a10ed6eb92 | 593 | |
| jbradshaw | 0:e4a10ed6eb92 | 594 | uint32_t max30001_RtoR_data; // This holds the RtoR data |
| jbradshaw | 0:e4a10ed6eb92 | 595 | |
| jbradshaw | 0:e4a10ed6eb92 | 596 | uint32_t max30001_DCLeadOff; // This holds the LeadOff data, Last 4 bits give |
| jbradshaw | 0:e4a10ed6eb92 | 597 | // the status, BIT3=LOFF_PH, BIT2=LOFF_PL, |
| jbradshaw | 0:e4a10ed6eb92 | 598 | // BIT1=LOFF_NH, BIT0=LOFF_NL |
| jbradshaw | 0:e4a10ed6eb92 | 599 | // 8th and 9th bits tell Lead off is due to ECG or BIOZ. |
| jbradshaw | 0:e4a10ed6eb92 | 600 | // 0b01 = ECG Lead Off and 0b10 = BIOZ Lead off |
| jbradshaw | 0:e4a10ed6eb92 | 601 | |
| jbradshaw | 0:e4a10ed6eb92 | 602 | uint32_t max30001_ACLeadOff; // This gives the state of the BIOZ AC Lead Off |
| jbradshaw | 0:e4a10ed6eb92 | 603 | // state. BIT 1 = BOVER, BIT 0 = BUNDR |
| jbradshaw | 0:e4a10ed6eb92 | 604 | |
| jbradshaw | 0:e4a10ed6eb92 | 605 | uint32_t max30001_bcgmon; // This holds the BCGMON data, BIT 1 = BCGMP, BIT0 = |
| jbradshaw | 0:e4a10ed6eb92 | 606 | // BCGMN |
| jbradshaw | 0:e4a10ed6eb92 | 607 | |
| jbradshaw | 0:e4a10ed6eb92 | 608 | uint32_t max30001_LeadOn; // This holds the LeadOn data, BIT1 = BIOZ Lead ON, |
| jbradshaw | 0:e4a10ed6eb92 | 609 | // BIT0 = ECG Lead ON, BIT8= Lead On Status Bit |
| jbradshaw | 0:e4a10ed6eb92 | 610 | |
| jbradshaw | 0:e4a10ed6eb92 | 611 | uint32_t max30001_timeout; // If the PLL does not respond, timeout and get out. |
| jbradshaw | 0:e4a10ed6eb92 | 612 | |
| jbradshaw | 0:e4a10ed6eb92 | 613 | typedef struct { // Creating a structure for BLE data |
| jbradshaw | 0:e4a10ed6eb92 | 614 | int16_t R2R; |
| jbradshaw | 0:e4a10ed6eb92 | 615 | int16_t fmstr; |
| jbradshaw | 0:e4a10ed6eb92 | 616 | } max30001_t; |
| jbradshaw | 0:e4a10ed6eb92 | 617 | |
| jbradshaw | 0:e4a10ed6eb92 | 618 | max30001_t hspValMax30001; // R2R, FMSTR |
| jbradshaw | 0:e4a10ed6eb92 | 619 | |
| jbradshaw | 0:e4a10ed6eb92 | 620 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 621 | * @brief Constructor that accepts pin names for the SPI interface |
| jbradshaw | 0:e4a10ed6eb92 | 622 | * @param spi pointer to the mbed SPI object |
| jbradshaw | 0:e4a10ed6eb92 | 623 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 624 | MAX30001(SPI *spi); |
| jbradshaw | 0:e4a10ed6eb92 | 625 | |
| jbradshaw | 0:e4a10ed6eb92 | 626 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 627 | * @brief Constructor that accepts pin names for the SPI interface |
| jbradshaw | 0:e4a10ed6eb92 | 628 | * @param mosi master out slave in pin name |
| jbradshaw | 0:e4a10ed6eb92 | 629 | * @param miso master in slave out pin name |
| jbradshaw | 0:e4a10ed6eb92 | 630 | * @param sclk serial clock pin name |
| jbradshaw | 0:e4a10ed6eb92 | 631 | * @param cs chip select pin name |
| jbradshaw | 0:e4a10ed6eb92 | 632 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 633 | MAX30001(PinName mosi, PinName miso, PinName sclk, PinName cs); |
| jbradshaw | 0:e4a10ed6eb92 | 634 | |
| jbradshaw | 0:e4a10ed6eb92 | 635 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 636 | * MAX30001 destructor |
| jbradshaw | 0:e4a10ed6eb92 | 637 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 638 | ~MAX30001(void); |
| jbradshaw | 0:e4a10ed6eb92 | 639 | |
| jbradshaw | 0:e4a10ed6eb92 | 640 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 641 | * @brief This function sets up the Resistive Bias mode and also selects the master clock frequency. |
| jbradshaw | 0:e4a10ed6eb92 | 642 | * @brief Uses Register: CNFG_GEN-0x10 |
| jbradshaw | 0:e4a10ed6eb92 | 643 | * @param En_rbias: Enable and Select Resitive Lead Bias Mode |
| jbradshaw | 0:e4a10ed6eb92 | 644 | * @param Rbiasv: Resistive Bias Mode Value Selection |
| jbradshaw | 0:e4a10ed6eb92 | 645 | * @param Rbiasp: Enables Resistive Bias on Positive Input |
| jbradshaw | 0:e4a10ed6eb92 | 646 | * @param Rbiasn: Enables Resistive Bias on Negative Input |
| jbradshaw | 0:e4a10ed6eb92 | 647 | * @param Fmstr: Selects Master Clock Frequency |
| jbradshaw | 0:e4a10ed6eb92 | 648 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 649 | * |
| jbradshaw | 0:e4a10ed6eb92 | 650 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 651 | int max30001_Rbias_FMSTR_Init(uint8_t En_rbias, uint8_t Rbiasv, |
| jbradshaw | 0:e4a10ed6eb92 | 652 | uint8_t Rbiasp, uint8_t Rbiasn, uint8_t Fmstr); |
| jbradshaw | 0:e4a10ed6eb92 | 653 | |
| jbradshaw | 0:e4a10ed6eb92 | 654 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 655 | * @brief This function uses sets up the calibration signal internally. If it is desired to use the internal signal, then |
| jbradshaw | 0:e4a10ed6eb92 | 656 | * @brief this function must be called and the registers set, prior to setting the CALP_SEL and CALN_SEL in the ECG_InitStart |
| jbradshaw | 0:e4a10ed6eb92 | 657 | * @brief and BIOZ_InitStart functions. |
| jbradshaw | 0:e4a10ed6eb92 | 658 | * @brief Uses Register: CNFG_CAL-0x12 |
| jbradshaw | 0:e4a10ed6eb92 | 659 | * @param En_Vcal: Calibration Source (VCALP and VCALN) Enable |
| jbradshaw | 0:e4a10ed6eb92 | 660 | * @param Vmode: Calibration Source Mode Selection |
| jbradshaw | 0:e4a10ed6eb92 | 661 | * @param Vmag: Calibration Source Magnitude Selection (VMAG) |
| jbradshaw | 0:e4a10ed6eb92 | 662 | * @param Fcal: Calibration Source Frequency Selection (FCAL) |
| jbradshaw | 0:e4a10ed6eb92 | 663 | * @param Thigh: Calibration Source Time High Selection |
| jbradshaw | 0:e4a10ed6eb92 | 664 | * @param Fifty: Calibration Source Duty Cycle Mode Selection |
| jbradshaw | 0:e4a10ed6eb92 | 665 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 666 | * |
| jbradshaw | 0:e4a10ed6eb92 | 667 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 668 | int max30001_CAL_InitStart(uint8_t En_Vcal, uint8_t Vmode, uint8_t Vmag, |
| jbradshaw | 0:e4a10ed6eb92 | 669 | uint8_t Fcal, uint16_t Thigh, uint8_t Fifty); |
| jbradshaw | 0:e4a10ed6eb92 | 670 | |
| jbradshaw | 0:e4a10ed6eb92 | 671 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 672 | * @brief This function disables the VCAL signal |
| jbradshaw | 0:e4a10ed6eb92 | 673 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 674 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 675 | int max30001_CAL_Stop(void); |
| jbradshaw | 0:e4a10ed6eb92 | 676 | |
| jbradshaw | 0:e4a10ed6eb92 | 677 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 678 | * @brief This function handles the assignment of the two interrupt pins (INTB & INT2B) with various |
| jbradshaw | 0:e4a10ed6eb92 | 679 | * @brief functions/behaviors of the MAX30001. Also, each pin can be configured for different drive capability. |
| jbradshaw | 0:e4a10ed6eb92 | 680 | * @brief Uses Registers: EN_INT-0x02 and EN_INT2-0x03. |
| jbradshaw | 0:e4a10ed6eb92 | 681 | * @param max30001_intrpt_Locatio_t <argument>: All the arguments with the aforementioned enumeration essentially |
| jbradshaw | 0:e4a10ed6eb92 | 682 | * can be configured to generate an interrupt on either INTB or INT2B or NONE. |
| jbradshaw | 0:e4a10ed6eb92 | 683 | * @param max30001_intrpt_type_t intb_Type: INTB Port Type (EN_INT Selections). |
| jbradshaw | 0:e4a10ed6eb92 | 684 | * @param max30001_intrpt_type _t int2b_Type: INT2B Port Type (EN_INT2 Selections) |
| jbradshaw | 0:e4a10ed6eb92 | 685 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 686 | * |
| jbradshaw | 0:e4a10ed6eb92 | 687 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 688 | int max30001_INT_assignment(max30001_intrpt_Location_t en_enint_loc, max30001_intrpt_Location_t en_eovf_loc, max30001_intrpt_Location_t en_fstint_loc, |
| jbradshaw | 0:e4a10ed6eb92 | 689 | max30001_intrpt_Location_t en_dcloffint_loc, max30001_intrpt_Location_t en_bint_loc, max30001_intrpt_Location_t en_bovf_loc, |
| jbradshaw | 0:e4a10ed6eb92 | 690 | max30001_intrpt_Location_t en_bover_loc, max30001_intrpt_Location_t en_bundr_loc, max30001_intrpt_Location_t en_bcgmon_loc, |
| jbradshaw | 0:e4a10ed6eb92 | 691 | max30001_intrpt_Location_t en_pint_loc, max30001_intrpt_Location_t en_povf_loc, max30001_intrpt_Location_t en_pedge_loc, |
| jbradshaw | 0:e4a10ed6eb92 | 692 | max30001_intrpt_Location_t en_lonint_loc, max30001_intrpt_Location_t en_rrint_loc, max30001_intrpt_Location_t en_samp_loc, |
| jbradshaw | 0:e4a10ed6eb92 | 693 | max30001_intrpt_type_t intb_Type, max30001_intrpt_type_t int2b_Type); |
| jbradshaw | 0:e4a10ed6eb92 | 694 | |
| jbradshaw | 0:e4a10ed6eb92 | 695 | |
| jbradshaw | 0:e4a10ed6eb92 | 696 | |
| jbradshaw | 0:e4a10ed6eb92 | 697 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 698 | * @brief For MAX30001/3 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 699 | * @brief This function sets up the MAX30001 for the ECG measurements. |
| jbradshaw | 0:e4a10ed6eb92 | 700 | * @brief Registers used: CNFG_EMUX, CNFG_GEN, MNGR_INT, CNFG_ECG. |
| jbradshaw | 0:e4a10ed6eb92 | 701 | * @param En_ecg: ECG Channel Enable <CNFG_GEN register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 702 | * @param Openp: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 703 | * @param Openn: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 704 | * @param Calp_sel: ECGP Calibration Selection <CNFG_EMUX register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 705 | * @param Caln_sel: ECGN Calibration Selection <CNFG_EMUX register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 706 | * @param E_fit: ECG FIFO Interrupt Threshold (issues EINT based on number of unread FIFO records) <CNFG_GEN register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 707 | * @param Clr_rrint: RTOR R Detect Interrupt (RRINT) Clear Behavior <CNFG_GEN register bits> |
| jbradshaw | 0:e4a10ed6eb92 | 708 | * @param Rate: ECG Data Rate |
| jbradshaw | 0:e4a10ed6eb92 | 709 | * @param Gain: ECG Channel Gain Setting |
| jbradshaw | 0:e4a10ed6eb92 | 710 | * @param Dhpf: ECG Channel Digital High Pass Filter Cutoff Frequency |
| jbradshaw | 0:e4a10ed6eb92 | 711 | * @param Dlpf: ECG Channel Digital Low Pass Filter Cutoff Frequency |
| jbradshaw | 0:e4a10ed6eb92 | 712 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 713 | * |
| jbradshaw | 0:e4a10ed6eb92 | 714 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 715 | int max30001_ECG_InitStart(uint8_t En_ecg, uint8_t Openp, uint8_t Openn, |
| jbradshaw | 0:e4a10ed6eb92 | 716 | uint8_t Pol, uint8_t Calp_sel, uint8_t Caln_sel, |
| jbradshaw | 0:e4a10ed6eb92 | 717 | uint8_t E_fit, uint8_t Rate, uint8_t Gain, |
| jbradshaw | 0:e4a10ed6eb92 | 718 | uint8_t Dhpf, uint8_t Dlpf); |
| jbradshaw | 0:e4a10ed6eb92 | 719 | |
| jbradshaw | 0:e4a10ed6eb92 | 720 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 721 | * @brief For MAX30001/3 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 722 | * @brief This function enables the Fast mode feature of the ECG. |
| jbradshaw | 0:e4a10ed6eb92 | 723 | * @brief Registers used: MNGR_INT-0x04, MNGR_DYN-0x05 |
| jbradshaw | 0:e4a10ed6eb92 | 724 | * @param Clr_Fast: FAST MODE Interrupt Clear Behavior <MNGR_INT Register> |
| jbradshaw | 0:e4a10ed6eb92 | 725 | * @param Fast: ECG Channel Fast Recovery Mode Selection (ECG High Pass Filter Bypass) <MNGR_DYN Register> |
| jbradshaw | 0:e4a10ed6eb92 | 726 | * @param Fast_Th: Automatic Fast Recovery Threshold |
| jbradshaw | 0:e4a10ed6eb92 | 727 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 728 | * |
| jbradshaw | 0:e4a10ed6eb92 | 729 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 730 | int max30001_ECGFast_Init(uint8_t Clr_Fast, uint8_t Fast, uint8_t Fast_Th); |
| jbradshaw | 0:e4a10ed6eb92 | 731 | |
| jbradshaw | 0:e4a10ed6eb92 | 732 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 733 | * @brief For MAX30001/3 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 734 | * @brief This function disables the ECG. |
| jbradshaw | 0:e4a10ed6eb92 | 735 | * @brief Uses Register CNFG_GEN-0x10. |
| jbradshaw | 0:e4a10ed6eb92 | 736 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 737 | * |
| jbradshaw | 0:e4a10ed6eb92 | 738 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 739 | int max30001_Stop_ECG(void); |
| jbradshaw | 0:e4a10ed6eb92 | 740 | |
| jbradshaw | 0:e4a10ed6eb92 | 741 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 742 | * @brief For MAX30001 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 743 | * @brief This function sets up the MAX30001 for pace signal detection. |
| jbradshaw | 0:e4a10ed6eb92 | 744 | * @brief If both PACE and BIOZ are turned ON, then make sure Fcgen is set for 80K or 40K in the |
| jbradshaw | 0:e4a10ed6eb92 | 745 | * @brief max30001_BIOZ_InitStart() function. However, if Only PACE is on but BIOZ off, then Fcgen can be set |
| jbradshaw | 0:e4a10ed6eb92 | 746 | * @brief for 80K only, in the max30001_BIOZ_InitStart() function |
| jbradshaw | 0:e4a10ed6eb92 | 747 | * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0x37, CNFG_PACE-0x1A. |
| jbradshaw | 0:e4a10ed6eb92 | 748 | * @param En_pace : PACE Channel Enable <CNFG_GEN Register> |
| jbradshaw | 0:e4a10ed6eb92 | 749 | * @param Clr_pedge : PACE Edge Detect Interrupt (PEDGE) Clear Behavior <MNGR_INT Register> |
| jbradshaw | 0:e4a10ed6eb92 | 750 | * @param Pol: PACE Input Polarity Selection <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 751 | * @param Gn_diff_off: PACE Differentiator Mode <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 752 | * @param Gain: PACE Channel Gain Selection <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 753 | * @param Aout_lbw: PACE Analog Output Buffer Bandwidth Mode <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 754 | * @param Aout: PACE Single Ended Analog Output Buffer Signal Monitoring Selection <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 755 | * @param Dacp (4bits): PACE Detector Positive Comparator Threshold <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 756 | * @param Dacn(4bits): PACE Detector Negative Comparator Threshold <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 757 | * @returns 0-if no error. A non-zero value indicates an error <CNFG_PACE Register> |
| jbradshaw | 0:e4a10ed6eb92 | 758 | * |
| jbradshaw | 0:e4a10ed6eb92 | 759 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 760 | int max30001_PACE_InitStart(uint8_t En_pace, uint8_t Clr_pedge, uint8_t Pol, |
| jbradshaw | 0:e4a10ed6eb92 | 761 | uint8_t Gn_diff_off, uint8_t Gain, |
| jbradshaw | 0:e4a10ed6eb92 | 762 | uint8_t Aout_lbw, uint8_t Aout, uint8_t Dacp, |
| jbradshaw | 0:e4a10ed6eb92 | 763 | uint8_t Dacn); |
| jbradshaw | 0:e4a10ed6eb92 | 764 | |
| jbradshaw | 0:e4a10ed6eb92 | 765 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 766 | *@brief For MAX30001 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 767 | *@param This function disables the PACE. Uses Register CNFG_GEN-0x10. |
| jbradshaw | 0:e4a10ed6eb92 | 768 | *@returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 769 | * |
| jbradshaw | 0:e4a10ed6eb92 | 770 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 771 | int max30001_Stop_PACE(void); |
| jbradshaw | 0:e4a10ed6eb92 | 772 | |
| jbradshaw | 0:e4a10ed6eb92 | 773 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 774 | * @brief For MAX30001/2 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 775 | * @brief This function sets up the MAX30001 for BIOZ measurement. |
| jbradshaw | 0:e4a10ed6eb92 | 776 | * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0X10, CNFG_BMUX-0x17,CNFG_BIOZ-0x18. |
| jbradshaw | 0:e4a10ed6eb92 | 777 | * @param En_bioz: BIOZ Channel Enable <CNFG_GEN Register> |
| jbradshaw | 0:e4a10ed6eb92 | 778 | * @param Openp: Open the BIP Input Switch <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 779 | * @param Openn: Open the BIN Input Switch <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 780 | * @param Calp_sel: BIP Calibration Selection <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 781 | * @param Caln_sel: BIN Calibration Selection <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 782 | * @param CG_mode: BIOZ Current Generator Mode Selection <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 783 | * @param B_fit: BIOZ FIFO Interrupt Threshold (issues BINT based on number of unread FIFO records) <MNGR_INT Register> |
| jbradshaw | 0:e4a10ed6eb92 | 784 | * @param Rate: BIOZ Data Rate <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 785 | * @param Ahpf: BIOZ/PACE Channel Analog High Pass Filter Cutoff Frequency and Bypass <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 786 | * @param Ext_rbias: External Resistor Bias Enable <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 787 | * @param Gain: BIOZ Channel Gain Setting <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 788 | * @param Dhpf: BIOZ Channel Digital High Pass Filter Cutoff Frequency <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 789 | * @param Dlpf: BIOZ Channel Digital Low Pass Filter Cutoff Frequency <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 790 | * @param Fcgen: BIOZ Current Generator Modulation Frequency <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 791 | * @param Cgmon: BIOZ Current Generator Monitor <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 792 | * @param Cgmag: BIOZ Current Generator Magnitude <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 793 | * @param Phoff: BIOZ Current Generator Modulation Phase Offset <CNFG_BIOZ Register> |
| jbradshaw | 0:e4a10ed6eb92 | 794 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 795 | * |
| jbradshaw | 0:e4a10ed6eb92 | 796 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 797 | int max30001_BIOZ_InitStart(uint8_t En_bioz, uint8_t Openp, uint8_t Openn, |
| jbradshaw | 0:e4a10ed6eb92 | 798 | uint8_t Calp_sel, uint8_t Caln_sel, |
| jbradshaw | 0:e4a10ed6eb92 | 799 | uint8_t CG_mode, |
| jbradshaw | 0:e4a10ed6eb92 | 800 | /* uint8_t En_bioz,*/ uint8_t B_fit, uint8_t Rate, |
| jbradshaw | 0:e4a10ed6eb92 | 801 | uint8_t Ahpf, uint8_t Ext_rbias, uint8_t Gain, |
| jbradshaw | 0:e4a10ed6eb92 | 802 | uint8_t Dhpf, uint8_t Dlpf, uint8_t Fcgen, |
| jbradshaw | 0:e4a10ed6eb92 | 803 | uint8_t Cgmon, uint8_t Cgmag, uint8_t Phoff); |
| jbradshaw | 0:e4a10ed6eb92 | 804 | |
| jbradshaw | 0:e4a10ed6eb92 | 805 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 806 | * @brief For MAX30001/2 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 807 | * @brief This function disables the BIOZ. Uses Register CNFG_GEN-0x10. |
| jbradshaw | 0:e4a10ed6eb92 | 808 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 809 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 810 | * |
| jbradshaw | 0:e4a10ed6eb92 | 811 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 812 | int max30001_Stop_BIOZ(void); |
| jbradshaw | 0:e4a10ed6eb92 | 813 | |
| jbradshaw | 0:e4a10ed6eb92 | 814 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 815 | * @brief For MAX30001/2 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 816 | * @brief BIOZ modulated Resistance Built-in-Self-Test, Registers used: CNFG_BMUX-0x17 |
| jbradshaw | 0:e4a10ed6eb92 | 817 | * @param En_bist: Enable Modulated Resistance Built-in-Self-test <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 818 | * @param Rnom: BIOZ RMOD BIST Nominal Resistance Selection <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 819 | * @param Rmod: BIOZ RMOD BIST Modulated Resistance Selection <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 820 | * @param Fbist: BIOZ RMOD BIST Frequency Selection <CNFG_BMUX Register> |
| jbradshaw | 0:e4a10ed6eb92 | 821 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 822 | * |
| jbradshaw | 0:e4a10ed6eb92 | 823 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 824 | int max30001_BIOZ_InitBist(uint8_t En_bist, uint8_t Rnom, uint8_t Rmod, |
| jbradshaw | 0:e4a10ed6eb92 | 825 | uint8_t Fbist); |
| jbradshaw | 0:e4a10ed6eb92 | 826 | |
| jbradshaw | 0:e4a10ed6eb92 | 827 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 828 | * @brief For MAX30001/3/4 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 829 | * @brief Sets up the device for RtoR measurement |
| jbradshaw | 0:e4a10ed6eb92 | 830 | * @param EN_rtor: ECG RTOR Detection Enable <RTOR1 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 831 | * @param Wndw: R to R Window Averaging (Window Width = RTOR_WNDW[3:0]*8mS) <RTOR1 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 832 | * @param Gain: R to R Gain (where Gain = 2^RTOR_GAIN[3:0], plus an auto-scale option) <RTOR1 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 833 | * @param Pavg: R to R Peak Averaging Weight Factor <RTOR1 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 834 | * @param Ptsf: R to R Peak Threshold Scaling Factor <RTOR1 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 835 | * @param Hoff: R to R minimum Hold Off <RTOR2 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 836 | * @param Ravg: R to R Interval Averaging Weight Factor <RTOR2 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 837 | * @param Rhsf: R to R Interval Hold Off Scaling Factor <RTOR2 Register> |
| jbradshaw | 0:e4a10ed6eb92 | 838 | * @param Clr_rrint: RTOR Detect Interrupt Clear behaviour <MNGR_INT Register> |
| jbradshaw | 0:e4a10ed6eb92 | 839 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 840 | * |
| jbradshaw | 0:e4a10ed6eb92 | 841 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 842 | int max30001_RtoR_InitStart(uint8_t En_rtor, uint8_t Wndw, uint8_t Gain, |
| jbradshaw | 0:e4a10ed6eb92 | 843 | uint8_t Pavg, uint8_t Ptsf, uint8_t Hoff, |
| jbradshaw | 0:e4a10ed6eb92 | 844 | uint8_t Ravg, uint8_t Rhsf, uint8_t Clr_rrint); |
| jbradshaw | 0:e4a10ed6eb92 | 845 | |
| jbradshaw | 0:e4a10ed6eb92 | 846 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 847 | * @brief For MAX30001/3/4 ONLY |
| jbradshaw | 0:e4a10ed6eb92 | 848 | * @brief This function disables the RtoR. Uses Register CNFG_RTOR1-0x1D |
| jbradshaw | 0:e4a10ed6eb92 | 849 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 850 | * |
| jbradshaw | 0:e4a10ed6eb92 | 851 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 852 | int max30001_Stop_RtoR(void); |
| jbradshaw | 0:e4a10ed6eb92 | 853 | |
| jbradshaw | 0:e4a10ed6eb92 | 854 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 855 | * @brief This is a function that waits for the PLL to lock; once a lock is achieved it exits out. (For convenience only) |
| jbradshaw | 0:e4a10ed6eb92 | 856 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 857 | * |
| jbradshaw | 0:e4a10ed6eb92 | 858 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 859 | int max30001_PLL_lock(void); |
| jbradshaw | 0:e4a10ed6eb92 | 860 | |
| jbradshaw | 0:e4a10ed6eb92 | 861 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 862 | * @brief This function causes the MAX30001 to reset. Uses Register SW_RST-0x08 |
| jbradshaw | 0:e4a10ed6eb92 | 863 | * @return 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 864 | * |
| jbradshaw | 0:e4a10ed6eb92 | 865 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 866 | int max30001_sw_rst(void); |
| jbradshaw | 0:e4a10ed6eb92 | 867 | |
| jbradshaw | 0:e4a10ed6eb92 | 868 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 869 | * @brief This function provides a SYNCH operation. Uses Register SYCNH-0x09. Please refer to the data sheet for |
| jbradshaw | 0:e4a10ed6eb92 | 870 | * @brief the details on how to use this. |
| jbradshaw | 0:e4a10ed6eb92 | 871 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 872 | * |
| jbradshaw | 0:e4a10ed6eb92 | 873 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 874 | int max30001_synch(void); |
| jbradshaw | 0:e4a10ed6eb92 | 875 | |
| jbradshaw | 0:e4a10ed6eb92 | 876 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 877 | * @brief This function performs a FIFO Reset. Uses Register FIFO_RST-0x0A. Please refer to the data sheet |
| jbradshaw | 0:e4a10ed6eb92 | 878 | * @brief for the details on how to use this. |
| jbradshaw | 0:e4a10ed6eb92 | 879 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 880 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 881 | int max300001_fifo_rst(void); |
| jbradshaw | 0:e4a10ed6eb92 | 882 | |
| jbradshaw | 0:e4a10ed6eb92 | 883 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 884 | * |
| jbradshaw | 0:e4a10ed6eb92 | 885 | * @brief This is a callback function which collects all the data from the ECG, BIOZ, PACE and RtoR. It also handles |
| jbradshaw | 0:e4a10ed6eb92 | 886 | * @brief Lead On/Off. This function is passed through the argument of max30001_COMMinit(). |
| jbradshaw | 0:e4a10ed6eb92 | 887 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 888 | * |
| jbradshaw | 0:e4a10ed6eb92 | 889 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 890 | int max30001_int_handler(void); |
| jbradshaw | 0:e4a10ed6eb92 | 891 | |
| jbradshaw | 0:e4a10ed6eb92 | 892 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 893 | * @brief This is function called from the max30001_int_handler() function and processes all the ECG, BIOZ, PACE |
| jbradshaw | 0:e4a10ed6eb92 | 894 | * @brief and the RtoR data and sticks them in appropriate arrays and variables each unsigned 32 bits. |
| jbradshaw | 0:e4a10ed6eb92 | 895 | * @param ECG data will be in the array (input): max30001_ECG_FIFO_buffer[] |
| jbradshaw | 0:e4a10ed6eb92 | 896 | * @param Pace data will be in the array (input): max30001_PACE[] |
| jbradshaw | 0:e4a10ed6eb92 | 897 | * @param RtoRdata will be in the variable (input): max30001_RtoR_data |
| jbradshaw | 0:e4a10ed6eb92 | 898 | * @param BIOZ data will be in the array (input): max30001_BIOZ_FIFO_buffer[] |
| jbradshaw | 0:e4a10ed6eb92 | 899 | * @param global max30001_ECG_FIFO_buffer[] |
| jbradshaw | 0:e4a10ed6eb92 | 900 | * @param global max30001_PACE[] |
| jbradshaw | 0:e4a10ed6eb92 | 901 | * @param global max30001_BIOZ_FIFO_buffer[] |
| jbradshaw | 0:e4a10ed6eb92 | 902 | * @param global max30001_RtoR_data |
| jbradshaw | 0:e4a10ed6eb92 | 903 | * @param global max30001_DCLeadOff |
| jbradshaw | 0:e4a10ed6eb92 | 904 | * @param global max30001_ACLeadOff |
| jbradshaw | 0:e4a10ed6eb92 | 905 | * @param global max30001_LeadON |
| jbradshaw | 0:e4a10ed6eb92 | 906 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 907 | * |
| jbradshaw | 0:e4a10ed6eb92 | 908 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 909 | int max30001_FIFO_LeadONOff_Read(void); |
| jbradshaw | 0:e4a10ed6eb92 | 910 | |
| jbradshaw | 0:e4a10ed6eb92 | 911 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 912 | * @brief This function allows writing to a register. |
| jbradshaw | 0:e4a10ed6eb92 | 913 | * @param addr: Address of the register to write to |
| jbradshaw | 0:e4a10ed6eb92 | 914 | * @param data: 24-bit data read from the register. |
| jbradshaw | 0:e4a10ed6eb92 | 915 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 916 | * |
| jbradshaw | 0:e4a10ed6eb92 | 917 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 918 | int max30001_reg_write(MAX30001_REG_map_t addr, uint32_t data); |
| jbradshaw | 0:e4a10ed6eb92 | 919 | |
| jbradshaw | 0:e4a10ed6eb92 | 920 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 921 | * @brief This function allows reading from a register |
| jbradshaw | 0:e4a10ed6eb92 | 922 | * @param addr: Address of the register to read from. |
| jbradshaw | 0:e4a10ed6eb92 | 923 | * @param *return_data: pointer to the value read from the register. |
| jbradshaw | 0:e4a10ed6eb92 | 924 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 925 | * |
| jbradshaw | 0:e4a10ed6eb92 | 926 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 927 | int max30001_reg_read(MAX30001_REG_map_t addr, uint32_t *return_data); |
| jbradshaw | 0:e4a10ed6eb92 | 928 | |
| jbradshaw | 0:e4a10ed6eb92 | 929 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 930 | * @brief This function enables the DC Lead Off detection. Either ECG or BIOZ can be detected, one at a time. |
| jbradshaw | 0:e4a10ed6eb92 | 931 | * @brief Registers Used: CNFG_GEN-0x10 |
| jbradshaw | 0:e4a10ed6eb92 | 932 | * @param En_dcloff: BIOZ Digital Lead Off Detection Enable |
| jbradshaw | 0:e4a10ed6eb92 | 933 | * @param Ipol: DC Lead Off Current Polarity (if current sources are enabled/connected) |
| jbradshaw | 0:e4a10ed6eb92 | 934 | * @param Imag: DC Lead off current Magnitude Selection |
| jbradshaw | 0:e4a10ed6eb92 | 935 | * @param Vth: DC Lead Off Voltage Threshold Selection |
| jbradshaw | 0:e4a10ed6eb92 | 936 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 937 | * |
| jbradshaw | 0:e4a10ed6eb92 | 938 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 939 | int max30001_Enable_DcLeadOFF_Init(int8_t En_dcloff, int8_t Ipol, int8_t Imag, |
| jbradshaw | 0:e4a10ed6eb92 | 940 | int8_t Vth); |
| jbradshaw | 0:e4a10ed6eb92 | 941 | |
| jbradshaw | 0:e4a10ed6eb92 | 942 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 943 | * @brief This function disables the DC Lead OFF feature, whichever is active. |
| jbradshaw | 0:e4a10ed6eb92 | 944 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 945 | * |
| jbradshaw | 0:e4a10ed6eb92 | 946 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 947 | int max30001_Disable_DcLeadOFF(void); |
| jbradshaw | 0:e4a10ed6eb92 | 948 | |
| jbradshaw | 0:e4a10ed6eb92 | 949 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 950 | * @brief This function sets up the BIOZ for AC Lead Off test. |
| jbradshaw | 0:e4a10ed6eb92 | 951 | * @brief Registers Used: CNFG_GEN-0x10, MNGR_DYN-0x05 |
| jbradshaw | 0:e4a10ed6eb92 | 952 | * @param En_bloff: BIOZ Digital Lead Off Detection Enable <CNFG_GEN register> |
| jbradshaw | 0:e4a10ed6eb92 | 953 | * @param Bloff_hi_it: DC Lead Off Current Polarity (if current sources are enabled/connected) <MNGR_DYN register> |
| jbradshaw | 0:e4a10ed6eb92 | 954 | * @param Bloff_lo_it: DC Lead off current Magnitude Selection <MNGR_DYN register> |
| jbradshaw | 0:e4a10ed6eb92 | 955 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 956 | * |
| jbradshaw | 0:e4a10ed6eb92 | 957 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 958 | int max30001_BIOZ_Enable_ACLeadOFF_Init(uint8_t En_bloff, uint8_t Bloff_hi_it, |
| jbradshaw | 0:e4a10ed6eb92 | 959 | uint8_t Bloff_lo_it); |
| jbradshaw | 0:e4a10ed6eb92 | 960 | |
| jbradshaw | 0:e4a10ed6eb92 | 961 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 962 | * @brief This function Turns of the BIOZ AC Lead OFF feature |
| jbradshaw | 0:e4a10ed6eb92 | 963 | * @brief Registers Used: CNFG_GEN-0x10 |
| jbradshaw | 0:e4a10ed6eb92 | 964 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 965 | * |
| jbradshaw | 0:e4a10ed6eb92 | 966 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 967 | int max30001_BIOZ_Disable_ACleadOFF(void); |
| jbradshaw | 0:e4a10ed6eb92 | 968 | |
| jbradshaw | 0:e4a10ed6eb92 | 969 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 970 | * @brief This function enables the Current Gnerator Monitor |
| jbradshaw | 0:e4a10ed6eb92 | 971 | * @brief Registers Used: CNFG_BIOZ-0x18 |
| jbradshaw | 0:e4a10ed6eb92 | 972 | * @returns 0-if no error. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 973 | * |
| jbradshaw | 0:e4a10ed6eb92 | 974 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 975 | int max30001_BIOZ_Enable_BCGMON(void); |
| jbradshaw | 0:e4a10ed6eb92 | 976 | |
| jbradshaw | 0:e4a10ed6eb92 | 977 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 978 | * |
| jbradshaw | 0:e4a10ed6eb92 | 979 | * @brief This function enables the Lead ON detection. Either ECG or BIOZ can be detected, one at a time. |
| jbradshaw | 0:e4a10ed6eb92 | 980 | * @brief Also, the en_bioz, en_ecg, en_pace setting is saved so that when this feature is disabled through the |
| jbradshaw | 0:e4a10ed6eb92 | 981 | * @brief max30001_Disable_LeadON() function (or otherwise) the enable/disable state of those features can be retrieved. |
| jbradshaw | 0:e4a10ed6eb92 | 982 | * @param Channel: ECG or BIOZ detection |
| jbradshaw | 0:e4a10ed6eb92 | 983 | * @returns 0-if everything is good. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 984 | * |
| jbradshaw | 0:e4a10ed6eb92 | 985 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 986 | int max30001_Enable_LeadON(int8_t Channel); |
| jbradshaw | 0:e4a10ed6eb92 | 987 | |
| jbradshaw | 0:e4a10ed6eb92 | 988 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 989 | * @brief This function turns off the Lead ON feature, whichever one is active. Also, retrieves the en_bioz, |
| jbradshaw | 0:e4a10ed6eb92 | 990 | * @brief en_ecg, en_pace and sets it back to as it was. |
| jbradshaw | 0:e4a10ed6eb92 | 991 | * @param 0-if everything is good. A non-zero value indicates an error. |
| jbradshaw | 0:e4a10ed6eb92 | 992 | * |
| jbradshaw | 0:e4a10ed6eb92 | 993 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 994 | int max30001_Disable_LeadON(void); |
| jbradshaw | 0:e4a10ed6eb92 | 995 | |
| jbradshaw | 0:e4a10ed6eb92 | 996 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 997 | * |
| jbradshaw | 0:e4a10ed6eb92 | 998 | * @brief This function is toggled every 2 seconds to switch between ECG Lead ON and BIOZ Lead ON detect |
| jbradshaw | 0:e4a10ed6eb92 | 999 | * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles. |
| jbradshaw | 0:e4a10ed6eb92 | 1000 | * @param CurrentTime - This gets fed the time by RTC_GetValue function |
| jbradshaw | 0:e4a10ed6eb92 | 1001 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1002 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1003 | void max30001_ServiceLeadON(uint32_t currentTime); |
| jbradshaw | 0:e4a10ed6eb92 | 1004 | |
| jbradshaw | 0:e4a10ed6eb92 | 1005 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1006 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1007 | * @brief This function is toggled every 2 seconds to switch between ECG DC Lead Off and BIOZ DC Lead Off |
| jbradshaw | 0:e4a10ed6eb92 | 1008 | * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles. |
| jbradshaw | 0:e4a10ed6eb92 | 1009 | * @param CurrentTime - This gets fed the time by RTC_GetValue function |
| jbradshaw | 0:e4a10ed6eb92 | 1010 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1011 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1012 | void max30001_ServiceLeadoff(uint32_t currentTime); |
| jbradshaw | 0:e4a10ed6eb92 | 1013 | |
| jbradshaw | 0:e4a10ed6eb92 | 1014 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1015 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1016 | * @brief This function sets current RtoR values and fmstr values in a pointer structure |
| jbradshaw | 0:e4a10ed6eb92 | 1017 | * @param hspValMax30001 - Pointer to a structure where to store the values |
| jbradshaw | 0:e4a10ed6eb92 | 1018 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1019 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1020 | void max30001_ReadHeartrateData(max30001_t *_hspValMax30001); |
| jbradshaw | 0:e4a10ed6eb92 | 1021 | |
| jbradshaw | 0:e4a10ed6eb92 | 1022 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1023 | * @brief type definition for data interrupt |
| jbradshaw | 0:e4a10ed6eb92 | 1024 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1025 | typedef void (*PtrFunction)(uint32_t id, uint32_t *buffer, uint32_t length); |
| jbradshaw | 0:e4a10ed6eb92 | 1026 | |
| jbradshaw | 0:e4a10ed6eb92 | 1027 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1028 | * @brief Used to connect a callback for when interrupt data is available |
| jbradshaw | 0:e4a10ed6eb92 | 1029 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1030 | void onDataAvailable(PtrFunction _onDataAvailable); |
| jbradshaw | 0:e4a10ed6eb92 | 1031 | |
| jbradshaw | 0:e4a10ed6eb92 | 1032 | static MAX30001 *instance; |
| jbradshaw | 0:e4a10ed6eb92 | 1033 | |
| jbradshaw | 0:e4a10ed6eb92 | 1034 | private: |
| jbradshaw | 0:e4a10ed6eb92 | 1035 | void dataAvailable(uint32_t id, uint32_t *buffer, uint32_t length); |
| jbradshaw | 0:e4a10ed6eb92 | 1036 | /// interrupt handler for async spi events |
| jbradshaw | 0:e4a10ed6eb92 | 1037 | static void spiHandler(int events); |
| jbradshaw | 0:e4a10ed6eb92 | 1038 | /// wrapper method to transmit and recieve SPI data |
| jbradshaw | 0:e4a10ed6eb92 | 1039 | int SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size, uint8_t *rx_buf, |
| jbradshaw | 0:e4a10ed6eb92 | 1040 | uint32_t rx_size); |
| jbradshaw | 0:e4a10ed6eb92 | 1041 | |
| jbradshaw | 0:e4a10ed6eb92 | 1042 | /// pointer to mbed SPI object |
| jbradshaw | 0:e4a10ed6eb92 | 1043 | SPI *spi; |
| jbradshaw | 0:e4a10ed6eb92 | 1044 | /// is this object the owner of the spi object |
| jbradshaw | 0:e4a10ed6eb92 | 1045 | bool spi_owner; |
| jbradshaw | 0:e4a10ed6eb92 | 1046 | /// buffer to use for async transfers |
| jbradshaw | 0:e4a10ed6eb92 | 1047 | uint8_t buffer[ASYNC_SPI_BUFFER_SIZE]; |
| jbradshaw | 0:e4a10ed6eb92 | 1048 | /// function pointer to the async callback |
| jbradshaw | 0:e4a10ed6eb92 | 1049 | event_callback_t functionpointer; |
| jbradshaw | 0:e4a10ed6eb92 | 1050 | /// callback function when interrupt data is available |
| jbradshaw | 0:e4a10ed6eb92 | 1051 | PtrFunction onDataAvailableCallback; |
| jbradshaw | 0:e4a10ed6eb92 | 1052 | |
| jbradshaw | 0:e4a10ed6eb92 | 1053 | }; // End of MAX30001 Class |
| jbradshaw | 0:e4a10ed6eb92 | 1054 | |
| jbradshaw | 0:e4a10ed6eb92 | 1055 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1056 | * @brief Preventive measure used to dismiss interrupts that fire too early during |
| jbradshaw | 0:e4a10ed6eb92 | 1057 | * @brief initialization on INTB line |
| jbradshaw | 0:e4a10ed6eb92 | 1058 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1059 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1060 | void MAX30001Mid_IntB_Handler(void); |
| jbradshaw | 0:e4a10ed6eb92 | 1061 | |
| jbradshaw | 0:e4a10ed6eb92 | 1062 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1063 | * @brief Preventive measure used to dismiss interrupts that fire too early during |
| jbradshaw | 0:e4a10ed6eb92 | 1064 | * @brief initialization on INT2B line |
| jbradshaw | 0:e4a10ed6eb92 | 1065 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1066 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1067 | void MAX30001Mid_Int2B_Handler(void); |
| jbradshaw | 0:e4a10ed6eb92 | 1068 | |
| jbradshaw | 0:e4a10ed6eb92 | 1069 | /** |
| jbradshaw | 0:e4a10ed6eb92 | 1070 | * @brief Allows Interrupts to be accepted as valid. |
| jbradshaw | 0:e4a10ed6eb92 | 1071 | * @param state: 1-Allow interrupts, Any-Don't allow interrupts. |
| jbradshaw | 0:e4a10ed6eb92 | 1072 | * |
| jbradshaw | 0:e4a10ed6eb92 | 1073 | */ |
| jbradshaw | 0:e4a10ed6eb92 | 1074 | void MAX30001_AllowInterrupts(int state); |
| jbradshaw | 0:e4a10ed6eb92 | 1075 | |
| jbradshaw | 0:e4a10ed6eb92 | 1076 | #endif /* MAX30001_H_ */ |