Maxim Integrated / Mbed OS HSP_RPC_GUI

MAX32620HSP (MAXREFDES100) RPC Example for Graphical User Interface

Dependencies:   USBDevice

Fork of HSP_Release by Jerry Bradshaw

This is an example program for the MAX32620HSP (MAXREFDES100 Health Sensor Platform). It demonstrates all the features of the platform and works with a companion graphical user interface (GUI) to help evaluate/configure/monitor the board. Go to the MAXREFDES100 product page and click on "design resources" to download the companion software. The GUI connects to the board through an RPC interface on a virtual serial port over the USB interface.

The RPC interface provides access to all the features of the board and is available to interface with other development environments such Matlab. This firmware provides realtime data streaming through the RPC interface over USB, and also provides the ability to log the data to flash for untethered battery operation. The data logging settings are configured through the GUI, and the GUI also provides the interface to download logged data.

Details on the RPC interface can be found here: HSP RPC Interface Documentation

Windows

With this program loaded, the MAX32620HSP will appear on your computer as a serial port. On Mac and Linux, this will happen by default. For Windows, you need to install a driver: HSP serial port windows driver

For more details about this platform and how to use it, see the MAXREFDES100 product page.

HSP/Devices/MAX30001/MAX30001/MAX30001.cpp@3:8e9b9f5818aa, 2017-04-25 (annotated)

Committer:
jbradshaw
Date:
Tue Apr 25 10:47:10 2017 -0500
Revision:
3:8e9b9f5818aa
Parent:
1:9490836294ea 
Removed Bulk Erasing, instead a small number of bytes are sampled from each and every page to determine if sector is "dirty", if so sector is erased

Prevents device from sleeping when the firmware detects a series of binary flash page RPC transfers, this increases flash page transfers by %450

  when 200mS elapse with the last flash page transfer, normal sleep behaviour is resumed

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jbradshaw 0:e4a10ed6eb92 1 /*******************************************************************************
jbradshaw 0:e4a10ed6eb92 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
jbradshaw 0:e4a10ed6eb92 3 *
jbradshaw 0:e4a10ed6eb92 4 * Permission is hereby granted, free of charge, to any person obtaining a
jbradshaw 0:e4a10ed6eb92 5 * copy of this software and associated documentation files (the "Software"),
jbradshaw 0:e4a10ed6eb92 6 * to deal in the Software without restriction, including without limitation
jbradshaw 0:e4a10ed6eb92 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
jbradshaw 0:e4a10ed6eb92 8 * and/or sell copies of the Software, and to permit persons to whom the
jbradshaw 0:e4a10ed6eb92 9 * Software is furnished to do so, subject to the following conditions:
jbradshaw 0:e4a10ed6eb92 10 *
jbradshaw 0:e4a10ed6eb92 11 * The above copyright notice and this permission notice shall be included
jbradshaw 0:e4a10ed6eb92 12 * in all copies or substantial portions of the Software.
jbradshaw 0:e4a10ed6eb92 13 *
jbradshaw 0:e4a10ed6eb92 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
jbradshaw 0:e4a10ed6eb92 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
jbradshaw 0:e4a10ed6eb92 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
jbradshaw 0:e4a10ed6eb92 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
jbradshaw 0:e4a10ed6eb92 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
jbradshaw 0:e4a10ed6eb92 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
jbradshaw 0:e4a10ed6eb92 20 * OTHER DEALINGS IN THE SOFTWARE.
jbradshaw 0:e4a10ed6eb92 21 *
jbradshaw 0:e4a10ed6eb92 22 * Except as contained in this notice, the name of Maxim Integrated
jbradshaw 0:e4a10ed6eb92 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
jbradshaw 0:e4a10ed6eb92 24 * Products, Inc. Branding Policy.
jbradshaw 0:e4a10ed6eb92 25 *
jbradshaw 0:e4a10ed6eb92 26 * The mere transfer of this software does not imply any licenses
jbradshaw 0:e4a10ed6eb92 27 * of trade secrets, proprietary technology, copyrights, patents,
jbradshaw 0:e4a10ed6eb92 28 * trademarks, maskwork rights, or any other form of intellectual
jbradshaw 0:e4a10ed6eb92 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
jbradshaw 0:e4a10ed6eb92 30 * ownership rights.
jbradshaw 0:e4a10ed6eb92 31 *******************************************************************************
jbradshaw 0:e4a10ed6eb92 32 */
jbradshaw 0:e4a10ed6eb92 33
jbradshaw 0:e4a10ed6eb92 34 #include "mbed.h"
jbradshaw 0:e4a10ed6eb92 35 #include "MAX30001.h"
jbradshaw 1:9490836294ea 36 #include "pwrseq_regs.h"
jbradshaw 0:e4a10ed6eb92 37
jbradshaw 0:e4a10ed6eb92 38 MAX30001 *MAX30001::instance = NULL;
jbradshaw 0:e4a10ed6eb92 39
jbradshaw 0:e4a10ed6eb92 40 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 41 MAX30001::MAX30001(PinName mosi, PinName miso, PinName sclk, PinName cs) {
jbradshaw 0:e4a10ed6eb92 42 spi = new SPI(mosi, miso, sclk, cs);
jbradshaw 0:e4a10ed6eb92 43 spi->frequency(3000000);
jbradshaw 0:e4a10ed6eb92 44 spi_owner = true;
jbradshaw 0:e4a10ed6eb92 45 functionpointer.attach(&spiHandler);
jbradshaw 0:e4a10ed6eb92 46 onDataAvailableCallback = NULL;
jbradshaw 1:9490836294ea 47 xferFlag = 0;
jbradshaw 0:e4a10ed6eb92 48 instance = this;
jbradshaw 0:e4a10ed6eb92 49 }
jbradshaw 0:e4a10ed6eb92 50
jbradshaw 0:e4a10ed6eb92 51 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 52 MAX30001::MAX30001(SPI *_spi) {
jbradshaw 0:e4a10ed6eb92 53 spi = _spi;
jbradshaw 0:e4a10ed6eb92 54 spi->frequency(3000000);
jbradshaw 0:e4a10ed6eb92 55 spi_owner = false;
jbradshaw 0:e4a10ed6eb92 56 functionpointer.attach(&spiHandler);
jbradshaw 0:e4a10ed6eb92 57 onDataAvailableCallback = NULL;
jbradshaw 1:9490836294ea 58 xferFlag = 0;
jbradshaw 0:e4a10ed6eb92 59 instance = this;
jbradshaw 0:e4a10ed6eb92 60 }
jbradshaw 0:e4a10ed6eb92 61
jbradshaw 0:e4a10ed6eb92 62 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 63 MAX30001::~MAX30001(void) {
jbradshaw 0:e4a10ed6eb92 64 if (spi_owner) {
jbradshaw 0:e4a10ed6eb92 65 delete spi;
jbradshaw 0:e4a10ed6eb92 66 }
jbradshaw 0:e4a10ed6eb92 67 }
jbradshaw 0:e4a10ed6eb92 68
jbradshaw 0:e4a10ed6eb92 69 //******************************************************************************
jbradshaw 1:9490836294ea 70 void MAX30001::FCLK_MaximOnly(void){
jbradshaw 1:9490836294ea 71
jbradshaw 1:9490836294ea 72 // Use RTC crystal clock for MAX30001 FCLK
jbradshaw 1:9490836294ea 73 /*
jbradshaw 1:9490836294ea 74 mxc_pwrseq_reg0_t pwr_reg0;
jbradshaw 1:9490836294ea 75 mxc_pwrseq_reg4_t pwr_reg4;
jbradshaw 1:9490836294ea 76
jbradshaw 1:9490836294ea 77 // Set the port pin connected to the MAX30001 FCLK pin as an output
jbradshaw 1:9490836294ea 78 GPIO_SetOutMode(MAX30001_INT_PORT_FCLK, MAX30001_INT_PIN_FCLK, MXC_E_GPIO_OUT_MODE_NORMAL);
jbradshaw 1:9490836294ea 79
jbradshaw 1:9490836294ea 80 // Enable Real Time Clock in Run and Sleep modes
jbradshaw 1:9490836294ea 81 pwr_reg0 = MXC_PWRSEQ->reg0_f;
jbradshaw 1:9490836294ea 82 pwr_reg0.pwr_rtcen_run = 1;
jbradshaw 1:9490836294ea 83 pwr_reg0.pwr_rtcen_slp = 1;
jbradshaw 1:9490836294ea 84 MXC_PWRSEQ->reg0_f = pwr_reg0;
jbradshaw 1:9490836294ea 85
jbradshaw 1:9490836294ea 86 // Enable the RTC clock output path on P1.7
jbradshaw 1:9490836294ea 87 pwr_reg4 = MXC_PWRSEQ->reg4_f;
jbradshaw 1:9490836294ea 88 pwr_reg4.pwr_pseq_32k_en = 1;
jbradshaw 1:9490836294ea 89 MXC_PWRSEQ->reg4_f = pwr_reg4;
jbradshaw 1:9490836294ea 90 */
jbradshaw 1:9490836294ea 91
jbradshaw 1:9490836294ea 92 #define PORT_FCLK 1
jbradshaw 1:9490836294ea 93 #define PIN_FCLK 7
jbradshaw 1:9490836294ea 94
jbradshaw 1:9490836294ea 95 // Set the Port pin connected to the MAX30001 FCLK pin as an output
jbradshaw 1:9490836294ea 96 uint32_t temp = MXC_GPIO->out_mode[PORT_FCLK]; // Port 1
jbradshaw 1:9490836294ea 97
jbradshaw 1:9490836294ea 98 // temp = (temp & ~(0xF << (pin * 4))) | (val << (pin * 4));
jbradshaw 1:9490836294ea 99 /* pin 7 */ /* NORMAL MODE */
jbradshaw 1:9490836294ea 100 temp = (temp & ~(0xF << (PIN_FCLK * 4))) | (MXC_V_GPIO_OUT_MODE_NORMAL << (PIN_FCLK * 4));
jbradshaw 1:9490836294ea 101
jbradshaw 1:9490836294ea 102
jbradshaw 1:9490836294ea 103 // temp = (temp & ~(0xF << (7 * 4))) | (5 << (7 * 4));
jbradshaw 1:9490836294ea 104
jbradshaw 1:9490836294ea 105 MXC_GPIO->out_mode[PORT_FCLK] = temp;
jbradshaw 1:9490836294ea 106
jbradshaw 1:9490836294ea 107
jbradshaw 1:9490836294ea 108 // Enable Real Time Clock in Run and Sleep Modes
jbradshaw 1:9490836294ea 109 MXC_PWRSEQ->reg0 = MXC_PWRSEQ->reg0 | MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP;
jbradshaw 1:9490836294ea 110
jbradshaw 1:9490836294ea 111 // Enable the RTC clock output path on P1.7
jbradshaw 1:9490836294ea 112 MXC_PWRSEQ->reg4 = MXC_PWRSEQ->reg4 | MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN;
jbradshaw 1:9490836294ea 113
jbradshaw 1:9490836294ea 114 }
jbradshaw 1:9490836294ea 115
jbradshaw 1:9490836294ea 116
jbradshaw 1:9490836294ea 117 //******************************************************************************
jbradshaw 1:9490836294ea 118 int MAX30001::Rbias_FMSTR_Init(uint8_t En_rbias, uint8_t Rbiasv,
jbradshaw 1:9490836294ea 119 uint8_t Rbiasp, uint8_t Rbiasn,
jbradshaw 1:9490836294ea 120 uint8_t Fmstr) {
jbradshaw 1:9490836294ea 121
jbradshaw 1:9490836294ea 122 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 123
jbradshaw 1:9490836294ea 124 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 125 return -1;
jbradshaw 0:e4a10ed6eb92 126 }
jbradshaw 0:e4a10ed6eb92 127
jbradshaw 1:9490836294ea 128 cnfg_gen.bit.en_rbias = En_rbias;
jbradshaw 1:9490836294ea 129 cnfg_gen.bit.rbiasv = Rbiasv;
jbradshaw 1:9490836294ea 130 cnfg_gen.bit.rbiasp = Rbiasp;
jbradshaw 1:9490836294ea 131 cnfg_gen.bit.rbiasn = Rbiasn;
jbradshaw 1:9490836294ea 132 cnfg_gen.bit.fmstr = Fmstr;
jbradshaw 0:e4a10ed6eb92 133
jbradshaw 1:9490836294ea 134 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 135 return -1;
jbradshaw 0:e4a10ed6eb92 136 }
jbradshaw 0:e4a10ed6eb92 137 return 0;
jbradshaw 0:e4a10ed6eb92 138 }
jbradshaw 0:e4a10ed6eb92 139
jbradshaw 0:e4a10ed6eb92 140 //******************************************************************************
jbradshaw 1:9490836294ea 141 int MAX30001::CAL_InitStart(uint8_t En_Vcal, uint8_t Vmode,
jbradshaw 1:9490836294ea 142 uint8_t Vmag, uint8_t Fcal, uint16_t Thigh,
jbradshaw 1:9490836294ea 143 uint8_t Fifty) {
jbradshaw 1:9490836294ea 144
jbradshaw 1:9490836294ea 145 max30001_cnfg_cal_t cnfg_cal;
jbradshaw 1:9490836294ea 146
jbradshaw 1:9490836294ea 147 ///< CNFG_CAL
jbradshaw 1:9490836294ea 148 if (reg_read(CNFG_CAL, &cnfg_cal.all) == -1) {
jbradshaw 0:e4a10ed6eb92 149 return -1;
jbradshaw 0:e4a10ed6eb92 150 }
jbradshaw 0:e4a10ed6eb92 151
jbradshaw 1:9490836294ea 152 cnfg_cal.bit.vmode = Vmode;
jbradshaw 1:9490836294ea 153 cnfg_cal.bit.vmag = Vmag;
jbradshaw 1:9490836294ea 154 cnfg_cal.bit.fcal = Fcal;
jbradshaw 1:9490836294ea 155 cnfg_cal.bit.thigh = Thigh;
jbradshaw 1:9490836294ea 156 cnfg_cal.bit.fifty = Fifty;
jbradshaw 0:e4a10ed6eb92 157
jbradshaw 1:9490836294ea 158 if (reg_write(CNFG_CAL, cnfg_cal.all) == -1) {
jbradshaw 0:e4a10ed6eb92 159 return -1;
jbradshaw 0:e4a10ed6eb92 160 }
jbradshaw 0:e4a10ed6eb92 161
jbradshaw 1:9490836294ea 162 /// @brief RTOS uses a 32768HZ clock. 32768ticks represents 1secs. 1sec/10 =
jbradshaw 1:9490836294ea 163 /// 100msecs.
jbradshaw 0:e4a10ed6eb92 164 wait(1.0 / 10.0);
jbradshaw 0:e4a10ed6eb92 165
jbradshaw 1:9490836294ea 166 if (reg_read(CNFG_CAL, &cnfg_cal.all) == -1) {
jbradshaw 0:e4a10ed6eb92 167 return -1;
jbradshaw 0:e4a10ed6eb92 168 }
jbradshaw 0:e4a10ed6eb92 169
jbradshaw 1:9490836294ea 170 cnfg_cal.bit.en_vcal = En_Vcal;
jbradshaw 0:e4a10ed6eb92 171
jbradshaw 1:9490836294ea 172 if (reg_write(CNFG_CAL, cnfg_cal.all) == -1) {
jbradshaw 0:e4a10ed6eb92 173 return -1;
jbradshaw 0:e4a10ed6eb92 174 }
jbradshaw 0:e4a10ed6eb92 175
jbradshaw 1:9490836294ea 176 /// @brief RTOS uses a 32768HZ clock. 32768ticks represents 1secs. 1sec/10 =
jbradshaw 1:9490836294ea 177 /// 100msecs.
jbradshaw 0:e4a10ed6eb92 178 wait(1.0 / 10.0);
jbradshaw 0:e4a10ed6eb92 179
jbradshaw 0:e4a10ed6eb92 180 return 0;
jbradshaw 0:e4a10ed6eb92 181 }
jbradshaw 0:e4a10ed6eb92 182
jbradshaw 0:e4a10ed6eb92 183 //******************************************************************************
jbradshaw 1:9490836294ea 184 int MAX30001::CAL_Stop(void) {
jbradshaw 0:e4a10ed6eb92 185
jbradshaw 1:9490836294ea 186 max30001_cnfg_cal_t cnfg_cal;
jbradshaw 1:9490836294ea 187
jbradshaw 1:9490836294ea 188 if (reg_read(CNFG_CAL, &cnfg_cal.all) == -1) {
jbradshaw 0:e4a10ed6eb92 189 return -1;
jbradshaw 0:e4a10ed6eb92 190 }
jbradshaw 0:e4a10ed6eb92 191
jbradshaw 1:9490836294ea 192 cnfg_cal.bit.en_vcal = 0; // Disable VCAL, all other settings are left unaffected
jbradshaw 0:e4a10ed6eb92 193
jbradshaw 1:9490836294ea 194 if (reg_write(CNFG_CAL, cnfg_cal.all) == -1) {
jbradshaw 0:e4a10ed6eb92 195 return -1;
jbradshaw 0:e4a10ed6eb92 196 }
jbradshaw 0:e4a10ed6eb92 197
jbradshaw 0:e4a10ed6eb92 198 return 0;
jbradshaw 0:e4a10ed6eb92 199 }
jbradshaw 0:e4a10ed6eb92 200 //******************************************************************************
jbradshaw 1:9490836294ea 201 int MAX30001::INT_assignment(max30001_intrpt_Location_t en_enint_loc, max30001_intrpt_Location_t en_eovf_loc, max30001_intrpt_Location_t en_fstint_loc,
jbradshaw 1:9490836294ea 202 max30001_intrpt_Location_t en_dcloffint_loc, max30001_intrpt_Location_t en_bint_loc, max30001_intrpt_Location_t en_bovf_loc,
jbradshaw 1:9490836294ea 203 max30001_intrpt_Location_t en_bover_loc, max30001_intrpt_Location_t en_bundr_loc, max30001_intrpt_Location_t en_bcgmon_loc,
jbradshaw 1:9490836294ea 204 max30001_intrpt_Location_t en_pint_loc, max30001_intrpt_Location_t en_povf_loc, max30001_intrpt_Location_t en_pedge_loc,
jbradshaw 1:9490836294ea 205 max30001_intrpt_Location_t en_lonint_loc, max30001_intrpt_Location_t en_rrint_loc, max30001_intrpt_Location_t en_samp_loc,
jbradshaw 1:9490836294ea 206 max30001_intrpt_type_t intb_Type, max30001_intrpt_type_t int2b_Type)
jbradshaw 0:e4a10ed6eb92 207
jbradshaw 0:e4a10ed6eb92 208
jbradshaw 0:e4a10ed6eb92 209 {
jbradshaw 1:9490836294ea 210
jbradshaw 1:9490836294ea 211 max30001_en_int_t en_int;
jbradshaw 1:9490836294ea 212 max30001_en_int2_t en_int2;
jbradshaw 1:9490836294ea 213
jbradshaw 1:9490836294ea 214 ///< INT1
jbradshaw 0:e4a10ed6eb92 215
jbradshaw 1:9490836294ea 216 if (reg_read(EN_INT, &en_int.all) == -1) {
jbradshaw 0:e4a10ed6eb92 217 return -1;
jbradshaw 0:e4a10ed6eb92 218 }
jbradshaw 0:e4a10ed6eb92 219
jbradshaw 0:e4a10ed6eb92 220 // max30001_en_int2.bit.en_pint = 0b1; // Keep this off...
jbradshaw 0:e4a10ed6eb92 221
jbradshaw 1:9490836294ea 222 en_int.bit.en_eint = 0b1 & en_enint_loc;
jbradshaw 1:9490836294ea 223 en_int.bit.en_eovf = 0b1 & en_eovf_loc;
jbradshaw 1:9490836294ea 224 en_int.bit.en_fstint = 0b1 & en_fstint_loc;
jbradshaw 0:e4a10ed6eb92 225
jbradshaw 1:9490836294ea 226 en_int.bit.en_dcloffint = 0b1 & en_dcloffint_loc;
jbradshaw 1:9490836294ea 227 en_int.bit.en_bint = 0b1 & en_bint_loc;
jbradshaw 1:9490836294ea 228 en_int.bit.en_bovf = 0b1 & en_bovf_loc;
jbradshaw 0:e4a10ed6eb92 229
jbradshaw 1:9490836294ea 230 en_int.bit.en_bover = 0b1 & en_bover_loc;
jbradshaw 1:9490836294ea 231 en_int.bit.en_bundr = 0b1 & en_bundr_loc;
jbradshaw 1:9490836294ea 232 en_int.bit.en_bcgmon = 0b1 & en_bcgmon_loc;
jbradshaw 0:e4a10ed6eb92 233
jbradshaw 1:9490836294ea 234 en_int.bit.en_pint = 0b1 & en_pint_loc;
jbradshaw 1:9490836294ea 235 en_int.bit.en_povf = 0b1 & en_povf_loc;
jbradshaw 1:9490836294ea 236 en_int.bit.en_pedge = 0b1 & en_pedge_loc;
jbradshaw 0:e4a10ed6eb92 237
jbradshaw 1:9490836294ea 238 en_int.bit.en_lonint = 0b1 & en_lonint_loc;
jbradshaw 1:9490836294ea 239 en_int.bit.en_rrint = 0b1 & en_rrint_loc;
jbradshaw 1:9490836294ea 240 en_int.bit.en_samp = 0b1 & en_samp_loc;
jbradshaw 0:e4a10ed6eb92 241
jbradshaw 1:9490836294ea 242 en_int.bit.intb_type = int2b_Type;
jbradshaw 0:e4a10ed6eb92 243
jbradshaw 1:9490836294ea 244 if (reg_write(EN_INT, en_int.all) == -1) {
jbradshaw 0:e4a10ed6eb92 245 return -1;
jbradshaw 0:e4a10ed6eb92 246 }
jbradshaw 0:e4a10ed6eb92 247
jbradshaw 1:9490836294ea 248 ///< INT2
jbradshaw 0:e4a10ed6eb92 249
jbradshaw 1:9490836294ea 250 if (reg_read(EN_INT2, &en_int2.all) == -1) {
jbradshaw 0:e4a10ed6eb92 251 return -1;
jbradshaw 0:e4a10ed6eb92 252 }
jbradshaw 0:e4a10ed6eb92 253
jbradshaw 1:9490836294ea 254 en_int2.bit.en_eint = 0b1 & (en_enint_loc >> 1);
jbradshaw 1:9490836294ea 255 en_int2.bit.en_eovf = 0b1 & (en_eovf_loc >> 1);
jbradshaw 1:9490836294ea 256 en_int2.bit.en_fstint = 0b1 & (en_fstint_loc >> 1);
jbradshaw 0:e4a10ed6eb92 257
jbradshaw 1:9490836294ea 258 en_int2.bit.en_dcloffint = 0b1 & (en_dcloffint_loc >> 1);
jbradshaw 1:9490836294ea 259 en_int2.bit.en_bint = 0b1 & (en_bint_loc >> 1);
jbradshaw 1:9490836294ea 260 en_int2.bit.en_bovf = 0b1 & (en_bovf_loc >> 1);
jbradshaw 0:e4a10ed6eb92 261
jbradshaw 1:9490836294ea 262 en_int2.bit.en_bover = 0b1 & (en_bover_loc >> 1);
jbradshaw 1:9490836294ea 263 en_int2.bit.en_bundr = 0b1 & (en_bundr_loc >> 1);
jbradshaw 1:9490836294ea 264 en_int2.bit.en_bcgmon = 0b1 & (en_bcgmon_loc >> 1);
jbradshaw 0:e4a10ed6eb92 265
jbradshaw 1:9490836294ea 266 en_int2.bit.en_pint = 0b1 & (en_pint_loc >> 1);
jbradshaw 1:9490836294ea 267 en_int2.bit.en_povf = 0b1 & (en_povf_loc >> 1);
jbradshaw 1:9490836294ea 268 en_int2.bit.en_pedge = 0b1 & (en_pedge_loc >> 1);
jbradshaw 0:e4a10ed6eb92 269
jbradshaw 1:9490836294ea 270 en_int2.bit.en_lonint = 0b1 & (en_lonint_loc >> 1);
jbradshaw 1:9490836294ea 271 en_int2.bit.en_rrint = 0b1 & (en_rrint_loc >> 1);
jbradshaw 1:9490836294ea 272 en_int2.bit.en_samp = 0b1 & (en_samp_loc >> 1);
jbradshaw 0:e4a10ed6eb92 273
jbradshaw 1:9490836294ea 274 en_int2.bit.intb_type = intb_Type;
jbradshaw 0:e4a10ed6eb92 275
jbradshaw 1:9490836294ea 276 if (reg_write(EN_INT2, en_int2.all) == -1) {
jbradshaw 0:e4a10ed6eb92 277 return -1;
jbradshaw 0:e4a10ed6eb92 278 }
jbradshaw 0:e4a10ed6eb92 279
jbradshaw 0:e4a10ed6eb92 280 return 0;
jbradshaw 0:e4a10ed6eb92 281 }
jbradshaw 0:e4a10ed6eb92 282
jbradshaw 0:e4a10ed6eb92 283 //******************************************************************************
jbradshaw 1:9490836294ea 284 int MAX30001::ECG_InitStart(uint8_t En_ecg, uint8_t Openp,
jbradshaw 1:9490836294ea 285 uint8_t Openn, uint8_t Pol,
jbradshaw 1:9490836294ea 286 uint8_t Calp_sel, uint8_t Caln_sel,
jbradshaw 1:9490836294ea 287 uint8_t E_fit, uint8_t Rate, uint8_t Gain,
jbradshaw 1:9490836294ea 288 uint8_t Dhpf, uint8_t Dlpf) {
jbradshaw 0:e4a10ed6eb92 289
jbradshaw 1:9490836294ea 290 max30001_cnfg_emux_t cnfg_emux;
jbradshaw 1:9490836294ea 291 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 292 max30001_status_t status;
jbradshaw 1:9490836294ea 293 max30001_mngr_int_t mngr_int;
jbradshaw 1:9490836294ea 294 max30001_cnfg_ecg_t cnfg_ecg;
jbradshaw 1:9490836294ea 295
jbradshaw 1:9490836294ea 296 ///< CNFG_EMUX
jbradshaw 0:e4a10ed6eb92 297
jbradshaw 1:9490836294ea 298 if (reg_read(CNFG_EMUX, &cnfg_emux.all) == -1) {
jbradshaw 0:e4a10ed6eb92 299 return -1;
jbradshaw 0:e4a10ed6eb92 300 }
jbradshaw 0:e4a10ed6eb92 301
jbradshaw 1:9490836294ea 302 cnfg_emux.bit.openp = Openp;
jbradshaw 1:9490836294ea 303 cnfg_emux.bit.openn = Openn;
jbradshaw 1:9490836294ea 304 cnfg_emux.bit.pol = Pol;
jbradshaw 1:9490836294ea 305 cnfg_emux.bit.calp_sel = Calp_sel;
jbradshaw 1:9490836294ea 306 cnfg_emux.bit.caln_sel = Caln_sel;
jbradshaw 0:e4a10ed6eb92 307
jbradshaw 1:9490836294ea 308 if (reg_write(CNFG_EMUX, cnfg_emux.all) == -1) {
jbradshaw 0:e4a10ed6eb92 309 return -1;
jbradshaw 0:e4a10ed6eb92 310 }
jbradshaw 0:e4a10ed6eb92 311
jbradshaw 0:e4a10ed6eb92 312 /**** ENABLE CHANNELS ****/
jbradshaw 1:9490836294ea 313 ///< CNFG_GEN
jbradshaw 1:9490836294ea 314
jbradshaw 1:9490836294ea 315 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 316 return -1;
jbradshaw 1:9490836294ea 317 }
jbradshaw 1:9490836294ea 318
jbradshaw 1:9490836294ea 319 cnfg_gen.bit.en_ecg = En_ecg; // 0b1
jbradshaw 1:9490836294ea 320
jbradshaw 1:9490836294ea 321 ///< fmstr is default
jbradshaw 1:9490836294ea 322
jbradshaw 1:9490836294ea 323 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 324 return -1;
jbradshaw 1:9490836294ea 325 }
jbradshaw 1:9490836294ea 326
jbradshaw 1:9490836294ea 327 ///< Wait for PLL Lock & References to settle down
jbradshaw 1:9490836294ea 328
jbradshaw 1:9490836294ea 329 max30001_timeout = 0;
jbradshaw 1:9490836294ea 330
jbradshaw 1:9490836294ea 331 do {
jbradshaw 1:9490836294ea 332 if (reg_read(STATUS, &status.all) == -1) {// Wait and spin for PLL to lock...
jbradshaw 1:9490836294ea 333
jbradshaw 1:9490836294ea 334 return -1;
jbradshaw 1:9490836294ea 335 }
jbradshaw 1:9490836294ea 336 } while (status.bit.pllint == 1 && max30001_timeout++ <= 1000);
jbradshaw 1:9490836294ea 337
jbradshaw 1:9490836294ea 338 ///< MNGR_INT
jbradshaw 1:9490836294ea 339
jbradshaw 1:9490836294ea 340 if (reg_read(MNGR_INT, &mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 341 return -1;
jbradshaw 1:9490836294ea 342 }
jbradshaw 1:9490836294ea 343
jbradshaw 1:9490836294ea 344 mngr_int.bit.e_fit = E_fit; // 31
jbradshaw 1:9490836294ea 345
jbradshaw 1:9490836294ea 346 if (reg_write(MNGR_INT, mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 347 return -1;
jbradshaw 1:9490836294ea 348 }
jbradshaw 1:9490836294ea 349
jbradshaw 1:9490836294ea 350 ///< CNFG_ECG
jbradshaw 1:9490836294ea 351
jbradshaw 1:9490836294ea 352 if (reg_read(CNFG_ECG, &cnfg_ecg.all) == -1) {
jbradshaw 1:9490836294ea 353 return -1;
jbradshaw 1:9490836294ea 354 }
jbradshaw 1:9490836294ea 355
jbradshaw 1:9490836294ea 356 cnfg_ecg.bit.rate = Rate;
jbradshaw 1:9490836294ea 357 cnfg_ecg.bit.gain = Gain;
jbradshaw 1:9490836294ea 358 cnfg_ecg.bit.dhpf = Dhpf;
jbradshaw 1:9490836294ea 359 cnfg_ecg.bit.dlpf = Dlpf;
jbradshaw 0:e4a10ed6eb92 360
jbradshaw 1:9490836294ea 361 if (reg_write(CNFG_ECG, cnfg_ecg.all) == -1) {
jbradshaw 1:9490836294ea 362 return -1;
jbradshaw 1:9490836294ea 363 }
jbradshaw 1:9490836294ea 364
jbradshaw 1:9490836294ea 365 return 0;
jbradshaw 1:9490836294ea 366 }
jbradshaw 1:9490836294ea 367
jbradshaw 1:9490836294ea 368 //******************************************************************************
jbradshaw 1:9490836294ea 369 int MAX30001::ECGFast_Init(uint8_t Clr_Fast, uint8_t Fast, uint8_t Fast_Th) {
jbradshaw 1:9490836294ea 370
jbradshaw 1:9490836294ea 371 max30001_mngr_int_t mngr_int;
jbradshaw 1:9490836294ea 372 max30001_mngr_dyn_t mngr_dyn;
jbradshaw 1:9490836294ea 373
jbradshaw 1:9490836294ea 374 if (reg_read(MNGR_INT, &mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 375 return -1;
jbradshaw 1:9490836294ea 376 }
jbradshaw 1:9490836294ea 377
jbradshaw 1:9490836294ea 378 mngr_int.bit.clr_fast = Clr_Fast;
jbradshaw 1:9490836294ea 379
jbradshaw 1:9490836294ea 380 if (reg_write(MNGR_INT, mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 381 return -1;
jbradshaw 1:9490836294ea 382 }
jbradshaw 1:9490836294ea 383
jbradshaw 1:9490836294ea 384 if (reg_read(MNGR_DYN, &mngr_dyn.all) == -1) {
jbradshaw 1:9490836294ea 385 return -1;
jbradshaw 1:9490836294ea 386 }
jbradshaw 1:9490836294ea 387
jbradshaw 1:9490836294ea 388 mngr_dyn.bit.fast = Fast;
jbradshaw 1:9490836294ea 389 mngr_dyn.bit.fast_th = Fast_Th;
jbradshaw 1:9490836294ea 390
jbradshaw 1:9490836294ea 391 if (reg_write(MNGR_INT, mngr_dyn.all) == -1) {
jbradshaw 1:9490836294ea 392 return -1;
jbradshaw 1:9490836294ea 393 }
jbradshaw 1:9490836294ea 394
jbradshaw 1:9490836294ea 395 return 0;
jbradshaw 1:9490836294ea 396 }
jbradshaw 1:9490836294ea 397
jbradshaw 1:9490836294ea 398 //******************************************************************************
jbradshaw 1:9490836294ea 399 int MAX30001::Stop_ECG(void) {
jbradshaw 1:9490836294ea 400
jbradshaw 1:9490836294ea 401 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 402
jbradshaw 1:9490836294ea 403 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 404 return -1;
jbradshaw 1:9490836294ea 405 }
jbradshaw 1:9490836294ea 406
jbradshaw 1:9490836294ea 407 cnfg_gen.bit.en_ecg = 0; ///< Stop ECG
jbradshaw 1:9490836294ea 408
jbradshaw 1:9490836294ea 409 ///< fmstr is default
jbradshaw 1:9490836294ea 410
jbradshaw 1:9490836294ea 411 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 412 return -1;
jbradshaw 0:e4a10ed6eb92 413 }
jbradshaw 0:e4a10ed6eb92 414
jbradshaw 1:9490836294ea 415 return 0;
jbradshaw 1:9490836294ea 416 }
jbradshaw 1:9490836294ea 417
jbradshaw 1:9490836294ea 418 //******************************************************************************
jbradshaw 1:9490836294ea 419 int MAX30001::PACE_InitStart(uint8_t En_pace, uint8_t Clr_pedge,
jbradshaw 1:9490836294ea 420 uint8_t Pol, uint8_t Gn_diff_off,
jbradshaw 1:9490836294ea 421 uint8_t Gain, uint8_t Aout_lbw,
jbradshaw 1:9490836294ea 422 uint8_t Aout, uint8_t Dacp,
jbradshaw 1:9490836294ea 423 uint8_t Dacn) {
jbradshaw 1:9490836294ea 424
jbradshaw 1:9490836294ea 425 /**** SET MASTER FREQUENCY, ENABLE CHANNELS ****/
jbradshaw 1:9490836294ea 426
jbradshaw 1:9490836294ea 427 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 428 max30001_status_t status;
jbradshaw 1:9490836294ea 429 max30001_mngr_int_t mngr_int;
jbradshaw 1:9490836294ea 430 max30001_cnfg_pace_t cnfg_pace;
jbradshaw 1:9490836294ea 431
jbradshaw 1:9490836294ea 432 ///< CNFG_GEN
jbradshaw 1:9490836294ea 433
jbradshaw 1:9490836294ea 434 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 435 return -1;
jbradshaw 1:9490836294ea 436 }
jbradshaw 1:9490836294ea 437
jbradshaw 1:9490836294ea 438 cnfg_gen.bit.en_pace = En_pace; // 0b1;
jbradshaw 1:9490836294ea 439
jbradshaw 1:9490836294ea 440 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 441 return -1;
jbradshaw 1:9490836294ea 442 }
jbradshaw 1:9490836294ea 443
jbradshaw 1:9490836294ea 444 /**** Wait for PLL Lock & References to settle down ****/
jbradshaw 1:9490836294ea 445 max30001_timeout = 0;
jbradshaw 1:9490836294ea 446
jbradshaw 1:9490836294ea 447 do {
jbradshaw 1:9490836294ea 448 if (reg_read(STATUS, &status.all) ==
jbradshaw 1:9490836294ea 449 -1) // Wait and spin for PLL to lock...
jbradshaw 1:9490836294ea 450 {
jbradshaw 1:9490836294ea 451 return -1;
jbradshaw 1:9490836294ea 452 }
jbradshaw 1:9490836294ea 453
jbradshaw 1:9490836294ea 454 } while (status.bit.pllint == 1 && max30001_timeout++ <= 1000);
jbradshaw 1:9490836294ea 455
jbradshaw 1:9490836294ea 456 ///< MNGR_INT
jbradshaw 1:9490836294ea 457
jbradshaw 1:9490836294ea 458 if (reg_read(MNGR_INT, &mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 459 return -1;
jbradshaw 1:9490836294ea 460 }
jbradshaw 1:9490836294ea 461
jbradshaw 1:9490836294ea 462 mngr_int.bit.clr_pedge = Clr_pedge; // 0b0;
jbradshaw 1:9490836294ea 463
jbradshaw 1:9490836294ea 464 if (reg_write(MNGR_INT, mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 465 return -1;
jbradshaw 1:9490836294ea 466 }
jbradshaw 1:9490836294ea 467
jbradshaw 1:9490836294ea 468 ///< CNFG_PACE
jbradshaw 1:9490836294ea 469
jbradshaw 1:9490836294ea 470 reg_read(CNFG_PACE, &cnfg_pace.all);
jbradshaw 1:9490836294ea 471
jbradshaw 1:9490836294ea 472 cnfg_pace.bit.pol = Pol;
jbradshaw 1:9490836294ea 473 cnfg_pace.bit.gn_diff_off = Gn_diff_off;
jbradshaw 1:9490836294ea 474 cnfg_pace.bit.gain = Gain;
jbradshaw 1:9490836294ea 475 cnfg_pace.bit.aout_lbw = Aout_lbw;
jbradshaw 1:9490836294ea 476 cnfg_pace.bit.aout = Aout;
jbradshaw 1:9490836294ea 477 cnfg_pace.bit.dacp = Dacp;
jbradshaw 1:9490836294ea 478 cnfg_pace.bit.dacn = Dacn;
jbradshaw 0:e4a10ed6eb92 479
jbradshaw 1:9490836294ea 480 reg_write(CNFG_PACE, cnfg_pace.all);
jbradshaw 1:9490836294ea 481
jbradshaw 1:9490836294ea 482 return 0;
jbradshaw 1:9490836294ea 483 }
jbradshaw 1:9490836294ea 484
jbradshaw 1:9490836294ea 485 //******************************************************************************
jbradshaw 1:9490836294ea 486 int MAX30001::Stop_PACE(void) {
jbradshaw 1:9490836294ea 487
jbradshaw 1:9490836294ea 488 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 489
jbradshaw 1:9490836294ea 490 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 491 return -1;
jbradshaw 1:9490836294ea 492 }
jbradshaw 1:9490836294ea 493
jbradshaw 1:9490836294ea 494 cnfg_gen.bit.en_pace = 0; ///< Stop PACE
jbradshaw 1:9490836294ea 495
jbradshaw 1:9490836294ea 496 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 497 return -1;
jbradshaw 1:9490836294ea 498 }
jbradshaw 1:9490836294ea 499
jbradshaw 1:9490836294ea 500 return 0;
jbradshaw 1:9490836294ea 501 }
jbradshaw 1:9490836294ea 502
jbradshaw 1:9490836294ea 503 //******************************************************************************
jbradshaw 1:9490836294ea 504 int MAX30001::BIOZ_InitStart(
jbradshaw 1:9490836294ea 505 uint8_t En_bioz, uint8_t Openp, uint8_t Openn, uint8_t Calp_sel,
jbradshaw 1:9490836294ea 506 uint8_t Caln_sel, uint8_t CG_mode, uint8_t B_fit, uint8_t Rate,
jbradshaw 1:9490836294ea 507 uint8_t Ahpf, uint8_t Ext_rbias, uint8_t Gain, uint8_t Dhpf, uint8_t Dlpf,
jbradshaw 1:9490836294ea 508 uint8_t Fcgen, uint8_t Cgmon, uint8_t Cgmag, uint8_t Phoff) {
jbradshaw 0:e4a10ed6eb92 509
jbradshaw 1:9490836294ea 510 max30001_cnfg_bmux_t cnfg_bmux;
jbradshaw 1:9490836294ea 511 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 512 max30001_status_t status;
jbradshaw 1:9490836294ea 513 max30001_mngr_int_t mngr_int;
jbradshaw 1:9490836294ea 514 max30001_cnfg_bioz_t cnfg_bioz;
jbradshaw 1:9490836294ea 515
jbradshaw 1:9490836294ea 516
jbradshaw 1:9490836294ea 517 // CNFG_BMUX
jbradshaw 1:9490836294ea 518
jbradshaw 1:9490836294ea 519 if (reg_read(CNFG_BMUX, &cnfg_bmux.all) == -1) {
jbradshaw 1:9490836294ea 520 return -1;
jbradshaw 1:9490836294ea 521 }
jbradshaw 1:9490836294ea 522
jbradshaw 1:9490836294ea 523 cnfg_bmux.bit.openp = Openp;
jbradshaw 1:9490836294ea 524 cnfg_bmux.bit.openn = Openn;
jbradshaw 1:9490836294ea 525 cnfg_bmux.bit.calp_sel = Calp_sel;
jbradshaw 1:9490836294ea 526 cnfg_bmux.bit.caln_sel = Caln_sel;
jbradshaw 1:9490836294ea 527 cnfg_bmux.bit.cg_mode = CG_mode;
jbradshaw 1:9490836294ea 528
jbradshaw 1:9490836294ea 529 if (reg_write(CNFG_BMUX, cnfg_bmux.all) == -1) {
jbradshaw 1:9490836294ea 530 return -1;
jbradshaw 1:9490836294ea 531 }
jbradshaw 1:9490836294ea 532
jbradshaw 1:9490836294ea 533 /**** SET MASTER FREQUENCY, ENABLE CHANNELS ****/
jbradshaw 1:9490836294ea 534
jbradshaw 1:9490836294ea 535 ///< CNFG_GEN
jbradshaw 1:9490836294ea 536
jbradshaw 1:9490836294ea 537 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 538 return -1;
jbradshaw 1:9490836294ea 539 }
jbradshaw 1:9490836294ea 540
jbradshaw 1:9490836294ea 541 cnfg_gen.bit.en_bioz = En_bioz;
jbradshaw 1:9490836294ea 542
jbradshaw 1:9490836294ea 543 ///< fmstr is default
jbradshaw 1:9490836294ea 544
jbradshaw 1:9490836294ea 545 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 546 return -1;
jbradshaw 0:e4a10ed6eb92 547 }
jbradshaw 0:e4a10ed6eb92 548
jbradshaw 0:e4a10ed6eb92 549 /**** Wait for PLL Lock & References to settle down ****/
jbradshaw 0:e4a10ed6eb92 550
jbradshaw 0:e4a10ed6eb92 551 max30001_timeout = 0;
jbradshaw 0:e4a10ed6eb92 552
jbradshaw 0:e4a10ed6eb92 553 do {
jbradshaw 1:9490836294ea 554 if (reg_read(STATUS, &status.all) == -1) { // Wait and spin for PLL to lock...
jbradshaw 0:e4a10ed6eb92 555 return -1;
jbradshaw 0:e4a10ed6eb92 556 }
jbradshaw 0:e4a10ed6eb92 557
jbradshaw 1:9490836294ea 558 } while (status.bit.pllint == 1 && max30001_timeout++ <= 1000);
jbradshaw 0:e4a10ed6eb92 559
jbradshaw 1:9490836294ea 560 /**** Start of CNFG_BIOZ ****/
jbradshaw 0:e4a10ed6eb92 561
jbradshaw 1:9490836294ea 562 ///< MNGR_INT
jbradshaw 0:e4a10ed6eb92 563
jbradshaw 1:9490836294ea 564 if (reg_read(MNGR_INT, &mngr_int.all) == -1) {
jbradshaw 0:e4a10ed6eb92 565 return -1;
jbradshaw 0:e4a10ed6eb92 566 }
jbradshaw 0:e4a10ed6eb92 567
jbradshaw 1:9490836294ea 568 mngr_int.bit.b_fit = B_fit; //;
jbradshaw 0:e4a10ed6eb92 569
jbradshaw 1:9490836294ea 570 if (reg_write(MNGR_INT, mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 571 return -1;
jbradshaw 1:9490836294ea 572 }
jbradshaw 1:9490836294ea 573
jbradshaw 1:9490836294ea 574 ///< CNFG_BIOZ
jbradshaw 1:9490836294ea 575
jbradshaw 1:9490836294ea 576 if (reg_read(CNFG_BIOZ, &cnfg_bioz.all) == -1) {
jbradshaw 0:e4a10ed6eb92 577 return -1;
jbradshaw 0:e4a10ed6eb92 578 }
jbradshaw 0:e4a10ed6eb92 579
jbradshaw 1:9490836294ea 580 cnfg_bioz.bit.rate = Rate;
jbradshaw 1:9490836294ea 581 cnfg_bioz.bit.ahpf = Ahpf;
jbradshaw 1:9490836294ea 582 cnfg_bioz.bit.ext_rbias = Ext_rbias;
jbradshaw 1:9490836294ea 583 cnfg_bioz.bit.gain = Gain;
jbradshaw 1:9490836294ea 584 cnfg_bioz.bit.dhpf = Dhpf;
jbradshaw 1:9490836294ea 585 cnfg_bioz.bit.dlpf = Dlpf;
jbradshaw 1:9490836294ea 586 cnfg_bioz.bit.fcgen = Fcgen;
jbradshaw 1:9490836294ea 587 cnfg_bioz.bit.cgmon = Cgmon;
jbradshaw 1:9490836294ea 588 cnfg_bioz.bit.cgmag = Cgmag;
jbradshaw 1:9490836294ea 589 cnfg_bioz.bit.phoff = Phoff;
jbradshaw 0:e4a10ed6eb92 590
jbradshaw 1:9490836294ea 591 if (reg_write(CNFG_BIOZ, cnfg_bioz.all) == -1) {
jbradshaw 0:e4a10ed6eb92 592 return -1;
jbradshaw 0:e4a10ed6eb92 593 }
jbradshaw 0:e4a10ed6eb92 594
jbradshaw 0:e4a10ed6eb92 595 return 0;
jbradshaw 0:e4a10ed6eb92 596 }
jbradshaw 0:e4a10ed6eb92 597
jbradshaw 0:e4a10ed6eb92 598 //******************************************************************************
jbradshaw 1:9490836294ea 599 int MAX30001::Stop_BIOZ(void) {
jbradshaw 0:e4a10ed6eb92 600
jbradshaw 1:9490836294ea 601 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 602
jbradshaw 1:9490836294ea 603 ///< CNFG_GEN
jbradshaw 0:e4a10ed6eb92 604
jbradshaw 1:9490836294ea 605 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 606 return -1;
jbradshaw 0:e4a10ed6eb92 607 }
jbradshaw 0:e4a10ed6eb92 608
jbradshaw 1:9490836294ea 609 cnfg_gen.bit.en_bioz = 0; // Stop BIOZ
jbradshaw 0:e4a10ed6eb92 610
jbradshaw 1:9490836294ea 611 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 612 return -1;
jbradshaw 0:e4a10ed6eb92 613 }
jbradshaw 0:e4a10ed6eb92 614
jbradshaw 0:e4a10ed6eb92 615 return 0;
jbradshaw 0:e4a10ed6eb92 616 }
jbradshaw 0:e4a10ed6eb92 617
jbradshaw 0:e4a10ed6eb92 618 //******************************************************************************
jbradshaw 1:9490836294ea 619 int MAX30001::BIOZ_InitBist(uint8_t En_bist, uint8_t Rnom,
jbradshaw 1:9490836294ea 620 uint8_t Rmod, uint8_t Fbist) {
jbradshaw 0:e4a10ed6eb92 621
jbradshaw 1:9490836294ea 622 max30001_cnfg_bmux_t cnfg_bmux;
jbradshaw 0:e4a10ed6eb92 623
jbradshaw 1:9490836294ea 624 ///< CNFG_BMUX
jbradshaw 0:e4a10ed6eb92 625
jbradshaw 1:9490836294ea 626 if (reg_read(CNFG_BMUX, &cnfg_bmux.all) == -1) {
jbradshaw 0:e4a10ed6eb92 627 return -1;
jbradshaw 0:e4a10ed6eb92 628 }
jbradshaw 0:e4a10ed6eb92 629
jbradshaw 1:9490836294ea 630 cnfg_bmux.bit.en_bist = En_bist;
jbradshaw 1:9490836294ea 631 cnfg_bmux.bit.rnom = Rnom;
jbradshaw 1:9490836294ea 632 cnfg_bmux.bit.rmod = Rmod;
jbradshaw 1:9490836294ea 633 cnfg_bmux.bit.fbist = Fbist;
jbradshaw 0:e4a10ed6eb92 634
jbradshaw 1:9490836294ea 635 if (reg_write(CNFG_BMUX, cnfg_bmux.all) == -1) {
jbradshaw 0:e4a10ed6eb92 636 return -1;
jbradshaw 0:e4a10ed6eb92 637 }
jbradshaw 0:e4a10ed6eb92 638
jbradshaw 0:e4a10ed6eb92 639 return 0;
jbradshaw 0:e4a10ed6eb92 640 }
jbradshaw 1:9490836294ea 641 //******************************************************************************
jbradshaw 1:9490836294ea 642 int MAX30001::RtoR_InitStart(uint8_t En_rtor, uint8_t Wndw,
jbradshaw 1:9490836294ea 643 uint8_t Gain, uint8_t Pavg, uint8_t Ptsf,
jbradshaw 1:9490836294ea 644 uint8_t Hoff, uint8_t Ravg, uint8_t Rhsf,
jbradshaw 1:9490836294ea 645 uint8_t Clr_rrint) {
jbradshaw 0:e4a10ed6eb92 646
jbradshaw 1:9490836294ea 647 max30001_mngr_int_t mngr_int;
jbradshaw 1:9490836294ea 648 max30001_cnfg_rtor1_t cnfg_rtor1;
jbradshaw 1:9490836294ea 649 max30001_cnfg_rtor2_t cnfg_rtor2;
jbradshaw 0:e4a10ed6eb92 650
jbradshaw 1:9490836294ea 651 ///< MNGR_INT
jbradshaw 1:9490836294ea 652 if (reg_read(MNGR_INT, &mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 653 return -1;
jbradshaw 1:9490836294ea 654 }
jbradshaw 1:9490836294ea 655
jbradshaw 1:9490836294ea 656 mngr_int.bit.clr_rrint = Clr_rrint;
jbradshaw 1:9490836294ea 657 ///< 0b01 & 0b00 are for interrupt mode...
jbradshaw 1:9490836294ea 658 ///< 0b10 is for monitoring mode... it just overwrites the data...
jbradshaw 1:9490836294ea 659
jbradshaw 1:9490836294ea 660 if (reg_write(MNGR_INT, mngr_int.all) == -1) {
jbradshaw 0:e4a10ed6eb92 661 return -1;
jbradshaw 0:e4a10ed6eb92 662 }
jbradshaw 0:e4a10ed6eb92 663
jbradshaw 1:9490836294ea 664 ///< RTOR1
jbradshaw 1:9490836294ea 665 if (reg_read(CNFG_RTOR1, &cnfg_rtor1.all) == -1) {
jbradshaw 1:9490836294ea 666 return -1;
jbradshaw 1:9490836294ea 667 }
jbradshaw 1:9490836294ea 668
jbradshaw 1:9490836294ea 669 cnfg_rtor1.bit.wndw = Wndw;
jbradshaw 1:9490836294ea 670 cnfg_rtor1.bit.gain = Gain;
jbradshaw 1:9490836294ea 671 cnfg_rtor1.bit.en_rtor = En_rtor;
jbradshaw 1:9490836294ea 672 cnfg_rtor1.bit.pavg = Pavg;
jbradshaw 1:9490836294ea 673 cnfg_rtor1.bit.ptsf = Ptsf;
jbradshaw 0:e4a10ed6eb92 674
jbradshaw 1:9490836294ea 675 if (reg_write(CNFG_RTOR1, cnfg_rtor1.all) == -1) {
jbradshaw 1:9490836294ea 676 return -1;
jbradshaw 1:9490836294ea 677 }
jbradshaw 1:9490836294ea 678
jbradshaw 1:9490836294ea 679 ///< RTOR2
jbradshaw 1:9490836294ea 680 if (reg_read(CNFG_RTOR2, &cnfg_rtor2.all) == -1) {
jbradshaw 1:9490836294ea 681 return -1;
jbradshaw 1:9490836294ea 682 }
jbradshaw 1:9490836294ea 683 cnfg_rtor2.bit.hoff = Hoff;
jbradshaw 1:9490836294ea 684 cnfg_rtor2.bit.ravg = Ravg;
jbradshaw 1:9490836294ea 685 cnfg_rtor2.bit.rhsf = Rhsf;
jbradshaw 1:9490836294ea 686
jbradshaw 1:9490836294ea 687 if (reg_write(CNFG_RTOR2, cnfg_rtor2.all) == -1) {
jbradshaw 0:e4a10ed6eb92 688 return -1;
jbradshaw 0:e4a10ed6eb92 689 }
jbradshaw 0:e4a10ed6eb92 690
jbradshaw 0:e4a10ed6eb92 691 return 0;
jbradshaw 0:e4a10ed6eb92 692 }
jbradshaw 0:e4a10ed6eb92 693
jbradshaw 0:e4a10ed6eb92 694 //******************************************************************************
jbradshaw 1:9490836294ea 695 int MAX30001::Stop_RtoR(void) {
jbradshaw 0:e4a10ed6eb92 696
jbradshaw 1:9490836294ea 697 max30001_cnfg_rtor1_t cnfg_rtor1;
jbradshaw 0:e4a10ed6eb92 698
jbradshaw 1:9490836294ea 699 if (reg_read(CNFG_RTOR1, &cnfg_rtor1.all) == -1) {
jbradshaw 0:e4a10ed6eb92 700 return -1;
jbradshaw 0:e4a10ed6eb92 701 }
jbradshaw 0:e4a10ed6eb92 702
jbradshaw 1:9490836294ea 703 cnfg_rtor1.bit.en_rtor = 0; ///< Stop RtoR
jbradshaw 0:e4a10ed6eb92 704
jbradshaw 1:9490836294ea 705 if (reg_write(CNFG_RTOR1, cnfg_rtor1.all) == -1) {
jbradshaw 0:e4a10ed6eb92 706 return -1;
jbradshaw 0:e4a10ed6eb92 707 }
jbradshaw 0:e4a10ed6eb92 708
jbradshaw 0:e4a10ed6eb92 709 return 0;
jbradshaw 0:e4a10ed6eb92 710 }
jbradshaw 0:e4a10ed6eb92 711
jbradshaw 0:e4a10ed6eb92 712 //******************************************************************************
jbradshaw 1:9490836294ea 713 int MAX30001::PLL_lock(void) {
jbradshaw 1:9490836294ea 714 ///< Spin to see PLLint become zero to indicate a lock.
jbradshaw 1:9490836294ea 715
jbradshaw 1:9490836294ea 716 max30001_status_t status;
jbradshaw 1:9490836294ea 717
jbradshaw 1:9490836294ea 718 max30001_timeout = 0;
jbradshaw 1:9490836294ea 719
jbradshaw 1:9490836294ea 720 do {
jbradshaw 1:9490836294ea 721 if (reg_read(STATUS, &status.all) == -1) { ///< Wait and spin for PLL to lock...
jbradshaw 0:e4a10ed6eb92 722
jbradshaw 1:9490836294ea 723 return -1;
jbradshaw 1:9490836294ea 724 }
jbradshaw 1:9490836294ea 725
jbradshaw 1:9490836294ea 726 } while (status.bit.pllint == 1 && max30001_timeout++ <= 1000);
jbradshaw 0:e4a10ed6eb92 727
jbradshaw 1:9490836294ea 728 return 0;
jbradshaw 1:9490836294ea 729 }
jbradshaw 0:e4a10ed6eb92 730
jbradshaw 1:9490836294ea 731 //******************************************************************************
jbradshaw 1:9490836294ea 732 int MAX30001::sw_rst(void) {
jbradshaw 1:9490836294ea 733 ///< SW reset for the MAX30001 chip
jbradshaw 1:9490836294ea 734
jbradshaw 1:9490836294ea 735 if (reg_write(SW_RST, 0x000000) == -1) {
jbradshaw 0:e4a10ed6eb92 736 return -1;
jbradshaw 0:e4a10ed6eb92 737 }
jbradshaw 0:e4a10ed6eb92 738
jbradshaw 0:e4a10ed6eb92 739 return 0;
jbradshaw 0:e4a10ed6eb92 740 }
jbradshaw 0:e4a10ed6eb92 741
jbradshaw 0:e4a10ed6eb92 742 //******************************************************************************
jbradshaw 1:9490836294ea 743 int MAX30001::synch(void) { ///< For synchronization
jbradshaw 1:9490836294ea 744 if (reg_write(SYNCH, 0x000000) == -1) {
jbradshaw 0:e4a10ed6eb92 745 return -1;
jbradshaw 0:e4a10ed6eb92 746 }
jbradshaw 0:e4a10ed6eb92 747 return 0;
jbradshaw 0:e4a10ed6eb92 748 }
jbradshaw 0:e4a10ed6eb92 749
jbradshaw 0:e4a10ed6eb92 750 //******************************************************************************
jbradshaw 1:9490836294ea 751 int MAX30001::fifo_rst(void) { ///< Resets the FIFO
jbradshaw 1:9490836294ea 752 if (reg_write(FIFO_RST, 0x000000) == -1) {
jbradshaw 0:e4a10ed6eb92 753 return -1;
jbradshaw 0:e4a10ed6eb92 754 }
jbradshaw 0:e4a10ed6eb92 755 return 0;
jbradshaw 0:e4a10ed6eb92 756 }
jbradshaw 0:e4a10ed6eb92 757
jbradshaw 0:e4a10ed6eb92 758 //******************************************************************************
jbradshaw 1:9490836294ea 759 int MAX30001::reg_write(MAX30001_REG_map_t addr, uint32_t data) {
jbradshaw 0:e4a10ed6eb92 760
jbradshaw 0:e4a10ed6eb92 761 uint8_t result[4];
jbradshaw 0:e4a10ed6eb92 762 uint8_t data_array[4];
jbradshaw 0:e4a10ed6eb92 763 int32_t success = 0;
jbradshaw 0:e4a10ed6eb92 764
jbradshaw 0:e4a10ed6eb92 765 data_array[0] = (addr << 1) & 0xff;
jbradshaw 0:e4a10ed6eb92 766
jbradshaw 0:e4a10ed6eb92 767 data_array[3] = data & 0xff;
jbradshaw 0:e4a10ed6eb92 768 data_array[2] = (data >> 8) & 0xff;
jbradshaw 0:e4a10ed6eb92 769 data_array[1] = (data >> 16) & 0xff;
jbradshaw 0:e4a10ed6eb92 770
jbradshaw 0:e4a10ed6eb92 771 success = SPI_Transmit(&data_array[0], 4, &result[0], 4);
jbradshaw 0:e4a10ed6eb92 772
jbradshaw 0:e4a10ed6eb92 773 if (success != 0) {
jbradshaw 0:e4a10ed6eb92 774 return -1;
jbradshaw 0:e4a10ed6eb92 775 } else {
jbradshaw 0:e4a10ed6eb92 776 return 0;
jbradshaw 0:e4a10ed6eb92 777 }
jbradshaw 0:e4a10ed6eb92 778 }
jbradshaw 0:e4a10ed6eb92 779
jbradshaw 0:e4a10ed6eb92 780 //******************************************************************************
jbradshaw 1:9490836294ea 781 int MAX30001::reg_read(MAX30001_REG_map_t addr,
jbradshaw 1:9490836294ea 782 uint32_t *return_data) {
jbradshaw 0:e4a10ed6eb92 783 uint8_t result[4];
jbradshaw 0:e4a10ed6eb92 784 uint8_t data_array[1];
jbradshaw 0:e4a10ed6eb92 785 int32_t success = 0;
jbradshaw 0:e4a10ed6eb92 786
jbradshaw 0:e4a10ed6eb92 787 data_array[0] = ((addr << 1) & 0xff) | 1; // For Read, Or with 1
jbradshaw 0:e4a10ed6eb92 788 success = SPI_Transmit(&data_array[0], 1, &result[0], 4);
jbradshaw 0:e4a10ed6eb92 789 *return_data = /*result[0] + */ (uint32_t)(result[1] << 16) +
jbradshaw 0:e4a10ed6eb92 790 (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 791 if (success != 0) {
jbradshaw 0:e4a10ed6eb92 792 return -1;
jbradshaw 0:e4a10ed6eb92 793 } else {
jbradshaw 0:e4a10ed6eb92 794 return 0;
jbradshaw 0:e4a10ed6eb92 795 }
jbradshaw 0:e4a10ed6eb92 796 }
jbradshaw 0:e4a10ed6eb92 797
jbradshaw 0:e4a10ed6eb92 798 //******************************************************************************
jbradshaw 1:9490836294ea 799 int MAX30001::Enable_DcLeadOFF_Init(int8_t En_dcloff, int8_t Ipol,
jbradshaw 1:9490836294ea 800 int8_t Imag, int8_t Vth) {
jbradshaw 1:9490836294ea 801 ///< the leads are not touching the body
jbradshaw 0:e4a10ed6eb92 802
jbradshaw 1:9490836294ea 803 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 0:e4a10ed6eb92 804
jbradshaw 1:9490836294ea 805 ///< CNFG_EMUX, Set ECGP and ECGN for external hook up...
jbradshaw 1:9490836294ea 806
jbradshaw 1:9490836294ea 807 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 808 return -1;
jbradshaw 0:e4a10ed6eb92 809 }
jbradshaw 0:e4a10ed6eb92 810
jbradshaw 1:9490836294ea 811 cnfg_gen.bit.en_dcloff = En_dcloff;
jbradshaw 1:9490836294ea 812 cnfg_gen.bit.ipol = Ipol;
jbradshaw 1:9490836294ea 813 cnfg_gen.bit.imag = Imag;
jbradshaw 1:9490836294ea 814 cnfg_gen.bit.vth = Vth;
jbradshaw 0:e4a10ed6eb92 815
jbradshaw 1:9490836294ea 816 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 817 return -1;
jbradshaw 0:e4a10ed6eb92 818 }
jbradshaw 0:e4a10ed6eb92 819
jbradshaw 0:e4a10ed6eb92 820 return 0;
jbradshaw 0:e4a10ed6eb92 821 }
jbradshaw 0:e4a10ed6eb92 822
jbradshaw 0:e4a10ed6eb92 823 //******************************************************************************
jbradshaw 1:9490836294ea 824 int MAX30001::Disable_DcLeadOFF(void) {
jbradshaw 1:9490836294ea 825
jbradshaw 1:9490836294ea 826 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 827
jbradshaw 1:9490836294ea 828 ///< CNFG_GEN
jbradshaw 1:9490836294ea 829 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 830 return -1;
jbradshaw 0:e4a10ed6eb92 831 }
jbradshaw 0:e4a10ed6eb92 832
jbradshaw 1:9490836294ea 833 cnfg_gen.bit.en_dcloff = 0; // Turned off the dc lead off.
jbradshaw 0:e4a10ed6eb92 834
jbradshaw 1:9490836294ea 835 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 836 return -1;
jbradshaw 0:e4a10ed6eb92 837 }
jbradshaw 0:e4a10ed6eb92 838
jbradshaw 0:e4a10ed6eb92 839 return 0;
jbradshaw 0:e4a10ed6eb92 840 }
jbradshaw 0:e4a10ed6eb92 841
jbradshaw 0:e4a10ed6eb92 842 //******************************************************************************
jbradshaw 1:9490836294ea 843 int MAX30001::BIOZ_Enable_ACLeadOFF_Init(uint8_t En_bloff, uint8_t Bloff_hi_it,
jbradshaw 1:9490836294ea 844 uint8_t Bloff_lo_it) {
jbradshaw 0:e4a10ed6eb92 845
jbradshaw 1:9490836294ea 846 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 847 max30001_mngr_dyn_t mngr_dyn;
jbradshaw 1:9490836294ea 848
jbradshaw 1:9490836294ea 849 ///< CNFG_GEN
jbradshaw 1:9490836294ea 850 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 851 return -1;
jbradshaw 0:e4a10ed6eb92 852 }
jbradshaw 0:e4a10ed6eb92 853
jbradshaw 1:9490836294ea 854 cnfg_gen.bit.en_bloff = En_bloff;
jbradshaw 0:e4a10ed6eb92 855
jbradshaw 1:9490836294ea 856 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 857 return -1;
jbradshaw 0:e4a10ed6eb92 858 }
jbradshaw 0:e4a10ed6eb92 859
jbradshaw 1:9490836294ea 860 ///< MNGR_DYN
jbradshaw 1:9490836294ea 861 if (reg_read(MNGR_DYN, &mngr_dyn.all) == -1) {
jbradshaw 0:e4a10ed6eb92 862 return -1;
jbradshaw 0:e4a10ed6eb92 863 }
jbradshaw 0:e4a10ed6eb92 864
jbradshaw 1:9490836294ea 865 mngr_dyn.bit.bloff_hi_it = Bloff_hi_it;
jbradshaw 1:9490836294ea 866 mngr_dyn.bit.bloff_lo_it = Bloff_lo_it;
jbradshaw 0:e4a10ed6eb92 867
jbradshaw 1:9490836294ea 868 if (reg_write(MNGR_DYN, mngr_dyn.all) == -1) {
jbradshaw 0:e4a10ed6eb92 869 return -1;
jbradshaw 0:e4a10ed6eb92 870 }
jbradshaw 0:e4a10ed6eb92 871
jbradshaw 0:e4a10ed6eb92 872 return 0;
jbradshaw 0:e4a10ed6eb92 873 }
jbradshaw 0:e4a10ed6eb92 874
jbradshaw 0:e4a10ed6eb92 875 //******************************************************************************
jbradshaw 1:9490836294ea 876 int MAX30001::BIOZ_Disable_ACleadOFF(void) {
jbradshaw 1:9490836294ea 877
jbradshaw 1:9490836294ea 878 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 879
jbradshaw 1:9490836294ea 880 ///< CNFG_GEN
jbradshaw 1:9490836294ea 881 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 882 return -1;
jbradshaw 0:e4a10ed6eb92 883 }
jbradshaw 0:e4a10ed6eb92 884
jbradshaw 1:9490836294ea 885 cnfg_gen.bit.en_bloff = 0b0; // Turns of the BIOZ AC Lead OFF feature
jbradshaw 0:e4a10ed6eb92 886
jbradshaw 1:9490836294ea 887 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 0:e4a10ed6eb92 888 return -1;
jbradshaw 0:e4a10ed6eb92 889 }
jbradshaw 0:e4a10ed6eb92 890
jbradshaw 0:e4a10ed6eb92 891 return 0;
jbradshaw 0:e4a10ed6eb92 892 }
jbradshaw 0:e4a10ed6eb92 893
jbradshaw 0:e4a10ed6eb92 894 //******************************************************************************
jbradshaw 1:9490836294ea 895 int MAX30001::BIOZ_Enable_BCGMON(void) {
jbradshaw 1:9490836294ea 896
jbradshaw 1:9490836294ea 897 max30001_cnfg_bioz_t cnfg_bioz;
jbradshaw 1:9490836294ea 898
jbradshaw 1:9490836294ea 899 ///< CNFG_BIOZ
jbradshaw 1:9490836294ea 900 if (reg_read(CNFG_BIOZ, &cnfg_bioz.all) == -1) {
jbradshaw 0:e4a10ed6eb92 901 return -1;
jbradshaw 0:e4a10ed6eb92 902 }
jbradshaw 0:e4a10ed6eb92 903
jbradshaw 1:9490836294ea 904 cnfg_bioz.bit.cgmon = 1;
jbradshaw 0:e4a10ed6eb92 905
jbradshaw 1:9490836294ea 906 if (reg_write(CNFG_BIOZ, cnfg_bioz.all) == -1) {
jbradshaw 0:e4a10ed6eb92 907 return -1;
jbradshaw 0:e4a10ed6eb92 908 }
jbradshaw 0:e4a10ed6eb92 909
jbradshaw 0:e4a10ed6eb92 910 return 0;
jbradshaw 0:e4a10ed6eb92 911 }
jbradshaw 1:9490836294ea 912
jbradshaw 1:9490836294ea 913
jbradshaw 0:e4a10ed6eb92 914 //******************************************************************************
jbradshaw 1:9490836294ea 915 int MAX30001::Enable_LeadON(int8_t Channel) // Channel: ECG = 0b01, BIOZ = 0b10, Disable = 0b00
jbradshaw 1:9490836294ea 916 {
jbradshaw 1:9490836294ea 917
jbradshaw 1:9490836294ea 918 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 919
jbradshaw 1:9490836294ea 920 ///< CNFG_GEN
jbradshaw 1:9490836294ea 921 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 922 return -1;
jbradshaw 1:9490836294ea 923 }
jbradshaw 1:9490836294ea 924
jbradshaw 1:9490836294ea 925 cnfg_gen.bit.en_ecg = 0b0;
jbradshaw 1:9490836294ea 926 cnfg_gen.bit.en_bioz = 0b0;
jbradshaw 1:9490836294ea 927 cnfg_gen.bit.en_pace = 0b0;
jbradshaw 1:9490836294ea 928
jbradshaw 1:9490836294ea 929 cnfg_gen.bit.en_ulp_lon = Channel; ///< BIOZ ULP lead on detection...
jbradshaw 1:9490836294ea 930
jbradshaw 1:9490836294ea 931 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 932 return -1;
jbradshaw 1:9490836294ea 933 }
jbradshaw 1:9490836294ea 934
jbradshaw 1:9490836294ea 935 return 0;
jbradshaw 1:9490836294ea 936 }
jbradshaw 1:9490836294ea 937
jbradshaw 1:9490836294ea 938 //******************************************************************************
jbradshaw 1:9490836294ea 939 int MAX30001::Disable_LeadON(void) {
jbradshaw 1:9490836294ea 940
jbradshaw 1:9490836294ea 941 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 942 ///< CNFG_GEN
jbradshaw 1:9490836294ea 943 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 944 return -1;
jbradshaw 1:9490836294ea 945 }
jbradshaw 1:9490836294ea 946
jbradshaw 1:9490836294ea 947 cnfg_gen.bit.en_ulp_lon = 0b0;
jbradshaw 1:9490836294ea 948
jbradshaw 1:9490836294ea 949 if (reg_write(CNFG_GEN, cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 950 return -1;
jbradshaw 1:9490836294ea 951 }
jbradshaw 1:9490836294ea 952
jbradshaw 1:9490836294ea 953 return 0;
jbradshaw 1:9490836294ea 954 }
jbradshaw 1:9490836294ea 955
jbradshaw 1:9490836294ea 956 //******************************************************************************
jbradshaw 1:9490836294ea 957 #define LEADOFF_SERVICE_TIME 0x2000 ///< 0x1000 = 1 second
jbradshaw 0:e4a10ed6eb92 958 #define LEADOFF_NUMSTATES 2
jbradshaw 0:e4a10ed6eb92 959 uint32_t leadoffState = 0;
jbradshaw 0:e4a10ed6eb92 960 uint32_t max30001_LeadOffoldTime = 0;
jbradshaw 1:9490836294ea 961 void MAX30001::ServiceLeadoff(uint32_t currentTime) {
jbradshaw 0:e4a10ed6eb92 962
jbradshaw 0:e4a10ed6eb92 963 uint32_t delta_Time;
jbradshaw 0:e4a10ed6eb92 964
jbradshaw 0:e4a10ed6eb92 965 delta_Time = currentTime - max30001_LeadOffoldTime;
jbradshaw 0:e4a10ed6eb92 966
jbradshaw 0:e4a10ed6eb92 967 if (delta_Time > LEADOFF_SERVICE_TIME) {
jbradshaw 0:e4a10ed6eb92 968 switch (leadoffState) {
jbradshaw 1:9490836294ea 969 case 0: ///< switch to ECG DC Lead OFF
jbradshaw 1:9490836294ea 970 Enable_DcLeadOFF_Init(0b01, 0b0, 0b001, 0b00);
jbradshaw 0:e4a10ed6eb92 971 break;
jbradshaw 0:e4a10ed6eb92 972
jbradshaw 1:9490836294ea 973 case 1: ///< switch to BIOZ DC Lead OFF
jbradshaw 1:9490836294ea 974 Enable_DcLeadOFF_Init(0b10, 0b0, 0b001, 0b00);
jbradshaw 0:e4a10ed6eb92 975 break;
jbradshaw 0:e4a10ed6eb92 976 }
jbradshaw 0:e4a10ed6eb92 977
jbradshaw 0:e4a10ed6eb92 978 leadoffState++;
jbradshaw 0:e4a10ed6eb92 979 leadoffState %= LEADOFF_NUMSTATES;
jbradshaw 0:e4a10ed6eb92 980
jbradshaw 0:e4a10ed6eb92 981 max30001_LeadOffoldTime = currentTime;
jbradshaw 0:e4a10ed6eb92 982 }
jbradshaw 0:e4a10ed6eb92 983 }
jbradshaw 0:e4a10ed6eb92 984 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 985 #define LEADON_SERVICE_TIME 0x2000 // 0x1000 = 1 second
jbradshaw 0:e4a10ed6eb92 986 #define LEADON_NUMSTATES 2
jbradshaw 0:e4a10ed6eb92 987 uint32_t leadOnState = 0;
jbradshaw 0:e4a10ed6eb92 988 uint32_t max30001_LeadOnoldTime = 0;
jbradshaw 1:9490836294ea 989 void MAX30001::ServiceLeadON(uint32_t currentTime) {
jbradshaw 0:e4a10ed6eb92 990
jbradshaw 0:e4a10ed6eb92 991 uint32_t delta_Time;
jbradshaw 0:e4a10ed6eb92 992
jbradshaw 0:e4a10ed6eb92 993 delta_Time = currentTime - max30001_LeadOnoldTime;
jbradshaw 0:e4a10ed6eb92 994
jbradshaw 0:e4a10ed6eb92 995 if (delta_Time > LEADON_SERVICE_TIME) {
jbradshaw 0:e4a10ed6eb92 996 switch (leadOnState) {
jbradshaw 1:9490836294ea 997 case 0: ///< switch to ECG DC Lead ON
jbradshaw 1:9490836294ea 998 Enable_LeadON(0b01);
jbradshaw 0:e4a10ed6eb92 999 break;
jbradshaw 0:e4a10ed6eb92 1000
jbradshaw 1:9490836294ea 1001 case 1: ///< switch to BIOZ DC Lead ON
jbradshaw 1:9490836294ea 1002 Enable_LeadON(0b10);
jbradshaw 0:e4a10ed6eb92 1003 break;
jbradshaw 0:e4a10ed6eb92 1004 }
jbradshaw 0:e4a10ed6eb92 1005
jbradshaw 0:e4a10ed6eb92 1006 leadOnState++;
jbradshaw 0:e4a10ed6eb92 1007 leadOnState %= LEADON_NUMSTATES;
jbradshaw 0:e4a10ed6eb92 1008
jbradshaw 0:e4a10ed6eb92 1009 max30001_LeadOnoldTime = currentTime;
jbradshaw 0:e4a10ed6eb92 1010 }
jbradshaw 0:e4a10ed6eb92 1011 }
jbradshaw 0:e4a10ed6eb92 1012
jbradshaw 0:e4a10ed6eb92 1013 //******************************************************************************
jbradshaw 1:9490836294ea 1014 int MAX30001::FIFO_LeadONOff_Read(void) {
jbradshaw 0:e4a10ed6eb92 1015
jbradshaw 1:9490836294ea 1016 uint8_t result[32 * 3]; ///< 32words - 3bytes each
jbradshaw 0:e4a10ed6eb92 1017 uint8_t data_array[4];
jbradshaw 0:e4a10ed6eb92 1018 int32_t success = 0;
jbradshaw 0:e4a10ed6eb92 1019 int i, j;
jbradshaw 0:e4a10ed6eb92 1020
jbradshaw 0:e4a10ed6eb92 1021 uint32_t total_databytes;
jbradshaw 0:e4a10ed6eb92 1022 uint8_t i_index;
jbradshaw 0:e4a10ed6eb92 1023 uint8_t data_chunk;
jbradshaw 0:e4a10ed6eb92 1024 uint8_t loop_logic;
jbradshaw 0:e4a10ed6eb92 1025
jbradshaw 0:e4a10ed6eb92 1026 uint8_t etag, ptag, btag;
jbradshaw 0:e4a10ed6eb92 1027
jbradshaw 0:e4a10ed6eb92 1028 uint8_t adr;
jbradshaw 0:e4a10ed6eb92 1029
jbradshaw 0:e4a10ed6eb92 1030 int8_t ReadAllPaceOnce;
jbradshaw 0:e4a10ed6eb92 1031
jbradshaw 0:e4a10ed6eb92 1032 static uint8_t dcloffint_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1033 static uint8_t acloffint_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1034 static uint8_t bcgmon_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1035 static uint8_t acleadon_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1036
jbradshaw 1:9490836294ea 1037 max30001_mngr_int_t mngr_int;
jbradshaw 1:9490836294ea 1038 max30001_cnfg_gen_t cnfg_gen;
jbradshaw 1:9490836294ea 1039
jbradshaw 0:e4a10ed6eb92 1040 int8_t ret_val;
jbradshaw 0:e4a10ed6eb92 1041
jbradshaw 1:9490836294ea 1042 etag = 0;
jbradshaw 1:9490836294ea 1043 if (global_status.bit.eint == 1 || global_status.bit.pint == 1) {
jbradshaw 0:e4a10ed6eb92 1044 adr = ECG_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1045 data_array[0] = ((adr << 1) & 0xff) | 1;
jbradshaw 0:e4a10ed6eb92 1046
jbradshaw 1:9490836294ea 1047 ///< The SPI routine only sends out data of 32 bytes in size. Therefore the
jbradshaw 1:9490836294ea 1048 ///< data is being read in
jbradshaw 1:9490836294ea 1049 ///< smaller chunks in this routine...
jbradshaw 1:9490836294ea 1050
jbradshaw 1:9490836294ea 1051 ///< READ mngr_int AND cnfg_gen;
jbradshaw 0:e4a10ed6eb92 1052
jbradshaw 1:9490836294ea 1053 if (reg_read(MNGR_INT, &mngr_int.all) == -1) {
jbradshaw 1:9490836294ea 1054 return -1;
jbradshaw 1:9490836294ea 1055 }
jbradshaw 1:9490836294ea 1056
jbradshaw 1:9490836294ea 1057 if (reg_read(CNFG_GEN, &cnfg_gen.all) == -1) {
jbradshaw 1:9490836294ea 1058 return -1;
jbradshaw 1:9490836294ea 1059 }
jbradshaw 1:9490836294ea 1060
jbradshaw 1:9490836294ea 1061 total_databytes = (mngr_int.bit.e_fit + 1) * 3;
jbradshaw 0:e4a10ed6eb92 1062
jbradshaw 0:e4a10ed6eb92 1063 i_index = 0;
jbradshaw 0:e4a10ed6eb92 1064 loop_logic = 1;
jbradshaw 0:e4a10ed6eb92 1065
jbradshaw 0:e4a10ed6eb92 1066 while (loop_logic) {
jbradshaw 0:e4a10ed6eb92 1067 if (total_databytes > 30) {
jbradshaw 0:e4a10ed6eb92 1068 data_chunk = 30;
jbradshaw 0:e4a10ed6eb92 1069 total_databytes = total_databytes - 30;
jbradshaw 0:e4a10ed6eb92 1070 } else {
jbradshaw 0:e4a10ed6eb92 1071 data_chunk = total_databytes;
jbradshaw 0:e4a10ed6eb92 1072 loop_logic = 0;
jbradshaw 0:e4a10ed6eb92 1073 }
jbradshaw 0:e4a10ed6eb92 1074
jbradshaw 1:9490836294ea 1075 ///< The extra 1 byte is for the extra byte that comes out of the SPI
jbradshaw 0:e4a10ed6eb92 1076 success = SPI_Transmit(&data_array[0], 1, &result[i_index], (data_chunk + 1)); // Make a copy of the FIFO over here...
jbradshaw 0:e4a10ed6eb92 1077
jbradshaw 0:e4a10ed6eb92 1078 if (success != 0) {
jbradshaw 0:e4a10ed6eb92 1079 return -1;
jbradshaw 0:e4a10ed6eb92 1080 }
jbradshaw 0:e4a10ed6eb92 1081
jbradshaw 1:9490836294ea 1082 ///< This is important, because every transaction above creates an empty
jbradshaw 1:9490836294ea 1083 ///< redundant data at result[0]
jbradshaw 0:e4a10ed6eb92 1084 for (j = i_index; j < (data_chunk + i_index); j++) /* get rid of the 1 extra byte by moving the whole array up one */
jbradshaw 0:e4a10ed6eb92 1085 {
jbradshaw 0:e4a10ed6eb92 1086 result[j] = result[j + 1];
jbradshaw 0:e4a10ed6eb92 1087 }
jbradshaw 0:e4a10ed6eb92 1088
jbradshaw 0:e4a10ed6eb92 1089 i_index = i_index + 30; /* point to the next array location to put the data in */
jbradshaw 0:e4a10ed6eb92 1090 }
jbradshaw 0:e4a10ed6eb92 1091
jbradshaw 0:e4a10ed6eb92 1092 ReadAllPaceOnce = 0;
jbradshaw 0:e4a10ed6eb92 1093
jbradshaw 1:9490836294ea 1094 ///< Put the content of the FIFO based on the EFIT value, We ignore the
jbradshaw 1:9490836294ea 1095 ///< result[0] and start concatenating indexes: 1,2,3 - 4,5,6 - 7,8,9 -
jbradshaw 1:9490836294ea 1096 for (i = 0, j = 0; i < mngr_int.bit.e_fit + 1; i++, j = j + 3) ///< index1=23-16 bit, index2=15-8 bit, index3=7-0 bit
jbradshaw 0:e4a10ed6eb92 1097 {
jbradshaw 0:e4a10ed6eb92 1098 max30001_ECG_FIFO_buffer[i] = ((uint32_t)result[j] << 16) + (result[j + 1] << 8) + result[j + 2];
jbradshaw 0:e4a10ed6eb92 1099
jbradshaw 0:e4a10ed6eb92 1100 etag = (0b00111000 & result[j + 2]) >> 3;
jbradshaw 0:e4a10ed6eb92 1101 ptag = 0b00000111 & result[j + 2];
jbradshaw 0:e4a10ed6eb92 1102
jbradshaw 0:e4a10ed6eb92 1103 if (ptag != 0b111 && ReadAllPaceOnce == 0) {
jbradshaw 0:e4a10ed6eb92 1104
jbradshaw 1:9490836294ea 1105 ReadAllPaceOnce = 1; ///< This will prevent extra read of PACE, once group
jbradshaw 1:9490836294ea 1106 ///< 0-5 is read ONCE.
jbradshaw 0:e4a10ed6eb92 1107
jbradshaw 0:e4a10ed6eb92 1108 adr = PACE0_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1109
jbradshaw 1:9490836294ea 1110 data_array[0] = ((adr << 1) & 0xff) | 1; ///< For Read Or with 1
jbradshaw 0:e4a10ed6eb92 1111
jbradshaw 0:e4a10ed6eb92 1112 success = SPI_Transmit(&data_array[0], 1, &result[0], 10);
jbradshaw 0:e4a10ed6eb92 1113
jbradshaw 0:e4a10ed6eb92 1114 max30001_PACE[0] = (uint32_t)(result[1] << 16) + (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 1115 max30001_PACE[1] = (uint32_t)(result[4] << 16) + (result[5] << 8) + result[6];
jbradshaw 0:e4a10ed6eb92 1116 max30001_PACE[2] = (uint32_t)(result[7] << 16) + (result[8] << 8) + result[9];
jbradshaw 0:e4a10ed6eb92 1117
jbradshaw 0:e4a10ed6eb92 1118 adr = PACE1_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1119
jbradshaw 1:9490836294ea 1120 data_array[0] = ((adr << 1) & 0xff) | 1; ///< For Read Or with 1
jbradshaw 0:e4a10ed6eb92 1121
jbradshaw 0:e4a10ed6eb92 1122 success = SPI_Transmit(&data_array[0], 1, &result[0], 10);
jbradshaw 0:e4a10ed6eb92 1123
jbradshaw 0:e4a10ed6eb92 1124 max30001_PACE[3] = (uint32_t)(result[1] << 16) + (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 1125 max30001_PACE[4] = (uint32_t)(result[4] << 16) + (result[5] << 8) + result[6];
jbradshaw 0:e4a10ed6eb92 1126 max30001_PACE[5] = (uint32_t)(result[7] << 16) + (result[8] << 8) + result[9];
jbradshaw 0:e4a10ed6eb92 1127
jbradshaw 0:e4a10ed6eb92 1128 adr = PACE2_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1129
jbradshaw 1:9490836294ea 1130 data_array[0] = ((adr << 1) & 0xff) | 1; ///< For Read Or with 1
jbradshaw 0:e4a10ed6eb92 1131
jbradshaw 0:e4a10ed6eb92 1132 success = SPI_Transmit(&data_array[0], 1, &result[0], 10);
jbradshaw 0:e4a10ed6eb92 1133
jbradshaw 0:e4a10ed6eb92 1134 max30001_PACE[6] = (uint32_t)(result[1] << 16) + (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 1135 max30001_PACE[7] = (uint32_t)(result[4] << 16) + (result[5] << 8) + result[6];
jbradshaw 0:e4a10ed6eb92 1136 max30001_PACE[8] = (uint32_t)(result[7] << 16) + (result[8] << 8) + result[9];
jbradshaw 0:e4a10ed6eb92 1137
jbradshaw 0:e4a10ed6eb92 1138 adr = PACE3_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1139
jbradshaw 1:9490836294ea 1140 data_array[0] = ((adr << 1) & 0xff) | 1; ///< For Read Or with 1
jbradshaw 0:e4a10ed6eb92 1141
jbradshaw 0:e4a10ed6eb92 1142 success = SPI_Transmit(&data_array[0], 1, &result[0], 10);
jbradshaw 0:e4a10ed6eb92 1143
jbradshaw 0:e4a10ed6eb92 1144 max30001_PACE[9] = (uint32_t)(result[1] << 16) + (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 1145 max30001_PACE[10] = (uint32_t)(result[4] << 16) + (result[5] << 8) + result[6];
jbradshaw 0:e4a10ed6eb92 1146 max30001_PACE[11] = (uint32_t)(result[7] << 16) + (result[8] << 8) + result[9];
jbradshaw 0:e4a10ed6eb92 1147
jbradshaw 0:e4a10ed6eb92 1148 adr = PACE4_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1149
jbradshaw 1:9490836294ea 1150 data_array[0] = ((adr << 1) & 0xff) | 1; ///< For Read Or with 1
jbradshaw 0:e4a10ed6eb92 1151
jbradshaw 0:e4a10ed6eb92 1152 success = SPI_Transmit(&data_array[0], 1, &result[0], 10);
jbradshaw 0:e4a10ed6eb92 1153
jbradshaw 0:e4a10ed6eb92 1154 max30001_PACE[12] = (uint32_t)(result[1] << 16) + (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 1155 max30001_PACE[13] = (uint32_t)(result[4] << 16) + (result[5] << 8) + result[6];
jbradshaw 0:e4a10ed6eb92 1156 max30001_PACE[14] = (uint32_t)(result[7] << 16) + (result[8] << 8) + result[9];
jbradshaw 0:e4a10ed6eb92 1157
jbradshaw 0:e4a10ed6eb92 1158 adr = PACE5_FIFO_BURST;
jbradshaw 0:e4a10ed6eb92 1159
jbradshaw 1:9490836294ea 1160 data_array[0] = ((adr << 1) & 0xff) | 1; ///< For Read Or with 1
jbradshaw 0:e4a10ed6eb92 1161
jbradshaw 0:e4a10ed6eb92 1162 success = SPI_Transmit(&data_array[0], 1, &result[0], 10);
jbradshaw 0:e4a10ed6eb92 1163
jbradshaw 0:e4a10ed6eb92 1164 max30001_PACE[15] = (uint32_t)(result[1] << 16) + (result[2] << 8) + result[3];
jbradshaw 0:e4a10ed6eb92 1165 max30001_PACE[16] = (uint32_t)(result[4] << 16) + (result[5] << 8) + result[6];
jbradshaw 0:e4a10ed6eb92 1166 max30001_PACE[17] = (uint32_t)(result[7] << 16) + (result[8] << 8) + result[9];
jbradshaw 0:e4a10ed6eb92 1167
jbradshaw 1:9490836294ea 1168 dataAvailable(MAX30001_DATA_PACE, max30001_PACE, 18); ///< Send out the Pace data once only
jbradshaw 0:e4a10ed6eb92 1169 }
jbradshaw 0:e4a10ed6eb92 1170 }
jbradshaw 0:e4a10ed6eb92 1171
jbradshaw 0:e4a10ed6eb92 1172 if (etag != 0b110) {
jbradshaw 0:e4a10ed6eb92 1173
jbradshaw 1:9490836294ea 1174 dataAvailable(MAX30001_DATA_ECG, max30001_ECG_FIFO_buffer, (mngr_int.bit.e_fit + 1));
jbradshaw 0:e4a10ed6eb92 1175 }
jbradshaw 0:e4a10ed6eb92 1176
jbradshaw 0:e4a10ed6eb92 1177 } /* End of ECG init */
jbradshaw 0:e4a10ed6eb92 1178
jbradshaw 0:e4a10ed6eb92 1179 /* RtoR */
jbradshaw 0:e4a10ed6eb92 1180
jbradshaw 1:9490836294ea 1181 if (global_status.bit.rrint == 1) {
jbradshaw 1:9490836294ea 1182 if (reg_read(RTOR, &max30001_RtoR_data) == -1) {
jbradshaw 0:e4a10ed6eb92 1183 return -1;
jbradshaw 0:e4a10ed6eb92 1184 }
jbradshaw 0:e4a10ed6eb92 1185
jbradshaw 0:e4a10ed6eb92 1186 max30001_RtoR_data = (0x00FFFFFF & max30001_RtoR_data) >> 10;
jbradshaw 0:e4a10ed6eb92 1187
jbradshaw 0:e4a10ed6eb92 1188 hspValMax30001.R2R = (uint16_t)max30001_RtoR_data;
jbradshaw 1:9490836294ea 1189 hspValMax30001.fmstr = (uint16_t)cnfg_gen.bit.fmstr;
jbradshaw 0:e4a10ed6eb92 1190
jbradshaw 0:e4a10ed6eb92 1191 dataAvailable(MAX30001_DATA_RTOR, &max30001_RtoR_data, 1);
jbradshaw 0:e4a10ed6eb92 1192 }
jbradshaw 0:e4a10ed6eb92 1193
jbradshaw 1:9490836294ea 1194 ///< Handling BIOZ data...
jbradshaw 0:e4a10ed6eb92 1195
jbradshaw 1:9490836294ea 1196 if (global_status.bit.bint == 1) {
jbradshaw 0:e4a10ed6eb92 1197 adr = 0x22;
jbradshaw 0:e4a10ed6eb92 1198 data_array[0] = ((adr << 1) & 0xff) | 1;
jbradshaw 0:e4a10ed6eb92 1199
jbradshaw 1:9490836294ea 1200 ///< [(BFIT+1)*3byte]+1extra byte due to the addr
jbradshaw 0:e4a10ed6eb92 1201
jbradshaw 1:9490836294ea 1202 if (SPI_Transmit(&data_array[0], 1, &result[0],((mngr_int.bit.b_fit + 1) * 3) + 1) == -1) { ///< Make a copy of the FIFO over here...
jbradshaw 0:e4a10ed6eb92 1203 return -1;
jbradshaw 0:e4a10ed6eb92 1204 }
jbradshaw 0:e4a10ed6eb92 1205
jbradshaw 0:e4a10ed6eb92 1206 btag = 0b00000111 & result[3];
jbradshaw 0:e4a10ed6eb92 1207
jbradshaw 1:9490836294ea 1208 ///< Put the content of the FIFO based on the BFIT value, We ignore the
jbradshaw 1:9490836294ea 1209 ///< result[0] and start concatenating indexes: 1,2,3 - 4,5,6 - 7,8,9 -
jbradshaw 1:9490836294ea 1210 for (i = 0, j = 0; i < mngr_int.bit.b_fit + 1; i++, j = j + 3) ///< index1=23-16 bit, index2=15-8 bit, index3=7-0 bit
jbradshaw 0:e4a10ed6eb92 1211 {
jbradshaw 0:e4a10ed6eb92 1212 max30001_BIOZ_FIFO_buffer[i] = ((uint32_t)result[j + 1] << 16) + (result[j + 2] << 8) + result[j + 3];
jbradshaw 0:e4a10ed6eb92 1213 }
jbradshaw 0:e4a10ed6eb92 1214
jbradshaw 0:e4a10ed6eb92 1215 if (btag != 0b110) {
jbradshaw 0:e4a10ed6eb92 1216 dataAvailable(MAX30001_DATA_BIOZ, max30001_BIOZ_FIFO_buffer, 8);
jbradshaw 0:e4a10ed6eb92 1217 }
jbradshaw 0:e4a10ed6eb92 1218 }
jbradshaw 0:e4a10ed6eb92 1219
jbradshaw 0:e4a10ed6eb92 1220 ret_val = 0;
jbradshaw 0:e4a10ed6eb92 1221
jbradshaw 1:9490836294ea 1222 if (global_status.bit.dcloffint == 1) { ///< ECG/BIOZ Lead Off
jbradshaw 0:e4a10ed6eb92 1223 dcloffint_OneShot = 1;
jbradshaw 0:e4a10ed6eb92 1224 max30001_DCLeadOff = 0;
jbradshaw 1:9490836294ea 1225 max30001_DCLeadOff = max30001_DCLeadOff | (cnfg_gen.bit.en_dcloff << 8) | (global_status.all & 0x00000F);
jbradshaw 0:e4a10ed6eb92 1226 dataAvailable(MAX30001_DATA_LEADOFF_DC, &max30001_DCLeadOff, 1);
jbradshaw 1:9490836294ea 1227 ///< Do a FIFO Reset
jbradshaw 1:9490836294ea 1228 reg_write(FIFO_RST, 0x000000);
jbradshaw 0:e4a10ed6eb92 1229
jbradshaw 0:e4a10ed6eb92 1230 ret_val = 0b100;
jbradshaw 0:e4a10ed6eb92 1231
jbradshaw 1:9490836294ea 1232 } else if (dcloffint_OneShot == 1 && global_status.bit.dcloffint == 0) { ///< Just send once when it comes out of dc lead off
jbradshaw 0:e4a10ed6eb92 1233 max30001_DCLeadOff = 0;
jbradshaw 1:9490836294ea 1234 max30001_DCLeadOff = max30001_DCLeadOff | (cnfg_gen.bit.en_dcloff << 8) | (global_status.all & 0x00000F);
jbradshaw 0:e4a10ed6eb92 1235 dataAvailable(MAX30001_DATA_LEADOFF_DC, &max30001_DCLeadOff, 1);
jbradshaw 0:e4a10ed6eb92 1236 dcloffint_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1237 }
jbradshaw 0:e4a10ed6eb92 1238
jbradshaw 1:9490836294ea 1239 if (global_status.bit.bover == 1 || global_status.bit.bundr == 1) { ///< BIOZ AC Lead Off
jbradshaw 0:e4a10ed6eb92 1240 acloffint_OneShot = 1;
jbradshaw 0:e4a10ed6eb92 1241 max30001_ACLeadOff = 0;
jbradshaw 0:e4a10ed6eb92 1242 max30001_ACLeadOff =
jbradshaw 1:9490836294ea 1243 max30001_ACLeadOff | ((global_status.all & 0x030000) >> 16);
jbradshaw 0:e4a10ed6eb92 1244 dataAvailable(MAX30001_DATA_LEADOFF_AC, &max30001_ACLeadOff, 1);
jbradshaw 1:9490836294ea 1245 ///< Do a FIFO Reset
jbradshaw 1:9490836294ea 1246 reg_write(FIFO_RST, 0x000000);
jbradshaw 0:e4a10ed6eb92 1247
jbradshaw 0:e4a10ed6eb92 1248 ret_val = 0b1000;
jbradshaw 1:9490836294ea 1249 } else if (acloffint_OneShot == 1 && global_status.bit.bover == 0 && global_status.bit.bundr == 0) { ///< Just send once when it comes out of ac lead off
jbradshaw 0:e4a10ed6eb92 1250 max30001_ACLeadOff = 0;
jbradshaw 1:9490836294ea 1251 max30001_ACLeadOff = max30001_ACLeadOff | ((global_status.all & 0x030000) >> 16);
jbradshaw 0:e4a10ed6eb92 1252 dataAvailable(MAX30001_DATA_LEADOFF_AC, &max30001_ACLeadOff, 1);
jbradshaw 0:e4a10ed6eb92 1253 acloffint_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1254 }
jbradshaw 0:e4a10ed6eb92 1255
jbradshaw 1:9490836294ea 1256 if (global_status.bit.bcgmon == 1) {///< BIOZ BCGMON check
jbradshaw 0:e4a10ed6eb92 1257 bcgmon_OneShot = 1;
jbradshaw 0:e4a10ed6eb92 1258 max30001_bcgmon = 0;
jbradshaw 1:9490836294ea 1259 max30001_bcgmon = max30001_bcgmon | ((global_status.all & 0x000030) >> 4);
jbradshaw 0:e4a10ed6eb92 1260 dataAvailable(MAX30001_DATA_BCGMON, &max30001_bcgmon, 1);
jbradshaw 0:e4a10ed6eb92 1261 // Do a FIFO Reset
jbradshaw 1:9490836294ea 1262 reg_write(FIFO_RST, 0x000000);
jbradshaw 0:e4a10ed6eb92 1263
jbradshaw 0:e4a10ed6eb92 1264 ret_val = 0b10000;
jbradshaw 1:9490836294ea 1265 } else if (bcgmon_OneShot == 1 && global_status.bit.bcgmon == 0) {
jbradshaw 0:e4a10ed6eb92 1266 max30001_bcgmon = 0;
jbradshaw 1:9490836294ea 1267 max30001_bcgmon = max30001_bcgmon | ((global_status.all & 0x000030) >> 4);
jbradshaw 0:e4a10ed6eb92 1268 bcgmon_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1269 dataAvailable(MAX30001_DATA_BCGMON, &max30001_bcgmon, 1);
jbradshaw 0:e4a10ed6eb92 1270 }
jbradshaw 0:e4a10ed6eb92 1271
jbradshaw 1:9490836294ea 1272 if (global_status.bit.lonint == 1 && acleadon_OneShot == 0) {///< AC LeadON Check, when lead is on
jbradshaw 0:e4a10ed6eb92 1273 max30001_LeadOn = 0;
jbradshaw 1:9490836294ea 1274 reg_read(STATUS, &global_status.all);
jbradshaw 0:e4a10ed6eb92 1275 max30001_LeadOn =
jbradshaw 1:9490836294ea 1276 max30001_LeadOn | (cnfg_gen.bit.en_ulp_lon << 8) |
jbradshaw 1:9490836294ea 1277 ((global_status.all & 0x000800) >>
jbradshaw 1:9490836294ea 1278 11); ///< 0b01 will mean ECG Lead On, 0b10 will mean BIOZ Lead On
jbradshaw 0:e4a10ed6eb92 1279
jbradshaw 0:e4a10ed6eb92 1280 // LEAD ON has been detected... Now take actions
jbradshaw 0:e4a10ed6eb92 1281 acleadon_OneShot = 1;
jbradshaw 1:9490836294ea 1282 dataAvailable(MAX30001_DATA_ACLEADON, &max30001_LeadOn, 1); ///< One shot data will be sent...
jbradshaw 1:9490836294ea 1283 } else if (global_status.bit.lonint == 0 && acleadon_OneShot == 1) {
jbradshaw 0:e4a10ed6eb92 1284 max30001_LeadOn = 0;
jbradshaw 1:9490836294ea 1285 reg_read(STATUS, &global_status.all);
jbradshaw 0:e4a10ed6eb92 1286 max30001_LeadOn =
jbradshaw 1:9490836294ea 1287 max30001_LeadOn | (cnfg_gen.bit.en_ulp_lon << 8) | ((global_status.all & 0x000800) >> 11); ///< 0b01 will mean ECG Lead On, 0b10 will mean BIOZ Lead On
jbradshaw 1:9490836294ea 1288 dataAvailable(MAX30001_DATA_ACLEADON, &max30001_LeadOn, 1); ///< One shot data will be sent...
jbradshaw 0:e4a10ed6eb92 1289 acleadon_OneShot = 0;
jbradshaw 0:e4a10ed6eb92 1290 }
jbradshaw 0:e4a10ed6eb92 1291
jbradshaw 0:e4a10ed6eb92 1292 return ret_val;
jbradshaw 0:e4a10ed6eb92 1293 }
jbradshaw 0:e4a10ed6eb92 1294
jbradshaw 0:e4a10ed6eb92 1295 //******************************************************************************
jbradshaw 1:9490836294ea 1296 int MAX30001::int_handler(void) {
jbradshaw 0:e4a10ed6eb92 1297
jbradshaw 0:e4a10ed6eb92 1298 static uint32_t InitReset = 0;
jbradshaw 0:e4a10ed6eb92 1299
jbradshaw 0:e4a10ed6eb92 1300 int8_t return_value;
jbradshaw 0:e4a10ed6eb92 1301
jbradshaw 1:9490836294ea 1302 reg_read(STATUS, &global_status.all);
jbradshaw 0:e4a10ed6eb92 1303
jbradshaw 1:9490836294ea 1304 ///< Inital Reset and any FIFO over flow invokes a FIFO reset
jbradshaw 1:9490836294ea 1305 if (InitReset == 0 || global_status.bit.eovf == 1 || global_status.bit.bovf == 1 || global_status.bit.povf == 1) {
jbradshaw 1:9490836294ea 1306 ///< Do a FIFO Reset
jbradshaw 1:9490836294ea 1307 reg_write(FIFO_RST, 0x000000);
jbradshaw 0:e4a10ed6eb92 1308
jbradshaw 0:e4a10ed6eb92 1309 InitReset++;
jbradshaw 0:e4a10ed6eb92 1310 return 2;
jbradshaw 0:e4a10ed6eb92 1311 }
jbradshaw 0:e4a10ed6eb92 1312
jbradshaw 0:e4a10ed6eb92 1313 return_value = 0;
jbradshaw 0:e4a10ed6eb92 1314
jbradshaw 1:9490836294ea 1315 ///< The four data handling goes on over here
jbradshaw 1:9490836294ea 1316 if (global_status.bit.eint == 1 || global_status.bit.pint == 1 || global_status.bit.bint == 1 || global_status.bit.rrint == 1) {
jbradshaw 1:9490836294ea 1317 return_value = return_value | FIFO_LeadONOff_Read();
jbradshaw 0:e4a10ed6eb92 1318 }
jbradshaw 0:e4a10ed6eb92 1319
jbradshaw 1:9490836294ea 1320 ///< ECG/BIOZ DC Lead Off test
jbradshaw 1:9490836294ea 1321 if (global_status.bit.dcloffint == 1) {
jbradshaw 1:9490836294ea 1322 return_value = return_value | FIFO_LeadONOff_Read();
jbradshaw 0:e4a10ed6eb92 1323 }
jbradshaw 0:e4a10ed6eb92 1324
jbradshaw 1:9490836294ea 1325 ///< BIOZ AC Lead Off test
jbradshaw 1:9490836294ea 1326 if (global_status.bit.bover == 1 || global_status.bit.bundr == 1) {
jbradshaw 1:9490836294ea 1327 return_value = return_value | FIFO_LeadONOff_Read();
jbradshaw 0:e4a10ed6eb92 1328 }
jbradshaw 0:e4a10ed6eb92 1329
jbradshaw 1:9490836294ea 1330 ///< BIOZ DRVP/N test using BCGMON.
jbradshaw 1:9490836294ea 1331 if (global_status.bit.bcgmon == 1) {
jbradshaw 1:9490836294ea 1332 return_value = return_value | FIFO_LeadONOff_Read();
jbradshaw 0:e4a10ed6eb92 1333 }
jbradshaw 0:e4a10ed6eb92 1334
jbradshaw 1:9490836294ea 1335 if (global_status.bit.lonint == 1) ///< ECG Lead ON test: i.e. the leads are touching the body...
jbradshaw 0:e4a10ed6eb92 1336 {
jbradshaw 0:e4a10ed6eb92 1337
jbradshaw 1:9490836294ea 1338 FIFO_LeadONOff_Read();
jbradshaw 0:e4a10ed6eb92 1339 }
jbradshaw 0:e4a10ed6eb92 1340
jbradshaw 0:e4a10ed6eb92 1341 return return_value;
jbradshaw 0:e4a10ed6eb92 1342 }
jbradshaw 0:e4a10ed6eb92 1343
jbradshaw 1:9490836294ea 1344
jbradshaw 1:9490836294ea 1345 event_callback_t MAX30001::functionpointer;
jbradshaw 1:9490836294ea 1346
jbradshaw 0:e4a10ed6eb92 1347
jbradshaw 1:9490836294ea 1348 volatile int MAX30001::xferFlag = 0;
jbradshaw 0:e4a10ed6eb92 1349
jbradshaw 1:9490836294ea 1350
jbradshaw 1:9490836294ea 1351 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 1352 int MAX30001::SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size, uint8_t *rx_buf, uint32_t rx_size) {
jbradshaw 0:e4a10ed6eb92 1353 xferFlag = 0;
jbradshaw 1:9490836294ea 1354 unsigned int i;
jbradshaw 0:e4a10ed6eb92 1355 for (i = 0; i < sizeof(buffer); i++) {
jbradshaw 1:9490836294ea 1356 if (i < tx_size) {
jbradshaw 0:e4a10ed6eb92 1357 buffer[i] = tx_buf[i];
jbradshaw 1:9490836294ea 1358 }
jbradshaw 1:9490836294ea 1359 else {
jbradshaw 0:e4a10ed6eb92 1360 buffer[i] = 0xFF;
jbradshaw 1:9490836294ea 1361 }
jbradshaw 0:e4a10ed6eb92 1362 }
jbradshaw 1:9490836294ea 1363 spi->transfer<uint8_t>(buffer, (int)rx_size, rx_buf, (int)rx_size, spiHandler);
jbradshaw 0:e4a10ed6eb92 1364 while (xferFlag == 0);
jbradshaw 0:e4a10ed6eb92 1365 return 0;
jbradshaw 0:e4a10ed6eb92 1366 }
jbradshaw 0:e4a10ed6eb92 1367
jbradshaw 0:e4a10ed6eb92 1368 //******************************************************************************
jbradshaw 1:9490836294ea 1369 void MAX30001::ReadHeartrateData(max30001_bledata_t *_hspValMax30001) {
jbradshaw 0:e4a10ed6eb92 1370 _hspValMax30001->R2R = hspValMax30001.R2R;
jbradshaw 0:e4a10ed6eb92 1371 _hspValMax30001->fmstr = hspValMax30001.fmstr;
jbradshaw 0:e4a10ed6eb92 1372 }
jbradshaw 0:e4a10ed6eb92 1373
jbradshaw 0:e4a10ed6eb92 1374 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 1375 void MAX30001::onDataAvailable(PtrFunction _onDataAvailable) {
jbradshaw 0:e4a10ed6eb92 1376 onDataAvailableCallback = _onDataAvailable;
jbradshaw 0:e4a10ed6eb92 1377 }
jbradshaw 0:e4a10ed6eb92 1378
jbradshaw 1:9490836294ea 1379 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 1380 void MAX30001::dataAvailable(uint32_t id, uint32_t *buffer, uint32_t length) {
jbradshaw 0:e4a10ed6eb92 1381 if (onDataAvailableCallback != NULL) {
jbradshaw 0:e4a10ed6eb92 1382 (*onDataAvailableCallback)(id, buffer, length);
jbradshaw 0:e4a10ed6eb92 1383 }
jbradshaw 0:e4a10ed6eb92 1384 }
jbradshaw 0:e4a10ed6eb92 1385
jbradshaw 1:9490836294ea 1386 //******************************************************************************
jbradshaw 1:9490836294ea 1387 void MAX30001::spiHandler(int events) {
jbradshaw 1:9490836294ea 1388 xferFlag = 1;
jbradshaw 1:9490836294ea 1389 }
jbradshaw 0:e4a10ed6eb92 1390
jbradshaw 0:e4a10ed6eb92 1391 //******************************************************************************
jbradshaw 0:e4a10ed6eb92 1392 static int allowInterrupts = 0;
jbradshaw 0:e4a10ed6eb92 1393
jbradshaw 1:9490836294ea 1394 void MAX30001::Mid_IntB_Handler(void) {
jbradshaw 1:9490836294ea 1395 if (allowInterrupts == 0) {
jbradshaw 1:9490836294ea 1396 return;
jbradshaw 1:9490836294ea 1397 }
jbradshaw 1:9490836294ea 1398 MAX30001::instance->int_handler();
jbradshaw 0:e4a10ed6eb92 1399 }
jbradshaw 0:e4a10ed6eb92 1400
jbradshaw 1:9490836294ea 1401 void MAX30001::Mid_Int2B_Handler(void) {
jbradshaw 1:9490836294ea 1402 if (allowInterrupts == 0) {
jbradshaw 1:9490836294ea 1403 return;
jbradshaw 1:9490836294ea 1404 }
jbradshaw 1:9490836294ea 1405 MAX30001::instance->int_handler();
jbradshaw 0:e4a10ed6eb92 1406 }
jbradshaw 0:e4a10ed6eb92 1407
jbradshaw 1:9490836294ea 1408 void MAX30001::AllowInterrupts(int state) {
jbradshaw 0:e4a10ed6eb92 1409 allowInterrupts = state;
jbradshaw 0:e4a10ed6eb92 1410 }