Maxim Integrated / OneWire

1-Wire® library for mbed. Complete 1-Wire library that supports our silicon masters along with a bit-bang master on the MAX32600MBED platform with one common interface for mbed. Slave support has also been included and more slaves will be added as time permits.

Dependents:   MAXREFDES131_Qt_Demo MAX32630FTHR_iButton_uSD_Logger MAX32630FTHR_DS18B20_uSD_Logger MAXREFDES130_131_Demo ... more

Superseded by MaximInterface.

OneWire_Masters/DS248x/ds248x.cpp@26:a361e3f42ba5, 2016-03-23 (annotated)

Committer:
IanBenzMaxim
Date:
Wed Mar 23 15:25:40 2016 -0500
Revision:
26:a361e3f42ba5
Parent:
23:e8e403d61359
Child:
27:d5aaefa252f1
Rework the OneWireMaster virtual interface for simplicity.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 1:91e52f8ab8bf 1 /******************************************************************//**
j3 1:91e52f8ab8bf 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 1:91e52f8ab8bf 3 *
j3 1:91e52f8ab8bf 4 * Permission is hereby granted, free of charge, to any person obtaining a
j3 1:91e52f8ab8bf 5 * copy of this software and associated documentation files (the "Software"),
j3 1:91e52f8ab8bf 6 * to deal in the Software without restriction, including without limitation
j3 1:91e52f8ab8bf 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 1:91e52f8ab8bf 8 * and/or sell copies of the Software, and to permit persons to whom the
j3 1:91e52f8ab8bf 9 * Software is furnished to do so, subject to the following conditions:
j3 1:91e52f8ab8bf 10 *
j3 1:91e52f8ab8bf 11 * The above copyright notice and this permission notice shall be included
j3 1:91e52f8ab8bf 12 * in all copies or substantial portions of the Software.
j3 1:91e52f8ab8bf 13 *
j3 1:91e52f8ab8bf 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 1:91e52f8ab8bf 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 1:91e52f8ab8bf 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 1:91e52f8ab8bf 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 1:91e52f8ab8bf 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 1:91e52f8ab8bf 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 1:91e52f8ab8bf 20 * OTHER DEALINGS IN THE SOFTWARE.
j3 1:91e52f8ab8bf 21 *
j3 1:91e52f8ab8bf 22 * Except as contained in this notice, the name of Maxim Integrated
j3 1:91e52f8ab8bf 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 1:91e52f8ab8bf 24 * Products, Inc. Branding Policy.
j3 1:91e52f8ab8bf 25 *
j3 1:91e52f8ab8bf 26 * The mere transfer of this software does not imply any licenses
j3 1:91e52f8ab8bf 27 * of trade secrets, proprietary technology, copyrights, patents,
j3 1:91e52f8ab8bf 28 * trademarks, maskwork rights, or any other form of intellectual
j3 1:91e52f8ab8bf 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 1:91e52f8ab8bf 30 * ownership rights.
j3 1:91e52f8ab8bf 31 **********************************************************************/
j3 1:91e52f8ab8bf 32
j3 1:91e52f8ab8bf 33
j3 1:91e52f8ab8bf 34 #include "ds248x.h"
j3 1:91e52f8ab8bf 35
j3 1:91e52f8ab8bf 36
j3 1:91e52f8ab8bf 37 //*********************************************************************
j3 5:ce108eeb878d 38 Ds248x::Ds248x(I2C &i2c_bus, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 39 :_p_i2c_bus(&i2c_bus), _i2c_owner(false)
j3 1:91e52f8ab8bf 40 {
j3 6:1faafa0b3cd7 41 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 42 }
j3 1:91e52f8ab8bf 43
j3 1:91e52f8ab8bf 44
j3 1:91e52f8ab8bf 45 //*********************************************************************
j3 5:ce108eeb878d 46 Ds248x::Ds248x(PinName sda, PinName scl, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 47 :_p_i2c_bus(new I2C(sda, scl)), _i2c_owner(true)
j3 1:91e52f8ab8bf 48 {
j3 6:1faafa0b3cd7 49 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 50 }
j3 1:91e52f8ab8bf 51
j3 1:91e52f8ab8bf 52
j3 1:91e52f8ab8bf 53 //*********************************************************************
j3 1:91e52f8ab8bf 54 Ds248x::~Ds248x()
j3 1:91e52f8ab8bf 55 {
j3 5:ce108eeb878d 56 if(_i2c_owner)
j3 1:91e52f8ab8bf 57 {
j3 1:91e52f8ab8bf 58 delete _p_i2c_bus;
j3 1:91e52f8ab8bf 59 }
j3 1:91e52f8ab8bf 60 }
j3 1:91e52f8ab8bf 61
j3 1:91e52f8ab8bf 62
j3 1:91e52f8ab8bf 63 //*********************************************************************
j3 23:e8e403d61359 64 OneWireMaster::CmdResult Ds248x::OWInitMaster(void)
j3 14:7b2886a50321 65 {
j3 14:7b2886a50321 66 return(detect());
j3 14:7b2886a50321 67 }
j3 14:7b2886a50321 68
j3 14:7b2886a50321 69
j3 14:7b2886a50321 70 //*********************************************************************
j3 23:e8e403d61359 71 OneWireMaster::CmdResult Ds248x::detect(void)
j3 2:02d228c25fd4 72 {
j3 23:e8e403d61359 73 OneWireMaster::CmdResult result;
j3 2:02d228c25fd4 74
j3 2:02d228c25fd4 75 // reset the ds2484 ON selected address
j3 17:b646b1e3970b 76 result = reset();
j3 23:e8e403d61359 77 if(result == OneWireMaster::Success)
j3 2:02d228c25fd4 78 {
j3 2:02d228c25fd4 79 // default configuration
j3 17:b646b1e3970b 80 _c1WS = 0;
j3 17:b646b1e3970b 81 _cSPU = 0;
j3 17:b646b1e3970b 82 _cPDN = 0;
j3 17:b646b1e3970b 83 _cAPU = 0;
j3 2:02d228c25fd4 84
j3 17:b646b1e3970b 85 result = write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 2:02d228c25fd4 86 }
j3 2:02d228c25fd4 87
j3 17:b646b1e3970b 88 return result;
j3 2:02d228c25fd4 89 }
j3 2:02d228c25fd4 90
j3 2:02d228c25fd4 91
j3 2:02d228c25fd4 92 //*********************************************************************
j3 23:e8e403d61359 93 OneWireMaster::CmdResult Ds248x::reset(void)
j3 1:91e52f8ab8bf 94 {
j3 23:e8e403d61359 95 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 96
j3 2:02d228c25fd4 97 char status;
j3 2:02d228c25fd4 98 char packet[] = {CMD_DRST};
j3 2:02d228c25fd4 99
j3 2:02d228c25fd4 100 // Device Reset
j3 2:02d228c25fd4 101 // S AD,0 [A] DRST [A] Sr AD,1 [A] [SS] A\ P
j3 2:02d228c25fd4 102 // [] indicates from slave
j3 2:02d228c25fd4 103 // SS status byte to read to verify state
j3 2:02d228c25fd4 104
j3 17:b646b1e3970b 105 if(_p_i2c_bus->write(_w_adrs, packet, 1) != I2C_WRITE_OK)
j3 17:b646b1e3970b 106 {
j3 23:e8e403d61359 107 result = OneWireMaster::CommunicationWriteError;
j3 17:b646b1e3970b 108 }
j3 17:b646b1e3970b 109 else
j3 17:b646b1e3970b 110 {
j3 17:b646b1e3970b 111 if(_p_i2c_bus->read(_r_adrs, &status, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 112 {
j3 23:e8e403d61359 113 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 114 }
j3 17:b646b1e3970b 115 else
j3 17:b646b1e3970b 116 {
j3 17:b646b1e3970b 117 if((status & 0xF7) == 0x10)
j3 17:b646b1e3970b 118 {
j3 23:e8e403d61359 119 result = OneWireMaster::Success;
j3 17:b646b1e3970b 120 }
j3 17:b646b1e3970b 121 else
j3 17:b646b1e3970b 122 {
j3 23:e8e403d61359 123 result = OneWireMaster::OperationFailure;
j3 17:b646b1e3970b 124 }
j3 17:b646b1e3970b 125 }
j3 17:b646b1e3970b 126 }
j3 2:02d228c25fd4 127
j3 17:b646b1e3970b 128 return result;
j3 2:02d228c25fd4 129 }
j3 2:02d228c25fd4 130
j3 2:02d228c25fd4 131
j3 2:02d228c25fd4 132 //*********************************************************************
j3 23:e8e403d61359 133 OneWireMaster::CmdResult Ds248x::write_config(uint8_t config)
j3 2:02d228c25fd4 134 {
j3 23:e8e403d61359 135 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 136
j3 2:02d228c25fd4 137 char read_config;
j3 2:02d228c25fd4 138 char packet [] = {CMD_WCFG, (config | (~config << 4))};
j3 2:02d228c25fd4 139
j3 17:b646b1e3970b 140 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 2:02d228c25fd4 141 {
j3 23:e8e403d61359 142 result = OneWireMaster::CommunicationWriteError;
j3 2:02d228c25fd4 143 }
j3 2:02d228c25fd4 144 else
j3 2:02d228c25fd4 145 {
j3 17:b646b1e3970b 146 if(_p_i2c_bus->read(_r_adrs, &read_config, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 147 {
j3 23:e8e403d61359 148 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 149 }
j3 17:b646b1e3970b 150 else
j3 17:b646b1e3970b 151 {
j3 17:b646b1e3970b 152 // check for failure due to incorrect read back
j3 17:b646b1e3970b 153 if (config != read_config)
j3 17:b646b1e3970b 154 {
j3 17:b646b1e3970b 155 reset();
j3 23:e8e403d61359 156 result = OneWireMaster::OperationFailure;
j3 17:b646b1e3970b 157 }
j3 17:b646b1e3970b 158 else
j3 17:b646b1e3970b 159 {
j3 23:e8e403d61359 160 result = OneWireMaster::Success;
j3 17:b646b1e3970b 161 }
j3 17:b646b1e3970b 162 }
j3 2:02d228c25fd4 163 }
j3 2:02d228c25fd4 164
j3 17:b646b1e3970b 165 return result;
j3 1:91e52f8ab8bf 166 }
j3 1:91e52f8ab8bf 167
j3 1:91e52f8ab8bf 168
j3 1:91e52f8ab8bf 169 //*********************************************************************
j3 23:e8e403d61359 170 OneWireMaster::CmdResult Ds248x::channel_select(uint8_t channel)
j3 1:91e52f8ab8bf 171 {
j3 23:e8e403d61359 172 OneWireMaster::CmdResult result;
j3 2:02d228c25fd4 173
j3 2:02d228c25fd4 174 char ch, ch_read, check;
j3 2:02d228c25fd4 175 char packet [2];
j3 2:02d228c25fd4 176
j3 2:02d228c25fd4 177 packet[0] = CMD_CHSL;
j3 2:02d228c25fd4 178
j3 2:02d228c25fd4 179 // Channel Select (Case A)
j3 2:02d228c25fd4 180 // S AD,0 [A] CHSL [A] CC [A] Sr AD,1 [A] [RR] A\ P
j3 2:02d228c25fd4 181 // [] indicates from slave
j3 2:02d228c25fd4 182 // CC channel value
j3 2:02d228c25fd4 183 // RR channel read back
j3 2:02d228c25fd4 184
j3 2:02d228c25fd4 185 switch (channel)
j3 2:02d228c25fd4 186 {
j3 2:02d228c25fd4 187 default: case 0: ch = 0xF0; ch_read = 0xB8; break;
j3 2:02d228c25fd4 188 case 1: ch = 0xE1; ch_read = 0xB1; break;
j3 2:02d228c25fd4 189 case 2: ch = 0xD2; ch_read = 0xAA; break;
j3 2:02d228c25fd4 190 case 3: ch = 0xC3; ch_read = 0xA3; break;
j3 2:02d228c25fd4 191 case 4: ch = 0xB4; ch_read = 0x9C; break;
j3 2:02d228c25fd4 192 case 5: ch = 0xA5; ch_read = 0x95; break;
j3 2:02d228c25fd4 193 case 6: ch = 0x96; ch_read = 0x8E; break;
j3 2:02d228c25fd4 194 case 7: ch = 0x87; ch_read = 0x87; break;
j3 2:02d228c25fd4 195 };
j3 2:02d228c25fd4 196
j3 2:02d228c25fd4 197 packet[1] = ch;
j3 2:02d228c25fd4 198
j3 17:b646b1e3970b 199 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 17:b646b1e3970b 200 {
j3 23:e8e403d61359 201 result = OneWireMaster::CommunicationWriteError;
j3 17:b646b1e3970b 202 }
j3 17:b646b1e3970b 203 else
j3 17:b646b1e3970b 204 {
j3 17:b646b1e3970b 205 if(_p_i2c_bus->read(_r_adrs, &check, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 206 {
j3 23:e8e403d61359 207 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 208 }
j3 17:b646b1e3970b 209 else
j3 17:b646b1e3970b 210 {
j3 17:b646b1e3970b 211 // check for failure due to incorrect read back of channel
j3 17:b646b1e3970b 212 if (check == ch_read)
j3 17:b646b1e3970b 213 {
j3 23:e8e403d61359 214 result = OneWireMaster::Success;
j3 17:b646b1e3970b 215 }
j3 17:b646b1e3970b 216 else
j3 17:b646b1e3970b 217 {
j3 23:e8e403d61359 218 result = OneWireMaster::OperationFailure;
j3 17:b646b1e3970b 219 }
j3 17:b646b1e3970b 220 }
j3 17:b646b1e3970b 221 }
j3 2:02d228c25fd4 222
j3 17:b646b1e3970b 223 return result;
j3 2:02d228c25fd4 224 }
j3 2:02d228c25fd4 225
j3 2:02d228c25fd4 226
j3 2:02d228c25fd4 227 //*********************************************************************
j3 23:e8e403d61359 228 OneWireMaster::CmdResult Ds248x::adjust_timing(uint8_t param, uint8_t val)
j3 2:02d228c25fd4 229 {
j3 23:e8e403d61359 230 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 231
j3 2:02d228c25fd4 232 char read_port_config;
j3 2:02d228c25fd4 233 char control_byte;
j3 2:02d228c25fd4 234
j3 2:02d228c25fd4 235 control_byte = (((param & 0x0F) << 4) | (val & 0x0F));
j3 2:02d228c25fd4 236
j3 2:02d228c25fd4 237 char packet [] = {CMD_A1WP, control_byte};
j3 2:02d228c25fd4 238
j3 17:b646b1e3970b 239 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 17:b646b1e3970b 240 {
j3 23:e8e403d61359 241 result = OneWireMaster::CommunicationWriteError;
j3 17:b646b1e3970b 242 }
j3 17:b646b1e3970b 243 else
j3 2:02d228c25fd4 244 {
j3 17:b646b1e3970b 245 if(_p_i2c_bus->read(_r_adrs, &read_port_config, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 246 {
j3 23:e8e403d61359 247 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 248 }
j3 17:b646b1e3970b 249 else
j3 17:b646b1e3970b 250 {
j3 17:b646b1e3970b 251 // check for failure due to incorrect read back
j3 17:b646b1e3970b 252 if ((control_byte & 0x0F) != read_port_config)
j3 17:b646b1e3970b 253 {
j3 23:e8e403d61359 254 result = OneWireMaster::OperationFailure;
j3 17:b646b1e3970b 255 reset();
j3 17:b646b1e3970b 256 }
j3 17:b646b1e3970b 257 else
j3 17:b646b1e3970b 258 {
j3 23:e8e403d61359 259 result = OneWireMaster::Success;
j3 17:b646b1e3970b 260 }
j3 17:b646b1e3970b 261 }
j3 2:02d228c25fd4 262 }
j3 17:b646b1e3970b 263
j3 17:b646b1e3970b 264 return result;
j3 1:91e52f8ab8bf 265 }
j3 1:91e52f8ab8bf 266
j3 1:91e52f8ab8bf 267
j3 1:91e52f8ab8bf 268 //*********************************************************************
j3 23:e8e403d61359 269 OneWireMaster::CmdResult Ds248x::search_triplet(uint8_t search_direction, uint8_t & status)
j3 1:91e52f8ab8bf 270 {
j3 23:e8e403d61359 271 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 272
j3 2:02d228c25fd4 273 uint8_t poll_count = 0;
j3 2:02d228c25fd4 274 char packet [] = {CMD_1WT, search_direction ? 0x80 : 0x00};
j3 17:b646b1e3970b 275 char read_data;
j3 2:02d228c25fd4 276
j3 2:02d228c25fd4 277 // 1-Wire Triplet (Case B)
j3 2:02d228c25fd4 278 // S AD,0 [A] 1WT [A] SS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 279 // \--------/
j3 2:02d228c25fd4 280 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 281 // [] indicates from slave
j3 2:02d228c25fd4 282 // SS indicates byte containing search direction bit value in msbit
j3 2:02d228c25fd4 283
j3 17:b646b1e3970b 284 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 2:02d228c25fd4 285 {
j3 23:e8e403d61359 286 result = OneWireMaster::CommunicationWriteError;
j3 2:02d228c25fd4 287 }
j3 2:02d228c25fd4 288 else
j3 2:02d228c25fd4 289 {
j3 17:b646b1e3970b 290 // loop checking 1WB bit for completion of 1-Wire operation
j3 17:b646b1e3970b 291 // abort if poll limit reached
j3 17:b646b1e3970b 292
j3 17:b646b1e3970b 293 //dummy write for loop
j3 23:e8e403d61359 294 result = OneWireMaster::Success; //so far
j3 17:b646b1e3970b 295 do
j3 17:b646b1e3970b 296 {
j3 17:b646b1e3970b 297 if(_p_i2c_bus->read(_r_adrs, &read_data, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 298 {
j3 23:e8e403d61359 299 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 300 }
j3 17:b646b1e3970b 301 }
j3 23:e8e403d61359 302 while ((read_data & STATUS_1WB) && (poll_count++ < POLL_LIMIT) && (result != OneWireMaster::CommunicationReadError));
j3 17:b646b1e3970b 303
j3 23:e8e403d61359 304 if((result == OneWireMaster::CommunicationReadError) || (poll_count >= POLL_LIMIT))
j3 17:b646b1e3970b 305 {
j3 17:b646b1e3970b 306 // check for failure due to poll limit reached
j3 17:b646b1e3970b 307 if(poll_count >= POLL_LIMIT)
j3 17:b646b1e3970b 308 {
j3 17:b646b1e3970b 309 // handle error
j3 17:b646b1e3970b 310 // ...
j3 17:b646b1e3970b 311 reset();
j3 23:e8e403d61359 312 result = OneWireMaster::TimeoutError;
j3 17:b646b1e3970b 313 }
j3 17:b646b1e3970b 314 }
j3 17:b646b1e3970b 315 else
j3 17:b646b1e3970b 316 {
j3 17:b646b1e3970b 317 status = read_data;
j3 23:e8e403d61359 318 result = OneWireMaster::Success;
j3 17:b646b1e3970b 319 }
j3 2:02d228c25fd4 320 }
j3 17:b646b1e3970b 321
j3 17:b646b1e3970b 322 return result;
j3 1:91e52f8ab8bf 323 }
j3 1:91e52f8ab8bf 324
j3 1:91e52f8ab8bf 325
j3 1:91e52f8ab8bf 326 //*********************************************************************
j3 23:e8e403d61359 327 OneWireMaster::CmdResult Ds248x::OWReset(void)
j3 2:02d228c25fd4 328 {
j3 23:e8e403d61359 329 OneWireMaster::CmdResult result;
j3 2:02d228c25fd4 330
j3 2:02d228c25fd4 331 uint8_t poll_count = 0;
j3 2:02d228c25fd4 332 char status;
j3 2:02d228c25fd4 333 char packet [] = {CMD_1WRS};
j3 1:91e52f8ab8bf 334
j3 2:02d228c25fd4 335 // 1-Wire reset (Case B)
j3 2:02d228c25fd4 336 // S AD,0 [A] 1WRS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 337 // \--------/
j3 2:02d228c25fd4 338 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 339 // [] indicates from slave
j3 2:02d228c25fd4 340
j3 17:b646b1e3970b 341 if(_p_i2c_bus->write(_w_adrs, packet, 1) != I2C_WRITE_OK)
j3 2:02d228c25fd4 342 {
j3 23:e8e403d61359 343 result = OneWireMaster::CommunicationWriteError;
j3 2:02d228c25fd4 344 }
j3 2:02d228c25fd4 345 else
j3 2:02d228c25fd4 346 {
j3 17:b646b1e3970b 347 // loop checking 1WB bit for completion of 1-Wire operation
j3 17:b646b1e3970b 348 // abort if poll limit reached
j3 17:b646b1e3970b 349 //dummy write for loop
j3 23:e8e403d61359 350 result = OneWireMaster::Success; //so far
j3 17:b646b1e3970b 351 do
j3 2:02d228c25fd4 352 {
j3 17:b646b1e3970b 353 if(_p_i2c_bus->read(_r_adrs, &status, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 354 {
j3 23:e8e403d61359 355 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 356 }
j3 17:b646b1e3970b 357 }
j3 23:e8e403d61359 358 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT) && (result != OneWireMaster::CommunicationReadError));
j3 17:b646b1e3970b 359
j3 23:e8e403d61359 360 if((result == OneWireMaster::CommunicationReadError) || (poll_count >= POLL_LIMIT))
j3 17:b646b1e3970b 361 {
j3 17:b646b1e3970b 362 // check for failure due to poll limit reached
j3 17:b646b1e3970b 363 if(poll_count >= POLL_LIMIT)
j3 17:b646b1e3970b 364 {
j3 17:b646b1e3970b 365 // handle error
j3 17:b646b1e3970b 366 // ...
j3 17:b646b1e3970b 367 reset();
j3 23:e8e403d61359 368 result = OneWireMaster::TimeoutError;
j3 17:b646b1e3970b 369 }
j3 2:02d228c25fd4 370 }
j3 2:02d228c25fd4 371 else
j3 2:02d228c25fd4 372 {
j3 17:b646b1e3970b 373 // check for short condition
j3 17:b646b1e3970b 374 if (status & STATUS_SD)
j3 17:b646b1e3970b 375 {
j3 17:b646b1e3970b 376 _short_detected = true;
j3 17:b646b1e3970b 377 }
j3 17:b646b1e3970b 378 else
j3 17:b646b1e3970b 379 {
j3 17:b646b1e3970b 380 _short_detected = false;
j3 17:b646b1e3970b 381 }
j3 17:b646b1e3970b 382
j3 17:b646b1e3970b 383 // check for presence detect
j3 17:b646b1e3970b 384 if (status & STATUS_PPD)
j3 17:b646b1e3970b 385 {
j3 23:e8e403d61359 386 result = OneWireMaster::Success;
j3 17:b646b1e3970b 387 }
j3 17:b646b1e3970b 388 else
j3 17:b646b1e3970b 389 {
j3 23:e8e403d61359 390 result = OneWireMaster::OperationFailure;
j3 17:b646b1e3970b 391 }
j3 2:02d228c25fd4 392 }
j3 2:02d228c25fd4 393 }
j3 17:b646b1e3970b 394
j3 17:b646b1e3970b 395 return result;
j3 1:91e52f8ab8bf 396 }
j3 1:91e52f8ab8bf 397
j3 1:91e52f8ab8bf 398
j3 1:91e52f8ab8bf 399 //*********************************************************************
IanBenzMaxim 26:a361e3f42ba5 400 OneWireMaster::CmdResult Ds248x::OWTouchBit(uint8_t & sendrecvbit, OW_LEVEL after_level)
j3 1:91e52f8ab8bf 401 {
j3 23:e8e403d61359 402 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 403
IanBenzMaxim 26:a361e3f42ba5 404 result = ConfigureSPU(after_level == LEVEL_STRONG);
IanBenzMaxim 26:a361e3f42ba5 405 if (result != OneWireMaster::Success)
IanBenzMaxim 26:a361e3f42ba5 406 return result;
IanBenzMaxim 26:a361e3f42ba5 407
j3 2:02d228c25fd4 408 uint8_t poll_count = 0;
j3 2:02d228c25fd4 409 char status;
j3 17:b646b1e3970b 410 char packet[] = {CMD_1WSB, sendrecvbit ? 0x80 : 0x00};
j3 2:02d228c25fd4 411
j3 2:02d228c25fd4 412 // 1-Wire bit (Case B)
j3 2:02d228c25fd4 413 // S AD,0 [A] 1WSB [A] BB [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 414 // \--------/
j3 2:02d228c25fd4 415 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 416 // [] indicates from slave
j3 2:02d228c25fd4 417 // BB indicates byte containing bit value in msbit
j3 2:02d228c25fd4 418
j3 17:b646b1e3970b 419 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 2:02d228c25fd4 420 {
j3 23:e8e403d61359 421 result = OneWireMaster::CommunicationWriteError;
j3 2:02d228c25fd4 422 }
j3 2:02d228c25fd4 423 else
j3 2:02d228c25fd4 424 {
j3 17:b646b1e3970b 425 // loop checking 1WB bit for completion of 1-Wire operation
j3 17:b646b1e3970b 426 // abort if poll limit reached
j3 17:b646b1e3970b 427 //dummy write for loop
j3 23:e8e403d61359 428 result = OneWireMaster::Success; //so far
j3 17:b646b1e3970b 429 do
j3 2:02d228c25fd4 430 {
j3 17:b646b1e3970b 431 if(_p_i2c_bus->read(_r_adrs, &status, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 432 {
j3 23:e8e403d61359 433 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 434 }
j3 17:b646b1e3970b 435 }
j3 23:e8e403d61359 436 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT) && (result != OneWireMaster::CommunicationReadError));
j3 17:b646b1e3970b 437
j3 23:e8e403d61359 438 if((result == OneWireMaster::CommunicationReadError) || (poll_count >= POLL_LIMIT))
j3 17:b646b1e3970b 439 {
j3 17:b646b1e3970b 440 // check for failure due to poll limit reached
j3 17:b646b1e3970b 441 if (poll_count >= POLL_LIMIT)
j3 17:b646b1e3970b 442 {
j3 17:b646b1e3970b 443 // handle error
j3 17:b646b1e3970b 444 // ...
j3 17:b646b1e3970b 445 reset();
j3 23:e8e403d61359 446 result = OneWireMaster::TimeoutError;
j3 17:b646b1e3970b 447 }
j3 2:02d228c25fd4 448 }
j3 2:02d228c25fd4 449 else
j3 2:02d228c25fd4 450 {
j3 17:b646b1e3970b 451 // return bit state through out param
j3 17:b646b1e3970b 452 if (status & STATUS_SBR)
j3 17:b646b1e3970b 453 {
j3 17:b646b1e3970b 454 sendrecvbit = 1;
j3 17:b646b1e3970b 455
j3 17:b646b1e3970b 456 }
j3 17:b646b1e3970b 457 else
j3 17:b646b1e3970b 458 {
j3 17:b646b1e3970b 459 sendrecvbit = 0;
j3 17:b646b1e3970b 460 }
j3 23:e8e403d61359 461 result = OneWireMaster::Success;
j3 2:02d228c25fd4 462 }
j3 2:02d228c25fd4 463 }
j3 17:b646b1e3970b 464
j3 17:b646b1e3970b 465 return result;
j3 1:91e52f8ab8bf 466 }
j3 1:91e52f8ab8bf 467
j3 1:91e52f8ab8bf 468
j3 1:91e52f8ab8bf 469 //*********************************************************************
IanBenzMaxim 26:a361e3f42ba5 470 OneWireMaster::CmdResult Ds248x::OWWriteByte(uint8_t sendbyte, OW_LEVEL after_level)
j3 1:91e52f8ab8bf 471 {
j3 23:e8e403d61359 472 OneWireMaster::CmdResult result;
j3 1:91e52f8ab8bf 473
IanBenzMaxim 26:a361e3f42ba5 474 result = ConfigureSPU(after_level == LEVEL_STRONG);
IanBenzMaxim 26:a361e3f42ba5 475 if (result != OneWireMaster::Success)
IanBenzMaxim 26:a361e3f42ba5 476 return result;
IanBenzMaxim 26:a361e3f42ba5 477
j3 2:02d228c25fd4 478 uint8_t poll_count = 0;
j3 2:02d228c25fd4 479 char status;
j3 2:02d228c25fd4 480 char packet [] = {CMD_1WWB, sendbyte};
j3 2:02d228c25fd4 481
j3 2:02d228c25fd4 482 // 1-Wire Write Byte (Case B)
j3 2:02d228c25fd4 483 // S AD,0 [A] 1WWB [A] DD [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 484 // \--------/
j3 2:02d228c25fd4 485 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 486 // [] indicates from slave
j3 2:02d228c25fd4 487 // DD data to write
j3 2:02d228c25fd4 488
j3 17:b646b1e3970b 489 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 2:02d228c25fd4 490 {
j3 23:e8e403d61359 491 result = OneWireMaster::CommunicationWriteError;
j3 2:02d228c25fd4 492 }
j3 2:02d228c25fd4 493 else
j3 2:02d228c25fd4 494 {
j3 17:b646b1e3970b 495 // loop checking 1WB bit for completion of 1-Wire operation
j3 17:b646b1e3970b 496 // abort if poll limit reached
j3 17:b646b1e3970b 497 //dummy write for loop
j3 23:e8e403d61359 498 result = OneWireMaster::Success; //so far
j3 17:b646b1e3970b 499 do
j3 17:b646b1e3970b 500 {
j3 17:b646b1e3970b 501 if(_p_i2c_bus->read(_r_adrs, &status, 1) != I2C_READ_OK)
j3 17:b646b1e3970b 502 {
j3 23:e8e403d61359 503 result = OneWireMaster::CommunicationReadError;
j3 17:b646b1e3970b 504 }
j3 17:b646b1e3970b 505 }
j3 23:e8e403d61359 506 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT) && (result != OneWireMaster::CommunicationReadError));
j3 17:b646b1e3970b 507
j3 23:e8e403d61359 508 if((result == OneWireMaster::CommunicationReadError) || (poll_count >= POLL_LIMIT))
j3 17:b646b1e3970b 509 {
j3 17:b646b1e3970b 510 // check for failure due to poll limit reached
j3 17:b646b1e3970b 511 if (poll_count >= POLL_LIMIT)
j3 17:b646b1e3970b 512 {
j3 17:b646b1e3970b 513 // handle error
j3 17:b646b1e3970b 514 // ...
j3 17:b646b1e3970b 515 reset();
j3 23:e8e403d61359 516 result = OneWireMaster::TimeoutError;
j3 17:b646b1e3970b 517 }
j3 17:b646b1e3970b 518 }
j3 17:b646b1e3970b 519 else
j3 17:b646b1e3970b 520 {
j3 23:e8e403d61359 521 result = OneWireMaster::Success;
j3 17:b646b1e3970b 522 }
j3 2:02d228c25fd4 523 }
j3 2:02d228c25fd4 524
j3 17:b646b1e3970b 525 return result;
j3 1:91e52f8ab8bf 526 }
j3 1:91e52f8ab8bf 527
j3 1:91e52f8ab8bf 528
j3 1:91e52f8ab8bf 529 //*********************************************************************
IanBenzMaxim 26:a361e3f42ba5 530 OneWireMaster::CmdResult Ds248x::OWReadByte(uint8_t & recvbyte, OW_LEVEL after_level)
j3 1:91e52f8ab8bf 531 {
j3 23:e8e403d61359 532 OneWireMaster::CmdResult result;
j3 2:02d228c25fd4 533
IanBenzMaxim 26:a361e3f42ba5 534 if (after_level == LEVEL_STRONG) // Enabling strong pull-up after a Read Byte command is not supported natively by the DS248x
j3 2:02d228c25fd4 535 {
IanBenzMaxim 26:a361e3f42ba5 536 uint8_t recvbit;
IanBenzMaxim 26:a361e3f42ba5 537 recvbyte = 0;
IanBenzMaxim 26:a361e3f42ba5 538
IanBenzMaxim 26:a361e3f42ba5 539 for (unsigned int i = 1; i <= 8; i++)
IanBenzMaxim 26:a361e3f42ba5 540 {
IanBenzMaxim 26:a361e3f42ba5 541 // Set strong pull-up on last bit
IanBenzMaxim 26:a361e3f42ba5 542 result = OWReadBit(recvbit, (i == 8 ? LEVEL_STRONG : LEVEL_NORMAL));
IanBenzMaxim 26:a361e3f42ba5 543 if (result != Success)
IanBenzMaxim 26:a361e3f42ba5 544 break;
IanBenzMaxim 26:a361e3f42ba5 545 recvbyte = (recvbyte << 1) | recvbit;
IanBenzMaxim 26:a361e3f42ba5 546 }
j3 2:02d228c25fd4 547 }
j3 2:02d228c25fd4 548 else
j3 2:02d228c25fd4 549 {
IanBenzMaxim 26:a361e3f42ba5 550 uint8_t poll_count = 0;
IanBenzMaxim 26:a361e3f42ba5 551 char data, status;
IanBenzMaxim 26:a361e3f42ba5 552 char packet[2] = {CMD_1WRB, 0};
IanBenzMaxim 26:a361e3f42ba5 553
IanBenzMaxim 26:a361e3f42ba5 554 // 1-Wire Read Bytes (Case C)
IanBenzMaxim 26:a361e3f42ba5 555 // S AD,0 [A] 1WRB [A] Sr AD,1 [A] [Status] A [Status] A\
IanBenzMaxim 26:a361e3f42ba5 556 // \--------/
IanBenzMaxim 26:a361e3f42ba5 557 // Repeat until 1WB bit has changed to 0
IanBenzMaxim 26:a361e3f42ba5 558 // Sr AD,0 [A] SRP [A] E1 [A] Sr AD,1 [A] DD A\ P
IanBenzMaxim 26:a361e3f42ba5 559 //
IanBenzMaxim 26:a361e3f42ba5 560 // [] indicates from slave
IanBenzMaxim 26:a361e3f42ba5 561 // DD data read
IanBenzMaxim 26:a361e3f42ba5 562
IanBenzMaxim 26:a361e3f42ba5 563 if(_p_i2c_bus->write(_w_adrs, packet, 1) != I2C_WRITE_OK)
j3 17:b646b1e3970b 564 {
IanBenzMaxim 26:a361e3f42ba5 565 result = OneWireMaster::CommunicationWriteError;
j3 17:b646b1e3970b 566 }
j3 17:b646b1e3970b 567 else
j3 17:b646b1e3970b 568 {
IanBenzMaxim 26:a361e3f42ba5 569 // loop checking 1WB bit for completion of 1-Wire operation
IanBenzMaxim 26:a361e3f42ba5 570 // abort if poll limit reached
IanBenzMaxim 26:a361e3f42ba5 571 //dummy write for loop
IanBenzMaxim 26:a361e3f42ba5 572 result = OneWireMaster::Success; //so far
IanBenzMaxim 26:a361e3f42ba5 573 do
j3 17:b646b1e3970b 574 {
IanBenzMaxim 26:a361e3f42ba5 575 if(_p_i2c_bus->read(_r_adrs, &status, 1) != I2C_READ_OK)
IanBenzMaxim 26:a361e3f42ba5 576 {
IanBenzMaxim 26:a361e3f42ba5 577 result = OneWireMaster::CommunicationReadError;
IanBenzMaxim 26:a361e3f42ba5 578 }
IanBenzMaxim 26:a361e3f42ba5 579 }
IanBenzMaxim 26:a361e3f42ba5 580 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT) && (result != OneWireMaster::CommunicationReadError));
IanBenzMaxim 26:a361e3f42ba5 581
IanBenzMaxim 26:a361e3f42ba5 582 if((result == OneWireMaster::CommunicationReadError) || (poll_count >= POLL_LIMIT))
IanBenzMaxim 26:a361e3f42ba5 583 {
IanBenzMaxim 26:a361e3f42ba5 584 // check for failure due to poll limit reached
IanBenzMaxim 26:a361e3f42ba5 585 if (poll_count >= POLL_LIMIT)
IanBenzMaxim 26:a361e3f42ba5 586 {
IanBenzMaxim 26:a361e3f42ba5 587 // handle error
IanBenzMaxim 26:a361e3f42ba5 588 // ...
IanBenzMaxim 26:a361e3f42ba5 589 reset();
IanBenzMaxim 26:a361e3f42ba5 590 result = OneWireMaster::TimeoutError;
IanBenzMaxim 26:a361e3f42ba5 591 }
j3 17:b646b1e3970b 592 }
j3 17:b646b1e3970b 593 else
j3 17:b646b1e3970b 594 {
IanBenzMaxim 26:a361e3f42ba5 595 packet[0] = CMD_SRP;
IanBenzMaxim 26:a361e3f42ba5 596 packet[1] = 0xE1;
IanBenzMaxim 26:a361e3f42ba5 597
IanBenzMaxim 26:a361e3f42ba5 598 if(_p_i2c_bus->write(_w_adrs, packet, 2) != I2C_WRITE_OK)
j3 17:b646b1e3970b 599 {
IanBenzMaxim 26:a361e3f42ba5 600 result = OneWireMaster::CommunicationWriteError;
j3 17:b646b1e3970b 601 }
j3 17:b646b1e3970b 602 else
j3 17:b646b1e3970b 603 {
IanBenzMaxim 26:a361e3f42ba5 604 if(_p_i2c_bus->read(_r_adrs, &data, 1) != I2C_READ_OK)
IanBenzMaxim 26:a361e3f42ba5 605 {
IanBenzMaxim 26:a361e3f42ba5 606 result = OneWireMaster::CommunicationReadError;
IanBenzMaxim 26:a361e3f42ba5 607 }
IanBenzMaxim 26:a361e3f42ba5 608 else
IanBenzMaxim 26:a361e3f42ba5 609 {
IanBenzMaxim 26:a361e3f42ba5 610 recvbyte = data;
IanBenzMaxim 26:a361e3f42ba5 611 result = OneWireMaster::Success;
IanBenzMaxim 26:a361e3f42ba5 612 }
j3 17:b646b1e3970b 613 }
j3 17:b646b1e3970b 614 }
j3 17:b646b1e3970b 615 }
j3 2:02d228c25fd4 616 }
j3 2:02d228c25fd4 617
j3 17:b646b1e3970b 618 return result;
j3 17:b646b1e3970b 619 }
j3 17:b646b1e3970b 620
j3 17:b646b1e3970b 621
j3 17:b646b1e3970b 622 //*********************************************************************
j3 23:e8e403d61359 623 OneWireMaster::CmdResult Ds248x::OWWriteBlock(const uint8_t *tran_buf, uint8_t tran_len)
j3 17:b646b1e3970b 624 {
j3 23:e8e403d61359 625 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 626
j3 17:b646b1e3970b 627 for(uint8_t idx = 0; idx < tran_len; idx++)
j3 17:b646b1e3970b 628 {
IanBenzMaxim 26:a361e3f42ba5 629 result = OneWireMaster::OWWriteByte(tran_buf[idx]);
j3 23:e8e403d61359 630 if(result != OneWireMaster::Success)
j3 17:b646b1e3970b 631 {
j3 17:b646b1e3970b 632 break;
j3 17:b646b1e3970b 633 }
j3 17:b646b1e3970b 634 }
j3 17:b646b1e3970b 635
j3 17:b646b1e3970b 636 return result;
j3 17:b646b1e3970b 637 }
j3 17:b646b1e3970b 638
j3 17:b646b1e3970b 639
j3 17:b646b1e3970b 640 //*********************************************************************
j3 23:e8e403d61359 641 OneWireMaster::CmdResult Ds248x::OWReadBlock(uint8_t *rx_buf, uint8_t rx_len)
j3 17:b646b1e3970b 642 {
j3 23:e8e403d61359 643 OneWireMaster::CmdResult result;
j3 17:b646b1e3970b 644
j3 17:b646b1e3970b 645 for(uint8_t idx = 0; idx < rx_len; idx++)
j3 17:b646b1e3970b 646 {
j3 17:b646b1e3970b 647 //OwReadByte() uses pass by reference
IanBenzMaxim 26:a361e3f42ba5 648 result = OneWireMaster::OWReadByte(rx_buf[idx]);
j3 23:e8e403d61359 649 if(result != OneWireMaster::Success)
j3 17:b646b1e3970b 650 {
j3 17:b646b1e3970b 651 break;
j3 17:b646b1e3970b 652 }
j3 17:b646b1e3970b 653 }
j3 17:b646b1e3970b 654
j3 17:b646b1e3970b 655 return result;
j3 1:91e52f8ab8bf 656 }
j3 1:91e52f8ab8bf 657
j3 1:91e52f8ab8bf 658
j3 1:91e52f8ab8bf 659 //*********************************************************************
j3 23:e8e403d61359 660 OneWireMaster::CmdResult Ds248x::OWSearch(RomId & romId)
j3 1:91e52f8ab8bf 661 {
j3 17:b646b1e3970b 662 int id_bit_number;
j3 17:b646b1e3970b 663 int last_zero, rom_byte_number;
j3 17:b646b1e3970b 664 int id_bit, cmp_id_bit;
j3 17:b646b1e3970b 665 unsigned char rom_byte_mask, status;
j3 17:b646b1e3970b 666 bool search_result;
j3 17:b646b1e3970b 667 unsigned char crc8 = 0;
j3 17:b646b1e3970b 668 SEARCH_DIRECTION search_direction;
j3 17:b646b1e3970b 669
j3 17:b646b1e3970b 670 // initialize for search
j3 17:b646b1e3970b 671 id_bit_number = 1;
j3 17:b646b1e3970b 672 last_zero = 0;
j3 17:b646b1e3970b 673 rom_byte_number = 0;
j3 17:b646b1e3970b 674 rom_byte_mask = 1;
j3 17:b646b1e3970b 675 search_result = false;
j3 2:02d228c25fd4 676
j3 17:b646b1e3970b 677 // if the last call was not the last one
j3 17:b646b1e3970b 678 if (!_last_device_flag)
j3 17:b646b1e3970b 679 {
j3 17:b646b1e3970b 680 // 1-Wire reset
j3 23:e8e403d61359 681 OneWireMaster::CmdResult result = OWReset();
j3 23:e8e403d61359 682 if (result != OneWireMaster::Success)
j3 17:b646b1e3970b 683 {
j3 17:b646b1e3970b 684 // reset the search
j3 17:b646b1e3970b 685 _last_discrepancy = 0;
j3 17:b646b1e3970b 686 _last_device_flag = false;
j3 17:b646b1e3970b 687 _last_family_discrepancy = 0;
j3 17:b646b1e3970b 688 return result;
j3 17:b646b1e3970b 689 }
j3 17:b646b1e3970b 690
j3 17:b646b1e3970b 691 // issue the search command
IanBenzMaxim 26:a361e3f42ba5 692 OneWireMaster::OWWriteByte(0xF0);
j3 2:02d228c25fd4 693
j3 17:b646b1e3970b 694 // loop to do the search
j3 17:b646b1e3970b 695 do
j3 17:b646b1e3970b 696 {
j3 17:b646b1e3970b 697 // if this discrepancy if before the Last Discrepancy
j3 17:b646b1e3970b 698 // on a previous next then pick the same as last time
j3 17:b646b1e3970b 699 if (id_bit_number < _last_discrepancy)
j3 17:b646b1e3970b 700 {
j3 17:b646b1e3970b 701 if ((romId[rom_byte_number] & rom_byte_mask) > 0)
j3 17:b646b1e3970b 702 search_direction = DIRECTION_WRITE_ONE;
j3 17:b646b1e3970b 703 else
j3 17:b646b1e3970b 704 search_direction = DIRECTION_WRITE_ZERO;
j3 17:b646b1e3970b 705 }
j3 17:b646b1e3970b 706 else
j3 17:b646b1e3970b 707 {
j3 17:b646b1e3970b 708 // if equal to last pick 1, if not then pick 0
j3 17:b646b1e3970b 709 if (id_bit_number == _last_discrepancy)
j3 17:b646b1e3970b 710 search_direction = DIRECTION_WRITE_ONE;
j3 17:b646b1e3970b 711 else
j3 17:b646b1e3970b 712 search_direction = DIRECTION_WRITE_ZERO;
j3 17:b646b1e3970b 713 }
j3 2:02d228c25fd4 714
j3 17:b646b1e3970b 715 // Peform a triple operation on the DS2465 which will perform 2 read bits and 1 write bit
j3 17:b646b1e3970b 716 search_triplet(search_direction, status);
j3 17:b646b1e3970b 717
j3 17:b646b1e3970b 718 // check bit results in status byte
j3 17:b646b1e3970b 719 id_bit = ((status & STATUS_SBR) == STATUS_SBR);
j3 17:b646b1e3970b 720 cmp_id_bit = ((status & STATUS_TSB) == STATUS_TSB);
j3 17:b646b1e3970b 721 search_direction = ((status & STATUS_DIR) == STATUS_DIR) ? DIRECTION_WRITE_ONE : DIRECTION_WRITE_ZERO;
j3 17:b646b1e3970b 722
j3 17:b646b1e3970b 723 // check for no devices on 1-wire
j3 17:b646b1e3970b 724 if ((id_bit) && (cmp_id_bit))
j3 17:b646b1e3970b 725 break;
j3 17:b646b1e3970b 726 else
j3 17:b646b1e3970b 727 {
j3 17:b646b1e3970b 728 if ((!id_bit) && (!cmp_id_bit) && (search_direction == DIRECTION_WRITE_ZERO))
j3 2:02d228c25fd4 729 {
j3 17:b646b1e3970b 730 last_zero = id_bit_number;
j3 17:b646b1e3970b 731
j3 17:b646b1e3970b 732 // check for Last discrepancy in family
j3 17:b646b1e3970b 733 if (last_zero < 9)
j3 17:b646b1e3970b 734 _last_family_discrepancy = last_zero;
j3 2:02d228c25fd4 735 }
j3 2:02d228c25fd4 736
j3 17:b646b1e3970b 737 // set or clear the bit in the ROM byte rom_byte_number
j3 17:b646b1e3970b 738 // with mask rom_byte_mask
j3 17:b646b1e3970b 739 if (search_direction == DIRECTION_WRITE_ONE)
j3 17:b646b1e3970b 740 romId[rom_byte_number] |= rom_byte_mask;
j3 17:b646b1e3970b 741 else
j3 17:b646b1e3970b 742 romId[rom_byte_number] &= (unsigned char)~rom_byte_mask;
j3 2:02d228c25fd4 743
j3 17:b646b1e3970b 744 // increment the byte counter id_bit_number
j3 17:b646b1e3970b 745 // and shift the mask rom_byte_mask
j3 17:b646b1e3970b 746 id_bit_number++;
j3 17:b646b1e3970b 747 rom_byte_mask <<= 1;
j3 2:02d228c25fd4 748
j3 17:b646b1e3970b 749 // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
j3 17:b646b1e3970b 750 if (rom_byte_mask == 0)
j3 17:b646b1e3970b 751 {
j3 17:b646b1e3970b 752 crc8 = romId.calculateCRC8(crc8, romId[rom_byte_number]); // accumulate the CRC
j3 17:b646b1e3970b 753 rom_byte_number++;
j3 17:b646b1e3970b 754 rom_byte_mask = 1;
j3 17:b646b1e3970b 755 }
j3 17:b646b1e3970b 756 }
j3 17:b646b1e3970b 757 }
j3 17:b646b1e3970b 758 while(rom_byte_number < RomId::byteLen); // loop until through all ROM bytes 0-7
j3 2:02d228c25fd4 759
j3 17:b646b1e3970b 760 // if the search was successful then
j3 17:b646b1e3970b 761 if (!((id_bit_number <= (RomId::byteLen * 8)) || (crc8 != 0)))
j3 17:b646b1e3970b 762 {
j3 17:b646b1e3970b 763 // search successful so set m_last_discrepancy,m_last_device_flag,search_result
j3 17:b646b1e3970b 764 _last_discrepancy = last_zero;
j3 2:02d228c25fd4 765
j3 17:b646b1e3970b 766 // check for last device
j3 17:b646b1e3970b 767 if (_last_discrepancy == 0)
j3 17:b646b1e3970b 768 _last_device_flag = true;
j3 2:02d228c25fd4 769
j3 17:b646b1e3970b 770 search_result = true;
j3 17:b646b1e3970b 771 }
j3 17:b646b1e3970b 772 }
j3 2:02d228c25fd4 773
j3 17:b646b1e3970b 774 // if no device found then reset counters so next 'search' will be like a first
j3 17:b646b1e3970b 775 if (!search_result || (romId.familyCode() == 0))
j3 17:b646b1e3970b 776 {
j3 17:b646b1e3970b 777 _last_discrepancy = 0;
j3 17:b646b1e3970b 778 _last_device_flag = false;
j3 17:b646b1e3970b 779 _last_family_discrepancy = 0;
j3 17:b646b1e3970b 780 search_result = false;
j3 17:b646b1e3970b 781 }
j3 2:02d228c25fd4 782
j3 23:e8e403d61359 783 return search_result ? OneWireMaster::Success : OneWireMaster::OperationFailure;
j3 1:91e52f8ab8bf 784 }
j3 1:91e52f8ab8bf 785
j3 1:91e52f8ab8bf 786
j3 1:91e52f8ab8bf 787 //*********************************************************************
j3 23:e8e403d61359 788 OneWireMaster::CmdResult Ds248x::OWSpeed(OW_SPEED new_speed)
j3 1:91e52f8ab8bf 789 {
j3 2:02d228c25fd4 790 // set the speed
j3 5:ce108eeb878d 791 if (new_speed == SPEED_OVERDRIVE)
j3 2:02d228c25fd4 792 {
j3 2:02d228c25fd4 793 _c1WS = CONFIG_1WS;
j3 2:02d228c25fd4 794 }
j3 2:02d228c25fd4 795 else
j3 2:02d228c25fd4 796 {
j3 17:b646b1e3970b 797 _c1WS = 0;
j3 2:02d228c25fd4 798 }
j3 2:02d228c25fd4 799
j3 17:b646b1e3970b 800 // write the new config, and return result of op
j3 17:b646b1e3970b 801 return write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 1:91e52f8ab8bf 802 }
j3 1:91e52f8ab8bf 803
j3 1:91e52f8ab8bf 804
j3 1:91e52f8ab8bf 805 //*********************************************************************
j3 23:e8e403d61359 806 OneWireMaster::CmdResult Ds248x::OWLevel(OW_LEVEL new_level)
j3 1:91e52f8ab8bf 807 {
j3 23:e8e403d61359 808 OneWireMaster::CmdResult result;
j3 2:02d228c25fd4 809
j3 2:02d228c25fd4 810 // function only will turn back to non-strong pull-up
j3 5:ce108eeb878d 811 if (new_level != LEVEL_NORMAL)
j3 2:02d228c25fd4 812 {
j3 23:e8e403d61359 813 result = OneWireMaster::OperationFailure;
j3 2:02d228c25fd4 814 }
j3 2:02d228c25fd4 815 else
j3 2:02d228c25fd4 816 {
j3 2:02d228c25fd4 817 // clear the strong pull-up bit in the global config state
j3 17:b646b1e3970b 818 _cSPU = 0;
j3 17:b646b1e3970b 819
j3 17:b646b1e3970b 820 result = write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 2:02d228c25fd4 821 }
j3 2:02d228c25fd4 822
j3 17:b646b1e3970b 823 return result;
j3 1:91e52f8ab8bf 824 }
j3 1:91e52f8ab8bf 825
j3 1:91e52f8ab8bf 826
IanBenzMaxim 26:a361e3f42ba5 827 OneWireMaster::CmdResult Ds248x::ConfigureSPU(bool spu_enable)
j3 1:91e52f8ab8bf 828 {
IanBenzMaxim 26:a361e3f42ba5 829 OneWireMaster::CmdResult result;
IanBenzMaxim 26:a361e3f42ba5 830 if ((_cSPU == CONFIG_SPU) != spu_enable)
IanBenzMaxim 26:a361e3f42ba5 831 {
IanBenzMaxim 26:a361e3f42ba5 832 _cSPU = spu_enable;
IanBenzMaxim 26:a361e3f42ba5 833 result = write_config(_c1WS | _cSPU | _cPDN | _cAPU);
IanBenzMaxim 26:a361e3f42ba5 834 }
IanBenzMaxim 26:a361e3f42ba5 835 else
IanBenzMaxim 26:a361e3f42ba5 836 {
IanBenzMaxim 26:a361e3f42ba5 837 result = OneWireMaster::Success;
IanBenzMaxim 26:a361e3f42ba5 838 }
IanBenzMaxim 26:a361e3f42ba5 839 return result;
IanBenzMaxim 21:00c94aeb533e 840 }
IanBenzMaxim 21:00c94aeb533e 841
IanBenzMaxim 21:00c94aeb533e 842
j3 1:91e52f8ab8bf 843 //*********************************************************************
j3 6:1faafa0b3cd7 844 void Ds248x::set_i2c_adrs(DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 845 {
j3 6:1faafa0b3cd7 846 _w_adrs = (adrs << 1);
j3 6:1faafa0b3cd7 847 _r_adrs = (_w_adrs | 1);
j3 6:1faafa0b3cd7 848 }