Maxim Integrated / OneWire

1-Wire® library for mbed. Complete 1-Wire library that supports our silicon masters along with a bit-bang master on the MAX32600MBED platform with one common interface for mbed. Slave support has also been included and more slaves will be added as time permits.

Dependents:   MAXREFDES131_Qt_Demo MAX32630FTHR_iButton_uSD_Logger MAX32630FTHR_DS18B20_uSD_Logger MAXREFDES130_131_Demo ... more

Superseded by MaximInterface.

OneWire_Masters/DS248x/ds248x.cpp@14:7b2886a50321, 2016-03-15 (annotated)

Committer:
j3
Date:
Tue Mar 15 01:38:17 2016 +0000
Revision:
14:7b2886a50321
Parent:
6:1faafa0b3cd7
Child:
15:f6cb0d906fb6
added OWInitMaster() to interface in order to encapsulate master specific functions

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 1:91e52f8ab8bf 1 /******************************************************************//**
j3 1:91e52f8ab8bf 2 * @file ds248x.cpp
j3 1:91e52f8ab8bf 3 *
j3 1:91e52f8ab8bf 4 * @author Justin Jordan
j3 1:91e52f8ab8bf 5 *
j3 1:91e52f8ab8bf 6 * @version 0.0.0
j3 1:91e52f8ab8bf 7 *
j3 1:91e52f8ab8bf 8 * Started: 30JAN16
j3 1:91e52f8ab8bf 9 *
j3 1:91e52f8ab8bf 10 * Updated:
j3 1:91e52f8ab8bf 11 *
j3 1:91e52f8ab8bf 12 * @brief Source file for Ds248x I2C to 1-wire master
j3 1:91e52f8ab8bf 13 ***********************************************************************
j3 1:91e52f8ab8bf 14 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 1:91e52f8ab8bf 15 *
j3 1:91e52f8ab8bf 16 * Permission is hereby granted, free of charge, to any person obtaining a
j3 1:91e52f8ab8bf 17 * copy of this software and associated documentation files (the "Software"),
j3 1:91e52f8ab8bf 18 * to deal in the Software without restriction, including without limitation
j3 1:91e52f8ab8bf 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 1:91e52f8ab8bf 20 * and/or sell copies of the Software, and to permit persons to whom the
j3 1:91e52f8ab8bf 21 * Software is furnished to do so, subject to the following conditions:
j3 1:91e52f8ab8bf 22 *
j3 1:91e52f8ab8bf 23 * The above copyright notice and this permission notice shall be included
j3 1:91e52f8ab8bf 24 * in all copies or substantial portions of the Software.
j3 1:91e52f8ab8bf 25 *
j3 1:91e52f8ab8bf 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 1:91e52f8ab8bf 27 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 1:91e52f8ab8bf 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 1:91e52f8ab8bf 29 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 1:91e52f8ab8bf 30 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 1:91e52f8ab8bf 31 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 1:91e52f8ab8bf 32 * OTHER DEALINGS IN THE SOFTWARE.
j3 1:91e52f8ab8bf 33 *
j3 1:91e52f8ab8bf 34 * Except as contained in this notice, the name of Maxim Integrated
j3 1:91e52f8ab8bf 35 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 1:91e52f8ab8bf 36 * Products, Inc. Branding Policy.
j3 1:91e52f8ab8bf 37 *
j3 1:91e52f8ab8bf 38 * The mere transfer of this software does not imply any licenses
j3 1:91e52f8ab8bf 39 * of trade secrets, proprietary technology, copyrights, patents,
j3 1:91e52f8ab8bf 40 * trademarks, maskwork rights, or any other form of intellectual
j3 1:91e52f8ab8bf 41 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 1:91e52f8ab8bf 42 * ownership rights.
j3 1:91e52f8ab8bf 43 **********************************************************************/
j3 1:91e52f8ab8bf 44
j3 1:91e52f8ab8bf 45
j3 1:91e52f8ab8bf 46 #include "ds248x.h"
j3 1:91e52f8ab8bf 47
j3 1:91e52f8ab8bf 48
j3 1:91e52f8ab8bf 49 //*********************************************************************
j3 5:ce108eeb878d 50 Ds248x::Ds248x(I2C &i2c_bus, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 51 :_p_i2c_bus(&i2c_bus), _i2c_owner(false)
j3 1:91e52f8ab8bf 52 {
j3 6:1faafa0b3cd7 53 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 54 }
j3 1:91e52f8ab8bf 55
j3 1:91e52f8ab8bf 56
j3 1:91e52f8ab8bf 57 //*********************************************************************
j3 5:ce108eeb878d 58 Ds248x::Ds248x(PinName sda, PinName scl, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 59 :_p_i2c_bus(new I2C(sda, scl)), _i2c_owner(true)
j3 1:91e52f8ab8bf 60 {
j3 6:1faafa0b3cd7 61 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 62 }
j3 1:91e52f8ab8bf 63
j3 1:91e52f8ab8bf 64
j3 1:91e52f8ab8bf 65 //*********************************************************************
j3 1:91e52f8ab8bf 66 Ds248x::~Ds248x()
j3 1:91e52f8ab8bf 67 {
j3 5:ce108eeb878d 68 if(_i2c_owner)
j3 1:91e52f8ab8bf 69 {
j3 1:91e52f8ab8bf 70 delete _p_i2c_bus;
j3 1:91e52f8ab8bf 71 }
j3 1:91e52f8ab8bf 72 }
j3 1:91e52f8ab8bf 73
j3 1:91e52f8ab8bf 74
j3 1:91e52f8ab8bf 75 //*********************************************************************
j3 14:7b2886a50321 76 bool Ds248x::OWInitMaster()
j3 14:7b2886a50321 77 {
j3 14:7b2886a50321 78 return(detect());
j3 14:7b2886a50321 79 }
j3 14:7b2886a50321 80
j3 14:7b2886a50321 81
j3 14:7b2886a50321 82 //*********************************************************************
j3 2:02d228c25fd4 83 bool Ds248x::detect(void)
j3 2:02d228c25fd4 84 {
j3 2:02d228c25fd4 85 bool rtn_val = false;
j3 2:02d228c25fd4 86
j3 2:02d228c25fd4 87 // reset the ds2484 ON selected address
j3 2:02d228c25fd4 88 if (!reset())
j3 2:02d228c25fd4 89 {
j3 2:02d228c25fd4 90 rtn_val = false;
j3 2:02d228c25fd4 91 }
j3 2:02d228c25fd4 92 else
j3 2:02d228c25fd4 93 {
j3 2:02d228c25fd4 94 // default configuration
j3 5:ce108eeb878d 95 _c1WS = false;
j3 5:ce108eeb878d 96 _cSPU = false;
j3 5:ce108eeb878d 97 _cPDN = false;
j3 5:ce108eeb878d 98 _cAPU = false;
j3 2:02d228c25fd4 99
j3 2:02d228c25fd4 100 // write the default configuration setup
j3 2:02d228c25fd4 101 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 102 {
j3 2:02d228c25fd4 103 rtn_val = false;
j3 2:02d228c25fd4 104 }
j3 2:02d228c25fd4 105 else
j3 2:02d228c25fd4 106 {
j3 2:02d228c25fd4 107 rtn_val = true;
j3 2:02d228c25fd4 108 }
j3 2:02d228c25fd4 109 }
j3 2:02d228c25fd4 110
j3 2:02d228c25fd4 111 return(rtn_val);
j3 2:02d228c25fd4 112 }
j3 2:02d228c25fd4 113
j3 2:02d228c25fd4 114
j3 2:02d228c25fd4 115 //*********************************************************************
j3 2:02d228c25fd4 116 bool Ds248x::reset(void)
j3 1:91e52f8ab8bf 117 {
j3 2:02d228c25fd4 118 char status;
j3 2:02d228c25fd4 119 char packet[] = {CMD_DRST};
j3 2:02d228c25fd4 120
j3 2:02d228c25fd4 121 // Device Reset
j3 2:02d228c25fd4 122 // S AD,0 [A] DRST [A] Sr AD,1 [A] [SS] A\ P
j3 2:02d228c25fd4 123 // [] indicates from slave
j3 2:02d228c25fd4 124 // SS status byte to read to verify state
j3 2:02d228c25fd4 125
j3 2:02d228c25fd4 126 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 127 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 128
j3 2:02d228c25fd4 129 return((status & 0xF7) == 0x10);
j3 2:02d228c25fd4 130 }
j3 2:02d228c25fd4 131
j3 2:02d228c25fd4 132
j3 2:02d228c25fd4 133 //*********************************************************************
j3 2:02d228c25fd4 134 bool Ds248x::write_config(uint8_t config)
j3 2:02d228c25fd4 135 {
j3 2:02d228c25fd4 136 bool rtn_val = false;
j3 2:02d228c25fd4 137 char read_config;
j3 2:02d228c25fd4 138 char packet [] = {CMD_WCFG, (config | (~config << 4))};
j3 2:02d228c25fd4 139
j3 2:02d228c25fd4 140 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 141 _p_i2c_bus->read(_r_adrs, &read_config, 1);
j3 2:02d228c25fd4 142
j3 2:02d228c25fd4 143 // check for failure due to incorrect read back
j3 2:02d228c25fd4 144 if (config != read_config)
j3 2:02d228c25fd4 145 {
j3 2:02d228c25fd4 146 // handle error
j3 2:02d228c25fd4 147 // ...
j3 2:02d228c25fd4 148 reset();
j3 2:02d228c25fd4 149 rtn_val = false;
j3 2:02d228c25fd4 150 }
j3 2:02d228c25fd4 151 else
j3 2:02d228c25fd4 152 {
j3 2:02d228c25fd4 153 rtn_val = true;
j3 2:02d228c25fd4 154 }
j3 2:02d228c25fd4 155
j3 1:91e52f8ab8bf 156 return(rtn_val);
j3 1:91e52f8ab8bf 157 }
j3 1:91e52f8ab8bf 158
j3 1:91e52f8ab8bf 159
j3 1:91e52f8ab8bf 160 //*********************************************************************
j3 2:02d228c25fd4 161 bool Ds248x::channel_select(uint8_t channel)
j3 1:91e52f8ab8bf 162 {
j3 2:02d228c25fd4 163
j3 2:02d228c25fd4 164 char ch, ch_read, check;
j3 2:02d228c25fd4 165 char packet [2];
j3 2:02d228c25fd4 166
j3 2:02d228c25fd4 167 packet[0] = CMD_CHSL;
j3 2:02d228c25fd4 168
j3 2:02d228c25fd4 169 // Channel Select (Case A)
j3 2:02d228c25fd4 170 // S AD,0 [A] CHSL [A] CC [A] Sr AD,1 [A] [RR] A\ P
j3 2:02d228c25fd4 171 // [] indicates from slave
j3 2:02d228c25fd4 172 // CC channel value
j3 2:02d228c25fd4 173 // RR channel read back
j3 2:02d228c25fd4 174
j3 2:02d228c25fd4 175 switch (channel)
j3 2:02d228c25fd4 176 {
j3 2:02d228c25fd4 177 default: case 0: ch = 0xF0; ch_read = 0xB8; break;
j3 2:02d228c25fd4 178 case 1: ch = 0xE1; ch_read = 0xB1; break;
j3 2:02d228c25fd4 179 case 2: ch = 0xD2; ch_read = 0xAA; break;
j3 2:02d228c25fd4 180 case 3: ch = 0xC3; ch_read = 0xA3; break;
j3 2:02d228c25fd4 181 case 4: ch = 0xB4; ch_read = 0x9C; break;
j3 2:02d228c25fd4 182 case 5: ch = 0xA5; ch_read = 0x95; break;
j3 2:02d228c25fd4 183 case 6: ch = 0x96; ch_read = 0x8E; break;
j3 2:02d228c25fd4 184 case 7: ch = 0x87; ch_read = 0x87; break;
j3 2:02d228c25fd4 185 };
j3 2:02d228c25fd4 186
j3 2:02d228c25fd4 187 packet[1] = ch;
j3 2:02d228c25fd4 188
j3 2:02d228c25fd4 189 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 190 _p_i2c_bus->read(_r_adrs, &check, 1);
j3 2:02d228c25fd4 191
j3 2:02d228c25fd4 192 // check for failure due to incorrect read back of channel
j3 2:02d228c25fd4 193 return (check == ch_read);
j3 2:02d228c25fd4 194 }
j3 2:02d228c25fd4 195
j3 2:02d228c25fd4 196
j3 2:02d228c25fd4 197 //*********************************************************************
j3 2:02d228c25fd4 198 bool Ds248x::adjust_timing(uint8_t param, uint8_t val)
j3 2:02d228c25fd4 199 {
j3 2:02d228c25fd4 200 bool rtn_val = false;
j3 2:02d228c25fd4 201 char read_port_config;
j3 2:02d228c25fd4 202 char control_byte;
j3 2:02d228c25fd4 203
j3 2:02d228c25fd4 204 control_byte = (((param & 0x0F) << 4) | (val & 0x0F));
j3 2:02d228c25fd4 205
j3 2:02d228c25fd4 206 char packet [] = {CMD_A1WP, control_byte};
j3 2:02d228c25fd4 207
j3 2:02d228c25fd4 208 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 209 _p_i2c_bus->read(_r_adrs, &read_port_config, 1);
j3 2:02d228c25fd4 210
j3 2:02d228c25fd4 211 // check for failure due to incorrect read back
j3 2:02d228c25fd4 212 if ((control_byte & 0x0F) != read_port_config)
j3 2:02d228c25fd4 213 {
j3 2:02d228c25fd4 214 // handle error
j3 2:02d228c25fd4 215 // ...
j3 2:02d228c25fd4 216 reset();
j3 2:02d228c25fd4 217
j3 2:02d228c25fd4 218 rtn_val = false;
j3 2:02d228c25fd4 219 }
j3 2:02d228c25fd4 220 else
j3 2:02d228c25fd4 221 {
j3 2:02d228c25fd4 222 rtn_val = true;
j3 2:02d228c25fd4 223 }
j3 2:02d228c25fd4 224
j3 2:02d228c25fd4 225 return(rtn_val);
j3 1:91e52f8ab8bf 226 }
j3 1:91e52f8ab8bf 227
j3 1:91e52f8ab8bf 228
j3 1:91e52f8ab8bf 229 //*********************************************************************
j3 2:02d228c25fd4 230 uint8_t Ds248x::search_triplet(uint8_t search_direction)
j3 1:91e52f8ab8bf 231 {
j3 2:02d228c25fd4 232 uint8_t rtn_val = 0;
j3 2:02d228c25fd4 233 uint8_t poll_count = 0;
j3 2:02d228c25fd4 234 char status;
j3 2:02d228c25fd4 235 char packet [] = {CMD_1WT, search_direction ? 0x80 : 0x00};
j3 2:02d228c25fd4 236
j3 2:02d228c25fd4 237 // 1-Wire Triplet (Case B)
j3 2:02d228c25fd4 238 // S AD,0 [A] 1WT [A] SS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 239 // \--------/
j3 2:02d228c25fd4 240 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 241 // [] indicates from slave
j3 2:02d228c25fd4 242 // SS indicates byte containing search direction bit value in msbit
j3 2:02d228c25fd4 243
j3 2:02d228c25fd4 244 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 245
j3 2:02d228c25fd4 246 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 247 // abort if poll limit reached
j3 2:02d228c25fd4 248 do
j3 2:02d228c25fd4 249 {
j3 2:02d228c25fd4 250 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 251 }
j3 2:02d228c25fd4 252 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 253
j3 2:02d228c25fd4 254 // check for failure due to poll limit reached
j3 2:02d228c25fd4 255 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 256 {
j3 2:02d228c25fd4 257 // handle error
j3 2:02d228c25fd4 258 // ...
j3 2:02d228c25fd4 259 reset();
j3 5:ce108eeb878d 260 rtn_val = false;
j3 2:02d228c25fd4 261 }
j3 2:02d228c25fd4 262 else
j3 2:02d228c25fd4 263 {
j3 2:02d228c25fd4 264 rtn_val = status;
j3 2:02d228c25fd4 265 }
j3 2:02d228c25fd4 266
j3 2:02d228c25fd4 267 return(rtn_val);
j3 1:91e52f8ab8bf 268 }
j3 1:91e52f8ab8bf 269
j3 1:91e52f8ab8bf 270
j3 1:91e52f8ab8bf 271 //*********************************************************************
j3 2:02d228c25fd4 272 bool Ds248x::OWReset()
j3 2:02d228c25fd4 273 {
j3 2:02d228c25fd4 274 bool rtn_val = false;
j3 2:02d228c25fd4 275
j3 2:02d228c25fd4 276 uint8_t poll_count = 0;
j3 2:02d228c25fd4 277 char status;
j3 2:02d228c25fd4 278 char packet [] = {CMD_1WRS};
j3 1:91e52f8ab8bf 279
j3 2:02d228c25fd4 280 // 1-Wire reset (Case B)
j3 2:02d228c25fd4 281 // S AD,0 [A] 1WRS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 282 // \--------/
j3 2:02d228c25fd4 283 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 284 // [] indicates from slave
j3 2:02d228c25fd4 285
j3 2:02d228c25fd4 286 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 287
j3 2:02d228c25fd4 288 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 289 // abort if poll limit reached
j3 2:02d228c25fd4 290 do
j3 2:02d228c25fd4 291 {
j3 2:02d228c25fd4 292 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 293 }
j3 2:02d228c25fd4 294 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 1:91e52f8ab8bf 295
j3 2:02d228c25fd4 296 // check for failure due to poll limit reached
j3 2:02d228c25fd4 297 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 298 {
j3 2:02d228c25fd4 299 // handle error
j3 2:02d228c25fd4 300 // ...
j3 2:02d228c25fd4 301 reset();
j3 2:02d228c25fd4 302 rtn_val = false;
j3 2:02d228c25fd4 303 }
j3 2:02d228c25fd4 304 else
j3 2:02d228c25fd4 305 {
j3 2:02d228c25fd4 306 // check for short condition
j3 2:02d228c25fd4 307 if (status & STATUS_SD)
j3 2:02d228c25fd4 308 {
j3 5:ce108eeb878d 309 _short_detected = true;
j3 2:02d228c25fd4 310 }
j3 2:02d228c25fd4 311 else
j3 2:02d228c25fd4 312 {
j3 5:ce108eeb878d 313 _short_detected = false;
j3 2:02d228c25fd4 314 }
j3 2:02d228c25fd4 315
j3 2:02d228c25fd4 316 // check for presence detect
j3 2:02d228c25fd4 317 if (status & STATUS_PPD)
j3 2:02d228c25fd4 318 {
j3 2:02d228c25fd4 319 rtn_val = true;
j3 2:02d228c25fd4 320 }
j3 2:02d228c25fd4 321 else
j3 2:02d228c25fd4 322 {
j3 2:02d228c25fd4 323 rtn_val = false;
j3 2:02d228c25fd4 324 }
j3 2:02d228c25fd4 325 }
j3 2:02d228c25fd4 326
j3 1:91e52f8ab8bf 327 return(rtn_val);
j3 1:91e52f8ab8bf 328 }
j3 1:91e52f8ab8bf 329
j3 1:91e52f8ab8bf 330
j3 1:91e52f8ab8bf 331 //*********************************************************************
j3 1:91e52f8ab8bf 332 void Ds248x::OWWriteBit(uint8_t sendbit)
j3 1:91e52f8ab8bf 333 {
j3 2:02d228c25fd4 334 OWTouchBit(sendbit);
j3 1:91e52f8ab8bf 335 }
j3 1:91e52f8ab8bf 336
j3 1:91e52f8ab8bf 337
j3 1:91e52f8ab8bf 338 //*********************************************************************
j3 1:91e52f8ab8bf 339 uint8_t Ds248x::OWReadBit()
j3 1:91e52f8ab8bf 340 {
j3 2:02d228c25fd4 341 return(OWTouchBit(0x01));
j3 1:91e52f8ab8bf 342 }
j3 1:91e52f8ab8bf 343
j3 1:91e52f8ab8bf 344
j3 1:91e52f8ab8bf 345 //*********************************************************************
j3 1:91e52f8ab8bf 346 uint8_t Ds248x::OWTouchBit(uint8_t sendbit)
j3 1:91e52f8ab8bf 347 {
j3 1:91e52f8ab8bf 348 uint8_t rtn_val;
j3 2:02d228c25fd4 349 uint8_t poll_count = 0;
j3 2:02d228c25fd4 350 char status;
j3 2:02d228c25fd4 351 char packet[] = {CMD_1WSB, sendbit ? 0x80 : 0x00};
j3 2:02d228c25fd4 352
j3 2:02d228c25fd4 353 // 1-Wire bit (Case B)
j3 2:02d228c25fd4 354 // S AD,0 [A] 1WSB [A] BB [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 355 // \--------/
j3 2:02d228c25fd4 356 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 357 // [] indicates from slave
j3 2:02d228c25fd4 358 // BB indicates byte containing bit value in msbit
j3 2:02d228c25fd4 359
j3 2:02d228c25fd4 360 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 361
j3 2:02d228c25fd4 362 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 363 // abort if poll limit reached
j3 2:02d228c25fd4 364 do
j3 2:02d228c25fd4 365 {
j3 2:02d228c25fd4 366 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 367 }
j3 2:02d228c25fd4 368 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 369
j3 2:02d228c25fd4 370 // check for failure due to poll limit reached
j3 2:02d228c25fd4 371 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 372 {
j3 2:02d228c25fd4 373 // handle error
j3 2:02d228c25fd4 374 // ...
j3 2:02d228c25fd4 375 reset();
j3 2:02d228c25fd4 376 rtn_val = 0;
j3 2:02d228c25fd4 377 }
j3 2:02d228c25fd4 378 else
j3 2:02d228c25fd4 379 {
j3 2:02d228c25fd4 380 // return bit state
j3 2:02d228c25fd4 381 if (status & STATUS_SBR)
j3 2:02d228c25fd4 382 {
j3 2:02d228c25fd4 383 rtn_val = 1;
j3 2:02d228c25fd4 384 }
j3 2:02d228c25fd4 385 else
j3 2:02d228c25fd4 386 {
j3 2:02d228c25fd4 387 rtn_val = 0;
j3 2:02d228c25fd4 388 }
j3 2:02d228c25fd4 389 }
j3 2:02d228c25fd4 390
j3 2:02d228c25fd4 391 return(rtn_val);
j3 1:91e52f8ab8bf 392 }
j3 1:91e52f8ab8bf 393
j3 1:91e52f8ab8bf 394
j3 1:91e52f8ab8bf 395 //*********************************************************************
j3 2:02d228c25fd4 396 bool Ds248x::OWWriteByte(uint8_t sendbyte)
j3 1:91e52f8ab8bf 397 {
j3 2:02d228c25fd4 398 bool rtn_val = false;
j3 1:91e52f8ab8bf 399
j3 2:02d228c25fd4 400 uint8_t poll_count = 0;
j3 2:02d228c25fd4 401 char status;
j3 2:02d228c25fd4 402 char packet [] = {CMD_1WWB, sendbyte};
j3 2:02d228c25fd4 403
j3 2:02d228c25fd4 404 // 1-Wire Write Byte (Case B)
j3 2:02d228c25fd4 405 // S AD,0 [A] 1WWB [A] DD [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 406 // \--------/
j3 2:02d228c25fd4 407 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 408 // [] indicates from slave
j3 2:02d228c25fd4 409 // DD data to write
j3 2:02d228c25fd4 410
j3 2:02d228c25fd4 411 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 412
j3 2:02d228c25fd4 413 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 414 // abort if poll limit reached
j3 2:02d228c25fd4 415 do
j3 2:02d228c25fd4 416 {
j3 2:02d228c25fd4 417 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 418 }
j3 2:02d228c25fd4 419 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 420
j3 2:02d228c25fd4 421 // check for failure due to poll limit reached
j3 2:02d228c25fd4 422 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 423 {
j3 2:02d228c25fd4 424 // handle error
j3 2:02d228c25fd4 425 // ...
j3 2:02d228c25fd4 426 reset();
j3 2:02d228c25fd4 427 rtn_val = false;
j3 2:02d228c25fd4 428 }
j3 2:02d228c25fd4 429 else
j3 2:02d228c25fd4 430 {
j3 2:02d228c25fd4 431 rtn_val = true;
j3 2:02d228c25fd4 432 }
j3 2:02d228c25fd4 433
j3 2:02d228c25fd4 434 return(rtn_val);
j3 1:91e52f8ab8bf 435 }
j3 1:91e52f8ab8bf 436
j3 1:91e52f8ab8bf 437
j3 1:91e52f8ab8bf 438 //*********************************************************************
j3 1:91e52f8ab8bf 439 uint8_t Ds248x::OWReadByte(void)
j3 1:91e52f8ab8bf 440 {
j3 1:91e52f8ab8bf 441 uint8_t rtn_val;
j3 2:02d228c25fd4 442
j3 2:02d228c25fd4 443 uint8_t poll_count = 0;
j3 2:02d228c25fd4 444 char data, status;
j3 2:02d228c25fd4 445 char packet[2] = {CMD_1WRB, 0};
j3 2:02d228c25fd4 446
j3 2:02d228c25fd4 447 // 1-Wire Read Bytes (Case C)
j3 2:02d228c25fd4 448 // S AD,0 [A] 1WRB [A] Sr AD,1 [A] [Status] A [Status] A\
j3 2:02d228c25fd4 449 // \--------/
j3 2:02d228c25fd4 450 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 451 // Sr AD,0 [A] SRP [A] E1 [A] Sr AD,1 [A] DD A\ P
j3 2:02d228c25fd4 452 //
j3 2:02d228c25fd4 453 // [] indicates from slave
j3 2:02d228c25fd4 454 // DD data read
j3 2:02d228c25fd4 455
j3 2:02d228c25fd4 456 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 457
j3 2:02d228c25fd4 458 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 459 // abort if poll limit reached
j3 2:02d228c25fd4 460 do
j3 2:02d228c25fd4 461 {
j3 2:02d228c25fd4 462 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 463 }
j3 2:02d228c25fd4 464 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 465
j3 2:02d228c25fd4 466 // check for failure due to poll limit reached
j3 2:02d228c25fd4 467 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 468 {
j3 2:02d228c25fd4 469 // handle error
j3 2:02d228c25fd4 470 // ...
j3 2:02d228c25fd4 471 reset();
j3 2:02d228c25fd4 472 rtn_val = 0;
j3 2:02d228c25fd4 473 }
j3 2:02d228c25fd4 474 else
j3 2:02d228c25fd4 475 {
j3 2:02d228c25fd4 476 packet[0] = CMD_SRP;
j3 2:02d228c25fd4 477 packet[1] = 0xE1;
j3 2:02d228c25fd4 478
j3 2:02d228c25fd4 479 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 480 _p_i2c_bus->read(_r_adrs, &data, 1);
j3 2:02d228c25fd4 481
j3 2:02d228c25fd4 482 rtn_val = data;
j3 2:02d228c25fd4 483 }
j3 2:02d228c25fd4 484
j3 1:91e52f8ab8bf 485 return(rtn_val);
j3 1:91e52f8ab8bf 486 }
j3 1:91e52f8ab8bf 487
j3 1:91e52f8ab8bf 488
j3 1:91e52f8ab8bf 489 //*********************************************************************
j3 1:91e52f8ab8bf 490 uint8_t Ds248x::OWTouchByte(uint8_t sendbyte)
j3 1:91e52f8ab8bf 491 {
j3 1:91e52f8ab8bf 492 uint8_t rtn_val;
j3 2:02d228c25fd4 493
j3 2:02d228c25fd4 494 if (sendbyte == 0xFF)
j3 2:02d228c25fd4 495 {
j3 2:02d228c25fd4 496 rtn_val = OWReadByte();
j3 2:02d228c25fd4 497 }
j3 2:02d228c25fd4 498 else
j3 2:02d228c25fd4 499 {
j3 2:02d228c25fd4 500 OWWriteByte(sendbyte);
j3 2:02d228c25fd4 501 rtn_val = sendbyte;
j3 2:02d228c25fd4 502 }
j3 2:02d228c25fd4 503
j3 1:91e52f8ab8bf 504 return(rtn_val);
j3 1:91e52f8ab8bf 505 }
j3 1:91e52f8ab8bf 506
j3 1:91e52f8ab8bf 507
j3 1:91e52f8ab8bf 508 //*********************************************************************
j3 1:91e52f8ab8bf 509 void Ds248x::OWBlock(uint8_t *tran_buf, uint8_t tran_len)
j3 1:91e52f8ab8bf 510 {
j3 2:02d228c25fd4 511 uint8_t i;
j3 2:02d228c25fd4 512
j3 2:02d228c25fd4 513 for (i = 0; i < tran_len; i++)
j3 2:02d228c25fd4 514 {
j3 2:02d228c25fd4 515 tran_buf[i] = OWTouchByte(tran_buf[i]);
j3 2:02d228c25fd4 516 }
j3 1:91e52f8ab8bf 517 }
j3 1:91e52f8ab8bf 518
j3 1:91e52f8ab8bf 519
j3 1:91e52f8ab8bf 520 //*********************************************************************
j3 5:ce108eeb878d 521 void Ds248x::OWWriteBlock(const uint8_t *tran_buf, uint8_t tran_len)
j3 5:ce108eeb878d 522 {
j3 5:ce108eeb878d 523 uint8_t idx;
j3 5:ce108eeb878d 524
j3 5:ce108eeb878d 525 for(idx = 0; idx < tran_len; idx++)
j3 5:ce108eeb878d 526 {
j3 5:ce108eeb878d 527 OWWriteByte(tran_buf[idx]);
j3 5:ce108eeb878d 528 }
j3 5:ce108eeb878d 529 }
j3 5:ce108eeb878d 530
j3 5:ce108eeb878d 531
j3 5:ce108eeb878d 532 //*********************************************************************
j3 5:ce108eeb878d 533 void Ds248x::OWReadBlock(uint8_t *recv_buf, uint8_t recv_len)
j3 5:ce108eeb878d 534 {
j3 5:ce108eeb878d 535 uint8_t idx;
j3 5:ce108eeb878d 536
j3 5:ce108eeb878d 537 for(idx = 0; idx < recv_len; idx++)
j3 5:ce108eeb878d 538 {
j3 5:ce108eeb878d 539 recv_buf[idx] = OWReadByte();
j3 5:ce108eeb878d 540 }
j3 5:ce108eeb878d 541 }
j3 5:ce108eeb878d 542
j3 5:ce108eeb878d 543
j3 5:ce108eeb878d 544 //*********************************************************************
j3 2:02d228c25fd4 545 bool Ds248x::OWFirst(void)
j3 1:91e52f8ab8bf 546 {
j3 2:02d228c25fd4 547 // reset the search state
j3 2:02d228c25fd4 548 _last_discrepancy = 0;
j3 5:ce108eeb878d 549 _last_device_flag = false;
j3 2:02d228c25fd4 550 _last_family_discrepancy = 0;
j3 2:02d228c25fd4 551
j3 2:02d228c25fd4 552 return OWSearch();
j3 2:02d228c25fd4 553 }
j3 2:02d228c25fd4 554
j3 2:02d228c25fd4 555
j3 2:02d228c25fd4 556 //*********************************************************************
j3 2:02d228c25fd4 557 bool Ds248x::OWNext(void)
j3 2:02d228c25fd4 558 {
j3 2:02d228c25fd4 559 // leave the search state alone
j3 2:02d228c25fd4 560 return OWSearch();
j3 1:91e52f8ab8bf 561 }
j3 1:91e52f8ab8bf 562
j3 1:91e52f8ab8bf 563
j3 1:91e52f8ab8bf 564 //*********************************************************************
j3 2:02d228c25fd4 565 bool Ds248x::OWVerify(void)
j3 1:91e52f8ab8bf 566 {
j3 2:02d228c25fd4 567 bool rtn_val = false;
j3 2:02d228c25fd4 568
j3 2:02d228c25fd4 569 uint8_t rom_backup[8];
j3 2:02d228c25fd4 570 uint8_t i,rslt,ld_backup,ldf_backup,lfd_backup;
j3 2:02d228c25fd4 571
j3 2:02d228c25fd4 572 // keep a backup copy of the current state
j3 2:02d228c25fd4 573 for (i = 0; i < 8; i++)
j3 2:02d228c25fd4 574 {
j3 2:02d228c25fd4 575 rom_backup[i] = _rom_number[i];
j3 2:02d228c25fd4 576 }
j3 2:02d228c25fd4 577
j3 2:02d228c25fd4 578 ld_backup = _last_discrepancy;
j3 2:02d228c25fd4 579 ldf_backup = _last_device_flag;
j3 2:02d228c25fd4 580 lfd_backup = _last_family_discrepancy;
j3 2:02d228c25fd4 581
j3 2:02d228c25fd4 582 // set search to find the same device
j3 2:02d228c25fd4 583 _last_discrepancy = 64;
j3 5:ce108eeb878d 584 _last_device_flag = false;
j3 1:91e52f8ab8bf 585
j3 2:02d228c25fd4 586 if (OWSearch())
j3 2:02d228c25fd4 587 {
j3 2:02d228c25fd4 588 // check if same device found
j3 5:ce108eeb878d 589 rslt = true;
j3 2:02d228c25fd4 590 for (i = 0; i < 8; i++)
j3 2:02d228c25fd4 591 {
j3 2:02d228c25fd4 592 if (rom_backup[i] != _rom_number[i])
j3 2:02d228c25fd4 593 {
j3 5:ce108eeb878d 594 rslt = false;
j3 2:02d228c25fd4 595 break;
j3 2:02d228c25fd4 596 }
j3 2:02d228c25fd4 597 }
j3 2:02d228c25fd4 598 }
j3 2:02d228c25fd4 599 else
j3 2:02d228c25fd4 600 {
j3 5:ce108eeb878d 601 rslt = false;
j3 2:02d228c25fd4 602 }
j3 1:91e52f8ab8bf 603
j3 2:02d228c25fd4 604 // restore the search state
j3 2:02d228c25fd4 605 for (i = 0; i < 8; i++)
j3 2:02d228c25fd4 606 {
j3 2:02d228c25fd4 607 _rom_number[i] = rom_backup[i];
j3 2:02d228c25fd4 608 }
j3 2:02d228c25fd4 609
j3 2:02d228c25fd4 610 _last_discrepancy = ld_backup;
j3 2:02d228c25fd4 611 _last_device_flag = ldf_backup;
j3 2:02d228c25fd4 612 _last_family_discrepancy = lfd_backup;
j3 2:02d228c25fd4 613
j3 2:02d228c25fd4 614 // return the result of the verify
j3 2:02d228c25fd4 615 rtn_val = rslt;
j3 2:02d228c25fd4 616
j3 1:91e52f8ab8bf 617 return(rtn_val);
j3 1:91e52f8ab8bf 618 }
j3 1:91e52f8ab8bf 619
j3 1:91e52f8ab8bf 620
j3 1:91e52f8ab8bf 621 //*********************************************************************
j3 1:91e52f8ab8bf 622 void Ds248x::OWTargetSetup(uint8_t family_code)
j3 1:91e52f8ab8bf 623 {
j3 2:02d228c25fd4 624 uint8_t i;
j3 2:02d228c25fd4 625
j3 2:02d228c25fd4 626 // set the search state to find SearchFamily type devices
j3 2:02d228c25fd4 627 _rom_number[0] = family_code;
j3 2:02d228c25fd4 628 for (i = 1; i < 8; i++)
j3 2:02d228c25fd4 629 {
j3 2:02d228c25fd4 630 _rom_number[i] = 0;
j3 2:02d228c25fd4 631 }
j3 1:91e52f8ab8bf 632
j3 2:02d228c25fd4 633 _last_discrepancy = 64;
j3 2:02d228c25fd4 634 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 635 _last_device_flag = false;
j3 1:91e52f8ab8bf 636 }
j3 1:91e52f8ab8bf 637
j3 1:91e52f8ab8bf 638
j3 1:91e52f8ab8bf 639 //*********************************************************************
j3 1:91e52f8ab8bf 640 void Ds248x::OWFamilySkipSetup(void)
j3 1:91e52f8ab8bf 641 {
j3 2:02d228c25fd4 642 // set the Last discrepancy to last family discrepancy
j3 2:02d228c25fd4 643 _last_discrepancy = _last_family_discrepancy;
j3 1:91e52f8ab8bf 644
j3 2:02d228c25fd4 645 // clear the last family discrpepancy
j3 2:02d228c25fd4 646 _last_family_discrepancy = 0;
j3 2:02d228c25fd4 647
j3 2:02d228c25fd4 648 // check for end of list
j3 2:02d228c25fd4 649 if (_last_discrepancy == 0)
j3 2:02d228c25fd4 650 {
j3 5:ce108eeb878d 651 _last_device_flag = true;
j3 2:02d228c25fd4 652 }
j3 1:91e52f8ab8bf 653 }
j3 1:91e52f8ab8bf 654
j3 1:91e52f8ab8bf 655
j3 1:91e52f8ab8bf 656 //*********************************************************************
j3 2:02d228c25fd4 657 bool Ds248x::OWSearch(void)
j3 1:91e52f8ab8bf 658 {
j3 2:02d228c25fd4 659 uint8_t id_bit_number;
j3 2:02d228c25fd4 660 uint8_t last_zero, rom_byte_number, search_result;
j3 2:02d228c25fd4 661 uint8_t id_bit, cmp_id_bit;
j3 2:02d228c25fd4 662 uint8_t rom_byte_mask, search_direction, status;
j3 2:02d228c25fd4 663
j3 2:02d228c25fd4 664 // initialize for search
j3 2:02d228c25fd4 665 id_bit_number = 1;
j3 2:02d228c25fd4 666 last_zero = 0;
j3 2:02d228c25fd4 667 rom_byte_number = 0;
j3 2:02d228c25fd4 668 rom_byte_mask = 1;
j3 5:ce108eeb878d 669 search_result = false;
j3 2:02d228c25fd4 670 _crc8 = 0;
j3 2:02d228c25fd4 671
j3 2:02d228c25fd4 672 // if the last call was not the last one
j3 2:02d228c25fd4 673 if (!_last_device_flag)
j3 2:02d228c25fd4 674 {
j3 2:02d228c25fd4 675 // 1-Wire reset
j3 2:02d228c25fd4 676 if (!OWReset())
j3 2:02d228c25fd4 677 {
j3 2:02d228c25fd4 678 // reset the search
j3 2:02d228c25fd4 679 _last_discrepancy = 0;
j3 5:ce108eeb878d 680 _last_device_flag = false;
j3 2:02d228c25fd4 681 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 682 return false;
j3 2:02d228c25fd4 683 }
j3 2:02d228c25fd4 684
j3 2:02d228c25fd4 685 // issue the search command
j3 2:02d228c25fd4 686 OWWriteByte(SEARCH_ROM);
j3 2:02d228c25fd4 687
j3 2:02d228c25fd4 688 // loop to do the search
j3 2:02d228c25fd4 689 do
j3 2:02d228c25fd4 690 {
j3 2:02d228c25fd4 691 // if this discrepancy if before the Last Discrepancy
j3 2:02d228c25fd4 692 // on a previous next then pick the same as last time
j3 2:02d228c25fd4 693 if (id_bit_number < _last_discrepancy)
j3 2:02d228c25fd4 694 {
j3 2:02d228c25fd4 695 if ((_rom_number[rom_byte_number] & rom_byte_mask) > 0)
j3 2:02d228c25fd4 696 search_direction = 1;
j3 2:02d228c25fd4 697 else
j3 2:02d228c25fd4 698 search_direction = 0;
j3 2:02d228c25fd4 699 }
j3 2:02d228c25fd4 700 else
j3 2:02d228c25fd4 701 {
j3 2:02d228c25fd4 702 // if equal to last pick 1, if not then pick 0
j3 2:02d228c25fd4 703 if (id_bit_number == _last_discrepancy)
j3 2:02d228c25fd4 704 search_direction = 1;
j3 2:02d228c25fd4 705 else
j3 2:02d228c25fd4 706 search_direction = 0;
j3 2:02d228c25fd4 707 }
j3 2:02d228c25fd4 708
j3 2:02d228c25fd4 709 // Perform a triple operation on the ds2484 which will perform 2 read bits and 1 write bit
j3 2:02d228c25fd4 710 status = search_triplet(search_direction);
j3 2:02d228c25fd4 711
j3 2:02d228c25fd4 712 // check bit results in status byte
j3 2:02d228c25fd4 713 id_bit = ((status & STATUS_SBR) == STATUS_SBR);
j3 2:02d228c25fd4 714 cmp_id_bit = ((status & STATUS_TSB) == STATUS_TSB);
j3 2:02d228c25fd4 715 search_direction = ((status & STATUS_DIR) == STATUS_DIR) ? (unsigned char)1 : (unsigned char)0;
j3 2:02d228c25fd4 716
j3 2:02d228c25fd4 717 // check for no devices on 1-Wire
j3 2:02d228c25fd4 718 if ((id_bit) && (cmp_id_bit))
j3 2:02d228c25fd4 719 break;
j3 2:02d228c25fd4 720 else
j3 2:02d228c25fd4 721 {
j3 2:02d228c25fd4 722 if ((!id_bit) && (!cmp_id_bit) && (search_direction == 0))
j3 2:02d228c25fd4 723 {
j3 2:02d228c25fd4 724 last_zero = id_bit_number;
j3 2:02d228c25fd4 725
j3 2:02d228c25fd4 726 // check for Last discrepancy in family
j3 2:02d228c25fd4 727 if (last_zero < 9)
j3 2:02d228c25fd4 728 _last_family_discrepancy = last_zero;
j3 2:02d228c25fd4 729 }
j3 2:02d228c25fd4 730
j3 2:02d228c25fd4 731 // set or clear the bit in the ROM byte rom_byte_number
j3 2:02d228c25fd4 732 // with mask rom_byte_mask
j3 2:02d228c25fd4 733 if (search_direction == 1)
j3 2:02d228c25fd4 734 _rom_number[rom_byte_number] |= rom_byte_mask;
j3 2:02d228c25fd4 735 else
j3 2:02d228c25fd4 736 _rom_number[rom_byte_number] &= (unsigned char)~rom_byte_mask;
j3 2:02d228c25fd4 737
j3 2:02d228c25fd4 738 // increment the byte counter id_bit_number
j3 2:02d228c25fd4 739 // and shift the mask rom_byte_mask
j3 2:02d228c25fd4 740 id_bit_number++;
j3 2:02d228c25fd4 741 rom_byte_mask <<= 1;
j3 2:02d228c25fd4 742
j3 2:02d228c25fd4 743 // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
j3 2:02d228c25fd4 744 if (rom_byte_mask == 0)
j3 2:02d228c25fd4 745 {
j3 5:ce108eeb878d 746 _crc8 = OWCalc_crc8(_rom_number[rom_byte_number], _crc8); // accumulate the CRC
j3 2:02d228c25fd4 747 rom_byte_number++;
j3 2:02d228c25fd4 748 rom_byte_mask = 1;
j3 2:02d228c25fd4 749 }
j3 2:02d228c25fd4 750 }
j3 2:02d228c25fd4 751 }
j3 2:02d228c25fd4 752 while(rom_byte_number < 8); // loop until through all ROM bytes 0-7
j3 2:02d228c25fd4 753
j3 2:02d228c25fd4 754 // if the search was successful then
j3 2:02d228c25fd4 755 if (!((id_bit_number < 65) || (_crc8 != 0)))
j3 2:02d228c25fd4 756 {
j3 2:02d228c25fd4 757 // search successful so set LastDiscrepancy,LastDeviceFlag,search_result
j3 2:02d228c25fd4 758 _last_discrepancy = last_zero;
j3 2:02d228c25fd4 759
j3 2:02d228c25fd4 760 // check for last device
j3 2:02d228c25fd4 761 if (_last_discrepancy == 0)
j3 5:ce108eeb878d 762 _last_device_flag = true;
j3 2:02d228c25fd4 763
j3 5:ce108eeb878d 764 search_result = true;
j3 2:02d228c25fd4 765 }
j3 2:02d228c25fd4 766 }
j3 2:02d228c25fd4 767
j3 2:02d228c25fd4 768 // if no device found then reset counters so next 'search' will be like a first
j3 2:02d228c25fd4 769 if (!search_result || (_rom_number[0] == 0))
j3 2:02d228c25fd4 770 {
j3 2:02d228c25fd4 771 _last_discrepancy = 0;
j3 5:ce108eeb878d 772 _last_device_flag = false;
j3 2:02d228c25fd4 773 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 774 search_result = false;
j3 2:02d228c25fd4 775 }
j3 2:02d228c25fd4 776
j3 2:02d228c25fd4 777 return search_result;
j3 1:91e52f8ab8bf 778 }
j3 1:91e52f8ab8bf 779
j3 1:91e52f8ab8bf 780
j3 1:91e52f8ab8bf 781 //*********************************************************************
j3 5:ce108eeb878d 782 bool Ds248x::OWReadROM(void)
j3 5:ce108eeb878d 783 {
j3 5:ce108eeb878d 784 bool rtn_val = false;
j3 5:ce108eeb878d 785
j3 5:ce108eeb878d 786 if(!OWReset())
j3 5:ce108eeb878d 787 {
j3 5:ce108eeb878d 788 rtn_val = false;
j3 5:ce108eeb878d 789 }
j3 5:ce108eeb878d 790 else
j3 5:ce108eeb878d 791 {
j3 5:ce108eeb878d 792 if(!OWWriteByte(READ_ROM))
j3 5:ce108eeb878d 793 {
j3 5:ce108eeb878d 794 rtn_val = false;
j3 5:ce108eeb878d 795 }
j3 5:ce108eeb878d 796 else
j3 5:ce108eeb878d 797 {
j3 5:ce108eeb878d 798 OWReadBlock(_rom_number, ROMnumberLen);
j3 5:ce108eeb878d 799 rtn_val = true;
j3 5:ce108eeb878d 800 }
j3 5:ce108eeb878d 801 }
j3 5:ce108eeb878d 802
j3 5:ce108eeb878d 803 return rtn_val;
j3 5:ce108eeb878d 804 }
j3 5:ce108eeb878d 805
j3 5:ce108eeb878d 806
j3 5:ce108eeb878d 807 //*********************************************************************
j3 5:ce108eeb878d 808 bool Ds248x::OWSkipROM(void)
j3 5:ce108eeb878d 809 {
j3 5:ce108eeb878d 810 bool rtn_val = false;
j3 5:ce108eeb878d 811
j3 5:ce108eeb878d 812 if(!OWReset())
j3 5:ce108eeb878d 813 {
j3 5:ce108eeb878d 814 rtn_val = false;
j3 5:ce108eeb878d 815 }
j3 5:ce108eeb878d 816 else
j3 5:ce108eeb878d 817 {
j3 5:ce108eeb878d 818 if(!OWWriteByte(SKIP_ROM))
j3 5:ce108eeb878d 819 {
j3 5:ce108eeb878d 820 rtn_val = false;
j3 5:ce108eeb878d 821 }
j3 5:ce108eeb878d 822 else
j3 5:ce108eeb878d 823 {
j3 5:ce108eeb878d 824 rtn_val = true;
j3 5:ce108eeb878d 825 }
j3 5:ce108eeb878d 826 }
j3 5:ce108eeb878d 827
j3 5:ce108eeb878d 828 return rtn_val;
j3 5:ce108eeb878d 829 }
j3 5:ce108eeb878d 830
j3 5:ce108eeb878d 831
j3 5:ce108eeb878d 832 //*********************************************************************
j3 5:ce108eeb878d 833 bool Ds248x::OWMatchROM(void)
j3 5:ce108eeb878d 834 {
j3 5:ce108eeb878d 835 bool rtn_val = false;
j3 5:ce108eeb878d 836 uint8_t idx;
j3 5:ce108eeb878d 837
j3 5:ce108eeb878d 838 if(!OWReset())
j3 5:ce108eeb878d 839 {
j3 5:ce108eeb878d 840 rtn_val = false;
j3 5:ce108eeb878d 841 }
j3 5:ce108eeb878d 842 else
j3 5:ce108eeb878d 843 {
j3 5:ce108eeb878d 844 if(!OWWriteByte(MATCH_ROM))
j3 5:ce108eeb878d 845 {
j3 5:ce108eeb878d 846 rtn_val = false;
j3 5:ce108eeb878d 847 }
j3 5:ce108eeb878d 848 else
j3 5:ce108eeb878d 849 {
j3 5:ce108eeb878d 850 for(idx = 0; idx < ROMnumberLen; idx++)
j3 5:ce108eeb878d 851 {
j3 5:ce108eeb878d 852 OWWriteByte(_rom_number[idx]);
j3 5:ce108eeb878d 853 }
j3 5:ce108eeb878d 854 rtn_val = true;
j3 5:ce108eeb878d 855 }
j3 5:ce108eeb878d 856 }
j3 5:ce108eeb878d 857
j3 5:ce108eeb878d 858 return rtn_val;
j3 5:ce108eeb878d 859 }
j3 5:ce108eeb878d 860
j3 5:ce108eeb878d 861
j3 5:ce108eeb878d 862 //*********************************************************************
j3 5:ce108eeb878d 863 bool Ds248x::OWOverdriveSkipROM(void)
j3 5:ce108eeb878d 864 {
j3 5:ce108eeb878d 865 bool rtn_val = false;
j3 5:ce108eeb878d 866
j3 5:ce108eeb878d 867 if(!OWReset())
j3 5:ce108eeb878d 868 {
j3 5:ce108eeb878d 869 rtn_val = false;
j3 5:ce108eeb878d 870 }
j3 5:ce108eeb878d 871 else
j3 5:ce108eeb878d 872 {
j3 5:ce108eeb878d 873 if(!OWWriteByte(OVERDRIVE_SKIP))
j3 5:ce108eeb878d 874 {
j3 5:ce108eeb878d 875 rtn_val = false;
j3 5:ce108eeb878d 876 }
j3 5:ce108eeb878d 877 else
j3 5:ce108eeb878d 878 {
j3 5:ce108eeb878d 879 //change speed for subsequent comands
j3 5:ce108eeb878d 880 OWSpeed(SPEED_OVERDRIVE);
j3 5:ce108eeb878d 881 rtn_val = true;
j3 5:ce108eeb878d 882 }
j3 5:ce108eeb878d 883 }
j3 5:ce108eeb878d 884
j3 5:ce108eeb878d 885 return rtn_val;
j3 5:ce108eeb878d 886 }
j3 5:ce108eeb878d 887
j3 5:ce108eeb878d 888
j3 5:ce108eeb878d 889 //*********************************************************************
j3 5:ce108eeb878d 890 bool Ds248x::OWOverdriveMatchROM(void)
j3 5:ce108eeb878d 891 {
j3 5:ce108eeb878d 892 bool rtn_val = false;
j3 5:ce108eeb878d 893 uint8_t idx;
j3 5:ce108eeb878d 894
j3 5:ce108eeb878d 895 if(!OWReset())
j3 5:ce108eeb878d 896 {
j3 5:ce108eeb878d 897 rtn_val = false;
j3 5:ce108eeb878d 898 }
j3 5:ce108eeb878d 899 else
j3 5:ce108eeb878d 900 {
j3 5:ce108eeb878d 901 if(!OWWriteByte(OVERDRIVE_MATCH))
j3 5:ce108eeb878d 902 {
j3 5:ce108eeb878d 903 rtn_val = false;
j3 5:ce108eeb878d 904 }
j3 5:ce108eeb878d 905 else
j3 5:ce108eeb878d 906 {
j3 5:ce108eeb878d 907 //change speed before sending ROM number
j3 5:ce108eeb878d 908 OWSpeed(SPEED_OVERDRIVE);
j3 5:ce108eeb878d 909
j3 5:ce108eeb878d 910 for(idx = 0; idx < ROMnumberLen; idx++)
j3 5:ce108eeb878d 911 {
j3 5:ce108eeb878d 912 OWWriteByte(_rom_number[idx]);
j3 5:ce108eeb878d 913 }
j3 5:ce108eeb878d 914 rtn_val = true;
j3 5:ce108eeb878d 915 }
j3 5:ce108eeb878d 916 }
j3 5:ce108eeb878d 917
j3 5:ce108eeb878d 918 return rtn_val;
j3 5:ce108eeb878d 919 }
j3 5:ce108eeb878d 920
j3 5:ce108eeb878d 921
j3 5:ce108eeb878d 922 //*********************************************************************
j3 5:ce108eeb878d 923 bool Ds248x::OWResume(void)
j3 5:ce108eeb878d 924 {
j3 5:ce108eeb878d 925 bool rtn_val = false;
j3 5:ce108eeb878d 926
j3 5:ce108eeb878d 927 if(!OWReset())
j3 5:ce108eeb878d 928 {
j3 5:ce108eeb878d 929 rtn_val = false;
j3 5:ce108eeb878d 930 }
j3 5:ce108eeb878d 931 else
j3 5:ce108eeb878d 932 {
j3 5:ce108eeb878d 933 if(!OWWriteByte(RESUME))
j3 5:ce108eeb878d 934 {
j3 5:ce108eeb878d 935 rtn_val = false;
j3 5:ce108eeb878d 936 }
j3 5:ce108eeb878d 937 else
j3 5:ce108eeb878d 938 {
j3 5:ce108eeb878d 939 rtn_val = true;
j3 5:ce108eeb878d 940 }
j3 5:ce108eeb878d 941 }
j3 5:ce108eeb878d 942
j3 5:ce108eeb878d 943 return rtn_val;
j3 5:ce108eeb878d 944 }
j3 5:ce108eeb878d 945
j3 5:ce108eeb878d 946
j3 5:ce108eeb878d 947 //*********************************************************************
j3 5:ce108eeb878d 948 uint8_t Ds248x::OWSpeed(OW_SPEED new_speed)
j3 1:91e52f8ab8bf 949 {
j3 2:02d228c25fd4 950 // set the speed
j3 5:ce108eeb878d 951 if (new_speed == SPEED_OVERDRIVE)
j3 2:02d228c25fd4 952 {
j3 2:02d228c25fd4 953 _c1WS = CONFIG_1WS;
j3 2:02d228c25fd4 954 }
j3 2:02d228c25fd4 955 else
j3 2:02d228c25fd4 956 {
j3 5:ce108eeb878d 957 _c1WS = false;
j3 2:02d228c25fd4 958 }
j3 2:02d228c25fd4 959
j3 2:02d228c25fd4 960 // write the new config
j3 2:02d228c25fd4 961 write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 2:02d228c25fd4 962
j3 2:02d228c25fd4 963 return(new_speed);
j3 1:91e52f8ab8bf 964 }
j3 1:91e52f8ab8bf 965
j3 1:91e52f8ab8bf 966
j3 1:91e52f8ab8bf 967 //*********************************************************************
j3 5:ce108eeb878d 968 uint8_t Ds248x::OWLevel(OW_LEVEL new_level)
j3 1:91e52f8ab8bf 969 {
j3 1:91e52f8ab8bf 970 uint8_t rtn_val;
j3 2:02d228c25fd4 971
j3 2:02d228c25fd4 972 // function only will turn back to non-strong pull-up
j3 5:ce108eeb878d 973 if (new_level != LEVEL_NORMAL)
j3 2:02d228c25fd4 974 {
j3 5:ce108eeb878d 975 rtn_val = LEVEL_STRONG;
j3 2:02d228c25fd4 976 }
j3 2:02d228c25fd4 977 else
j3 2:02d228c25fd4 978 {
j3 2:02d228c25fd4 979 // clear the strong pull-up bit in the global config state
j3 5:ce108eeb878d 980 _cSPU = false;
j3 2:02d228c25fd4 981 // write the new config
j3 2:02d228c25fd4 982 write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 5:ce108eeb878d 983 rtn_val = LEVEL_NORMAL;
j3 2:02d228c25fd4 984 }
j3 2:02d228c25fd4 985
j3 1:91e52f8ab8bf 986 return(rtn_val);
j3 1:91e52f8ab8bf 987 }
j3 1:91e52f8ab8bf 988
j3 1:91e52f8ab8bf 989
j3 1:91e52f8ab8bf 990 //*********************************************************************
j3 2:02d228c25fd4 991 bool Ds248x::OWWriteBytePower(uint8_t sendbyte)
j3 1:91e52f8ab8bf 992 {
j3 2:02d228c25fd4 993 bool rtn_val = false;
j3 2:02d228c25fd4 994
j3 2:02d228c25fd4 995 // set strong pull-up enable
j3 2:02d228c25fd4 996 _cSPU = CONFIG_SPU;
j3 2:02d228c25fd4 997
j3 2:02d228c25fd4 998 // write the new config
j3 2:02d228c25fd4 999 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 1000 {
j3 2:02d228c25fd4 1001 rtn_val = false;
j3 2:02d228c25fd4 1002 }
j3 2:02d228c25fd4 1003 else
j3 2:02d228c25fd4 1004 {
j3 2:02d228c25fd4 1005 // perform write byte
j3 2:02d228c25fd4 1006 OWWriteByte(sendbyte);
j3 2:02d228c25fd4 1007 rtn_val = true;
j3 2:02d228c25fd4 1008 }
j3 2:02d228c25fd4 1009
j3 1:91e52f8ab8bf 1010 return(rtn_val);
j3 1:91e52f8ab8bf 1011 }
j3 1:91e52f8ab8bf 1012
j3 1:91e52f8ab8bf 1013
j3 1:91e52f8ab8bf 1014 //*********************************************************************
j3 2:02d228c25fd4 1015 bool Ds248x::OWReadBitPower(uint8_t applyPowerResponse)
j3 1:91e52f8ab8bf 1016 {
j3 2:02d228c25fd4 1017 bool rtn_val = false;
j3 2:02d228c25fd4 1018
j3 2:02d228c25fd4 1019 uint8_t rdbit;
j3 2:02d228c25fd4 1020
j3 2:02d228c25fd4 1021 // set strong pull-up enable
j3 2:02d228c25fd4 1022 _cSPU = CONFIG_SPU;
j3 2:02d228c25fd4 1023
j3 2:02d228c25fd4 1024 // write the new config
j3 2:02d228c25fd4 1025 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 1026 {
j3 2:02d228c25fd4 1027 rtn_val = false;
j3 2:02d228c25fd4 1028 }
j3 2:02d228c25fd4 1029 else
j3 2:02d228c25fd4 1030 {
j3 2:02d228c25fd4 1031 // perform read bit
j3 2:02d228c25fd4 1032 rdbit = OWReadBit();
j3 2:02d228c25fd4 1033
j3 2:02d228c25fd4 1034 // check if response was correct, if not then turn off strong pull-up
j3 2:02d228c25fd4 1035 if (rdbit != applyPowerResponse)
j3 2:02d228c25fd4 1036 {
j3 5:ce108eeb878d 1037 OWLevel(LEVEL_NORMAL);
j3 2:02d228c25fd4 1038 rtn_val = false;
j3 2:02d228c25fd4 1039 }
j3 2:02d228c25fd4 1040
j3 2:02d228c25fd4 1041 rtn_val = true;
j3 2:02d228c25fd4 1042 }
j3 2:02d228c25fd4 1043
j3 1:91e52f8ab8bf 1044 return(rtn_val);
j3 1:91e52f8ab8bf 1045 }
j3 1:91e52f8ab8bf 1046
j3 1:91e52f8ab8bf 1047
j3 1:91e52f8ab8bf 1048 //*********************************************************************
j3 5:ce108eeb878d 1049 const uint8_t (&Ds248x::OWgetROMnumber() const)[ROMnumberLen]
j3 1:91e52f8ab8bf 1050 {
j3 5:ce108eeb878d 1051 return _rom_number;
j3 2:02d228c25fd4 1052 }
j3 6:1faafa0b3cd7 1053
j3 6:1faafa0b3cd7 1054
j3 6:1faafa0b3cd7 1055 //*********************************************************************
j3 6:1faafa0b3cd7 1056 void Ds248x::set_i2c_adrs(DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 1057 {
j3 6:1faafa0b3cd7 1058 _w_adrs = (adrs << 1);
j3 6:1faafa0b3cd7 1059 _r_adrs = (_w_adrs | 1);
j3 6:1faafa0b3cd7 1060 }