Maxim Integrated / OneWire

1-Wire® library for mbed. Complete 1-Wire library that supports our silicon masters along with a bit-bang master on the MAX32600MBED platform with one common interface for mbed. Slave support has also been included and more slaves will be added as time permits.

Dependents:   MAXREFDES131_Qt_Demo MAX32630FTHR_iButton_uSD_Logger MAX32630FTHR_DS18B20_uSD_Logger MAXREFDES130_131_Demo ... more

Superseded by MaximInterface.

OneWire_Masters/DS248x/ds248x.cpp@6:1faafa0b3cd7, 2016-02-09 (annotated)

Committer:
j3
Date:
Tue Feb 09 20:08:51 2016 +0000
Revision:
6:1faafa0b3cd7
Parent:
5:ce108eeb878d
Child:
14:7b2886a50321
removed private constructor for setting i2c adrs from Ds248x class and added private fx which is used in body of other constructors.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 1:91e52f8ab8bf 1 /******************************************************************//**
j3 1:91e52f8ab8bf 2 * @file ds248x.cpp
j3 1:91e52f8ab8bf 3 *
j3 1:91e52f8ab8bf 4 * @author Justin Jordan
j3 1:91e52f8ab8bf 5 *
j3 1:91e52f8ab8bf 6 * @version 0.0.0
j3 1:91e52f8ab8bf 7 *
j3 1:91e52f8ab8bf 8 * Started: 30JAN16
j3 1:91e52f8ab8bf 9 *
j3 1:91e52f8ab8bf 10 * Updated:
j3 1:91e52f8ab8bf 11 *
j3 1:91e52f8ab8bf 12 * @brief Source file for Ds248x I2C to 1-wire master
j3 1:91e52f8ab8bf 13 ***********************************************************************
j3 1:91e52f8ab8bf 14 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 1:91e52f8ab8bf 15 *
j3 1:91e52f8ab8bf 16 * Permission is hereby granted, free of charge, to any person obtaining a
j3 1:91e52f8ab8bf 17 * copy of this software and associated documentation files (the "Software"),
j3 1:91e52f8ab8bf 18 * to deal in the Software without restriction, including without limitation
j3 1:91e52f8ab8bf 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 1:91e52f8ab8bf 20 * and/or sell copies of the Software, and to permit persons to whom the
j3 1:91e52f8ab8bf 21 * Software is furnished to do so, subject to the following conditions:
j3 1:91e52f8ab8bf 22 *
j3 1:91e52f8ab8bf 23 * The above copyright notice and this permission notice shall be included
j3 1:91e52f8ab8bf 24 * in all copies or substantial portions of the Software.
j3 1:91e52f8ab8bf 25 *
j3 1:91e52f8ab8bf 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 1:91e52f8ab8bf 27 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 1:91e52f8ab8bf 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 1:91e52f8ab8bf 29 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 1:91e52f8ab8bf 30 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 1:91e52f8ab8bf 31 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 1:91e52f8ab8bf 32 * OTHER DEALINGS IN THE SOFTWARE.
j3 1:91e52f8ab8bf 33 *
j3 1:91e52f8ab8bf 34 * Except as contained in this notice, the name of Maxim Integrated
j3 1:91e52f8ab8bf 35 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 1:91e52f8ab8bf 36 * Products, Inc. Branding Policy.
j3 1:91e52f8ab8bf 37 *
j3 1:91e52f8ab8bf 38 * The mere transfer of this software does not imply any licenses
j3 1:91e52f8ab8bf 39 * of trade secrets, proprietary technology, copyrights, patents,
j3 1:91e52f8ab8bf 40 * trademarks, maskwork rights, or any other form of intellectual
j3 1:91e52f8ab8bf 41 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 1:91e52f8ab8bf 42 * ownership rights.
j3 1:91e52f8ab8bf 43 **********************************************************************/
j3 1:91e52f8ab8bf 44
j3 1:91e52f8ab8bf 45
j3 1:91e52f8ab8bf 46 #include "ds248x.h"
j3 1:91e52f8ab8bf 47
j3 1:91e52f8ab8bf 48
j3 1:91e52f8ab8bf 49 //*********************************************************************
j3 5:ce108eeb878d 50 Ds248x::Ds248x(I2C &i2c_bus, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 51 :_p_i2c_bus(&i2c_bus), _i2c_owner(false)
j3 1:91e52f8ab8bf 52 {
j3 6:1faafa0b3cd7 53 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 54 }
j3 1:91e52f8ab8bf 55
j3 1:91e52f8ab8bf 56
j3 1:91e52f8ab8bf 57 //*********************************************************************
j3 5:ce108eeb878d 58 Ds248x::Ds248x(PinName sda, PinName scl, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 59 :_p_i2c_bus(new I2C(sda, scl)), _i2c_owner(true)
j3 1:91e52f8ab8bf 60 {
j3 6:1faafa0b3cd7 61 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 62 }
j3 1:91e52f8ab8bf 63
j3 1:91e52f8ab8bf 64
j3 1:91e52f8ab8bf 65 //*********************************************************************
j3 1:91e52f8ab8bf 66 Ds248x::~Ds248x()
j3 1:91e52f8ab8bf 67 {
j3 5:ce108eeb878d 68 if(_i2c_owner)
j3 1:91e52f8ab8bf 69 {
j3 1:91e52f8ab8bf 70 delete _p_i2c_bus;
j3 1:91e52f8ab8bf 71 }
j3 1:91e52f8ab8bf 72 }
j3 1:91e52f8ab8bf 73
j3 1:91e52f8ab8bf 74
j3 1:91e52f8ab8bf 75 //*********************************************************************
j3 2:02d228c25fd4 76 bool Ds248x::detect(void)
j3 2:02d228c25fd4 77 {
j3 2:02d228c25fd4 78 bool rtn_val = false;
j3 2:02d228c25fd4 79
j3 2:02d228c25fd4 80 // reset the ds2484 ON selected address
j3 2:02d228c25fd4 81 if (!reset())
j3 2:02d228c25fd4 82 {
j3 2:02d228c25fd4 83 rtn_val = false;
j3 2:02d228c25fd4 84 }
j3 2:02d228c25fd4 85 else
j3 2:02d228c25fd4 86 {
j3 2:02d228c25fd4 87 // default configuration
j3 5:ce108eeb878d 88 _c1WS = false;
j3 5:ce108eeb878d 89 _cSPU = false;
j3 5:ce108eeb878d 90 _cPDN = false;
j3 5:ce108eeb878d 91 _cAPU = false;
j3 2:02d228c25fd4 92
j3 2:02d228c25fd4 93 // write the default configuration setup
j3 2:02d228c25fd4 94 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 95 {
j3 2:02d228c25fd4 96 rtn_val = false;
j3 2:02d228c25fd4 97 }
j3 2:02d228c25fd4 98 else
j3 2:02d228c25fd4 99 {
j3 2:02d228c25fd4 100 rtn_val = true;
j3 2:02d228c25fd4 101 }
j3 2:02d228c25fd4 102 }
j3 2:02d228c25fd4 103
j3 2:02d228c25fd4 104 return(rtn_val);
j3 2:02d228c25fd4 105 }
j3 2:02d228c25fd4 106
j3 2:02d228c25fd4 107
j3 2:02d228c25fd4 108 //*********************************************************************
j3 2:02d228c25fd4 109 bool Ds248x::reset(void)
j3 1:91e52f8ab8bf 110 {
j3 2:02d228c25fd4 111 char status;
j3 2:02d228c25fd4 112 char packet[] = {CMD_DRST};
j3 2:02d228c25fd4 113
j3 2:02d228c25fd4 114 // Device Reset
j3 2:02d228c25fd4 115 // S AD,0 [A] DRST [A] Sr AD,1 [A] [SS] A\ P
j3 2:02d228c25fd4 116 // [] indicates from slave
j3 2:02d228c25fd4 117 // SS status byte to read to verify state
j3 2:02d228c25fd4 118
j3 2:02d228c25fd4 119 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 120 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 121
j3 2:02d228c25fd4 122 return((status & 0xF7) == 0x10);
j3 2:02d228c25fd4 123 }
j3 2:02d228c25fd4 124
j3 2:02d228c25fd4 125
j3 2:02d228c25fd4 126 //*********************************************************************
j3 2:02d228c25fd4 127 bool Ds248x::write_config(uint8_t config)
j3 2:02d228c25fd4 128 {
j3 2:02d228c25fd4 129 bool rtn_val = false;
j3 2:02d228c25fd4 130 char read_config;
j3 2:02d228c25fd4 131 char packet [] = {CMD_WCFG, (config | (~config << 4))};
j3 2:02d228c25fd4 132
j3 2:02d228c25fd4 133 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 134 _p_i2c_bus->read(_r_adrs, &read_config, 1);
j3 2:02d228c25fd4 135
j3 2:02d228c25fd4 136 // check for failure due to incorrect read back
j3 2:02d228c25fd4 137 if (config != read_config)
j3 2:02d228c25fd4 138 {
j3 2:02d228c25fd4 139 // handle error
j3 2:02d228c25fd4 140 // ...
j3 2:02d228c25fd4 141 reset();
j3 2:02d228c25fd4 142 rtn_val = false;
j3 2:02d228c25fd4 143 }
j3 2:02d228c25fd4 144 else
j3 2:02d228c25fd4 145 {
j3 2:02d228c25fd4 146 rtn_val = true;
j3 2:02d228c25fd4 147 }
j3 2:02d228c25fd4 148
j3 1:91e52f8ab8bf 149 return(rtn_val);
j3 1:91e52f8ab8bf 150 }
j3 1:91e52f8ab8bf 151
j3 1:91e52f8ab8bf 152
j3 1:91e52f8ab8bf 153 //*********************************************************************
j3 2:02d228c25fd4 154 bool Ds248x::channel_select(uint8_t channel)
j3 1:91e52f8ab8bf 155 {
j3 2:02d228c25fd4 156
j3 2:02d228c25fd4 157 char ch, ch_read, check;
j3 2:02d228c25fd4 158 char packet [2];
j3 2:02d228c25fd4 159
j3 2:02d228c25fd4 160 packet[0] = CMD_CHSL;
j3 2:02d228c25fd4 161
j3 2:02d228c25fd4 162 // Channel Select (Case A)
j3 2:02d228c25fd4 163 // S AD,0 [A] CHSL [A] CC [A] Sr AD,1 [A] [RR] A\ P
j3 2:02d228c25fd4 164 // [] indicates from slave
j3 2:02d228c25fd4 165 // CC channel value
j3 2:02d228c25fd4 166 // RR channel read back
j3 2:02d228c25fd4 167
j3 2:02d228c25fd4 168 switch (channel)
j3 2:02d228c25fd4 169 {
j3 2:02d228c25fd4 170 default: case 0: ch = 0xF0; ch_read = 0xB8; break;
j3 2:02d228c25fd4 171 case 1: ch = 0xE1; ch_read = 0xB1; break;
j3 2:02d228c25fd4 172 case 2: ch = 0xD2; ch_read = 0xAA; break;
j3 2:02d228c25fd4 173 case 3: ch = 0xC3; ch_read = 0xA3; break;
j3 2:02d228c25fd4 174 case 4: ch = 0xB4; ch_read = 0x9C; break;
j3 2:02d228c25fd4 175 case 5: ch = 0xA5; ch_read = 0x95; break;
j3 2:02d228c25fd4 176 case 6: ch = 0x96; ch_read = 0x8E; break;
j3 2:02d228c25fd4 177 case 7: ch = 0x87; ch_read = 0x87; break;
j3 2:02d228c25fd4 178 };
j3 2:02d228c25fd4 179
j3 2:02d228c25fd4 180 packet[1] = ch;
j3 2:02d228c25fd4 181
j3 2:02d228c25fd4 182 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 183 _p_i2c_bus->read(_r_adrs, &check, 1);
j3 2:02d228c25fd4 184
j3 2:02d228c25fd4 185 // check for failure due to incorrect read back of channel
j3 2:02d228c25fd4 186 return (check == ch_read);
j3 2:02d228c25fd4 187 }
j3 2:02d228c25fd4 188
j3 2:02d228c25fd4 189
j3 2:02d228c25fd4 190 //*********************************************************************
j3 2:02d228c25fd4 191 bool Ds248x::adjust_timing(uint8_t param, uint8_t val)
j3 2:02d228c25fd4 192 {
j3 2:02d228c25fd4 193 bool rtn_val = false;
j3 2:02d228c25fd4 194 char read_port_config;
j3 2:02d228c25fd4 195 char control_byte;
j3 2:02d228c25fd4 196
j3 2:02d228c25fd4 197 control_byte = (((param & 0x0F) << 4) | (val & 0x0F));
j3 2:02d228c25fd4 198
j3 2:02d228c25fd4 199 char packet [] = {CMD_A1WP, control_byte};
j3 2:02d228c25fd4 200
j3 2:02d228c25fd4 201 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 202 _p_i2c_bus->read(_r_adrs, &read_port_config, 1);
j3 2:02d228c25fd4 203
j3 2:02d228c25fd4 204 // check for failure due to incorrect read back
j3 2:02d228c25fd4 205 if ((control_byte & 0x0F) != read_port_config)
j3 2:02d228c25fd4 206 {
j3 2:02d228c25fd4 207 // handle error
j3 2:02d228c25fd4 208 // ...
j3 2:02d228c25fd4 209 reset();
j3 2:02d228c25fd4 210
j3 2:02d228c25fd4 211 rtn_val = false;
j3 2:02d228c25fd4 212 }
j3 2:02d228c25fd4 213 else
j3 2:02d228c25fd4 214 {
j3 2:02d228c25fd4 215 rtn_val = true;
j3 2:02d228c25fd4 216 }
j3 2:02d228c25fd4 217
j3 2:02d228c25fd4 218 return(rtn_val);
j3 1:91e52f8ab8bf 219 }
j3 1:91e52f8ab8bf 220
j3 1:91e52f8ab8bf 221
j3 1:91e52f8ab8bf 222 //*********************************************************************
j3 2:02d228c25fd4 223 uint8_t Ds248x::search_triplet(uint8_t search_direction)
j3 1:91e52f8ab8bf 224 {
j3 2:02d228c25fd4 225 uint8_t rtn_val = 0;
j3 2:02d228c25fd4 226 uint8_t poll_count = 0;
j3 2:02d228c25fd4 227 char status;
j3 2:02d228c25fd4 228 char packet [] = {CMD_1WT, search_direction ? 0x80 : 0x00};
j3 2:02d228c25fd4 229
j3 2:02d228c25fd4 230 // 1-Wire Triplet (Case B)
j3 2:02d228c25fd4 231 // S AD,0 [A] 1WT [A] SS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 232 // \--------/
j3 2:02d228c25fd4 233 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 234 // [] indicates from slave
j3 2:02d228c25fd4 235 // SS indicates byte containing search direction bit value in msbit
j3 2:02d228c25fd4 236
j3 2:02d228c25fd4 237 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 238
j3 2:02d228c25fd4 239 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 240 // abort if poll limit reached
j3 2:02d228c25fd4 241 do
j3 2:02d228c25fd4 242 {
j3 2:02d228c25fd4 243 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 244 }
j3 2:02d228c25fd4 245 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 246
j3 2:02d228c25fd4 247 // check for failure due to poll limit reached
j3 2:02d228c25fd4 248 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 249 {
j3 2:02d228c25fd4 250 // handle error
j3 2:02d228c25fd4 251 // ...
j3 2:02d228c25fd4 252 reset();
j3 5:ce108eeb878d 253 rtn_val = false;
j3 2:02d228c25fd4 254 }
j3 2:02d228c25fd4 255 else
j3 2:02d228c25fd4 256 {
j3 2:02d228c25fd4 257 rtn_val = status;
j3 2:02d228c25fd4 258 }
j3 2:02d228c25fd4 259
j3 2:02d228c25fd4 260 return(rtn_val);
j3 1:91e52f8ab8bf 261 }
j3 1:91e52f8ab8bf 262
j3 1:91e52f8ab8bf 263
j3 1:91e52f8ab8bf 264 //*********************************************************************
j3 2:02d228c25fd4 265 bool Ds248x::OWReset()
j3 2:02d228c25fd4 266 {
j3 2:02d228c25fd4 267 bool rtn_val = false;
j3 2:02d228c25fd4 268
j3 2:02d228c25fd4 269 uint8_t poll_count = 0;
j3 2:02d228c25fd4 270 char status;
j3 2:02d228c25fd4 271 char packet [] = {CMD_1WRS};
j3 1:91e52f8ab8bf 272
j3 2:02d228c25fd4 273 // 1-Wire reset (Case B)
j3 2:02d228c25fd4 274 // S AD,0 [A] 1WRS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 275 // \--------/
j3 2:02d228c25fd4 276 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 277 // [] indicates from slave
j3 2:02d228c25fd4 278
j3 2:02d228c25fd4 279 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 280
j3 2:02d228c25fd4 281 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 282 // abort if poll limit reached
j3 2:02d228c25fd4 283 do
j3 2:02d228c25fd4 284 {
j3 2:02d228c25fd4 285 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 286 }
j3 2:02d228c25fd4 287 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 1:91e52f8ab8bf 288
j3 2:02d228c25fd4 289 // check for failure due to poll limit reached
j3 2:02d228c25fd4 290 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 291 {
j3 2:02d228c25fd4 292 // handle error
j3 2:02d228c25fd4 293 // ...
j3 2:02d228c25fd4 294 reset();
j3 2:02d228c25fd4 295 rtn_val = false;
j3 2:02d228c25fd4 296 }
j3 2:02d228c25fd4 297 else
j3 2:02d228c25fd4 298 {
j3 2:02d228c25fd4 299 // check for short condition
j3 2:02d228c25fd4 300 if (status & STATUS_SD)
j3 2:02d228c25fd4 301 {
j3 5:ce108eeb878d 302 _short_detected = true;
j3 2:02d228c25fd4 303 }
j3 2:02d228c25fd4 304 else
j3 2:02d228c25fd4 305 {
j3 5:ce108eeb878d 306 _short_detected = false;
j3 2:02d228c25fd4 307 }
j3 2:02d228c25fd4 308
j3 2:02d228c25fd4 309 // check for presence detect
j3 2:02d228c25fd4 310 if (status & STATUS_PPD)
j3 2:02d228c25fd4 311 {
j3 2:02d228c25fd4 312 rtn_val = true;
j3 2:02d228c25fd4 313 }
j3 2:02d228c25fd4 314 else
j3 2:02d228c25fd4 315 {
j3 2:02d228c25fd4 316 rtn_val = false;
j3 2:02d228c25fd4 317 }
j3 2:02d228c25fd4 318 }
j3 2:02d228c25fd4 319
j3 1:91e52f8ab8bf 320 return(rtn_val);
j3 1:91e52f8ab8bf 321 }
j3 1:91e52f8ab8bf 322
j3 1:91e52f8ab8bf 323
j3 1:91e52f8ab8bf 324 //*********************************************************************
j3 1:91e52f8ab8bf 325 void Ds248x::OWWriteBit(uint8_t sendbit)
j3 1:91e52f8ab8bf 326 {
j3 2:02d228c25fd4 327 OWTouchBit(sendbit);
j3 1:91e52f8ab8bf 328 }
j3 1:91e52f8ab8bf 329
j3 1:91e52f8ab8bf 330
j3 1:91e52f8ab8bf 331 //*********************************************************************
j3 1:91e52f8ab8bf 332 uint8_t Ds248x::OWReadBit()
j3 1:91e52f8ab8bf 333 {
j3 2:02d228c25fd4 334 return(OWTouchBit(0x01));
j3 1:91e52f8ab8bf 335 }
j3 1:91e52f8ab8bf 336
j3 1:91e52f8ab8bf 337
j3 1:91e52f8ab8bf 338 //*********************************************************************
j3 1:91e52f8ab8bf 339 uint8_t Ds248x::OWTouchBit(uint8_t sendbit)
j3 1:91e52f8ab8bf 340 {
j3 1:91e52f8ab8bf 341 uint8_t rtn_val;
j3 2:02d228c25fd4 342 uint8_t poll_count = 0;
j3 2:02d228c25fd4 343 char status;
j3 2:02d228c25fd4 344 char packet[] = {CMD_1WSB, sendbit ? 0x80 : 0x00};
j3 2:02d228c25fd4 345
j3 2:02d228c25fd4 346 // 1-Wire bit (Case B)
j3 2:02d228c25fd4 347 // S AD,0 [A] 1WSB [A] BB [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 348 // \--------/
j3 2:02d228c25fd4 349 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 350 // [] indicates from slave
j3 2:02d228c25fd4 351 // BB indicates byte containing bit value in msbit
j3 2:02d228c25fd4 352
j3 2:02d228c25fd4 353 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 354
j3 2:02d228c25fd4 355 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 356 // abort if poll limit reached
j3 2:02d228c25fd4 357 do
j3 2:02d228c25fd4 358 {
j3 2:02d228c25fd4 359 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 360 }
j3 2:02d228c25fd4 361 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 362
j3 2:02d228c25fd4 363 // check for failure due to poll limit reached
j3 2:02d228c25fd4 364 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 365 {
j3 2:02d228c25fd4 366 // handle error
j3 2:02d228c25fd4 367 // ...
j3 2:02d228c25fd4 368 reset();
j3 2:02d228c25fd4 369 rtn_val = 0;
j3 2:02d228c25fd4 370 }
j3 2:02d228c25fd4 371 else
j3 2:02d228c25fd4 372 {
j3 2:02d228c25fd4 373 // return bit state
j3 2:02d228c25fd4 374 if (status & STATUS_SBR)
j3 2:02d228c25fd4 375 {
j3 2:02d228c25fd4 376 rtn_val = 1;
j3 2:02d228c25fd4 377 }
j3 2:02d228c25fd4 378 else
j3 2:02d228c25fd4 379 {
j3 2:02d228c25fd4 380 rtn_val = 0;
j3 2:02d228c25fd4 381 }
j3 2:02d228c25fd4 382 }
j3 2:02d228c25fd4 383
j3 2:02d228c25fd4 384 return(rtn_val);
j3 1:91e52f8ab8bf 385 }
j3 1:91e52f8ab8bf 386
j3 1:91e52f8ab8bf 387
j3 1:91e52f8ab8bf 388 //*********************************************************************
j3 2:02d228c25fd4 389 bool Ds248x::OWWriteByte(uint8_t sendbyte)
j3 1:91e52f8ab8bf 390 {
j3 2:02d228c25fd4 391 bool rtn_val = false;
j3 1:91e52f8ab8bf 392
j3 2:02d228c25fd4 393 uint8_t poll_count = 0;
j3 2:02d228c25fd4 394 char status;
j3 2:02d228c25fd4 395 char packet [] = {CMD_1WWB, sendbyte};
j3 2:02d228c25fd4 396
j3 2:02d228c25fd4 397 // 1-Wire Write Byte (Case B)
j3 2:02d228c25fd4 398 // S AD,0 [A] 1WWB [A] DD [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 399 // \--------/
j3 2:02d228c25fd4 400 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 401 // [] indicates from slave
j3 2:02d228c25fd4 402 // DD data to write
j3 2:02d228c25fd4 403
j3 2:02d228c25fd4 404 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 405
j3 2:02d228c25fd4 406 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 407 // abort if poll limit reached
j3 2:02d228c25fd4 408 do
j3 2:02d228c25fd4 409 {
j3 2:02d228c25fd4 410 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 411 }
j3 2:02d228c25fd4 412 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 413
j3 2:02d228c25fd4 414 // check for failure due to poll limit reached
j3 2:02d228c25fd4 415 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 416 {
j3 2:02d228c25fd4 417 // handle error
j3 2:02d228c25fd4 418 // ...
j3 2:02d228c25fd4 419 reset();
j3 2:02d228c25fd4 420 rtn_val = false;
j3 2:02d228c25fd4 421 }
j3 2:02d228c25fd4 422 else
j3 2:02d228c25fd4 423 {
j3 2:02d228c25fd4 424 rtn_val = true;
j3 2:02d228c25fd4 425 }
j3 2:02d228c25fd4 426
j3 2:02d228c25fd4 427 return(rtn_val);
j3 1:91e52f8ab8bf 428 }
j3 1:91e52f8ab8bf 429
j3 1:91e52f8ab8bf 430
j3 1:91e52f8ab8bf 431 //*********************************************************************
j3 1:91e52f8ab8bf 432 uint8_t Ds248x::OWReadByte(void)
j3 1:91e52f8ab8bf 433 {
j3 1:91e52f8ab8bf 434 uint8_t rtn_val;
j3 2:02d228c25fd4 435
j3 2:02d228c25fd4 436 uint8_t poll_count = 0;
j3 2:02d228c25fd4 437 char data, status;
j3 2:02d228c25fd4 438 char packet[2] = {CMD_1WRB, 0};
j3 2:02d228c25fd4 439
j3 2:02d228c25fd4 440 // 1-Wire Read Bytes (Case C)
j3 2:02d228c25fd4 441 // S AD,0 [A] 1WRB [A] Sr AD,1 [A] [Status] A [Status] A\
j3 2:02d228c25fd4 442 // \--------/
j3 2:02d228c25fd4 443 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 444 // Sr AD,0 [A] SRP [A] E1 [A] Sr AD,1 [A] DD A\ P
j3 2:02d228c25fd4 445 //
j3 2:02d228c25fd4 446 // [] indicates from slave
j3 2:02d228c25fd4 447 // DD data read
j3 2:02d228c25fd4 448
j3 2:02d228c25fd4 449 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 450
j3 2:02d228c25fd4 451 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 452 // abort if poll limit reached
j3 2:02d228c25fd4 453 do
j3 2:02d228c25fd4 454 {
j3 2:02d228c25fd4 455 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 456 }
j3 2:02d228c25fd4 457 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 458
j3 2:02d228c25fd4 459 // check for failure due to poll limit reached
j3 2:02d228c25fd4 460 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 461 {
j3 2:02d228c25fd4 462 // handle error
j3 2:02d228c25fd4 463 // ...
j3 2:02d228c25fd4 464 reset();
j3 2:02d228c25fd4 465 rtn_val = 0;
j3 2:02d228c25fd4 466 }
j3 2:02d228c25fd4 467 else
j3 2:02d228c25fd4 468 {
j3 2:02d228c25fd4 469 packet[0] = CMD_SRP;
j3 2:02d228c25fd4 470 packet[1] = 0xE1;
j3 2:02d228c25fd4 471
j3 2:02d228c25fd4 472 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 473 _p_i2c_bus->read(_r_adrs, &data, 1);
j3 2:02d228c25fd4 474
j3 2:02d228c25fd4 475 rtn_val = data;
j3 2:02d228c25fd4 476 }
j3 2:02d228c25fd4 477
j3 1:91e52f8ab8bf 478 return(rtn_val);
j3 1:91e52f8ab8bf 479 }
j3 1:91e52f8ab8bf 480
j3 1:91e52f8ab8bf 481
j3 1:91e52f8ab8bf 482 //*********************************************************************
j3 1:91e52f8ab8bf 483 uint8_t Ds248x::OWTouchByte(uint8_t sendbyte)
j3 1:91e52f8ab8bf 484 {
j3 1:91e52f8ab8bf 485 uint8_t rtn_val;
j3 2:02d228c25fd4 486
j3 2:02d228c25fd4 487 if (sendbyte == 0xFF)
j3 2:02d228c25fd4 488 {
j3 2:02d228c25fd4 489 rtn_val = OWReadByte();
j3 2:02d228c25fd4 490 }
j3 2:02d228c25fd4 491 else
j3 2:02d228c25fd4 492 {
j3 2:02d228c25fd4 493 OWWriteByte(sendbyte);
j3 2:02d228c25fd4 494 rtn_val = sendbyte;
j3 2:02d228c25fd4 495 }
j3 2:02d228c25fd4 496
j3 1:91e52f8ab8bf 497 return(rtn_val);
j3 1:91e52f8ab8bf 498 }
j3 1:91e52f8ab8bf 499
j3 1:91e52f8ab8bf 500
j3 1:91e52f8ab8bf 501 //*********************************************************************
j3 1:91e52f8ab8bf 502 void Ds248x::OWBlock(uint8_t *tran_buf, uint8_t tran_len)
j3 1:91e52f8ab8bf 503 {
j3 2:02d228c25fd4 504 uint8_t i;
j3 2:02d228c25fd4 505
j3 2:02d228c25fd4 506 for (i = 0; i < tran_len; i++)
j3 2:02d228c25fd4 507 {
j3 2:02d228c25fd4 508 tran_buf[i] = OWTouchByte(tran_buf[i]);
j3 2:02d228c25fd4 509 }
j3 1:91e52f8ab8bf 510 }
j3 1:91e52f8ab8bf 511
j3 1:91e52f8ab8bf 512
j3 1:91e52f8ab8bf 513 //*********************************************************************
j3 5:ce108eeb878d 514 void Ds248x::OWWriteBlock(const uint8_t *tran_buf, uint8_t tran_len)
j3 5:ce108eeb878d 515 {
j3 5:ce108eeb878d 516 uint8_t idx;
j3 5:ce108eeb878d 517
j3 5:ce108eeb878d 518 for(idx = 0; idx < tran_len; idx++)
j3 5:ce108eeb878d 519 {
j3 5:ce108eeb878d 520 OWWriteByte(tran_buf[idx]);
j3 5:ce108eeb878d 521 }
j3 5:ce108eeb878d 522 }
j3 5:ce108eeb878d 523
j3 5:ce108eeb878d 524
j3 5:ce108eeb878d 525 //*********************************************************************
j3 5:ce108eeb878d 526 void Ds248x::OWReadBlock(uint8_t *recv_buf, uint8_t recv_len)
j3 5:ce108eeb878d 527 {
j3 5:ce108eeb878d 528 uint8_t idx;
j3 5:ce108eeb878d 529
j3 5:ce108eeb878d 530 for(idx = 0; idx < recv_len; idx++)
j3 5:ce108eeb878d 531 {
j3 5:ce108eeb878d 532 recv_buf[idx] = OWReadByte();
j3 5:ce108eeb878d 533 }
j3 5:ce108eeb878d 534 }
j3 5:ce108eeb878d 535
j3 5:ce108eeb878d 536
j3 5:ce108eeb878d 537 //*********************************************************************
j3 2:02d228c25fd4 538 bool Ds248x::OWFirst(void)
j3 1:91e52f8ab8bf 539 {
j3 2:02d228c25fd4 540 // reset the search state
j3 2:02d228c25fd4 541 _last_discrepancy = 0;
j3 5:ce108eeb878d 542 _last_device_flag = false;
j3 2:02d228c25fd4 543 _last_family_discrepancy = 0;
j3 2:02d228c25fd4 544
j3 2:02d228c25fd4 545 return OWSearch();
j3 2:02d228c25fd4 546 }
j3 2:02d228c25fd4 547
j3 2:02d228c25fd4 548
j3 2:02d228c25fd4 549 //*********************************************************************
j3 2:02d228c25fd4 550 bool Ds248x::OWNext(void)
j3 2:02d228c25fd4 551 {
j3 2:02d228c25fd4 552 // leave the search state alone
j3 2:02d228c25fd4 553 return OWSearch();
j3 1:91e52f8ab8bf 554 }
j3 1:91e52f8ab8bf 555
j3 1:91e52f8ab8bf 556
j3 1:91e52f8ab8bf 557 //*********************************************************************
j3 2:02d228c25fd4 558 bool Ds248x::OWVerify(void)
j3 1:91e52f8ab8bf 559 {
j3 2:02d228c25fd4 560 bool rtn_val = false;
j3 2:02d228c25fd4 561
j3 2:02d228c25fd4 562 uint8_t rom_backup[8];
j3 2:02d228c25fd4 563 uint8_t i,rslt,ld_backup,ldf_backup,lfd_backup;
j3 2:02d228c25fd4 564
j3 2:02d228c25fd4 565 // keep a backup copy of the current state
j3 2:02d228c25fd4 566 for (i = 0; i < 8; i++)
j3 2:02d228c25fd4 567 {
j3 2:02d228c25fd4 568 rom_backup[i] = _rom_number[i];
j3 2:02d228c25fd4 569 }
j3 2:02d228c25fd4 570
j3 2:02d228c25fd4 571 ld_backup = _last_discrepancy;
j3 2:02d228c25fd4 572 ldf_backup = _last_device_flag;
j3 2:02d228c25fd4 573 lfd_backup = _last_family_discrepancy;
j3 2:02d228c25fd4 574
j3 2:02d228c25fd4 575 // set search to find the same device
j3 2:02d228c25fd4 576 _last_discrepancy = 64;
j3 5:ce108eeb878d 577 _last_device_flag = false;
j3 1:91e52f8ab8bf 578
j3 2:02d228c25fd4 579 if (OWSearch())
j3 2:02d228c25fd4 580 {
j3 2:02d228c25fd4 581 // check if same device found
j3 5:ce108eeb878d 582 rslt = true;
j3 2:02d228c25fd4 583 for (i = 0; i < 8; i++)
j3 2:02d228c25fd4 584 {
j3 2:02d228c25fd4 585 if (rom_backup[i] != _rom_number[i])
j3 2:02d228c25fd4 586 {
j3 5:ce108eeb878d 587 rslt = false;
j3 2:02d228c25fd4 588 break;
j3 2:02d228c25fd4 589 }
j3 2:02d228c25fd4 590 }
j3 2:02d228c25fd4 591 }
j3 2:02d228c25fd4 592 else
j3 2:02d228c25fd4 593 {
j3 5:ce108eeb878d 594 rslt = false;
j3 2:02d228c25fd4 595 }
j3 1:91e52f8ab8bf 596
j3 2:02d228c25fd4 597 // restore the search state
j3 2:02d228c25fd4 598 for (i = 0; i < 8; i++)
j3 2:02d228c25fd4 599 {
j3 2:02d228c25fd4 600 _rom_number[i] = rom_backup[i];
j3 2:02d228c25fd4 601 }
j3 2:02d228c25fd4 602
j3 2:02d228c25fd4 603 _last_discrepancy = ld_backup;
j3 2:02d228c25fd4 604 _last_device_flag = ldf_backup;
j3 2:02d228c25fd4 605 _last_family_discrepancy = lfd_backup;
j3 2:02d228c25fd4 606
j3 2:02d228c25fd4 607 // return the result of the verify
j3 2:02d228c25fd4 608 rtn_val = rslt;
j3 2:02d228c25fd4 609
j3 1:91e52f8ab8bf 610 return(rtn_val);
j3 1:91e52f8ab8bf 611 }
j3 1:91e52f8ab8bf 612
j3 1:91e52f8ab8bf 613
j3 1:91e52f8ab8bf 614 //*********************************************************************
j3 1:91e52f8ab8bf 615 void Ds248x::OWTargetSetup(uint8_t family_code)
j3 1:91e52f8ab8bf 616 {
j3 2:02d228c25fd4 617 uint8_t i;
j3 2:02d228c25fd4 618
j3 2:02d228c25fd4 619 // set the search state to find SearchFamily type devices
j3 2:02d228c25fd4 620 _rom_number[0] = family_code;
j3 2:02d228c25fd4 621 for (i = 1; i < 8; i++)
j3 2:02d228c25fd4 622 {
j3 2:02d228c25fd4 623 _rom_number[i] = 0;
j3 2:02d228c25fd4 624 }
j3 1:91e52f8ab8bf 625
j3 2:02d228c25fd4 626 _last_discrepancy = 64;
j3 2:02d228c25fd4 627 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 628 _last_device_flag = false;
j3 1:91e52f8ab8bf 629 }
j3 1:91e52f8ab8bf 630
j3 1:91e52f8ab8bf 631
j3 1:91e52f8ab8bf 632 //*********************************************************************
j3 1:91e52f8ab8bf 633 void Ds248x::OWFamilySkipSetup(void)
j3 1:91e52f8ab8bf 634 {
j3 2:02d228c25fd4 635 // set the Last discrepancy to last family discrepancy
j3 2:02d228c25fd4 636 _last_discrepancy = _last_family_discrepancy;
j3 1:91e52f8ab8bf 637
j3 2:02d228c25fd4 638 // clear the last family discrpepancy
j3 2:02d228c25fd4 639 _last_family_discrepancy = 0;
j3 2:02d228c25fd4 640
j3 2:02d228c25fd4 641 // check for end of list
j3 2:02d228c25fd4 642 if (_last_discrepancy == 0)
j3 2:02d228c25fd4 643 {
j3 5:ce108eeb878d 644 _last_device_flag = true;
j3 2:02d228c25fd4 645 }
j3 1:91e52f8ab8bf 646 }
j3 1:91e52f8ab8bf 647
j3 1:91e52f8ab8bf 648
j3 1:91e52f8ab8bf 649 //*********************************************************************
j3 2:02d228c25fd4 650 bool Ds248x::OWSearch(void)
j3 1:91e52f8ab8bf 651 {
j3 2:02d228c25fd4 652 uint8_t id_bit_number;
j3 2:02d228c25fd4 653 uint8_t last_zero, rom_byte_number, search_result;
j3 2:02d228c25fd4 654 uint8_t id_bit, cmp_id_bit;
j3 2:02d228c25fd4 655 uint8_t rom_byte_mask, search_direction, status;
j3 2:02d228c25fd4 656
j3 2:02d228c25fd4 657 // initialize for search
j3 2:02d228c25fd4 658 id_bit_number = 1;
j3 2:02d228c25fd4 659 last_zero = 0;
j3 2:02d228c25fd4 660 rom_byte_number = 0;
j3 2:02d228c25fd4 661 rom_byte_mask = 1;
j3 5:ce108eeb878d 662 search_result = false;
j3 2:02d228c25fd4 663 _crc8 = 0;
j3 2:02d228c25fd4 664
j3 2:02d228c25fd4 665 // if the last call was not the last one
j3 2:02d228c25fd4 666 if (!_last_device_flag)
j3 2:02d228c25fd4 667 {
j3 2:02d228c25fd4 668 // 1-Wire reset
j3 2:02d228c25fd4 669 if (!OWReset())
j3 2:02d228c25fd4 670 {
j3 2:02d228c25fd4 671 // reset the search
j3 2:02d228c25fd4 672 _last_discrepancy = 0;
j3 5:ce108eeb878d 673 _last_device_flag = false;
j3 2:02d228c25fd4 674 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 675 return false;
j3 2:02d228c25fd4 676 }
j3 2:02d228c25fd4 677
j3 2:02d228c25fd4 678 // issue the search command
j3 2:02d228c25fd4 679 OWWriteByte(SEARCH_ROM);
j3 2:02d228c25fd4 680
j3 2:02d228c25fd4 681 // loop to do the search
j3 2:02d228c25fd4 682 do
j3 2:02d228c25fd4 683 {
j3 2:02d228c25fd4 684 // if this discrepancy if before the Last Discrepancy
j3 2:02d228c25fd4 685 // on a previous next then pick the same as last time
j3 2:02d228c25fd4 686 if (id_bit_number < _last_discrepancy)
j3 2:02d228c25fd4 687 {
j3 2:02d228c25fd4 688 if ((_rom_number[rom_byte_number] & rom_byte_mask) > 0)
j3 2:02d228c25fd4 689 search_direction = 1;
j3 2:02d228c25fd4 690 else
j3 2:02d228c25fd4 691 search_direction = 0;
j3 2:02d228c25fd4 692 }
j3 2:02d228c25fd4 693 else
j3 2:02d228c25fd4 694 {
j3 2:02d228c25fd4 695 // if equal to last pick 1, if not then pick 0
j3 2:02d228c25fd4 696 if (id_bit_number == _last_discrepancy)
j3 2:02d228c25fd4 697 search_direction = 1;
j3 2:02d228c25fd4 698 else
j3 2:02d228c25fd4 699 search_direction = 0;
j3 2:02d228c25fd4 700 }
j3 2:02d228c25fd4 701
j3 2:02d228c25fd4 702 // Perform a triple operation on the ds2484 which will perform 2 read bits and 1 write bit
j3 2:02d228c25fd4 703 status = search_triplet(search_direction);
j3 2:02d228c25fd4 704
j3 2:02d228c25fd4 705 // check bit results in status byte
j3 2:02d228c25fd4 706 id_bit = ((status & STATUS_SBR) == STATUS_SBR);
j3 2:02d228c25fd4 707 cmp_id_bit = ((status & STATUS_TSB) == STATUS_TSB);
j3 2:02d228c25fd4 708 search_direction = ((status & STATUS_DIR) == STATUS_DIR) ? (unsigned char)1 : (unsigned char)0;
j3 2:02d228c25fd4 709
j3 2:02d228c25fd4 710 // check for no devices on 1-Wire
j3 2:02d228c25fd4 711 if ((id_bit) && (cmp_id_bit))
j3 2:02d228c25fd4 712 break;
j3 2:02d228c25fd4 713 else
j3 2:02d228c25fd4 714 {
j3 2:02d228c25fd4 715 if ((!id_bit) && (!cmp_id_bit) && (search_direction == 0))
j3 2:02d228c25fd4 716 {
j3 2:02d228c25fd4 717 last_zero = id_bit_number;
j3 2:02d228c25fd4 718
j3 2:02d228c25fd4 719 // check for Last discrepancy in family
j3 2:02d228c25fd4 720 if (last_zero < 9)
j3 2:02d228c25fd4 721 _last_family_discrepancy = last_zero;
j3 2:02d228c25fd4 722 }
j3 2:02d228c25fd4 723
j3 2:02d228c25fd4 724 // set or clear the bit in the ROM byte rom_byte_number
j3 2:02d228c25fd4 725 // with mask rom_byte_mask
j3 2:02d228c25fd4 726 if (search_direction == 1)
j3 2:02d228c25fd4 727 _rom_number[rom_byte_number] |= rom_byte_mask;
j3 2:02d228c25fd4 728 else
j3 2:02d228c25fd4 729 _rom_number[rom_byte_number] &= (unsigned char)~rom_byte_mask;
j3 2:02d228c25fd4 730
j3 2:02d228c25fd4 731 // increment the byte counter id_bit_number
j3 2:02d228c25fd4 732 // and shift the mask rom_byte_mask
j3 2:02d228c25fd4 733 id_bit_number++;
j3 2:02d228c25fd4 734 rom_byte_mask <<= 1;
j3 2:02d228c25fd4 735
j3 2:02d228c25fd4 736 // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
j3 2:02d228c25fd4 737 if (rom_byte_mask == 0)
j3 2:02d228c25fd4 738 {
j3 5:ce108eeb878d 739 _crc8 = OWCalc_crc8(_rom_number[rom_byte_number], _crc8); // accumulate the CRC
j3 2:02d228c25fd4 740 rom_byte_number++;
j3 2:02d228c25fd4 741 rom_byte_mask = 1;
j3 2:02d228c25fd4 742 }
j3 2:02d228c25fd4 743 }
j3 2:02d228c25fd4 744 }
j3 2:02d228c25fd4 745 while(rom_byte_number < 8); // loop until through all ROM bytes 0-7
j3 2:02d228c25fd4 746
j3 2:02d228c25fd4 747 // if the search was successful then
j3 2:02d228c25fd4 748 if (!((id_bit_number < 65) || (_crc8 != 0)))
j3 2:02d228c25fd4 749 {
j3 2:02d228c25fd4 750 // search successful so set LastDiscrepancy,LastDeviceFlag,search_result
j3 2:02d228c25fd4 751 _last_discrepancy = last_zero;
j3 2:02d228c25fd4 752
j3 2:02d228c25fd4 753 // check for last device
j3 2:02d228c25fd4 754 if (_last_discrepancy == 0)
j3 5:ce108eeb878d 755 _last_device_flag = true;
j3 2:02d228c25fd4 756
j3 5:ce108eeb878d 757 search_result = true;
j3 2:02d228c25fd4 758 }
j3 2:02d228c25fd4 759 }
j3 2:02d228c25fd4 760
j3 2:02d228c25fd4 761 // if no device found then reset counters so next 'search' will be like a first
j3 2:02d228c25fd4 762 if (!search_result || (_rom_number[0] == 0))
j3 2:02d228c25fd4 763 {
j3 2:02d228c25fd4 764 _last_discrepancy = 0;
j3 5:ce108eeb878d 765 _last_device_flag = false;
j3 2:02d228c25fd4 766 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 767 search_result = false;
j3 2:02d228c25fd4 768 }
j3 2:02d228c25fd4 769
j3 2:02d228c25fd4 770 return search_result;
j3 1:91e52f8ab8bf 771 }
j3 1:91e52f8ab8bf 772
j3 1:91e52f8ab8bf 773
j3 1:91e52f8ab8bf 774 //*********************************************************************
j3 5:ce108eeb878d 775 bool Ds248x::OWReadROM(void)
j3 5:ce108eeb878d 776 {
j3 5:ce108eeb878d 777 bool rtn_val = false;
j3 5:ce108eeb878d 778
j3 5:ce108eeb878d 779 if(!OWReset())
j3 5:ce108eeb878d 780 {
j3 5:ce108eeb878d 781 rtn_val = false;
j3 5:ce108eeb878d 782 }
j3 5:ce108eeb878d 783 else
j3 5:ce108eeb878d 784 {
j3 5:ce108eeb878d 785 if(!OWWriteByte(READ_ROM))
j3 5:ce108eeb878d 786 {
j3 5:ce108eeb878d 787 rtn_val = false;
j3 5:ce108eeb878d 788 }
j3 5:ce108eeb878d 789 else
j3 5:ce108eeb878d 790 {
j3 5:ce108eeb878d 791 OWReadBlock(_rom_number, ROMnumberLen);
j3 5:ce108eeb878d 792 rtn_val = true;
j3 5:ce108eeb878d 793 }
j3 5:ce108eeb878d 794 }
j3 5:ce108eeb878d 795
j3 5:ce108eeb878d 796 return rtn_val;
j3 5:ce108eeb878d 797 }
j3 5:ce108eeb878d 798
j3 5:ce108eeb878d 799
j3 5:ce108eeb878d 800 //*********************************************************************
j3 5:ce108eeb878d 801 bool Ds248x::OWSkipROM(void)
j3 5:ce108eeb878d 802 {
j3 5:ce108eeb878d 803 bool rtn_val = false;
j3 5:ce108eeb878d 804
j3 5:ce108eeb878d 805 if(!OWReset())
j3 5:ce108eeb878d 806 {
j3 5:ce108eeb878d 807 rtn_val = false;
j3 5:ce108eeb878d 808 }
j3 5:ce108eeb878d 809 else
j3 5:ce108eeb878d 810 {
j3 5:ce108eeb878d 811 if(!OWWriteByte(SKIP_ROM))
j3 5:ce108eeb878d 812 {
j3 5:ce108eeb878d 813 rtn_val = false;
j3 5:ce108eeb878d 814 }
j3 5:ce108eeb878d 815 else
j3 5:ce108eeb878d 816 {
j3 5:ce108eeb878d 817 rtn_val = true;
j3 5:ce108eeb878d 818 }
j3 5:ce108eeb878d 819 }
j3 5:ce108eeb878d 820
j3 5:ce108eeb878d 821 return rtn_val;
j3 5:ce108eeb878d 822 }
j3 5:ce108eeb878d 823
j3 5:ce108eeb878d 824
j3 5:ce108eeb878d 825 //*********************************************************************
j3 5:ce108eeb878d 826 bool Ds248x::OWMatchROM(void)
j3 5:ce108eeb878d 827 {
j3 5:ce108eeb878d 828 bool rtn_val = false;
j3 5:ce108eeb878d 829 uint8_t idx;
j3 5:ce108eeb878d 830
j3 5:ce108eeb878d 831 if(!OWReset())
j3 5:ce108eeb878d 832 {
j3 5:ce108eeb878d 833 rtn_val = false;
j3 5:ce108eeb878d 834 }
j3 5:ce108eeb878d 835 else
j3 5:ce108eeb878d 836 {
j3 5:ce108eeb878d 837 if(!OWWriteByte(MATCH_ROM))
j3 5:ce108eeb878d 838 {
j3 5:ce108eeb878d 839 rtn_val = false;
j3 5:ce108eeb878d 840 }
j3 5:ce108eeb878d 841 else
j3 5:ce108eeb878d 842 {
j3 5:ce108eeb878d 843 for(idx = 0; idx < ROMnumberLen; idx++)
j3 5:ce108eeb878d 844 {
j3 5:ce108eeb878d 845 OWWriteByte(_rom_number[idx]);
j3 5:ce108eeb878d 846 }
j3 5:ce108eeb878d 847 rtn_val = true;
j3 5:ce108eeb878d 848 }
j3 5:ce108eeb878d 849 }
j3 5:ce108eeb878d 850
j3 5:ce108eeb878d 851 return rtn_val;
j3 5:ce108eeb878d 852 }
j3 5:ce108eeb878d 853
j3 5:ce108eeb878d 854
j3 5:ce108eeb878d 855 //*********************************************************************
j3 5:ce108eeb878d 856 bool Ds248x::OWOverdriveSkipROM(void)
j3 5:ce108eeb878d 857 {
j3 5:ce108eeb878d 858 bool rtn_val = false;
j3 5:ce108eeb878d 859
j3 5:ce108eeb878d 860 if(!OWReset())
j3 5:ce108eeb878d 861 {
j3 5:ce108eeb878d 862 rtn_val = false;
j3 5:ce108eeb878d 863 }
j3 5:ce108eeb878d 864 else
j3 5:ce108eeb878d 865 {
j3 5:ce108eeb878d 866 if(!OWWriteByte(OVERDRIVE_SKIP))
j3 5:ce108eeb878d 867 {
j3 5:ce108eeb878d 868 rtn_val = false;
j3 5:ce108eeb878d 869 }
j3 5:ce108eeb878d 870 else
j3 5:ce108eeb878d 871 {
j3 5:ce108eeb878d 872 //change speed for subsequent comands
j3 5:ce108eeb878d 873 OWSpeed(SPEED_OVERDRIVE);
j3 5:ce108eeb878d 874 rtn_val = true;
j3 5:ce108eeb878d 875 }
j3 5:ce108eeb878d 876 }
j3 5:ce108eeb878d 877
j3 5:ce108eeb878d 878 return rtn_val;
j3 5:ce108eeb878d 879 }
j3 5:ce108eeb878d 880
j3 5:ce108eeb878d 881
j3 5:ce108eeb878d 882 //*********************************************************************
j3 5:ce108eeb878d 883 bool Ds248x::OWOverdriveMatchROM(void)
j3 5:ce108eeb878d 884 {
j3 5:ce108eeb878d 885 bool rtn_val = false;
j3 5:ce108eeb878d 886 uint8_t idx;
j3 5:ce108eeb878d 887
j3 5:ce108eeb878d 888 if(!OWReset())
j3 5:ce108eeb878d 889 {
j3 5:ce108eeb878d 890 rtn_val = false;
j3 5:ce108eeb878d 891 }
j3 5:ce108eeb878d 892 else
j3 5:ce108eeb878d 893 {
j3 5:ce108eeb878d 894 if(!OWWriteByte(OVERDRIVE_MATCH))
j3 5:ce108eeb878d 895 {
j3 5:ce108eeb878d 896 rtn_val = false;
j3 5:ce108eeb878d 897 }
j3 5:ce108eeb878d 898 else
j3 5:ce108eeb878d 899 {
j3 5:ce108eeb878d 900 //change speed before sending ROM number
j3 5:ce108eeb878d 901 OWSpeed(SPEED_OVERDRIVE);
j3 5:ce108eeb878d 902
j3 5:ce108eeb878d 903 for(idx = 0; idx < ROMnumberLen; idx++)
j3 5:ce108eeb878d 904 {
j3 5:ce108eeb878d 905 OWWriteByte(_rom_number[idx]);
j3 5:ce108eeb878d 906 }
j3 5:ce108eeb878d 907 rtn_val = true;
j3 5:ce108eeb878d 908 }
j3 5:ce108eeb878d 909 }
j3 5:ce108eeb878d 910
j3 5:ce108eeb878d 911 return rtn_val;
j3 5:ce108eeb878d 912 }
j3 5:ce108eeb878d 913
j3 5:ce108eeb878d 914
j3 5:ce108eeb878d 915 //*********************************************************************
j3 5:ce108eeb878d 916 bool Ds248x::OWResume(void)
j3 5:ce108eeb878d 917 {
j3 5:ce108eeb878d 918 bool rtn_val = false;
j3 5:ce108eeb878d 919
j3 5:ce108eeb878d 920 if(!OWReset())
j3 5:ce108eeb878d 921 {
j3 5:ce108eeb878d 922 rtn_val = false;
j3 5:ce108eeb878d 923 }
j3 5:ce108eeb878d 924 else
j3 5:ce108eeb878d 925 {
j3 5:ce108eeb878d 926 if(!OWWriteByte(RESUME))
j3 5:ce108eeb878d 927 {
j3 5:ce108eeb878d 928 rtn_val = false;
j3 5:ce108eeb878d 929 }
j3 5:ce108eeb878d 930 else
j3 5:ce108eeb878d 931 {
j3 5:ce108eeb878d 932 rtn_val = true;
j3 5:ce108eeb878d 933 }
j3 5:ce108eeb878d 934 }
j3 5:ce108eeb878d 935
j3 5:ce108eeb878d 936 return rtn_val;
j3 5:ce108eeb878d 937 }
j3 5:ce108eeb878d 938
j3 5:ce108eeb878d 939
j3 5:ce108eeb878d 940 //*********************************************************************
j3 5:ce108eeb878d 941 uint8_t Ds248x::OWSpeed(OW_SPEED new_speed)
j3 1:91e52f8ab8bf 942 {
j3 2:02d228c25fd4 943 // set the speed
j3 5:ce108eeb878d 944 if (new_speed == SPEED_OVERDRIVE)
j3 2:02d228c25fd4 945 {
j3 2:02d228c25fd4 946 _c1WS = CONFIG_1WS;
j3 2:02d228c25fd4 947 }
j3 2:02d228c25fd4 948 else
j3 2:02d228c25fd4 949 {
j3 5:ce108eeb878d 950 _c1WS = false;
j3 2:02d228c25fd4 951 }
j3 2:02d228c25fd4 952
j3 2:02d228c25fd4 953 // write the new config
j3 2:02d228c25fd4 954 write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 2:02d228c25fd4 955
j3 2:02d228c25fd4 956 return(new_speed);
j3 1:91e52f8ab8bf 957 }
j3 1:91e52f8ab8bf 958
j3 1:91e52f8ab8bf 959
j3 1:91e52f8ab8bf 960 //*********************************************************************
j3 5:ce108eeb878d 961 uint8_t Ds248x::OWLevel(OW_LEVEL new_level)
j3 1:91e52f8ab8bf 962 {
j3 1:91e52f8ab8bf 963 uint8_t rtn_val;
j3 2:02d228c25fd4 964
j3 2:02d228c25fd4 965 // function only will turn back to non-strong pull-up
j3 5:ce108eeb878d 966 if (new_level != LEVEL_NORMAL)
j3 2:02d228c25fd4 967 {
j3 5:ce108eeb878d 968 rtn_val = LEVEL_STRONG;
j3 2:02d228c25fd4 969 }
j3 2:02d228c25fd4 970 else
j3 2:02d228c25fd4 971 {
j3 2:02d228c25fd4 972 // clear the strong pull-up bit in the global config state
j3 5:ce108eeb878d 973 _cSPU = false;
j3 2:02d228c25fd4 974 // write the new config
j3 2:02d228c25fd4 975 write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 5:ce108eeb878d 976 rtn_val = LEVEL_NORMAL;
j3 2:02d228c25fd4 977 }
j3 2:02d228c25fd4 978
j3 1:91e52f8ab8bf 979 return(rtn_val);
j3 1:91e52f8ab8bf 980 }
j3 1:91e52f8ab8bf 981
j3 1:91e52f8ab8bf 982
j3 1:91e52f8ab8bf 983 //*********************************************************************
j3 2:02d228c25fd4 984 bool Ds248x::OWWriteBytePower(uint8_t sendbyte)
j3 1:91e52f8ab8bf 985 {
j3 2:02d228c25fd4 986 bool rtn_val = false;
j3 2:02d228c25fd4 987
j3 2:02d228c25fd4 988 // set strong pull-up enable
j3 2:02d228c25fd4 989 _cSPU = CONFIG_SPU;
j3 2:02d228c25fd4 990
j3 2:02d228c25fd4 991 // write the new config
j3 2:02d228c25fd4 992 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 993 {
j3 2:02d228c25fd4 994 rtn_val = false;
j3 2:02d228c25fd4 995 }
j3 2:02d228c25fd4 996 else
j3 2:02d228c25fd4 997 {
j3 2:02d228c25fd4 998 // perform write byte
j3 2:02d228c25fd4 999 OWWriteByte(sendbyte);
j3 2:02d228c25fd4 1000 rtn_val = true;
j3 2:02d228c25fd4 1001 }
j3 2:02d228c25fd4 1002
j3 1:91e52f8ab8bf 1003 return(rtn_val);
j3 1:91e52f8ab8bf 1004 }
j3 1:91e52f8ab8bf 1005
j3 1:91e52f8ab8bf 1006
j3 1:91e52f8ab8bf 1007 //*********************************************************************
j3 2:02d228c25fd4 1008 bool Ds248x::OWReadBitPower(uint8_t applyPowerResponse)
j3 1:91e52f8ab8bf 1009 {
j3 2:02d228c25fd4 1010 bool rtn_val = false;
j3 2:02d228c25fd4 1011
j3 2:02d228c25fd4 1012 uint8_t rdbit;
j3 2:02d228c25fd4 1013
j3 2:02d228c25fd4 1014 // set strong pull-up enable
j3 2:02d228c25fd4 1015 _cSPU = CONFIG_SPU;
j3 2:02d228c25fd4 1016
j3 2:02d228c25fd4 1017 // write the new config
j3 2:02d228c25fd4 1018 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 1019 {
j3 2:02d228c25fd4 1020 rtn_val = false;
j3 2:02d228c25fd4 1021 }
j3 2:02d228c25fd4 1022 else
j3 2:02d228c25fd4 1023 {
j3 2:02d228c25fd4 1024 // perform read bit
j3 2:02d228c25fd4 1025 rdbit = OWReadBit();
j3 2:02d228c25fd4 1026
j3 2:02d228c25fd4 1027 // check if response was correct, if not then turn off strong pull-up
j3 2:02d228c25fd4 1028 if (rdbit != applyPowerResponse)
j3 2:02d228c25fd4 1029 {
j3 5:ce108eeb878d 1030 OWLevel(LEVEL_NORMAL);
j3 2:02d228c25fd4 1031 rtn_val = false;
j3 2:02d228c25fd4 1032 }
j3 2:02d228c25fd4 1033
j3 2:02d228c25fd4 1034 rtn_val = true;
j3 2:02d228c25fd4 1035 }
j3 2:02d228c25fd4 1036
j3 1:91e52f8ab8bf 1037 return(rtn_val);
j3 1:91e52f8ab8bf 1038 }
j3 1:91e52f8ab8bf 1039
j3 1:91e52f8ab8bf 1040
j3 1:91e52f8ab8bf 1041 //*********************************************************************
j3 5:ce108eeb878d 1042 const uint8_t (&Ds248x::OWgetROMnumber() const)[ROMnumberLen]
j3 1:91e52f8ab8bf 1043 {
j3 5:ce108eeb878d 1044 return _rom_number;
j3 2:02d228c25fd4 1045 }
j3 6:1faafa0b3cd7 1046
j3 6:1faafa0b3cd7 1047
j3 6:1faafa0b3cd7 1048 //*********************************************************************
j3 6:1faafa0b3cd7 1049 void Ds248x::set_i2c_adrs(DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 1050 {
j3 6:1faafa0b3cd7 1051 _w_adrs = (adrs << 1);
j3 6:1faafa0b3cd7 1052 _r_adrs = (_w_adrs | 1);
j3 6:1faafa0b3cd7 1053 }