Diff: main.cpp

Revision:

5:202ed7222217

Parent:

4:828118be72d0

Child:

6:e380af098d52

--- a/main.cpp	Mon Aug 28 20:55:47 2017 +0000
+++ b/main.cpp	Tue Aug 29 20:23:45 2017 +0000
@@ -50,13 +50,19 @@
 
 int main()
 {   
-
+    
+    // Constants
     const int EINT_STATUS_MASK =  1 << 23;
+    const int FIFO_OVF_MASK =  0x7;
+    const int FIFO_VALID_SAMPLE_MASK =  0x0;
+    const int FIFO_FAST_SAMPLE_MASK =  0x1;
+    const int ETAG_BITS_MASK = 0x7;
     
+    // Ports and serial connections
     Serial pc(USBTX, USBRX);            // Use USB debug probe for serial link
     pc.baud(115200);                    // Baud rate = 115200
     
-    DigitalOut rLed(LED1, LED_OFF);      // Debug LEDs
+    DigitalOut rLed(LED1, LED_OFF);     // Debug LEDs
     DigitalOut gLed(LED2, LED_OFF);
     DigitalOut bLed(LED3, LED_OFF);
     
@@ -79,6 +85,7 @@
         
         /* Read back ECG samples from the FIFO */
         if( ecgFIFOIntFlag ) {
+            
             ecgFIFOIntFlag = 0;
             pc.printf("Interrupt received....\r\n");
             status = ecgAFE.readRegister( MAX30003::STATUS );      // Read the STATUS register
@@ -91,27 +98,28 @@
                 readECGSamples = 0;                        // Reset sample counter
                 
                 do {
-                    ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO );   // Read FIFO
+                    ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO );       // Read FIFO
                     ecgSample[readECGSamples] = ecgFIFO >> 8;                  // Isolate voltage data
-                    ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & 0b111;           // Isolate ETAG
+                    ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK;  // Isolate ETAG
                     readECGSamples++;                                          // Increment sample counter
                 
                 // Check that sample is not last sample in FIFO                                              
-                } while ( ETAG[readECGSamples-1] == 0x0 || 
-                          ETAG[readECGSamples-1] == 0x1 ); 
+                } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK || 
+                          ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK ); 
             
                 pc.printf("%d samples read from FIFO \r\n", readECGSamples);
                 
                 // Check if FIFO has overflowed
-                if( ETAG[readECGSamples - 1] == 0x7 ){                  
+                if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){                  
                     ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
                 }
                 
-                /* Print results */
+                // Print results 
                 for( idx = 0; idx < readECGSamples; idx++ ) {
                     pc.printf("Sample : %6d, \tETAG : 0x%x\r\n", ecgSample[idx], ETAG[idx]);           
                 }
-                pc.printf("\r\n\r\n\r\n");                          
+                pc.printf("\r\n\r\n\r\n"); 
+                                         
             }
         }
     }