Maxim Integrated / Mbed OS MAX11301WING_Demo

Demo code for the MAX11301WING. Programs a +5V on Port 0, -5V on Port 1 and a single-ended ADC on Port 9.

Dependencies:   MAX113XX_Pixi max32630fthr

Fork of MAX11301_Demo by John Greene

MAX11301Hex.h@6:fe500943de11, 2017-08-29 (annotated)

Committer:
coreyharris
Date:
Tue Aug 29 20:21:18 2017 +0000
Revision:
6:fe500943de11
Parent:
0:6727152ebfbb 
Updated comments

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coreyharris 0:6727152ebfbb 1 /*******************************************************************************
coreyharris 0:6727152ebfbb 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
coreyharris 0:6727152ebfbb 3 *
coreyharris 0:6727152ebfbb 4 * Permission is hereby granted, free of charge, to any person obtaining a
coreyharris 0:6727152ebfbb 5 * copy of this software and associated documentation files (the "Software"),
coreyharris 0:6727152ebfbb 6 * to deal in the Software without restriction, including without limitation
coreyharris 0:6727152ebfbb 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
coreyharris 0:6727152ebfbb 8 * and/or sell copies of the Software, and to permit persons to whom the
coreyharris 0:6727152ebfbb 9 * Software is furnished to do so, subject to the following conditions:
coreyharris 0:6727152ebfbb 10 *
coreyharris 0:6727152ebfbb 11 * The above copyright notice and this permission notice shall be included
coreyharris 0:6727152ebfbb 12 * in all copies or substantial portions of the Software.
coreyharris 0:6727152ebfbb 13 *
coreyharris 0:6727152ebfbb 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
coreyharris 0:6727152ebfbb 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
coreyharris 0:6727152ebfbb 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
coreyharris 0:6727152ebfbb 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
coreyharris 0:6727152ebfbb 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
coreyharris 0:6727152ebfbb 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
coreyharris 0:6727152ebfbb 20 * OTHER DEALINGS IN THE SOFTWARE.
coreyharris 0:6727152ebfbb 21 *
coreyharris 0:6727152ebfbb 22 * Except as contained in this notice, the name of Maxim Integrated
coreyharris 0:6727152ebfbb 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
coreyharris 0:6727152ebfbb 24 * Products, Inc. Branding Policy.
coreyharris 0:6727152ebfbb 25 *
coreyharris 0:6727152ebfbb 26 * The mere transfer of this software does not imply any licenses
coreyharris 0:6727152ebfbb 27 * of trade secrets, proprietary technology, copyrights, patents,
coreyharris 0:6727152ebfbb 28 * trademarks, maskwork rights, or any other form of intellectual
coreyharris 0:6727152ebfbb 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
coreyharris 0:6727152ebfbb 30 * ownership rights.
coreyharris 0:6727152ebfbb 31 *******************************************************************************
coreyharris 0:6727152ebfbb 32 */
coreyharris 0:6727152ebfbb 33 /// Generated by: MAX11300/01/11/12 Configuration Software (Ver. 1.1.0.5) 04/08/2017 13:35
coreyharris 0:6727152ebfbb 34 /// Description: New Empty Design
coreyharris 0:6727152ebfbb 35 /// Port P0:
coreyharris 0:6727152ebfbb 36 /// Port P1:
coreyharris 0:6727152ebfbb 37 /// Port P2:
coreyharris 0:6727152ebfbb 38 /// Port P3:
coreyharris 0:6727152ebfbb 39 /// Port P4:
coreyharris 0:6727152ebfbb 40 /// Port P5:
coreyharris 0:6727152ebfbb 41 /// Port P6:
coreyharris 0:6727152ebfbb 42 /// Port P7:
coreyharris 0:6727152ebfbb 43 /// Port P8:
coreyharris 0:6727152ebfbb 44 /// Port P9:
coreyharris 0:6727152ebfbb 45 /// Port P10:
coreyharris 0:6727152ebfbb 46 /// Port P11:
coreyharris 0:6727152ebfbb 47 /// Port P12:
coreyharris 0:6727152ebfbb 48 /// Port P13:
coreyharris 0:6727152ebfbb 49 /// Port P14:
coreyharris 0:6727152ebfbb 50 /// Port P15:
coreyharris 0:6727152ebfbb 51 /// Port P16:
coreyharris 0:6727152ebfbb 52 /// Port P17:
coreyharris 0:6727152ebfbb 53 /// Port P18:
coreyharris 0:6727152ebfbb 54 /// Port P19:
coreyharris 0:6727152ebfbb 55 /// Notes: Optional: Enter design notes here
coreyharris 0:6727152ebfbb 56 #ifndef _MAX11300_DESIGNVALUE_H_
coreyharris 0:6727152ebfbb 57 #define _MAX11300_DESIGNVALUE_H_
coreyharris 0:6727152ebfbb 58
coreyharris 0:6727152ebfbb 59 /// Supply voltage on AVSSIO
coreyharris 0:6727152ebfbb 60 #define MAX11300_AVSSIO_VOLTAGE -7.5
coreyharris 0:6727152ebfbb 61
coreyharris 0:6727152ebfbb 62 /// Supply voltage on AVDDIO
coreyharris 0:6727152ebfbb 63 #define MAX11300_AVDDIO_VOLTAGE 7.5
coreyharris 0:6727152ebfbb 64
coreyharris 0:6727152ebfbb 65 /// Supply voltage on DVDD
coreyharris 0:6727152ebfbb 66 #define MAX11300_DVDD_VOLTAGE 3.3
coreyharris 0:6727152ebfbb 67
coreyharris 0:6727152ebfbb 68 /// Supply voltage on AVDD
coreyharris 0:6727152ebfbb 69 #define MAX11300_AVDD_VOLTAGE 5
coreyharris 0:6727152ebfbb 70
coreyharris 0:6727152ebfbb 71 /// Supply voltage on DAC_REF
coreyharris 0:6727152ebfbb 72 #define MAX11300_DAC_REF_VOLTAGE 2.5
coreyharris 0:6727152ebfbb 73
coreyharris 0:6727152ebfbb 74 /// Supply voltage on ADC_EXT_REF
coreyharris 0:6727152ebfbb 75 #define MAX11300_ADC_EXT_REF_VOLTAGE 2.5
coreyharris 0:6727152ebfbb 76
coreyharris 0:6727152ebfbb 77 /// SPI first byte when writing MAX11300 (7-bit address in bits 0x7E; LSB=0 for write)
coreyharris 0:6727152ebfbb 78 #define MAX11300Addr_SPI_Write(RegAddr) ( (RegAddr << 1) )
coreyharris 0:6727152ebfbb 79
coreyharris 0:6727152ebfbb 80 /// SPI first byte when reading MAX11300 (7-bit address in bits 0x7E; LSB=1 for read)
coreyharris 0:6727152ebfbb 81 #define MAX11300Addr_SPI_Read(RegAddr) ( (RegAddr << 1) | 1 )
coreyharris 0:6727152ebfbb 82
coreyharris 0:6727152ebfbb 83 /// MAX11300EVKIT Register Addresses
coreyharris 0:6727152ebfbb 84 typedef enum MAX11300RegAddressEnum {
coreyharris 0:6727152ebfbb 85
coreyharris 0:6727152ebfbb 86 /// 0x00 r/o dev_id Device Identification
coreyharris 0:6727152ebfbb 87 dev_id = 0x00,
coreyharris 0:6727152ebfbb 88
coreyharris 0:6727152ebfbb 89 /// 0x01 r/o interrupt_flag Interrupt flags
coreyharris 0:6727152ebfbb 90 interrupt_flag = 0x01,
coreyharris 0:6727152ebfbb 91
coreyharris 0:6727152ebfbb 92 /// 0x02 r/o adc_status_15_to_0 new ADC data available
coreyharris 0:6727152ebfbb 93 adc_status_15_to_0 = 0x02,
coreyharris 0:6727152ebfbb 94
coreyharris 0:6727152ebfbb 95 /// 0x03 r/o adc_status_19_to_16 new ADC data available
coreyharris 0:6727152ebfbb 96 adc_status_19_to_16 = 0x03,
coreyharris 0:6727152ebfbb 97
coreyharris 0:6727152ebfbb 98 /// 0x04 r/o dac_oi_status_15_to_0 DAC Overcurrent Interrupt
coreyharris 0:6727152ebfbb 99 dac_oi_status_15_to_0 = 0x04,
coreyharris 0:6727152ebfbb 100
coreyharris 0:6727152ebfbb 101 /// 0x05 r/o dac_oi_status_19_to_16 DAC Overcurrent Interrupt
coreyharris 0:6727152ebfbb 102 dac_oi_status_19_to_16 = 0x05,
coreyharris 0:6727152ebfbb 103
coreyharris 0:6727152ebfbb 104 /// 0x06 r/o gpi_status_15_to_0 GPI event ready
coreyharris 0:6727152ebfbb 105 gpi_status_15_to_0 = 0x06,
coreyharris 0:6727152ebfbb 106
coreyharris 0:6727152ebfbb 107 /// 0x07 r/o gpi_status_19_to_16 GPI event ready
coreyharris 0:6727152ebfbb 108 gpi_status_19_to_16 = 0x07,
coreyharris 0:6727152ebfbb 109
coreyharris 0:6727152ebfbb 110 /// 0x08 r/o tmp_int_data Internal Temeprature
coreyharris 0:6727152ebfbb 111 tmp_int_data = 0x08,
coreyharris 0:6727152ebfbb 112
coreyharris 0:6727152ebfbb 113 /// 0x09 r/o tmp_ext1_data External Temperature D0P/D0N
coreyharris 0:6727152ebfbb 114 tmp_ext1_data = 0x09,
coreyharris 0:6727152ebfbb 115
coreyharris 0:6727152ebfbb 116 /// 0x0a r/o tmp_ext2_data External Temperature D1P/D1N
coreyharris 0:6727152ebfbb 117 tmp_ext2_data = 0x0a,
coreyharris 0:6727152ebfbb 118
coreyharris 0:6727152ebfbb 119 /// 0x0b r/o gpi_data_15_to_0 GPI input ports data
coreyharris 0:6727152ebfbb 120 gpi_data_15_to_0 = 0x0b,
coreyharris 0:6727152ebfbb 121
coreyharris 0:6727152ebfbb 122 /// 0x0c r/o gpi_data_19_to_16 GPI input ports data
coreyharris 0:6727152ebfbb 123 gpi_data_19_to_16 = 0x0c,
coreyharris 0:6727152ebfbb 124
coreyharris 0:6727152ebfbb 125 /// 0x0d r/w gpo_data_15_to_0 GPO output ports data
coreyharris 0:6727152ebfbb 126 gpo_data_15_to_0 = 0x0d,
coreyharris 0:6727152ebfbb 127
coreyharris 0:6727152ebfbb 128 /// 0x0e r/w gpo_data_19_to_16 GPO output ports data
coreyharris 0:6727152ebfbb 129 gpo_data_19_to_16 = 0x0e,
coreyharris 0:6727152ebfbb 130
coreyharris 0:6727152ebfbb 131 /// 0x0f r/o reserved_0F reserved
coreyharris 0:6727152ebfbb 132 reserved_0F = 0x0f,
coreyharris 0:6727152ebfbb 133
coreyharris 0:6727152ebfbb 134 /// 0x10 r/w device_control Global device control register
coreyharris 0:6727152ebfbb 135 device_control = 0x10,
coreyharris 0:6727152ebfbb 136
coreyharris 0:6727152ebfbb 137 /// 0x11 r/w interrupt_mask interrupt mask (1 = disable interrupt source)
coreyharris 0:6727152ebfbb 138 interrupt_mask = 0x11,
coreyharris 0:6727152ebfbb 139
coreyharris 0:6727152ebfbb 140 /// 0x12 r/w gpi_irqmode_7_to_0 GPI port 0 to 7 mode register
coreyharris 0:6727152ebfbb 141 gpi_irqmode_7_to_0 = 0x12,
coreyharris 0:6727152ebfbb 142
coreyharris 0:6727152ebfbb 143 /// 0x13 r/w gpi_irqmode_15_to_8 GPI port 8 to 15 mode register
coreyharris 0:6727152ebfbb 144 gpi_irqmode_15_to_8 = 0x13,
coreyharris 0:6727152ebfbb 145
coreyharris 0:6727152ebfbb 146 /// 0x14 r/w gpi_irqmode_19_to_16 GPI port 16 to 19 mode register
coreyharris 0:6727152ebfbb 147 gpi_irqmode_19_to_16 = 0x14,
coreyharris 0:6727152ebfbb 148
coreyharris 0:6727152ebfbb 149 /// 0x15 r/w gpi_irqmode_31_to_24 (reserved)
coreyharris 0:6727152ebfbb 150 gpi_irqmode_31_to_24 = 0x15,
coreyharris 0:6727152ebfbb 151
coreyharris 0:6727152ebfbb 152 /// 0x16 r/w dac_preset_data_1 DAC preset activated by <see cref="device_control"/>
coreyharris 0:6727152ebfbb 153 dac_preset_data_1 = 0x16,
coreyharris 0:6727152ebfbb 154
coreyharris 0:6727152ebfbb 155 /// 0x17 r/w dac_preset_data_2 DAC preset activated by <see cref="device_control"/>
coreyharris 0:6727152ebfbb 156 dac_preset_data_2 = 0x17,
coreyharris 0:6727152ebfbb 157
coreyharris 0:6727152ebfbb 158 /// 0x18 r/w tmp_mon_cfg Temperautre Monitor Configuration
coreyharris 0:6727152ebfbb 159 tmp_mon_cfg = 0x18,
coreyharris 0:6727152ebfbb 160
coreyharris 0:6727152ebfbb 161 /// 0x19 r/w tmp_mon_int_hi_thresh Internal Temeprature Hot Threshold
coreyharris 0:6727152ebfbb 162 tmp_mon_int_hi_thresh = 0x19,
coreyharris 0:6727152ebfbb 163
coreyharris 0:6727152ebfbb 164 /// 0x1a r/w tmp_mon_int_lo_thresh Internal Temeprature Cold Threshold
coreyharris 0:6727152ebfbb 165 tmp_mon_int_lo_thresh = 0x1a,
coreyharris 0:6727152ebfbb 166
coreyharris 0:6727152ebfbb 167 /// 0x1b r/w tmp_mon_ext1_hi_thresh External Temperature D0P/D0N Hot Threshold
coreyharris 0:6727152ebfbb 168 tmp_mon_ext1_hi_thresh = 0x1b,
coreyharris 0:6727152ebfbb 169
coreyharris 0:6727152ebfbb 170 /// 0x1c r/w tmp_mon_ext1_lo_thresh External Temperature D0P/D0N Cold Threshold
coreyharris 0:6727152ebfbb 171 tmp_mon_ext1_lo_thresh = 0x1c,
coreyharris 0:6727152ebfbb 172
coreyharris 0:6727152ebfbb 173 /// 0x1d r/w tmp_mon_ext2_hi_thresh External Temperature D1P/D1N Hot Threshold
coreyharris 0:6727152ebfbb 174 tmp_mon_ext2_hi_thresh = 0x1d,
coreyharris 0:6727152ebfbb 175
coreyharris 0:6727152ebfbb 176 /// 0x1e r/w tmp_mon_ext2_lo_thresh External Temperature D1P/D1N Cold Threshold
coreyharris 0:6727152ebfbb 177 tmp_mon_ext2_lo_thresh = 0x1e,
coreyharris 0:6727152ebfbb 178
coreyharris 0:6727152ebfbb 179 /// 0x1f r/w reserved_1F reserved
coreyharris 0:6727152ebfbb 180 reserved_1F = 0x1f,
coreyharris 0:6727152ebfbb 181
coreyharris 0:6727152ebfbb 182 /// 0x20 r/w port_cfg_00 PIXI port 0 configuration register
coreyharris 0:6727152ebfbb 183 port_cfg_00 = 0x20,
coreyharris 0:6727152ebfbb 184
coreyharris 0:6727152ebfbb 185 /// 0x21 r/w port_cfg_01 PIXI port 1 configuration register
coreyharris 0:6727152ebfbb 186 port_cfg_01 = 0x21,
coreyharris 0:6727152ebfbb 187
coreyharris 0:6727152ebfbb 188 /// 0x22 r/w port_cfg_02 PIXI port 2 configuration register
coreyharris 0:6727152ebfbb 189 port_cfg_02 = 0x22,
coreyharris 0:6727152ebfbb 190
coreyharris 0:6727152ebfbb 191 /// 0x23 r/w port_cfg_03 PIXI port 3 configuration register
coreyharris 0:6727152ebfbb 192 port_cfg_03 = 0x23,
coreyharris 0:6727152ebfbb 193
coreyharris 0:6727152ebfbb 194 /// 0x24 r/w port_cfg_04 PIXI port 4 configuration register
coreyharris 0:6727152ebfbb 195 port_cfg_04 = 0x24,
coreyharris 0:6727152ebfbb 196
coreyharris 0:6727152ebfbb 197 /// 0x25 r/w port_cfg_05 PIXI port 5 configuration register
coreyharris 0:6727152ebfbb 198 port_cfg_05 = 0x25,
coreyharris 0:6727152ebfbb 199
coreyharris 0:6727152ebfbb 200 /// 0x26 r/w port_cfg_06 PIXI port 6 configuration register
coreyharris 0:6727152ebfbb 201 port_cfg_06 = 0x26,
coreyharris 0:6727152ebfbb 202
coreyharris 0:6727152ebfbb 203 /// 0x27 r/w port_cfg_07 PIXI port 7 configuration register
coreyharris 0:6727152ebfbb 204 port_cfg_07 = 0x27,
coreyharris 0:6727152ebfbb 205
coreyharris 0:6727152ebfbb 206 /// 0x28 r/w port_cfg_08 PIXI port 8 configuration register
coreyharris 0:6727152ebfbb 207 port_cfg_08 = 0x28,
coreyharris 0:6727152ebfbb 208
coreyharris 0:6727152ebfbb 209 /// 0x29 r/w port_cfg_09 PIXI port 9 configuration register
coreyharris 0:6727152ebfbb 210 port_cfg_09 = 0x29,
coreyharris 0:6727152ebfbb 211
coreyharris 0:6727152ebfbb 212 /// 0x2a r/w port_cfg_10 PIXI port 10 configuration register
coreyharris 0:6727152ebfbb 213 port_cfg_10 = 0x2a,
coreyharris 0:6727152ebfbb 214
coreyharris 0:6727152ebfbb 215 /// 0x2b r/w port_cfg_11 PIXI port 11 configuration register
coreyharris 0:6727152ebfbb 216 port_cfg_11 = 0x2b,
coreyharris 0:6727152ebfbb 217
coreyharris 0:6727152ebfbb 218 /// 0x2c r/w port_cfg_12 PIXI port 12 configuration register
coreyharris 0:6727152ebfbb 219 port_cfg_12 = 0x2c,
coreyharris 0:6727152ebfbb 220
coreyharris 0:6727152ebfbb 221 /// 0x2d r/w port_cfg_13 PIXI port 13 configuration register
coreyharris 0:6727152ebfbb 222 port_cfg_13 = 0x2d,
coreyharris 0:6727152ebfbb 223
coreyharris 0:6727152ebfbb 224 /// 0x2e r/w port_cfg_14 PIXI port 14 configuration register
coreyharris 0:6727152ebfbb 225 port_cfg_14 = 0x2e,
coreyharris 0:6727152ebfbb 226
coreyharris 0:6727152ebfbb 227 /// 0x2f r/w port_cfg_15 PIXI port 15 configuration register
coreyharris 0:6727152ebfbb 228 port_cfg_15 = 0x2f,
coreyharris 0:6727152ebfbb 229
coreyharris 0:6727152ebfbb 230 /// 0x30 r/w port_cfg_16 PIXI port 16 configuration register
coreyharris 0:6727152ebfbb 231 port_cfg_16 = 0x30,
coreyharris 0:6727152ebfbb 232
coreyharris 0:6727152ebfbb 233 /// 0x31 r/w port_cfg_17 PIXI port 17 configuration register
coreyharris 0:6727152ebfbb 234 port_cfg_17 = 0x31,
coreyharris 0:6727152ebfbb 235
coreyharris 0:6727152ebfbb 236 /// 0x32 r/w port_cfg_18 PIXI port 18 configuration register
coreyharris 0:6727152ebfbb 237 port_cfg_18 = 0x32,
coreyharris 0:6727152ebfbb 238
coreyharris 0:6727152ebfbb 239 /// 0x33 r/w port_cfg_19 PIXI port 19 configuration register
coreyharris 0:6727152ebfbb 240 port_cfg_19 = 0x33,
coreyharris 0:6727152ebfbb 241
coreyharris 0:6727152ebfbb 242 /// 0x40 r/o adc_data_port_00 PIXI port 0 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 243 adc_data_port_00 = 0x40,
coreyharris 0:6727152ebfbb 244
coreyharris 0:6727152ebfbb 245 /// 0x41 r/o adc_data_port_01 PIXI port 1 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 246 adc_data_port_01 = 0x41,
coreyharris 0:6727152ebfbb 247
coreyharris 0:6727152ebfbb 248 /// 0x42 r/o adc_data_port_02 PIXI port 2 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 249 adc_data_port_02 = 0x42,
coreyharris 0:6727152ebfbb 250
coreyharris 0:6727152ebfbb 251 /// 0x43 r/o adc_data_port_03 PIXI port 3 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 252 adc_data_port_03 = 0x43,
coreyharris 0:6727152ebfbb 253
coreyharris 0:6727152ebfbb 254 /// 0x44 r/o adc_data_port_04 PIXI port 4 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 255 adc_data_port_04 = 0x44,
coreyharris 0:6727152ebfbb 256
coreyharris 0:6727152ebfbb 257 /// 0x45 r/o adc_data_port_05 PIXI port 5 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 258 adc_data_port_05 = 0x45,
coreyharris 0:6727152ebfbb 259
coreyharris 0:6727152ebfbb 260 /// 0x46 r/o adc_data_port_06 PIXI port 6 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 261 adc_data_port_06 = 0x46,
coreyharris 0:6727152ebfbb 262
coreyharris 0:6727152ebfbb 263 /// 0x47 r/o adc_data_port_07 PIXI port 7 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 264 adc_data_port_07 = 0x47,
coreyharris 0:6727152ebfbb 265
coreyharris 0:6727152ebfbb 266 /// 0x48 r/o adc_data_port_08 PIXI port 8 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 267 adc_data_port_08 = 0x48,
coreyharris 0:6727152ebfbb 268
coreyharris 0:6727152ebfbb 269 /// 0x49 r/o adc_data_port_09 PIXI port 9 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 270 adc_data_port_09 = 0x49,
coreyharris 0:6727152ebfbb 271
coreyharris 0:6727152ebfbb 272 /// 0x4a r/o adc_data_port_10 PIXI port 10 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 273 adc_data_port_10 = 0x4a,
coreyharris 0:6727152ebfbb 274
coreyharris 0:6727152ebfbb 275 /// 0x4b r/o adc_data_port_11 PIXI port 11 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 276 adc_data_port_11 = 0x4b,
coreyharris 0:6727152ebfbb 277
coreyharris 0:6727152ebfbb 278 /// 0x4c r/o adc_data_port_12 PIXI port 12 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 279 adc_data_port_12 = 0x4c,
coreyharris 0:6727152ebfbb 280
coreyharris 0:6727152ebfbb 281 /// 0x4d r/o adc_data_port_13 PIXI port 13 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 282 adc_data_port_13 = 0x4d,
coreyharris 0:6727152ebfbb 283
coreyharris 0:6727152ebfbb 284 /// 0x4e r/o adc_data_port_14 PIXI port 14 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 285 adc_data_port_14 = 0x4e,
coreyharris 0:6727152ebfbb 286
coreyharris 0:6727152ebfbb 287 /// 0x4f r/o adc_data_port_15 PIXI port 15 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 288 adc_data_port_15 = 0x4f,
coreyharris 0:6727152ebfbb 289
coreyharris 0:6727152ebfbb 290 /// 0x50 r/o adc_data_port_16 PIXI port 16 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 291 adc_data_port_16 = 0x50,
coreyharris 0:6727152ebfbb 292
coreyharris 0:6727152ebfbb 293 /// 0x51 r/o adc_data_port_17 PIXI port 17 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 294 adc_data_port_17 = 0x51,
coreyharris 0:6727152ebfbb 295
coreyharris 0:6727152ebfbb 296 /// 0x52 r/o adc_data_port_18 PIXI port 18 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 297 adc_data_port_18 = 0x52,
coreyharris 0:6727152ebfbb 298
coreyharris 0:6727152ebfbb 299 /// 0x53 r/o adc_data_port_19 PIXI port 19 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 300 adc_data_port_19 = 0x53,
coreyharris 0:6727152ebfbb 301
coreyharris 0:6727152ebfbb 302 /// 0x60 r/w dac_data_port_00 PIXI port 0 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 303 dac_data_port_00 = 0x60,
coreyharris 0:6727152ebfbb 304
coreyharris 0:6727152ebfbb 305 /// 0x61 r/w dac_data_port_01 PIXI port 1 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 306 dac_data_port_01 = 0x61,
coreyharris 0:6727152ebfbb 307
coreyharris 0:6727152ebfbb 308 /// 0x62 r/w dac_data_port_02 PIXI port 2 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 309 dac_data_port_02 = 0x62,
coreyharris 0:6727152ebfbb 310
coreyharris 0:6727152ebfbb 311 /// 0x63 r/w dac_data_port_03 PIXI port 3 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 312 dac_data_port_03 = 0x63,
coreyharris 0:6727152ebfbb 313
coreyharris 0:6727152ebfbb 314 /// 0x64 r/w dac_data_port_04 PIXI port 4 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 315 dac_data_port_04 = 0x64,
coreyharris 0:6727152ebfbb 316
coreyharris 0:6727152ebfbb 317 /// 0x65 r/w dac_data_port_05 PIXI port 5 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 318 dac_data_port_05 = 0x65,
coreyharris 0:6727152ebfbb 319
coreyharris 0:6727152ebfbb 320 /// 0x66 r/w dac_data_port_06 PIXI port 6 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 321 dac_data_port_06 = 0x66,
coreyharris 0:6727152ebfbb 322
coreyharris 0:6727152ebfbb 323 /// 0x67 r/w dac_data_port_07 PIXI port 7 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 324 dac_data_port_07 = 0x67,
coreyharris 0:6727152ebfbb 325
coreyharris 0:6727152ebfbb 326 /// 0x68 r/w dac_data_port_08 PIXI port 8 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 327 dac_data_port_08 = 0x68,
coreyharris 0:6727152ebfbb 328
coreyharris 0:6727152ebfbb 329 /// 0x69 r/w dac_data_port_09 PIXI port 9 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 330 dac_data_port_09 = 0x69,
coreyharris 0:6727152ebfbb 331
coreyharris 0:6727152ebfbb 332 /// 0x6a r/w dac_data_port_10 PIXI port 10 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 333 dac_data_port_10 = 0x6a,
coreyharris 0:6727152ebfbb 334
coreyharris 0:6727152ebfbb 335 /// 0x6b r/w dac_data_port_11 PIXI port 11 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 336 dac_data_port_11 = 0x6b,
coreyharris 0:6727152ebfbb 337
coreyharris 0:6727152ebfbb 338 /// 0x6c r/w dac_data_port_12 PIXI port 12 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 339 dac_data_port_12 = 0x6c,
coreyharris 0:6727152ebfbb 340
coreyharris 0:6727152ebfbb 341 /// 0x6d r/w dac_data_port_13 PIXI port 13 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 342 dac_data_port_13 = 0x6d,
coreyharris 0:6727152ebfbb 343
coreyharris 0:6727152ebfbb 344 /// 0x6e r/w dac_data_port_14 PIXI port 14 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 345 dac_data_port_14 = 0x6e,
coreyharris 0:6727152ebfbb 346
coreyharris 0:6727152ebfbb 347 /// 0x6f r/w dac_data_port_15 PIXI port 15 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 348 dac_data_port_15 = 0x6f,
coreyharris 0:6727152ebfbb 349
coreyharris 0:6727152ebfbb 350 /// 0x70 r/w dac_data_port_16 PIXI port 16 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 351 dac_data_port_16 = 0x70,
coreyharris 0:6727152ebfbb 352
coreyharris 0:6727152ebfbb 353 /// 0x71 r/w dac_data_port_17 PIXI port 17 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 354 dac_data_port_17 = 0x71,
coreyharris 0:6727152ebfbb 355
coreyharris 0:6727152ebfbb 356 /// 0x72 r/w dac_data_port_18 PIXI port 18 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 357 dac_data_port_18 = 0x72,
coreyharris 0:6727152ebfbb 358
coreyharris 0:6727152ebfbb 359 /// 0x73 r/w dac_data_port_19 PIXI port 19 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 360 dac_data_port_19 = 0x73,
coreyharris 0:6727152ebfbb 361
coreyharris 0:6727152ebfbb 362 } MAX11300RegAddress_t;
coreyharris 0:6727152ebfbb 363
coreyharris 0:6727152ebfbb 364 /// 0x00 r/o dev_id Device Identification
coreyharris 0:6727152ebfbb 365 /// <code>1111xxxxxxxxxxxx</code> PART Part field
coreyharris 0:6727152ebfbb 366 /// <code>xxxx11xxxxxxxxxx</code> REV Revision
coreyharris 0:6727152ebfbb 367 /// <code>xxxxxx11xxxxxxxx</code> IFMODE Inteface Mode
coreyharris 0:6727152ebfbb 368 /// <code>xxxxxxxx11xxxxxx</code> IFSP Inteface Speed
coreyharris 0:6727152ebfbb 369 /// <code>xxxxxxxxxx11xxxx</code> NBRPRTS Number of ports
coreyharris 0:6727152ebfbb 370 /// <code>xxxxxxxxxxxx11xx</code> RES Resolution
coreyharris 0:6727152ebfbb 371 /// <code>xxxxxxxxxxxxxx11</code> VRNG Voltage Range
coreyharris 0:6727152ebfbb 372 #define dev_id_PART 0xf000
coreyharris 0:6727152ebfbb 373 #define dev_id_REV 0x0c00
coreyharris 0:6727152ebfbb 374 #define dev_id_IFMODE 0x0300
coreyharris 0:6727152ebfbb 375 #define dev_id_IFSP 0x00c0
coreyharris 0:6727152ebfbb 376 #define dev_id_NBRPRTS 0x0030
coreyharris 0:6727152ebfbb 377 #define dev_id_RES 0x000c
coreyharris 0:6727152ebfbb 378 #define dev_id_VRNG 0x0003
coreyharris 0:6727152ebfbb 379
coreyharris 0:6727152ebfbb 380 /// 0x01 r/o interrupt_flag Interrupt flags
coreyharris 0:6727152ebfbb 381 /// <code>1xxxxxxxxxxxxxxx</code> VMON High Voltage Supply Monitor
coreyharris 0:6727152ebfbb 382 /// <code>x1xxxxxxxxxxxxxx</code> TMPEXT2HOT External Temperature D1P/D1N Hot
coreyharris 0:6727152ebfbb 383 /// <code>xx1xxxxxxxxxxxxx</code> TMPEXT2COLD External Temperature D1P/D1N Cold
coreyharris 0:6727152ebfbb 384 /// <code>xxx1xxxxxxxxxxxx</code> TMPEXT2NEW External Temperature D1P/D1N New
coreyharris 0:6727152ebfbb 385 /// <code>xxxx1xxxxxxxxxxx</code> TMPEXT1HOT External Temperature D0P/D0N Hot
coreyharris 0:6727152ebfbb 386 /// <code>xxxxx1xxxxxxxxxx</code> TMPEXT1COLD External Temperature D0P/D0N Cold
coreyharris 0:6727152ebfbb 387 /// <code>xxxxxx1xxxxxxxxx</code> TMPEXT1NEW External Temperature D0P/D0N New
coreyharris 0:6727152ebfbb 388 /// <code>xxxxxxx1xxxxxxxx</code> TMPINTHOT Internal Temeprature Hot
coreyharris 0:6727152ebfbb 389 /// <code>xxxxxxxx1xxxxxxx</code> TMPINTCOLD Internal Temeprature Cold
coreyharris 0:6727152ebfbb 390 /// <code>xxxxxxxxx1xxxxxx</code> TMPINTNEW Internal Temeprature New
coreyharris 0:6727152ebfbb 391 /// <code>xxxxxxxxxx1xxxxx</code> DACOI DAC over-current
coreyharris 0:6727152ebfbb 392 /// <code>xxxxxxxxxxx1xxxx</code> GPIDM GPI event missed
coreyharris 0:6727152ebfbb 393 /// <code>xxxxxxxxxxxx1xxx</code> GPIDR GPI event ready
coreyharris 0:6727152ebfbb 394 /// <code>xxxxxxxxxxxxx1xx</code> ADCDM ADC data missed
coreyharris 0:6727152ebfbb 395 /// <code>xxxxxxxxxxxxxx1x</code> ADCDR ADC data ready
coreyharris 0:6727152ebfbb 396 /// <code>xxxxxxxxxxxxxxx1</code> ADCFLAG ADC conversion/sweep complete
coreyharris 0:6727152ebfbb 397 #define interrupt_flag_VMON 0x8000
coreyharris 0:6727152ebfbb 398 #define interrupt_flag_TMPEXT2HOT 0x4000
coreyharris 0:6727152ebfbb 399 #define interrupt_flag_TMPEXT2COLD 0x2000
coreyharris 0:6727152ebfbb 400 #define interrupt_flag_TMPEXT2NEW 0x1000
coreyharris 0:6727152ebfbb 401 #define interrupt_flag_TMPEXT1HOT 0x0800
coreyharris 0:6727152ebfbb 402 #define interrupt_flag_TMPEXT1COLD 0x0400
coreyharris 0:6727152ebfbb 403 #define interrupt_flag_TMPEXT1NEW 0x0200
coreyharris 0:6727152ebfbb 404 #define interrupt_flag_TMPINTHOT 0x0100
coreyharris 0:6727152ebfbb 405 #define interrupt_flag_TMPINTCOLD 0x0080
coreyharris 0:6727152ebfbb 406 #define interrupt_flag_TMPINTNEW 0x0040
coreyharris 0:6727152ebfbb 407 #define interrupt_flag_DACOI 0x0020
coreyharris 0:6727152ebfbb 408 #define interrupt_flag_GPIDM 0x0010
coreyharris 0:6727152ebfbb 409 #define interrupt_flag_GPIDR 0x0008
coreyharris 0:6727152ebfbb 410 #define interrupt_flag_ADCDM 0x0004
coreyharris 0:6727152ebfbb 411 #define interrupt_flag_ADCDR 0x0002
coreyharris 0:6727152ebfbb 412 #define interrupt_flag_ADCFLAG 0x0001
coreyharris 0:6727152ebfbb 413
coreyharris 0:6727152ebfbb 414 /// 0x02 r/o adc_status_15_to_0 new ADC data available
coreyharris 0:6727152ebfbb 415 /// <code>1xxxxxxxxxxxxxxx</code> ADCST15 ADCST[15] new <see cref="adc_data_port_15"/>
coreyharris 0:6727152ebfbb 416 /// <code>x1xxxxxxxxxxxxxx</code> ADCST14 ADCST[14] new <see cref="adc_data_port_14"/>
coreyharris 0:6727152ebfbb 417 /// <code>xx1xxxxxxxxxxxxx</code> ADCST13 ADCST[13] new <see cref="adc_data_port_13"/>
coreyharris 0:6727152ebfbb 418 /// <code>xxx1xxxxxxxxxxxx</code> ADCST12 ADCST[12] new <see cref="adc_data_port_12"/>
coreyharris 0:6727152ebfbb 419 /// <code>xxxx1xxxxxxxxxxx</code> ADCST11 ADCST[11] new <see cref="adc_data_port_11"/>
coreyharris 0:6727152ebfbb 420 /// <code>xxxxx1xxxxxxxxxx</code> ADCST10 ADCST[10] new <see cref="adc_data_port_10"/>
coreyharris 0:6727152ebfbb 421 /// <code>xxxxxx1xxxxxxxxx</code> ADCST09 ADCST[9] new <see cref="adc_data_port_09"/>
coreyharris 0:6727152ebfbb 422 /// <code>xxxxxxx1xxxxxxxx</code> ADCST08 ADCST[8] new <see cref="adc_data_port_08"/>
coreyharris 0:6727152ebfbb 423 /// <code>xxxxxxxx1xxxxxxx</code> ADCST07 ADCST[7] new <see cref="adc_data_port_07"/>
coreyharris 0:6727152ebfbb 424 /// <code>xxxxxxxxx1xxxxxx</code> ADCST06 ADCST[6] new <see cref="adc_data_port_06"/>
coreyharris 0:6727152ebfbb 425 /// <code>xxxxxxxxxx1xxxxx</code> ADCST05 ADCST[5] new <see cref="adc_data_port_05"/>
coreyharris 0:6727152ebfbb 426 /// <code>xxxxxxxxxxx1xxxx</code> ADCST04 ADCST[4] new <see cref="adc_data_port_04"/>
coreyharris 0:6727152ebfbb 427 /// <code>xxxxxxxxxxxx1xxx</code> ADCST03 ADCST[3] new <see cref="adc_data_port_03"/>
coreyharris 0:6727152ebfbb 428 /// <code>xxxxxxxxxxxxx1xx</code> ADCST02 ADCST[2] new <see cref="adc_data_port_02"/>
coreyharris 0:6727152ebfbb 429 /// <code>xxxxxxxxxxxxxx1x</code> ADCST01 ADCST[1] new <see cref="adc_data_port_01"/>
coreyharris 0:6727152ebfbb 430 /// <code>xxxxxxxxxxxxxxx1</code> ADCST00 ADCST[0] new <see cref="adc_data_port_00"/>
coreyharris 0:6727152ebfbb 431 #define adc_status_15_to_0_ADCST15 0x8000
coreyharris 0:6727152ebfbb 432 #define adc_status_15_to_0_ADCST14 0x4000
coreyharris 0:6727152ebfbb 433 #define adc_status_15_to_0_ADCST13 0x2000
coreyharris 0:6727152ebfbb 434 #define adc_status_15_to_0_ADCST12 0x1000
coreyharris 0:6727152ebfbb 435 #define adc_status_15_to_0_ADCST11 0x0800
coreyharris 0:6727152ebfbb 436 #define adc_status_15_to_0_ADCST10 0x0400
coreyharris 0:6727152ebfbb 437 #define adc_status_15_to_0_ADCST09 0x0200
coreyharris 0:6727152ebfbb 438 #define adc_status_15_to_0_ADCST08 0x0100
coreyharris 0:6727152ebfbb 439 #define adc_status_15_to_0_ADCST07 0x0080
coreyharris 0:6727152ebfbb 440 #define adc_status_15_to_0_ADCST06 0x0040
coreyharris 0:6727152ebfbb 441 #define adc_status_15_to_0_ADCST05 0x0020
coreyharris 0:6727152ebfbb 442 #define adc_status_15_to_0_ADCST04 0x0010
coreyharris 0:6727152ebfbb 443 #define adc_status_15_to_0_ADCST03 0x0008
coreyharris 0:6727152ebfbb 444 #define adc_status_15_to_0_ADCST02 0x0004
coreyharris 0:6727152ebfbb 445 #define adc_status_15_to_0_ADCST01 0x0002
coreyharris 0:6727152ebfbb 446 #define adc_status_15_to_0_ADCST00 0x0001
coreyharris 0:6727152ebfbb 447
coreyharris 0:6727152ebfbb 448 /// 0x03 r/o adc_status_19_to_16 new ADC data available
coreyharris 0:6727152ebfbb 449 /// <code>1xxxxxxxxxxxxxxx</code> ADCST31 ADCST[31] new <see cref="adc_data_port_31"/>
coreyharris 0:6727152ebfbb 450 /// <code>x1xxxxxxxxxxxxxx</code> ADCST30 ADCST[30] new <see cref="adc_data_port_30"/>
coreyharris 0:6727152ebfbb 451 /// <code>xx1xxxxxxxxxxxxx</code> ADCST29 ADCST[29] new <see cref="adc_data_port_29"/>
coreyharris 0:6727152ebfbb 452 /// <code>xxx1xxxxxxxxxxxx</code> ADCST28 ADCST[28] new <see cref="adc_data_port_28"/>
coreyharris 0:6727152ebfbb 453 /// <code>xxxx1xxxxxxxxxxx</code> ADCST27 ADCST[27] new <see cref="adc_data_port_27"/>
coreyharris 0:6727152ebfbb 454 /// <code>xxxxx1xxxxxxxxxx</code> ADCST26 ADCST[26] new <see cref="adc_data_port_26"/>
coreyharris 0:6727152ebfbb 455 /// <code>xxxxxx1xxxxxxxxx</code> ADCST25 ADCST[25] new <see cref="adc_data_port_25"/>
coreyharris 0:6727152ebfbb 456 /// <code>xxxxxxx1xxxxxxxx</code> ADCST24 ADCST[24] new <see cref="adc_data_port_24"/>
coreyharris 0:6727152ebfbb 457 /// <code>xxxxxxxx1xxxxxxx</code> ADCST23 ADCST[23] new <see cref="adc_data_port_23"/>
coreyharris 0:6727152ebfbb 458 /// <code>xxxxxxxxx1xxxxxx</code> ADCST22 ADCST[22] new <see cref="adc_data_port_22"/>
coreyharris 0:6727152ebfbb 459 /// <code>xxxxxxxxxx1xxxxx</code> ADCST21 ADCST[21] new <see cref="adc_data_port_21"/>
coreyharris 0:6727152ebfbb 460 /// <code>xxxxxxxxxxx1xxxx</code> ADCST20 ADCST[20] new <see cref="adc_data_port_20"/>
coreyharris 0:6727152ebfbb 461 /// <code>xxxxxxxxxxxx1xxx</code> ADCST19 ADCST[19] new <see cref="adc_data_port_19"/>
coreyharris 0:6727152ebfbb 462 /// <code>xxxxxxxxxxxxx1xx</code> ADCST18 ADCST[18] new <see cref="adc_data_port_18"/>
coreyharris 0:6727152ebfbb 463 /// <code>xxxxxxxxxxxxxx1x</code> ADCST17 ADCST[17] new <see cref="adc_data_port_17"/>
coreyharris 0:6727152ebfbb 464 /// <code>xxxxxxxxxxxxxxx1</code> ADCST16 ADCST[16] new <see cref="adc_data_port_16"/>
coreyharris 0:6727152ebfbb 465 #define adc_status_19_to_16_ADCST31 0x8000
coreyharris 0:6727152ebfbb 466 #define adc_status_19_to_16_ADCST30 0x4000
coreyharris 0:6727152ebfbb 467 #define adc_status_19_to_16_ADCST29 0x2000
coreyharris 0:6727152ebfbb 468 #define adc_status_19_to_16_ADCST28 0x1000
coreyharris 0:6727152ebfbb 469 #define adc_status_19_to_16_ADCST27 0x0800
coreyharris 0:6727152ebfbb 470 #define adc_status_19_to_16_ADCST26 0x0400
coreyharris 0:6727152ebfbb 471 #define adc_status_19_to_16_ADCST25 0x0200
coreyharris 0:6727152ebfbb 472 #define adc_status_19_to_16_ADCST24 0x0100
coreyharris 0:6727152ebfbb 473 #define adc_status_19_to_16_ADCST23 0x0080
coreyharris 0:6727152ebfbb 474 #define adc_status_19_to_16_ADCST22 0x0040
coreyharris 0:6727152ebfbb 475 #define adc_status_19_to_16_ADCST21 0x0020
coreyharris 0:6727152ebfbb 476 #define adc_status_19_to_16_ADCST20 0x0010
coreyharris 0:6727152ebfbb 477 #define adc_status_19_to_16_ADCST19 0x0008
coreyharris 0:6727152ebfbb 478 #define adc_status_19_to_16_ADCST18 0x0004
coreyharris 0:6727152ebfbb 479 #define adc_status_19_to_16_ADCST17 0x0002
coreyharris 0:6727152ebfbb 480 #define adc_status_19_to_16_ADCST16 0x0001
coreyharris 0:6727152ebfbb 481
coreyharris 0:6727152ebfbb 482 /// 0x04 r/o dac_oi_status_15_to_0 DAC Overcurrent Interrupt
coreyharris 0:6727152ebfbb 483 /// <code>1xxxxxxxxxxxxxxx</code> DACOIST15 DACOIST[15] new <see cref="dac_data_port_15"/>
coreyharris 0:6727152ebfbb 484 /// <code>x1xxxxxxxxxxxxxx</code> DACOIST14 DACOIST[14] new <see cref="dac_data_port_14"/>
coreyharris 0:6727152ebfbb 485 /// <code>xx1xxxxxxxxxxxxx</code> DACOIST13 DACOIST[13] new <see cref="dac_data_port_13"/>
coreyharris 0:6727152ebfbb 486 /// <code>xxx1xxxxxxxxxxxx</code> DACOIST12 DACOIST[12] new <see cref="dac_data_port_12"/>
coreyharris 0:6727152ebfbb 487 /// <code>xxxx1xxxxxxxxxxx</code> DACOIST11 DACOIST[11] new <see cref="dac_data_port_11"/>
coreyharris 0:6727152ebfbb 488 /// <code>xxxxx1xxxxxxxxxx</code> DACOIST10 DACOIST[10] new <see cref="dac_data_port_10"/>
coreyharris 0:6727152ebfbb 489 /// <code>xxxxxx1xxxxxxxxx</code> DACOIST09 DACOIST[9] new <see cref="dac_data_port_09"/>
coreyharris 0:6727152ebfbb 490 /// <code>xxxxxxx1xxxxxxxx</code> DACOIST08 DACOIST[8] new <see cref="dac_data_port_08"/>
coreyharris 0:6727152ebfbb 491 /// <code>xxxxxxxx1xxxxxxx</code> DACOIST07 DACOIST[7] new <see cref="dac_data_port_07"/>
coreyharris 0:6727152ebfbb 492 /// <code>xxxxxxxxx1xxxxxx</code> DACOIST06 DACOIST[6] new <see cref="dac_data_port_06"/>
coreyharris 0:6727152ebfbb 493 /// <code>xxxxxxxxxx1xxxxx</code> DACOIST05 DACOIST[5] new <see cref="dac_data_port_05"/>
coreyharris 0:6727152ebfbb 494 /// <code>xxxxxxxxxxx1xxxx</code> DACOIST04 DACOIST[4] new <see cref="dac_data_port_04"/>
coreyharris 0:6727152ebfbb 495 /// <code>xxxxxxxxxxxx1xxx</code> DACOIST03 DACOIST[3] new <see cref="dac_data_port_03"/>
coreyharris 0:6727152ebfbb 496 /// <code>xxxxxxxxxxxxx1xx</code> DACOIST02 DACOIST[2] new <see cref="dac_data_port_02"/>
coreyharris 0:6727152ebfbb 497 /// <code>xxxxxxxxxxxxxx1x</code> DACOIST01 DACOIST[1] new <see cref="dac_data_port_01"/>
coreyharris 0:6727152ebfbb 498 /// <code>xxxxxxxxxxxxxxx1</code> DACOIST00 DACOIST[0] new <see cref="dac_data_port_00"/>
coreyharris 0:6727152ebfbb 499 #define dac_oi_status_15_to_0_DACOIST15 0x8000
coreyharris 0:6727152ebfbb 500 #define dac_oi_status_15_to_0_DACOIST14 0x4000
coreyharris 0:6727152ebfbb 501 #define dac_oi_status_15_to_0_DACOIST13 0x2000
coreyharris 0:6727152ebfbb 502 #define dac_oi_status_15_to_0_DACOIST12 0x1000
coreyharris 0:6727152ebfbb 503 #define dac_oi_status_15_to_0_DACOIST11 0x0800
coreyharris 0:6727152ebfbb 504 #define dac_oi_status_15_to_0_DACOIST10 0x0400
coreyharris 0:6727152ebfbb 505 #define dac_oi_status_15_to_0_DACOIST09 0x0200
coreyharris 0:6727152ebfbb 506 #define dac_oi_status_15_to_0_DACOIST08 0x0100
coreyharris 0:6727152ebfbb 507 #define dac_oi_status_15_to_0_DACOIST07 0x0080
coreyharris 0:6727152ebfbb 508 #define dac_oi_status_15_to_0_DACOIST06 0x0040
coreyharris 0:6727152ebfbb 509 #define dac_oi_status_15_to_0_DACOIST05 0x0020
coreyharris 0:6727152ebfbb 510 #define dac_oi_status_15_to_0_DACOIST04 0x0010
coreyharris 0:6727152ebfbb 511 #define dac_oi_status_15_to_0_DACOIST03 0x0008
coreyharris 0:6727152ebfbb 512 #define dac_oi_status_15_to_0_DACOIST02 0x0004
coreyharris 0:6727152ebfbb 513 #define dac_oi_status_15_to_0_DACOIST01 0x0002
coreyharris 0:6727152ebfbb 514 #define dac_oi_status_15_to_0_DACOIST00 0x0001
coreyharris 0:6727152ebfbb 515
coreyharris 0:6727152ebfbb 516 /// 0x05 r/o dac_oi_status_19_to_16 DAC Overcurrent Interrupt
coreyharris 0:6727152ebfbb 517 /// <code>1xxxxxxxxxxxxxxx</code> DACOIST31 DACOIST[31] new <see cref="dac_data_port_31"/>
coreyharris 0:6727152ebfbb 518 /// <code>x1xxxxxxxxxxxxxx</code> DACOIST30 DACOIST[30] new <see cref="dac_data_port_30"/>
coreyharris 0:6727152ebfbb 519 /// <code>xx1xxxxxxxxxxxxx</code> DACOIST29 DACOIST[29] new <see cref="dac_data_port_29"/>
coreyharris 0:6727152ebfbb 520 /// <code>xxx1xxxxxxxxxxxx</code> DACOIST28 DACOIST[28] new <see cref="dac_data_port_28"/>
coreyharris 0:6727152ebfbb 521 /// <code>xxxx1xxxxxxxxxxx</code> DACOIST27 DACOIST[27] new <see cref="dac_data_port_27"/>
coreyharris 0:6727152ebfbb 522 /// <code>xxxxx1xxxxxxxxxx</code> DACOIST26 DACOIST[26] new <see cref="dac_data_port_26"/>
coreyharris 0:6727152ebfbb 523 /// <code>xxxxxx1xxxxxxxxx</code> DACOIST25 DACOIST[25] new <see cref="dac_data_port_25"/>
coreyharris 0:6727152ebfbb 524 /// <code>xxxxxxx1xxxxxxxx</code> DACOIST24 DACOIST[24] new <see cref="dac_data_port_24"/>
coreyharris 0:6727152ebfbb 525 /// <code>xxxxxxxx1xxxxxxx</code> DACOIST23 DACOIST[23] new <see cref="dac_data_port_23"/>
coreyharris 0:6727152ebfbb 526 /// <code>xxxxxxxxx1xxxxxx</code> DACOIST22 DACOIST[22] new <see cref="dac_data_port_22"/>
coreyharris 0:6727152ebfbb 527 /// <code>xxxxxxxxxx1xxxxx</code> DACOIST21 DACOIST[21] new <see cref="dac_data_port_21"/>
coreyharris 0:6727152ebfbb 528 /// <code>xxxxxxxxxxx1xxxx</code> DACOIST20 DACOIST[20] new <see cref="dac_data_port_20"/>
coreyharris 0:6727152ebfbb 529 /// <code>xxxxxxxxxxxx1xxx</code> DACOIST19 DACOIST[19] new <see cref="dac_data_port_19"/>
coreyharris 0:6727152ebfbb 530 /// <code>xxxxxxxxxxxxx1xx</code> DACOIST18 DACOIST[18] new <see cref="dac_data_port_18"/>
coreyharris 0:6727152ebfbb 531 /// <code>xxxxxxxxxxxxxx1x</code> DACOIST17 DACOIST[17] new <see cref="dac_data_port_17"/>
coreyharris 0:6727152ebfbb 532 /// <code>xxxxxxxxxxxxxxx1</code> DACOIST16 DACOIST[16] new <see cref="dac_data_port_16"/>
coreyharris 0:6727152ebfbb 533 #define dac_oi_status_19_to_16_DACOIST31 0x8000
coreyharris 0:6727152ebfbb 534 #define dac_oi_status_19_to_16_DACOIST30 0x4000
coreyharris 0:6727152ebfbb 535 #define dac_oi_status_19_to_16_DACOIST29 0x2000
coreyharris 0:6727152ebfbb 536 #define dac_oi_status_19_to_16_DACOIST28 0x1000
coreyharris 0:6727152ebfbb 537 #define dac_oi_status_19_to_16_DACOIST27 0x0800
coreyharris 0:6727152ebfbb 538 #define dac_oi_status_19_to_16_DACOIST26 0x0400
coreyharris 0:6727152ebfbb 539 #define dac_oi_status_19_to_16_DACOIST25 0x0200
coreyharris 0:6727152ebfbb 540 #define dac_oi_status_19_to_16_DACOIST24 0x0100
coreyharris 0:6727152ebfbb 541 #define dac_oi_status_19_to_16_DACOIST23 0x0080
coreyharris 0:6727152ebfbb 542 #define dac_oi_status_19_to_16_DACOIST22 0x0040
coreyharris 0:6727152ebfbb 543 #define dac_oi_status_19_to_16_DACOIST21 0x0020
coreyharris 0:6727152ebfbb 544 #define dac_oi_status_19_to_16_DACOIST20 0x0010
coreyharris 0:6727152ebfbb 545 #define dac_oi_status_19_to_16_DACOIST19 0x0008
coreyharris 0:6727152ebfbb 546 #define dac_oi_status_19_to_16_DACOIST18 0x0004
coreyharris 0:6727152ebfbb 547 #define dac_oi_status_19_to_16_DACOIST17 0x0002
coreyharris 0:6727152ebfbb 548 #define dac_oi_status_19_to_16_DACOIST16 0x0001
coreyharris 0:6727152ebfbb 549
coreyharris 0:6727152ebfbb 550 /// 0x06 r/o gpi_status_15_to_0 GPI event ready
coreyharris 0:6727152ebfbb 551 /// <code>1xxxxxxxxxxxxxxx</code> GPIST15 GPIST[15]
coreyharris 0:6727152ebfbb 552 /// <code>x1xxxxxxxxxxxxxx</code> GPIST14 GPIST[14]
coreyharris 0:6727152ebfbb 553 /// <code>xx1xxxxxxxxxxxxx</code> GPIST13 GPIST[13]
coreyharris 0:6727152ebfbb 554 /// <code>xxx1xxxxxxxxxxxx</code> GPIST12 GPIST[12]
coreyharris 0:6727152ebfbb 555 /// <code>xxxx1xxxxxxxxxxx</code> GPIST11 GPIST[11]
coreyharris 0:6727152ebfbb 556 /// <code>xxxxx1xxxxxxxxxx</code> GPIST10 GPIST[10]
coreyharris 0:6727152ebfbb 557 /// <code>xxxxxx1xxxxxxxxx</code> GPIST09 GPIST[9]
coreyharris 0:6727152ebfbb 558 /// <code>xxxxxxx1xxxxxxxx</code> GPIST08 GPIST[8]
coreyharris 0:6727152ebfbb 559 /// <code>xxxxxxxx1xxxxxxx</code> GPIST07 GPIST[7]
coreyharris 0:6727152ebfbb 560 /// <code>xxxxxxxxx1xxxxxx</code> GPIST06 GPIST[6]
coreyharris 0:6727152ebfbb 561 /// <code>xxxxxxxxxx1xxxxx</code> GPIST05 GPIST[5]
coreyharris 0:6727152ebfbb 562 /// <code>xxxxxxxxxxx1xxxx</code> GPIST04 GPIST[4]
coreyharris 0:6727152ebfbb 563 /// <code>xxxxxxxxxxxx1xxx</code> GPIST03 GPIST[3]
coreyharris 0:6727152ebfbb 564 /// <code>xxxxxxxxxxxxx1xx</code> GPIST02 GPIST[2]
coreyharris 0:6727152ebfbb 565 /// <code>xxxxxxxxxxxxxx1x</code> GPIST01 GPIST[1]
coreyharris 0:6727152ebfbb 566 /// <code>xxxxxxxxxxxxxxx1</code> GPIST00 GPIST[0]
coreyharris 0:6727152ebfbb 567 #define gpi_status_15_to_0_GPIST15 0x8000
coreyharris 0:6727152ebfbb 568 #define gpi_status_15_to_0_GPIST14 0x4000
coreyharris 0:6727152ebfbb 569 #define gpi_status_15_to_0_GPIST13 0x2000
coreyharris 0:6727152ebfbb 570 #define gpi_status_15_to_0_GPIST12 0x1000
coreyharris 0:6727152ebfbb 571 #define gpi_status_15_to_0_GPIST11 0x0800
coreyharris 0:6727152ebfbb 572 #define gpi_status_15_to_0_GPIST10 0x0400
coreyharris 0:6727152ebfbb 573 #define gpi_status_15_to_0_GPIST09 0x0200
coreyharris 0:6727152ebfbb 574 #define gpi_status_15_to_0_GPIST08 0x0100
coreyharris 0:6727152ebfbb 575 #define gpi_status_15_to_0_GPIST07 0x0080
coreyharris 0:6727152ebfbb 576 #define gpi_status_15_to_0_GPIST06 0x0040
coreyharris 0:6727152ebfbb 577 #define gpi_status_15_to_0_GPIST05 0x0020
coreyharris 0:6727152ebfbb 578 #define gpi_status_15_to_0_GPIST04 0x0010
coreyharris 0:6727152ebfbb 579 #define gpi_status_15_to_0_GPIST03 0x0008
coreyharris 0:6727152ebfbb 580 #define gpi_status_15_to_0_GPIST02 0x0004
coreyharris 0:6727152ebfbb 581 #define gpi_status_15_to_0_GPIST01 0x0002
coreyharris 0:6727152ebfbb 582 #define gpi_status_15_to_0_GPIST00 0x0001
coreyharris 0:6727152ebfbb 583
coreyharris 0:6727152ebfbb 584 /// 0x07 r/o gpi_status_19_to_16 GPI event ready
coreyharris 0:6727152ebfbb 585 /// <code>1xxxxxxxxxxxxxxx</code> GPIST31 GPIST[31]
coreyharris 0:6727152ebfbb 586 /// <code>x1xxxxxxxxxxxxxx</code> GPIST30 GPIST[30]
coreyharris 0:6727152ebfbb 587 /// <code>xx1xxxxxxxxxxxxx</code> GPIST29 GPIST[29]
coreyharris 0:6727152ebfbb 588 /// <code>xxx1xxxxxxxxxxxx</code> GPIST28 GPIST[28]
coreyharris 0:6727152ebfbb 589 /// <code>xxxx1xxxxxxxxxxx</code> GPIST27 GPIST[27]
coreyharris 0:6727152ebfbb 590 /// <code>xxxxx1xxxxxxxxxx</code> GPIST26 GPIST[26]
coreyharris 0:6727152ebfbb 591 /// <code>xxxxxx1xxxxxxxxx</code> GPIST25 GPIST[25]
coreyharris 0:6727152ebfbb 592 /// <code>xxxxxxx1xxxxxxxx</code> GPIST24 GPIST[24]
coreyharris 0:6727152ebfbb 593 /// <code>xxxxxxxx1xxxxxxx</code> GPIST23 GPIST[23]
coreyharris 0:6727152ebfbb 594 /// <code>xxxxxxxxx1xxxxxx</code> GPIST22 GPIST[22]
coreyharris 0:6727152ebfbb 595 /// <code>xxxxxxxxxx1xxxxx</code> GPIST21 GPIST[21]
coreyharris 0:6727152ebfbb 596 /// <code>xxxxxxxxxxx1xxxx</code> GPIST20 GPIST[20]
coreyharris 0:6727152ebfbb 597 /// <code>xxxxxxxxxxxx1xxx</code> GPIST19 GPIST[19]
coreyharris 0:6727152ebfbb 598 /// <code>xxxxxxxxxxxxx1xx</code> GPIST18 GPIST[18]
coreyharris 0:6727152ebfbb 599 /// <code>xxxxxxxxxxxxxx1x</code> GPIST17 GPIST[17]
coreyharris 0:6727152ebfbb 600 /// <code>xxxxxxxxxxxxxxx1</code> GPIST16 GPIST[16]
coreyharris 0:6727152ebfbb 601 #define gpi_status_19_to_16_GPIST31 0x8000
coreyharris 0:6727152ebfbb 602 #define gpi_status_19_to_16_GPIST30 0x4000
coreyharris 0:6727152ebfbb 603 #define gpi_status_19_to_16_GPIST29 0x2000
coreyharris 0:6727152ebfbb 604 #define gpi_status_19_to_16_GPIST28 0x1000
coreyharris 0:6727152ebfbb 605 #define gpi_status_19_to_16_GPIST27 0x0800
coreyharris 0:6727152ebfbb 606 #define gpi_status_19_to_16_GPIST26 0x0400
coreyharris 0:6727152ebfbb 607 #define gpi_status_19_to_16_GPIST25 0x0200
coreyharris 0:6727152ebfbb 608 #define gpi_status_19_to_16_GPIST24 0x0100
coreyharris 0:6727152ebfbb 609 #define gpi_status_19_to_16_GPIST23 0x0080
coreyharris 0:6727152ebfbb 610 #define gpi_status_19_to_16_GPIST22 0x0040
coreyharris 0:6727152ebfbb 611 #define gpi_status_19_to_16_GPIST21 0x0020
coreyharris 0:6727152ebfbb 612 #define gpi_status_19_to_16_GPIST20 0x0010
coreyharris 0:6727152ebfbb 613 #define gpi_status_19_to_16_GPIST19 0x0008
coreyharris 0:6727152ebfbb 614 #define gpi_status_19_to_16_GPIST18 0x0004
coreyharris 0:6727152ebfbb 615 #define gpi_status_19_to_16_GPIST17 0x0002
coreyharris 0:6727152ebfbb 616 #define gpi_status_19_to_16_GPIST16 0x0001
coreyharris 0:6727152ebfbb 617
coreyharris 0:6727152ebfbb 618 /// 0x08 r/o tmp_int_data Internal Temeprature
coreyharris 0:6727152ebfbb 619 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 620 #define tmp_int_data_tempcode 0x0fff
coreyharris 0:6727152ebfbb 621
coreyharris 0:6727152ebfbb 622 /// 0x09 r/o tmp_ext1_data External Temperature D0P/D0N
coreyharris 0:6727152ebfbb 623 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 624 #define tmp_ext1_data_tempcode 0x0fff
coreyharris 0:6727152ebfbb 625
coreyharris 0:6727152ebfbb 626 /// 0x0a r/o tmp_ext2_data External Temperature D1P/D1N
coreyharris 0:6727152ebfbb 627 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 628 #define tmp_ext2_data_tempcode 0x0fff
coreyharris 0:6727152ebfbb 629
coreyharris 0:6727152ebfbb 630 /// 0x0b r/o gpi_data_15_to_0 GPI input ports data
coreyharris 0:6727152ebfbb 631 /// <code>1xxxxxxxxxxxxxxx</code> GPIDAT15 GPIDAT[15]
coreyharris 0:6727152ebfbb 632 /// <code>x1xxxxxxxxxxxxxx</code> GPIDAT14 GPIDAT[14]
coreyharris 0:6727152ebfbb 633 /// <code>xx1xxxxxxxxxxxxx</code> GPIDAT13 GPIDAT[13]
coreyharris 0:6727152ebfbb 634 /// <code>xxx1xxxxxxxxxxxx</code> GPIDAT12 GPIDAT[12]
coreyharris 0:6727152ebfbb 635 /// <code>xxxx1xxxxxxxxxxx</code> GPIDAT11 GPIDAT[11]
coreyharris 0:6727152ebfbb 636 /// <code>xxxxx1xxxxxxxxxx</code> GPIDAT10 GPIDAT[10]
coreyharris 0:6727152ebfbb 637 /// <code>xxxxxx1xxxxxxxxx</code> GPIDAT09 GPIDAT[9]
coreyharris 0:6727152ebfbb 638 /// <code>xxxxxxx1xxxxxxxx</code> GPIDAT08 GPIDAT[8]
coreyharris 0:6727152ebfbb 639 /// <code>xxxxxxxx1xxxxxxx</code> GPIDAT07 GPIDAT[7]
coreyharris 0:6727152ebfbb 640 /// <code>xxxxxxxxx1xxxxxx</code> GPIDAT06 GPIDAT[6]
coreyharris 0:6727152ebfbb 641 /// <code>xxxxxxxxxx1xxxxx</code> GPIDAT05 GPIDAT[5]
coreyharris 0:6727152ebfbb 642 /// <code>xxxxxxxxxxx1xxxx</code> GPIDAT04 GPIDAT[4]
coreyharris 0:6727152ebfbb 643 /// <code>xxxxxxxxxxxx1xxx</code> GPIDAT03 GPIDAT[3]
coreyharris 0:6727152ebfbb 644 /// <code>xxxxxxxxxxxxx1xx</code> GPIDAT02 GPIDAT[2]
coreyharris 0:6727152ebfbb 645 /// <code>xxxxxxxxxxxxxx1x</code> GPIDAT01 GPIDAT[1]
coreyharris 0:6727152ebfbb 646 /// <code>xxxxxxxxxxxxxxx1</code> GPIDAT00 GPIDAT[0]
coreyharris 0:6727152ebfbb 647 #define gpi_data_15_to_0_GPIDAT15 0x8000
coreyharris 0:6727152ebfbb 648 #define gpi_data_15_to_0_GPIDAT14 0x4000
coreyharris 0:6727152ebfbb 649 #define gpi_data_15_to_0_GPIDAT13 0x2000
coreyharris 0:6727152ebfbb 650 #define gpi_data_15_to_0_GPIDAT12 0x1000
coreyharris 0:6727152ebfbb 651 #define gpi_data_15_to_0_GPIDAT11 0x0800
coreyharris 0:6727152ebfbb 652 #define gpi_data_15_to_0_GPIDAT10 0x0400
coreyharris 0:6727152ebfbb 653 #define gpi_data_15_to_0_GPIDAT09 0x0200
coreyharris 0:6727152ebfbb 654 #define gpi_data_15_to_0_GPIDAT08 0x0100
coreyharris 0:6727152ebfbb 655 #define gpi_data_15_to_0_GPIDAT07 0x0080
coreyharris 0:6727152ebfbb 656 #define gpi_data_15_to_0_GPIDAT06 0x0040
coreyharris 0:6727152ebfbb 657 #define gpi_data_15_to_0_GPIDAT05 0x0020
coreyharris 0:6727152ebfbb 658 #define gpi_data_15_to_0_GPIDAT04 0x0010
coreyharris 0:6727152ebfbb 659 #define gpi_data_15_to_0_GPIDAT03 0x0008
coreyharris 0:6727152ebfbb 660 #define gpi_data_15_to_0_GPIDAT02 0x0004
coreyharris 0:6727152ebfbb 661 #define gpi_data_15_to_0_GPIDAT01 0x0002
coreyharris 0:6727152ebfbb 662 #define gpi_data_15_to_0_GPIDAT00 0x0001
coreyharris 0:6727152ebfbb 663
coreyharris 0:6727152ebfbb 664 /// 0x0c r/o gpi_data_19_to_16 GPI input ports data
coreyharris 0:6727152ebfbb 665 /// <code>1xxxxxxxxxxxxxxx</code> GPIDAT31 GPIDAT[31]
coreyharris 0:6727152ebfbb 666 /// <code>x1xxxxxxxxxxxxxx</code> GPIDAT30 GPIDAT[30]
coreyharris 0:6727152ebfbb 667 /// <code>xx1xxxxxxxxxxxxx</code> GPIDAT29 GPIDAT[29]
coreyharris 0:6727152ebfbb 668 /// <code>xxx1xxxxxxxxxxxx</code> GPIDAT28 GPIDAT[28]
coreyharris 0:6727152ebfbb 669 /// <code>xxxx1xxxxxxxxxxx</code> GPIDAT27 GPIDAT[27]
coreyharris 0:6727152ebfbb 670 /// <code>xxxxx1xxxxxxxxxx</code> GPIDAT26 GPIDAT[26]
coreyharris 0:6727152ebfbb 671 /// <code>xxxxxx1xxxxxxxxx</code> GPIDAT25 GPIDAT[25]
coreyharris 0:6727152ebfbb 672 /// <code>xxxxxxx1xxxxxxxx</code> GPIDAT24 GPIDAT[24]
coreyharris 0:6727152ebfbb 673 /// <code>xxxxxxxx1xxxxxxx</code> GPIDAT23 GPIDAT[23]
coreyharris 0:6727152ebfbb 674 /// <code>xxxxxxxxx1xxxxxx</code> GPIDAT22 GPIDAT[22]
coreyharris 0:6727152ebfbb 675 /// <code>xxxxxxxxxx1xxxxx</code> GPIDAT21 GPIDAT[21]
coreyharris 0:6727152ebfbb 676 /// <code>xxxxxxxxxxx1xxxx</code> GPIDAT20 GPIDAT[20]
coreyharris 0:6727152ebfbb 677 /// <code>xxxxxxxxxxxx1xxx</code> GPIDAT19 GPIDAT[19]
coreyharris 0:6727152ebfbb 678 /// <code>xxxxxxxxxxxxx1xx</code> GPIDAT18 GPIDAT[18]
coreyharris 0:6727152ebfbb 679 /// <code>xxxxxxxxxxxxxx1x</code> GPIDAT17 GPIDAT[17]
coreyharris 0:6727152ebfbb 680 /// <code>xxxxxxxxxxxxxxx1</code> GPIDAT16 GPIDAT[16]
coreyharris 0:6727152ebfbb 681 #define gpi_data_19_to_16_GPIDAT31 0x8000
coreyharris 0:6727152ebfbb 682 #define gpi_data_19_to_16_GPIDAT30 0x4000
coreyharris 0:6727152ebfbb 683 #define gpi_data_19_to_16_GPIDAT29 0x2000
coreyharris 0:6727152ebfbb 684 #define gpi_data_19_to_16_GPIDAT28 0x1000
coreyharris 0:6727152ebfbb 685 #define gpi_data_19_to_16_GPIDAT27 0x0800
coreyharris 0:6727152ebfbb 686 #define gpi_data_19_to_16_GPIDAT26 0x0400
coreyharris 0:6727152ebfbb 687 #define gpi_data_19_to_16_GPIDAT25 0x0200
coreyharris 0:6727152ebfbb 688 #define gpi_data_19_to_16_GPIDAT24 0x0100
coreyharris 0:6727152ebfbb 689 #define gpi_data_19_to_16_GPIDAT23 0x0080
coreyharris 0:6727152ebfbb 690 #define gpi_data_19_to_16_GPIDAT22 0x0040
coreyharris 0:6727152ebfbb 691 #define gpi_data_19_to_16_GPIDAT21 0x0020
coreyharris 0:6727152ebfbb 692 #define gpi_data_19_to_16_GPIDAT20 0x0010
coreyharris 0:6727152ebfbb 693 #define gpi_data_19_to_16_GPIDAT19 0x0008
coreyharris 0:6727152ebfbb 694 #define gpi_data_19_to_16_GPIDAT18 0x0004
coreyharris 0:6727152ebfbb 695 #define gpi_data_19_to_16_GPIDAT17 0x0002
coreyharris 0:6727152ebfbb 696 #define gpi_data_19_to_16_GPIDAT16 0x0001
coreyharris 0:6727152ebfbb 697
coreyharris 0:6727152ebfbb 698 /// 0x0d r/w gpo_data_15_to_0 GPO output ports data
coreyharris 0:6727152ebfbb 699 /// <code>1xxxxxxxxxxxxxxx</code> GPODAT15 GPODAT[15]
coreyharris 0:6727152ebfbb 700 /// <code>x1xxxxxxxxxxxxxx</code> GPODAT14 GPODAT[14]
coreyharris 0:6727152ebfbb 701 /// <code>xx1xxxxxxxxxxxxx</code> GPODAT13 GPODAT[13]
coreyharris 0:6727152ebfbb 702 /// <code>xxx1xxxxxxxxxxxx</code> GPODAT12 GPODAT[12]
coreyharris 0:6727152ebfbb 703 /// <code>xxxx1xxxxxxxxxxx</code> GPODAT11 GPODAT[11]
coreyharris 0:6727152ebfbb 704 /// <code>xxxxx1xxxxxxxxxx</code> GPODAT10 GPODAT[10]
coreyharris 0:6727152ebfbb 705 /// <code>xxxxxx1xxxxxxxxx</code> GPODAT09 GPODAT[9]
coreyharris 0:6727152ebfbb 706 /// <code>xxxxxxx1xxxxxxxx</code> GPODAT08 GPODAT[8]
coreyharris 0:6727152ebfbb 707 /// <code>xxxxxxxx1xxxxxxx</code> GPODAT07 GPODAT[7]
coreyharris 0:6727152ebfbb 708 /// <code>xxxxxxxxx1xxxxxx</code> GPODAT06 GPODAT[6]
coreyharris 0:6727152ebfbb 709 /// <code>xxxxxxxxxx1xxxxx</code> GPODAT05 GPODAT[5]
coreyharris 0:6727152ebfbb 710 /// <code>xxxxxxxxxxx1xxxx</code> GPODAT04 GPODAT[4]
coreyharris 0:6727152ebfbb 711 /// <code>xxxxxxxxxxxx1xxx</code> GPODAT03 GPODAT[3]
coreyharris 0:6727152ebfbb 712 /// <code>xxxxxxxxxxxxx1xx</code> GPODAT02 GPODAT[2]
coreyharris 0:6727152ebfbb 713 /// <code>xxxxxxxxxxxxxx1x</code> GPODAT01 GPODAT[1]
coreyharris 0:6727152ebfbb 714 /// <code>xxxxxxxxxxxxxxx1</code> GPODAT00 GPODAT[0]
coreyharris 0:6727152ebfbb 715 #define gpo_data_15_to_0_GPODAT15 0x8000
coreyharris 0:6727152ebfbb 716 #define gpo_data_15_to_0_GPODAT14 0x4000
coreyharris 0:6727152ebfbb 717 #define gpo_data_15_to_0_GPODAT13 0x2000
coreyharris 0:6727152ebfbb 718 #define gpo_data_15_to_0_GPODAT12 0x1000
coreyharris 0:6727152ebfbb 719 #define gpo_data_15_to_0_GPODAT11 0x0800
coreyharris 0:6727152ebfbb 720 #define gpo_data_15_to_0_GPODAT10 0x0400
coreyharris 0:6727152ebfbb 721 #define gpo_data_15_to_0_GPODAT09 0x0200
coreyharris 0:6727152ebfbb 722 #define gpo_data_15_to_0_GPODAT08 0x0100
coreyharris 0:6727152ebfbb 723 #define gpo_data_15_to_0_GPODAT07 0x0080
coreyharris 0:6727152ebfbb 724 #define gpo_data_15_to_0_GPODAT06 0x0040
coreyharris 0:6727152ebfbb 725 #define gpo_data_15_to_0_GPODAT05 0x0020
coreyharris 0:6727152ebfbb 726 #define gpo_data_15_to_0_GPODAT04 0x0010
coreyharris 0:6727152ebfbb 727 #define gpo_data_15_to_0_GPODAT03 0x0008
coreyharris 0:6727152ebfbb 728 #define gpo_data_15_to_0_GPODAT02 0x0004
coreyharris 0:6727152ebfbb 729 #define gpo_data_15_to_0_GPODAT01 0x0002
coreyharris 0:6727152ebfbb 730 #define gpo_data_15_to_0_GPODAT00 0x0001
coreyharris 0:6727152ebfbb 731 #define gpo_data_15_to_0_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 732
coreyharris 0:6727152ebfbb 733 /// 0x0e r/w gpo_data_19_to_16 GPO output ports data
coreyharris 0:6727152ebfbb 734 /// <code>1xxxxxxxxxxxxxxx</code> GPODAT31 GPODAT[31]
coreyharris 0:6727152ebfbb 735 /// <code>x1xxxxxxxxxxxxxx</code> GPODAT30 GPODAT[30]
coreyharris 0:6727152ebfbb 736 /// <code>xx1xxxxxxxxxxxxx</code> GPODAT29 GPODAT[29]
coreyharris 0:6727152ebfbb 737 /// <code>xxx1xxxxxxxxxxxx</code> GPODAT28 GPODAT[28]
coreyharris 0:6727152ebfbb 738 /// <code>xxxx1xxxxxxxxxxx</code> GPODAT27 GPODAT[27]
coreyharris 0:6727152ebfbb 739 /// <code>xxxxx1xxxxxxxxxx</code> GPODAT26 GPODAT[26]
coreyharris 0:6727152ebfbb 740 /// <code>xxxxxx1xxxxxxxxx</code> GPODAT25 GPODAT[25]
coreyharris 0:6727152ebfbb 741 /// <code>xxxxxxx1xxxxxxxx</code> GPODAT24 GPODAT[24]
coreyharris 0:6727152ebfbb 742 /// <code>xxxxxxxx1xxxxxxx</code> GPODAT23 GPODAT[23]
coreyharris 0:6727152ebfbb 743 /// <code>xxxxxxxxx1xxxxxx</code> GPODAT22 GPODAT[22]
coreyharris 0:6727152ebfbb 744 /// <code>xxxxxxxxxx1xxxxx</code> GPODAT21 GPODAT[21]
coreyharris 0:6727152ebfbb 745 /// <code>xxxxxxxxxxx1xxxx</code> GPODAT20 GPODAT[20]
coreyharris 0:6727152ebfbb 746 /// <code>xxxxxxxxxxxx1xxx</code> GPODAT19 GPODAT[19]
coreyharris 0:6727152ebfbb 747 /// <code>xxxxxxxxxxxxx1xx</code> GPODAT18 GPODAT[18]
coreyharris 0:6727152ebfbb 748 /// <code>xxxxxxxxxxxxxx1x</code> GPODAT17 GPODAT[17]
coreyharris 0:6727152ebfbb 749 /// <code>xxxxxxxxxxxxxxx1</code> GPODAT16 GPODAT[16]
coreyharris 0:6727152ebfbb 750 #define gpo_data_19_to_16_GPODAT31 0x8000
coreyharris 0:6727152ebfbb 751 #define gpo_data_19_to_16_GPODAT30 0x4000
coreyharris 0:6727152ebfbb 752 #define gpo_data_19_to_16_GPODAT29 0x2000
coreyharris 0:6727152ebfbb 753 #define gpo_data_19_to_16_GPODAT28 0x1000
coreyharris 0:6727152ebfbb 754 #define gpo_data_19_to_16_GPODAT27 0x0800
coreyharris 0:6727152ebfbb 755 #define gpo_data_19_to_16_GPODAT26 0x0400
coreyharris 0:6727152ebfbb 756 #define gpo_data_19_to_16_GPODAT25 0x0200
coreyharris 0:6727152ebfbb 757 #define gpo_data_19_to_16_GPODAT24 0x0100
coreyharris 0:6727152ebfbb 758 #define gpo_data_19_to_16_GPODAT23 0x0080
coreyharris 0:6727152ebfbb 759 #define gpo_data_19_to_16_GPODAT22 0x0040
coreyharris 0:6727152ebfbb 760 #define gpo_data_19_to_16_GPODAT21 0x0020
coreyharris 0:6727152ebfbb 761 #define gpo_data_19_to_16_GPODAT20 0x0010
coreyharris 0:6727152ebfbb 762 #define gpo_data_19_to_16_GPODAT19 0x0008
coreyharris 0:6727152ebfbb 763 #define gpo_data_19_to_16_GPODAT18 0x0004
coreyharris 0:6727152ebfbb 764 #define gpo_data_19_to_16_GPODAT17 0x0002
coreyharris 0:6727152ebfbb 765 #define gpo_data_19_to_16_GPODAT16 0x0001
coreyharris 0:6727152ebfbb 766 #define gpo_data_19_to_16_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 767
coreyharris 0:6727152ebfbb 768 /// 0x0f r/o reserved_0F reserved
coreyharris 0:6727152ebfbb 769
coreyharris 0:6727152ebfbb 770
coreyharris 0:6727152ebfbb 771 /// 0x10 r/w device_control Global device control register
coreyharris 0:6727152ebfbb 772 /// <code>1xxxxxxxxxxxxxxx</code> RESET Soft reset command
coreyharris 0:6727152ebfbb 773 /// - 0 = No operation
coreyharris 0:6727152ebfbb 774 /// - 1 = Perform power-on reset. (This bit is self-clearing.)
coreyharris 0:6727152ebfbb 775 /// <code>x1xxxxxxxxxxxxxx</code> BRST Burst Mode
coreyharris 0:6727152ebfbb 776 /// - 0 = Automatically increment register address in serial interface burst mode.
coreyharris 0:6727152ebfbb 777 /// - 1 = Burst Read cycle through only the ADC data ports;
coreyharris 0:6727152ebfbb 778 /// Burst Write cycle through only the DAC data ports.
coreyharris 0:6727152ebfbb 779 /// <code>xx1xxxxxxxxxxxxx</code> LPEN Low Power Enable
coreyharris 0:6727152ebfbb 780 /// - 0 = Normal operation
coreyharris 0:6727152ebfbb 781 /// - 1 = Sleep mode
coreyharris 0:6727152ebfbb 782 /// <code>xxx1xxxxxxxxxxxx</code> RS_CANCEL series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N
coreyharris 0:6727152ebfbb 783 /// - 0 = Disable series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N
coreyharris 0:6727152ebfbb 784 /// - 1 = Enable series resistance cancelation on external temperature monitors D0P/D0N and D1P/D1N
coreyharris 0:6727152ebfbb 785 /// <code>xxxx1xxxxxxxxxxx</code> TMPPER temperature monitor period
coreyharris 0:6727152ebfbb 786 /// - 0 = min IH period is 32.5μsec, hold time of SAMPLE is 7μsec.
coreyharris 0:6727152ebfbb 787 /// - 1 = min IH period is 65.0μsec, hold time of SAMPLE is 15μsec.
coreyharris 0:6727152ebfbb 788 /// <code>xxxxx1xxxxxxxxxx</code> TMPCTLEXT1 monitor external temperature D1P/D1N
coreyharris 0:6727152ebfbb 789 /// <code>xxxxxx1xxxxxxxxx</code> TMPCTLEXT0 monitor external temperature D0P/D0N
coreyharris 0:6727152ebfbb 790 /// <code>xxxxxxx1xxxxxxxx</code> TMPCTLINT monitor internal temperature
coreyharris 0:6727152ebfbb 791 /// <code>xxxxxxxx1xxxxxxx</code> THSHDN Thermal Shutdown
coreyharris 0:6727152ebfbb 792 /// - 0 = Disable Thermal Shutdown
coreyharris 0:6727152ebfbb 793 /// - 1 = Enable Thermal Shutdown: reset all ports to hi-Z if <see cref="tmp_int_data"/> is greater than 145 degrees C
coreyharris 0:6727152ebfbb 794 /// <code>xxxxxxxxx1xxxxxx</code> DACREF DAC voltage reference
coreyharris 0:6727152ebfbb 795 /// - 0 = External DAC voltage reference
coreyharris 0:6727152ebfbb 796 /// - 1 = Internal DAC voltage reference
coreyharris 0:6727152ebfbb 797 /// <code>xxxxxxxxxx11xxxx</code> ADCCONV ADC conversion rate
coreyharris 0:6727152ebfbb 798 /// - 0 = 200Ksps
coreyharris 0:6727152ebfbb 799 /// - 1 = 250Ksps
coreyharris 0:6727152ebfbb 800 /// - 2 = 333Ksps
coreyharris 0:6727152ebfbb 801 /// - 3 = 400Ksps
coreyharris 0:6727152ebfbb 802 /// <code>xxxxxxxxxxxx11xx</code> DACCTL DAC update mode
coreyharris 0:6727152ebfbb 803 /// - 0 = Update DAC values in normal sequence
coreyharris 0:6727152ebfbb 804 /// - 1 = Update DAC immediately after dac_data_port_xx write
coreyharris 0:6727152ebfbb 805 /// - 2 = All DAC data registers loaded with <see cref="dac_preset_data_1"/>
coreyharris 0:6727152ebfbb 806 /// - 3 = All DAC data registers loaded with <see cref="dac_preset_data_2"/>
coreyharris 0:6727152ebfbb 807 /// <code>xxxxxxxxxxxxxx11</code> ADCCTL ADC conversion mode
coreyharris 0:6727152ebfbb 808 /// - 0 = Idle mode
coreyharris 0:6727152ebfbb 809 /// - 1 = Single sweep triggered by CNVTB pin
coreyharris 0:6727152ebfbb 810 /// - 2 = Single conversion triggered by CNVTB pin
coreyharris 0:6727152ebfbb 811 /// - 3 = Continuous sweep
coreyharris 0:6727152ebfbb 812 #define device_control_RESET 0x8000
coreyharris 0:6727152ebfbb 813 #define device_control_BRST 0x4000
coreyharris 0:6727152ebfbb 814 #define device_control_LPEN 0x2000
coreyharris 0:6727152ebfbb 815 #define device_control_RS_CANCEL 0x1000
coreyharris 0:6727152ebfbb 816 #define device_control_TMPPER 0x0800
coreyharris 0:6727152ebfbb 817 #define device_control_TMPCTLEXT1 0x0400
coreyharris 0:6727152ebfbb 818 #define device_control_TMPCTLEXT0 0x0200
coreyharris 0:6727152ebfbb 819 #define device_control_TMPCTLINT 0x0100
coreyharris 0:6727152ebfbb 820 #define device_control_THSHDN 0x0080
coreyharris 0:6727152ebfbb 821 #define device_control_DACREF 0x0040
coreyharris 0:6727152ebfbb 822 #define device_control_ADCCONV 0x0030
coreyharris 0:6727152ebfbb 823 #define device_control_DACCTL 0x000c
coreyharris 0:6727152ebfbb 824 #define device_control_ADCCTL 0x0003
coreyharris 0:6727152ebfbb 825 #define device_control_DESIGNVALUE 0x00c6
coreyharris 0:6727152ebfbb 826
coreyharris 0:6727152ebfbb 827 /// 0x11 r/w interrupt_mask interrupt mask (1 = disable interrupt source)
coreyharris 0:6727152ebfbb 828 /// <code>1xxxxxxxxxxxxxxx</code> VMON High Voltage Supply Monitor
coreyharris 0:6727152ebfbb 829 /// <code>x1xxxxxxxxxxxxxx</code> TMPEXT2HOT External Temperature D1P/D1N Hot
coreyharris 0:6727152ebfbb 830 /// <code>xx1xxxxxxxxxxxxx</code> TMPEXT2COLD External Temperature D1P/D1N Cold
coreyharris 0:6727152ebfbb 831 /// <code>xxx1xxxxxxxxxxxx</code> TMPEXT2NEW External Temperature D1P/D1N New
coreyharris 0:6727152ebfbb 832 /// <code>xxxx1xxxxxxxxxxx</code> TMPEXT1HOT External Temperature D0P/D0N Hot
coreyharris 0:6727152ebfbb 833 /// <code>xxxxx1xxxxxxxxxx</code> TMPEXT1COLD External Temperature D0P/D0N Cold
coreyharris 0:6727152ebfbb 834 /// <code>xxxxxx1xxxxxxxxx</code> TMPEXT1NEW External Temperature D0P/D0N New
coreyharris 0:6727152ebfbb 835 /// <code>xxxxxxx1xxxxxxxx</code> TMPINTHOT Internal Temeprature Hot
coreyharris 0:6727152ebfbb 836 /// <code>xxxxxxxx1xxxxxxx</code> TMPINTCOLD Internal Temeprature Cold
coreyharris 0:6727152ebfbb 837 /// <code>xxxxxxxxx1xxxxxx</code> TMPINTNEW Internal Temeprature New
coreyharris 0:6727152ebfbb 838 /// <code>xxxxxxxxxx1xxxxx</code> DACOI DAC over-current
coreyharris 0:6727152ebfbb 839 /// <code>xxxxxxxxxxx1xxxx</code> GPIDM GPI event missed
coreyharris 0:6727152ebfbb 840 /// <code>xxxxxxxxxxxx1xxx</code> GPIDR GPI event ready
coreyharris 0:6727152ebfbb 841 /// <code>xxxxxxxxxxxxx1xx</code> ADCDM ADC data missed
coreyharris 0:6727152ebfbb 842 /// <code>xxxxxxxxxxxxxx1x</code> ADCDR ADC data ready
coreyharris 0:6727152ebfbb 843 /// <code>xxxxxxxxxxxxxxx1</code> ADCFLAG ADC conversion/sweep complete
coreyharris 0:6727152ebfbb 844 #define interrupt_mask_VMON 0x8000
coreyharris 0:6727152ebfbb 845 #define interrupt_mask_TMPEXT2HOT 0x4000
coreyharris 0:6727152ebfbb 846 #define interrupt_mask_TMPEXT2COLD 0x2000
coreyharris 0:6727152ebfbb 847 #define interrupt_mask_TMPEXT2NEW 0x1000
coreyharris 0:6727152ebfbb 848 #define interrupt_mask_TMPEXT1HOT 0x0800
coreyharris 0:6727152ebfbb 849 #define interrupt_mask_TMPEXT1COLD 0x0400
coreyharris 0:6727152ebfbb 850 #define interrupt_mask_TMPEXT1NEW 0x0200
coreyharris 0:6727152ebfbb 851 #define interrupt_mask_TMPINTHOT 0x0100
coreyharris 0:6727152ebfbb 852 #define interrupt_mask_TMPINTCOLD 0x0080
coreyharris 0:6727152ebfbb 853 #define interrupt_mask_TMPINTNEW 0x0040
coreyharris 0:6727152ebfbb 854 #define interrupt_mask_DACOI 0x0020
coreyharris 0:6727152ebfbb 855 #define interrupt_mask_GPIDM 0x0010
coreyharris 0:6727152ebfbb 856 #define interrupt_mask_GPIDR 0x0008
coreyharris 0:6727152ebfbb 857 #define interrupt_mask_ADCDM 0x0004
coreyharris 0:6727152ebfbb 858 #define interrupt_mask_ADCDR 0x0002
coreyharris 0:6727152ebfbb 859 #define interrupt_mask_ADCFLAG 0x0001
coreyharris 0:6727152ebfbb 860 #define interrupt_mask_DESIGNVALUE 0xffff
coreyharris 0:6727152ebfbb 861
coreyharris 0:6727152ebfbb 862 /// 0x12 r/w gpi_irqmode_7_to_0 GPI port 0 to 7 mode register
coreyharris 0:6727152ebfbb 863 /// <code>11xxxxxxxxxxxxxx</code> GPIMD07 GPIMD[7]
coreyharris 0:6727152ebfbb 864 /// <code>xx11xxxxxxxxxxxx</code> GPIMD06 GPIMD[6]
coreyharris 0:6727152ebfbb 865 /// <code>xxxx11xxxxxxxxxx</code> GPIMD05 GPIMD[5]
coreyharris 0:6727152ebfbb 866 /// <code>xxxxxx11xxxxxxxx</code> GPIMD04 GPIMD[4]
coreyharris 0:6727152ebfbb 867 /// <code>xxxxxxxx11xxxxxx</code> GPIMD03 GPIMD[3]
coreyharris 0:6727152ebfbb 868 /// <code>xxxxxxxxxx11xxxx</code> GPIMD02 GPIMD[2]
coreyharris 0:6727152ebfbb 869 /// <code>xxxxxxxxxxxx11xx</code> GPIMD01 GPIMD[1]
coreyharris 0:6727152ebfbb 870 /// <code>xxxxxxxxxxxxxx11</code> GPIMD00 GPIMD[0]
coreyharris 0:6727152ebfbb 871 /// <para>GPIMD[portId] interrupt mask bits:
coreyharris 0:6727152ebfbb 872 /// - 0 = masked
coreyharris 0:6727152ebfbb 873 /// - 1 = detect positive edge
coreyharris 0:6727152ebfbb 874 /// - 2 = detect negative edge
coreyharris 0:6727152ebfbb 875 /// - 3 = detect positive or negative edge
coreyharris 0:6727152ebfbb 876 /// </para>
coreyharris 0:6727152ebfbb 877 #define gpi_irqmode_7_to_0_GPIMD07 0xc000
coreyharris 0:6727152ebfbb 878 #define gpi_irqmode_7_to_0_GPIMD06 0x3000
coreyharris 0:6727152ebfbb 879 #define gpi_irqmode_7_to_0_GPIMD05 0x0c00
coreyharris 0:6727152ebfbb 880 #define gpi_irqmode_7_to_0_GPIMD04 0x0300
coreyharris 0:6727152ebfbb 881 #define gpi_irqmode_7_to_0_GPIMD03 0x00c0
coreyharris 0:6727152ebfbb 882 #define gpi_irqmode_7_to_0_GPIMD02 0x0030
coreyharris 0:6727152ebfbb 883 #define gpi_irqmode_7_to_0_GPIMD01 0x000c
coreyharris 0:6727152ebfbb 884 #define gpi_irqmode_7_to_0_GPIMD00 0x0003
coreyharris 0:6727152ebfbb 885 #define gpi_irqmode_7_to_0_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 886
coreyharris 0:6727152ebfbb 887 /// 0x13 r/w gpi_irqmode_15_to_8 GPI port 8 to 15 mode register
coreyharris 0:6727152ebfbb 888 /// <code>11xxxxxxxxxxxxxx</code> GPIMD15 GPIMD[15]
coreyharris 0:6727152ebfbb 889 /// <code>xx11xxxxxxxxxxxx</code> GPIMD14 GPIMD[14]
coreyharris 0:6727152ebfbb 890 /// <code>xxxx11xxxxxxxxxx</code> GPIMD13 GPIMD[13]
coreyharris 0:6727152ebfbb 891 /// <code>xxxxxx11xxxxxxxx</code> GPIMD12 GPIMD[12]
coreyharris 0:6727152ebfbb 892 /// <code>xxxxxxxx11xxxxxx</code> GPIMD11 GPIMD[11]
coreyharris 0:6727152ebfbb 893 /// <code>xxxxxxxxxx11xxxx</code> GPIMD10 GPIMD[10]
coreyharris 0:6727152ebfbb 894 /// <code>xxxxxxxxxxxx11xx</code> GPIMD09 GPIMD[9]
coreyharris 0:6727152ebfbb 895 /// <code>xxxxxxxxxxxxxx11</code> GPIMD08 GPIMD[8]
coreyharris 0:6727152ebfbb 896 /// <para>GPIMD[portId] interrupt mask bits:
coreyharris 0:6727152ebfbb 897 /// - 0 = masked
coreyharris 0:6727152ebfbb 898 /// - 1 = detect positive edge
coreyharris 0:6727152ebfbb 899 /// - 2 = detect negative edge
coreyharris 0:6727152ebfbb 900 /// - 3 = detect positive or negative edge
coreyharris 0:6727152ebfbb 901 /// </para>
coreyharris 0:6727152ebfbb 902 #define gpi_irqmode_15_to_8_GPIMD15 0xc000
coreyharris 0:6727152ebfbb 903 #define gpi_irqmode_15_to_8_GPIMD14 0x3000
coreyharris 0:6727152ebfbb 904 #define gpi_irqmode_15_to_8_GPIMD13 0x0c00
coreyharris 0:6727152ebfbb 905 #define gpi_irqmode_15_to_8_GPIMD12 0x0300
coreyharris 0:6727152ebfbb 906 #define gpi_irqmode_15_to_8_GPIMD11 0x00c0
coreyharris 0:6727152ebfbb 907 #define gpi_irqmode_15_to_8_GPIMD10 0x0030
coreyharris 0:6727152ebfbb 908 #define gpi_irqmode_15_to_8_GPIMD09 0x000c
coreyharris 0:6727152ebfbb 909 #define gpi_irqmode_15_to_8_GPIMD08 0x0003
coreyharris 0:6727152ebfbb 910 #define gpi_irqmode_15_to_8_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 911
coreyharris 0:6727152ebfbb 912 /// 0x14 r/w gpi_irqmode_19_to_16 GPI port 16 to 19 mode register
coreyharris 0:6727152ebfbb 913 /// <code>11xxxxxxxxxxxxxx</code> GPIMD23 GPIMD[23]
coreyharris 0:6727152ebfbb 914 /// <code>xx11xxxxxxxxxxxx</code> GPIMD22 GPIMD[22]
coreyharris 0:6727152ebfbb 915 /// <code>xxxx11xxxxxxxxxx</code> GPIMD21 GPIMD[21]
coreyharris 0:6727152ebfbb 916 /// <code>xxxxxx11xxxxxxxx</code> GPIMD20 GPIMD[20]
coreyharris 0:6727152ebfbb 917 /// <code>xxxxxxxx11xxxxxx</code> GPIMD19 GPIMD[19]
coreyharris 0:6727152ebfbb 918 /// <code>xxxxxxxxxx11xxxx</code> GPIMD18 GPIMD[18]
coreyharris 0:6727152ebfbb 919 /// <code>xxxxxxxxxxxx11xx</code> GPIMD17 GPIMD[17]
coreyharris 0:6727152ebfbb 920 /// <code>xxxxxxxxxxxxxx11</code> GPIMD16 GPIMD[16]
coreyharris 0:6727152ebfbb 921 /// <para>GPIMD[portId] interrupt mask bits:
coreyharris 0:6727152ebfbb 922 /// - 0 = masked
coreyharris 0:6727152ebfbb 923 /// - 1 = detect positive edge
coreyharris 0:6727152ebfbb 924 /// - 2 = detect negative edge
coreyharris 0:6727152ebfbb 925 /// - 3 = detect positive or negative edge
coreyharris 0:6727152ebfbb 926 /// </para>
coreyharris 0:6727152ebfbb 927 #define gpi_irqmode_19_to_16_GPIMD23 0xc000
coreyharris 0:6727152ebfbb 928 #define gpi_irqmode_19_to_16_GPIMD22 0x3000
coreyharris 0:6727152ebfbb 929 #define gpi_irqmode_19_to_16_GPIMD21 0x0c00
coreyharris 0:6727152ebfbb 930 #define gpi_irqmode_19_to_16_GPIMD20 0x0300
coreyharris 0:6727152ebfbb 931 #define gpi_irqmode_19_to_16_GPIMD19 0x00c0
coreyharris 0:6727152ebfbb 932 #define gpi_irqmode_19_to_16_GPIMD18 0x0030
coreyharris 0:6727152ebfbb 933 #define gpi_irqmode_19_to_16_GPIMD17 0x000c
coreyharris 0:6727152ebfbb 934 #define gpi_irqmode_19_to_16_GPIMD16 0x0003
coreyharris 0:6727152ebfbb 935 #define gpi_irqmode_19_to_16_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 936
coreyharris 0:6727152ebfbb 937 /// 0x15 r/w gpi_irqmode_31_to_24 (reserved)
coreyharris 0:6727152ebfbb 938 /// <code>11xxxxxxxxxxxxxx</code> GPIMD31 GPIMD[31]
coreyharris 0:6727152ebfbb 939 /// <code>xx11xxxxxxxxxxxx</code> GPIMD30 GPIMD[30]
coreyharris 0:6727152ebfbb 940 /// <code>xxxx11xxxxxxxxxx</code> GPIMD29 GPIMD[29]
coreyharris 0:6727152ebfbb 941 /// <code>xxxxxx11xxxxxxxx</code> GPIMD28 GPIMD[28]
coreyharris 0:6727152ebfbb 942 /// <code>xxxxxxxx11xxxxxx</code> GPIMD27 GPIMD[27]
coreyharris 0:6727152ebfbb 943 /// <code>xxxxxxxxxx11xxxx</code> GPIMD26 GPIMD[26]
coreyharris 0:6727152ebfbb 944 /// <code>xxxxxxxxxxxx11xx</code> GPIMD25 GPIMD[25]
coreyharris 0:6727152ebfbb 945 /// <code>xxxxxxxxxxxxxx11</code> GPIMD24 GPIMD[24]
coreyharris 0:6727152ebfbb 946 /// <para>GPIMD[portId] interrupt mask bits:
coreyharris 0:6727152ebfbb 947 /// - 0 = masked
coreyharris 0:6727152ebfbb 948 /// - 1 = detect positive edge
coreyharris 0:6727152ebfbb 949 /// - 2 = detect negative edge
coreyharris 0:6727152ebfbb 950 /// - 3 = detect positive or negative edge
coreyharris 0:6727152ebfbb 951 /// </para>
coreyharris 0:6727152ebfbb 952 #define gpi_irqmode_31_to_24_GPIMD31 0xc000
coreyharris 0:6727152ebfbb 953 #define gpi_irqmode_31_to_24_GPIMD30 0x3000
coreyharris 0:6727152ebfbb 954 #define gpi_irqmode_31_to_24_GPIMD29 0x0c00
coreyharris 0:6727152ebfbb 955 #define gpi_irqmode_31_to_24_GPIMD28 0x0300
coreyharris 0:6727152ebfbb 956 #define gpi_irqmode_31_to_24_GPIMD27 0x00c0
coreyharris 0:6727152ebfbb 957 #define gpi_irqmode_31_to_24_GPIMD26 0x0030
coreyharris 0:6727152ebfbb 958 #define gpi_irqmode_31_to_24_GPIMD25 0x000c
coreyharris 0:6727152ebfbb 959 #define gpi_irqmode_31_to_24_GPIMD24 0x0003
coreyharris 0:6727152ebfbb 960
coreyharris 0:6727152ebfbb 961 /// 0x16 r/w dac_preset_data_1 DAC preset activated by <see cref="device_control"/>
coreyharris 0:6727152ebfbb 962 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 963 #define dac_preset_data_1_daccode 0x0fff
coreyharris 0:6727152ebfbb 964 #define dac_preset_data_1_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 965
coreyharris 0:6727152ebfbb 966 /// 0x17 r/w dac_preset_data_2 DAC preset activated by <see cref="device_control"/>
coreyharris 0:6727152ebfbb 967 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 968 #define dac_preset_data_2_daccode 0x0fff
coreyharris 0:6727152ebfbb 969 #define dac_preset_data_2_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 970
coreyharris 0:6727152ebfbb 971 /// 0x18 r/w tmp_mon_cfg Temperautre Monitor Configuration
coreyharris 0:6727152ebfbb 972 /// <code>xxxxxxxxxx11xxxx</code> TMPEXT2MONCFG average 4, 8, 16, or 32 measurements
coreyharris 0:6727152ebfbb 973 /// <code>xxxxxxxxxxxx11xx</code> TMPEXT1MONCFG average 4, 8, 16, or 32 measurements
coreyharris 0:6727152ebfbb 974 /// <code>xxxxxxxxxxxxxx11</code> TMPINTMONCFG average 4, 8, 16, or 32 measurements
coreyharris 0:6727152ebfbb 975 /// <para>Temperautre Monitor Configuration:
coreyharris 0:6727152ebfbb 976 /// - 0 = 4 measurements (default)
coreyharris 0:6727152ebfbb 977 /// - 1 = 8 measurements
coreyharris 0:6727152ebfbb 978 /// - 2 = 16 measurements
coreyharris 0:6727152ebfbb 979 /// - 3 = 32 measurements
coreyharris 0:6727152ebfbb 980 /// </para>
coreyharris 0:6727152ebfbb 981 #define tmp_mon_cfg_TMPEXT2MONCFG 0x0030
coreyharris 0:6727152ebfbb 982 #define tmp_mon_cfg_TMPEXT1MONCFG 0x000c
coreyharris 0:6727152ebfbb 983 #define tmp_mon_cfg_TMPINTMONCFG 0x0003
coreyharris 0:6727152ebfbb 984 #define tmp_mon_cfg_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 985
coreyharris 0:6727152ebfbb 986 /// 0x19 r/w tmp_mon_int_hi_thresh Internal Temeprature Hot Threshold
coreyharris 0:6727152ebfbb 987 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 988 #define tmp_mon_int_hi_thresh_tempcode 0x0fff
coreyharris 0:6727152ebfbb 989 #define tmp_mon_int_hi_thresh_DESIGNVALUE 0x07ff
coreyharris 0:6727152ebfbb 990
coreyharris 0:6727152ebfbb 991 /// 0x1a r/w tmp_mon_int_lo_thresh Internal Temeprature Cold Threshold
coreyharris 0:6727152ebfbb 992 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 993 #define tmp_mon_int_lo_thresh_tempcode 0x0fff
coreyharris 0:6727152ebfbb 994 #define tmp_mon_int_lo_thresh_DESIGNVALUE 0x0800
coreyharris 0:6727152ebfbb 995
coreyharris 0:6727152ebfbb 996 /// 0x1b r/w tmp_mon_ext1_hi_thresh External Temperature D0P/D0N Hot Threshold
coreyharris 0:6727152ebfbb 997 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 998 #define tmp_mon_ext1_hi_thresh_tempcode 0x0fff
coreyharris 0:6727152ebfbb 999 #define tmp_mon_ext1_hi_thresh_DESIGNVALUE 0x07ff
coreyharris 0:6727152ebfbb 1000
coreyharris 0:6727152ebfbb 1001 /// 0x1c r/w tmp_mon_ext1_lo_thresh External Temperature D0P/D0N Cold Threshold
coreyharris 0:6727152ebfbb 1002 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 1003 #define tmp_mon_ext1_lo_thresh_tempcode 0x0fff
coreyharris 0:6727152ebfbb 1004 #define tmp_mon_ext1_lo_thresh_DESIGNVALUE 0x0800
coreyharris 0:6727152ebfbb 1005
coreyharris 0:6727152ebfbb 1006 /// 0x1d r/w tmp_mon_ext2_hi_thresh External Temperature D1P/D1N Hot Threshold
coreyharris 0:6727152ebfbb 1007 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 1008 #define tmp_mon_ext2_hi_thresh_tempcode 0x0fff
coreyharris 0:6727152ebfbb 1009 #define tmp_mon_ext2_hi_thresh_DESIGNVALUE 0x07ff
coreyharris 0:6727152ebfbb 1010
coreyharris 0:6727152ebfbb 1011 /// 0x1e r/w tmp_mon_ext2_lo_thresh External Temperature D1P/D1N Cold Threshold
coreyharris 0:6727152ebfbb 1012 /// <code>xxxx111111111111</code> tempcode Temperature code, LSB=0.125 degrees C, 12-bit 2's complement
coreyharris 0:6727152ebfbb 1013 #define tmp_mon_ext2_lo_thresh_tempcode 0x0fff
coreyharris 0:6727152ebfbb 1014 #define tmp_mon_ext2_lo_thresh_DESIGNVALUE 0x0800
coreyharris 0:6727152ebfbb 1015
coreyharris 0:6727152ebfbb 1016 /// 0x1f r/w reserved_1F reserved
coreyharris 0:6727152ebfbb 1017
coreyharris 0:6727152ebfbb 1018
coreyharris 0:6727152ebfbb 1019 /// 0x20 r/w port_cfg_00 PIXI port 0 configuration register
coreyharris 0:6727152ebfbb 1020 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1021 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1022 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1023 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1024 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1025 #define port_cfg_00_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1026 #define port_cfg_00_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1027 #define port_cfg_00_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1028 #define port_cfg_00_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1029 #define port_cfg_00_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1030 #define port_cfg_00_DESIGNVALUE 0x5200
coreyharris 0:6727152ebfbb 1031
coreyharris 0:6727152ebfbb 1032 /// 0x21 r/w port_cfg_01 PIXI port 1 configuration register
coreyharris 0:6727152ebfbb 1033 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1034 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1035 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1036 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1037 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1038 #define port_cfg_01_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1039 #define port_cfg_01_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1040 #define port_cfg_01_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1041 #define port_cfg_01_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1042 #define port_cfg_01_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1043 #define port_cfg_01_DESIGNVALUE 0x5200
coreyharris 0:6727152ebfbb 1044
coreyharris 0:6727152ebfbb 1045 /// 0x22 r/w port_cfg_02 PIXI port 2 configuration register
coreyharris 0:6727152ebfbb 1046 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1047 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1048 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1049 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1050 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1051 #define port_cfg_02_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1052 #define port_cfg_02_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1053 #define port_cfg_02_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1054 #define port_cfg_02_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1055 #define port_cfg_02_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1056 #define port_cfg_02_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1057
coreyharris 0:6727152ebfbb 1058 /// 0x23 r/w port_cfg_03 PIXI port 3 configuration register
coreyharris 0:6727152ebfbb 1059 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1060 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1061 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1062 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1063 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1064 #define port_cfg_03_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1065 #define port_cfg_03_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1066 #define port_cfg_03_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1067 #define port_cfg_03_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1068 #define port_cfg_03_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1069 #define port_cfg_03_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1070
coreyharris 0:6727152ebfbb 1071 /// 0x24 r/w port_cfg_04 PIXI port 4 configuration register
coreyharris 0:6727152ebfbb 1072 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1073 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1074 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1075 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1076 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1077 #define port_cfg_04_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1078 #define port_cfg_04_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1079 #define port_cfg_04_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1080 #define port_cfg_04_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1081 #define port_cfg_04_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1082 #define port_cfg_04_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1083
coreyharris 0:6727152ebfbb 1084 /// 0x25 r/w port_cfg_05 PIXI port 5 configuration register
coreyharris 0:6727152ebfbb 1085 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1086 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1087 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1088 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1089 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1090 #define port_cfg_05_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1091 #define port_cfg_05_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1092 #define port_cfg_05_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1093 #define port_cfg_05_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1094 #define port_cfg_05_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1095 #define port_cfg_05_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1096
coreyharris 0:6727152ebfbb 1097 /// 0x26 r/w port_cfg_06 PIXI port 6 configuration register
coreyharris 0:6727152ebfbb 1098 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1099 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1100 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1101 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1102 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1103 #define port_cfg_06_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1104 #define port_cfg_06_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1105 #define port_cfg_06_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1106 #define port_cfg_06_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1107 #define port_cfg_06_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1108 #define port_cfg_06_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1109
coreyharris 0:6727152ebfbb 1110 /// 0x27 r/w port_cfg_07 PIXI port 7 configuration register
coreyharris 0:6727152ebfbb 1111 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1112 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1113 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1114 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1115 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1116 #define port_cfg_07_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1117 #define port_cfg_07_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1118 #define port_cfg_07_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1119 #define port_cfg_07_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1120 #define port_cfg_07_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1121 #define port_cfg_07_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1122
coreyharris 0:6727152ebfbb 1123 /// 0x28 r/w port_cfg_08 PIXI port 8 configuration register
coreyharris 0:6727152ebfbb 1124 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1125 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1126 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1127 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1128 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1129 #define port_cfg_08_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1130 #define port_cfg_08_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1131 #define port_cfg_08_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1132 #define port_cfg_08_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1133 #define port_cfg_08_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1134 #define port_cfg_08_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1135
coreyharris 0:6727152ebfbb 1136 /// 0x29 r/w port_cfg_09 PIXI port 9 configuration register
coreyharris 0:6727152ebfbb 1137 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1138 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1139 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1140 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1141 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1142 #define port_cfg_09_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1143 #define port_cfg_09_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1144 #define port_cfg_09_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1145 #define port_cfg_09_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1146 #define port_cfg_09_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1147 #define port_cfg_09_DESIGNVALUE 0x7260
coreyharris 0:6727152ebfbb 1148
coreyharris 0:6727152ebfbb 1149 /// 0x2a r/w port_cfg_10 PIXI port 10 configuration register
coreyharris 0:6727152ebfbb 1150 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1151 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1152 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1153 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1154 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1155 #define port_cfg_10_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1156 #define port_cfg_10_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1157 #define port_cfg_10_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1158 #define port_cfg_10_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1159 #define port_cfg_10_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1160 #define port_cfg_10_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1161
coreyharris 0:6727152ebfbb 1162 /// 0x2b r/w port_cfg_11 PIXI port 11 configuration register
coreyharris 0:6727152ebfbb 1163 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1164 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1165 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1166 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1167 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1168 #define port_cfg_11_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1169 #define port_cfg_11_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1170 #define port_cfg_11_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1171 #define port_cfg_11_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1172 #define port_cfg_11_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1173 #define port_cfg_11_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1174
coreyharris 0:6727152ebfbb 1175 /// 0x2c r/w port_cfg_12 PIXI port 12 configuration register
coreyharris 0:6727152ebfbb 1176 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1177 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1178 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1179 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1180 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1181 #define port_cfg_12_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1182 #define port_cfg_12_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1183 #define port_cfg_12_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1184 #define port_cfg_12_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1185 #define port_cfg_12_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1186 #define port_cfg_12_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1187
coreyharris 0:6727152ebfbb 1188 /// 0x2d r/w port_cfg_13 PIXI port 13 configuration register
coreyharris 0:6727152ebfbb 1189 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1190 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1191 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1192 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1193 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1194 #define port_cfg_13_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1195 #define port_cfg_13_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1196 #define port_cfg_13_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1197 #define port_cfg_13_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1198 #define port_cfg_13_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1199 #define port_cfg_13_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1200
coreyharris 0:6727152ebfbb 1201 /// 0x2e r/w port_cfg_14 PIXI port 14 configuration register
coreyharris 0:6727152ebfbb 1202 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1203 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1204 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1205 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1206 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1207 #define port_cfg_14_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1208 #define port_cfg_14_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1209 #define port_cfg_14_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1210 #define port_cfg_14_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1211 #define port_cfg_14_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1212 #define port_cfg_14_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1213
coreyharris 0:6727152ebfbb 1214 /// 0x2f r/w port_cfg_15 PIXI port 15 configuration register
coreyharris 0:6727152ebfbb 1215 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1216 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1217 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1218 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1219 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1220 #define port_cfg_15_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1221 #define port_cfg_15_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1222 #define port_cfg_15_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1223 #define port_cfg_15_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1224 #define port_cfg_15_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1225 #define port_cfg_15_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1226
coreyharris 0:6727152ebfbb 1227 /// 0x30 r/w port_cfg_16 PIXI port 16 configuration register
coreyharris 0:6727152ebfbb 1228 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1229 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1230 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1231 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1232 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1233 #define port_cfg_16_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1234 #define port_cfg_16_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1235 #define port_cfg_16_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1236 #define port_cfg_16_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1237 #define port_cfg_16_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1238 #define port_cfg_16_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1239
coreyharris 0:6727152ebfbb 1240 /// 0x31 r/w port_cfg_17 PIXI port 17 configuration register
coreyharris 0:6727152ebfbb 1241 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1242 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1243 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1244 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1245 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1246 #define port_cfg_17_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1247 #define port_cfg_17_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1248 #define port_cfg_17_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1249 #define port_cfg_17_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1250 #define port_cfg_17_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1251 #define port_cfg_17_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1252
coreyharris 0:6727152ebfbb 1253 /// 0x32 r/w port_cfg_18 PIXI port 18 configuration register
coreyharris 0:6727152ebfbb 1254 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1255 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1256 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1257 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1258 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1259 #define port_cfg_18_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1260 #define port_cfg_18_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1261 #define port_cfg_18_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1262 #define port_cfg_18_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1263 #define port_cfg_18_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1264 #define port_cfg_18_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1265
coreyharris 0:6727152ebfbb 1266 /// 0x33 r/w port_cfg_19 PIXI port 19 configuration register
coreyharris 0:6727152ebfbb 1267 /// <code>1111xxxxxxxxxxxx</code> PortCfgFuncID Port function / mode
coreyharris 0:6727152ebfbb 1268 /// <code>xxxx1xxxxxxxxxxx</code> funcprm_avrInv AVR / INV
coreyharris 0:6727152ebfbb 1269 /// <code>xxxxx111xxxxxxxx</code> funcprm_range DAC Range / ADC Range
coreyharris 0:6727152ebfbb 1270 /// <code>xxxxxxxx111xxxxx</code> funcprm_nsamples Number of samples / CAP
coreyharris 0:6727152ebfbb 1271 /// <code>xxxxxxxxxxx11111</code> funcprm_port Associated port 0..31
coreyharris 0:6727152ebfbb 1272 #define port_cfg_19_PortCfgFuncID 0xf000
coreyharris 0:6727152ebfbb 1273 #define port_cfg_19_funcprm_avrInv 0x0800
coreyharris 0:6727152ebfbb 1274 #define port_cfg_19_funcprm_range 0x0700
coreyharris 0:6727152ebfbb 1275 #define port_cfg_19_funcprm_nsamples 0x00e0
coreyharris 0:6727152ebfbb 1276 #define port_cfg_19_funcprm_port 0x001f
coreyharris 0:6727152ebfbb 1277 #define port_cfg_19_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1278
coreyharris 0:6727152ebfbb 1279 /// 0x40 r/o adc_data_port_00 PIXI port 0 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1280 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1281 #define adc_data_port_00_adccode 0x0fff
coreyharris 0:6727152ebfbb 1282
coreyharris 0:6727152ebfbb 1283 /// 0x41 r/o adc_data_port_01 PIXI port 1 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1284 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1285 #define adc_data_port_01_adccode 0x0fff
coreyharris 0:6727152ebfbb 1286
coreyharris 0:6727152ebfbb 1287 /// 0x42 r/o adc_data_port_02 PIXI port 2 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1288 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1289 #define adc_data_port_02_adccode 0x0fff
coreyharris 0:6727152ebfbb 1290
coreyharris 0:6727152ebfbb 1291 /// 0x43 r/o adc_data_port_03 PIXI port 3 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1292 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1293 #define adc_data_port_03_adccode 0x0fff
coreyharris 0:6727152ebfbb 1294
coreyharris 0:6727152ebfbb 1295 /// 0x44 r/o adc_data_port_04 PIXI port 4 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1296 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1297 #define adc_data_port_04_adccode 0x0fff
coreyharris 0:6727152ebfbb 1298
coreyharris 0:6727152ebfbb 1299 /// 0x45 r/o adc_data_port_05 PIXI port 5 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1300 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1301 #define adc_data_port_05_adccode 0x0fff
coreyharris 0:6727152ebfbb 1302
coreyharris 0:6727152ebfbb 1303 /// 0x46 r/o adc_data_port_06 PIXI port 6 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1304 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1305 #define adc_data_port_06_adccode 0x0fff
coreyharris 0:6727152ebfbb 1306
coreyharris 0:6727152ebfbb 1307 /// 0x47 r/o adc_data_port_07 PIXI port 7 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1308 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1309 #define adc_data_port_07_adccode 0x0fff
coreyharris 0:6727152ebfbb 1310
coreyharris 0:6727152ebfbb 1311 /// 0x48 r/o adc_data_port_08 PIXI port 8 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1312 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1313 #define adc_data_port_08_adccode 0x0fff
coreyharris 0:6727152ebfbb 1314
coreyharris 0:6727152ebfbb 1315 /// 0x49 r/o adc_data_port_09 PIXI port 9 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1316 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1317 #define adc_data_port_09_adccode 0x0fff
coreyharris 0:6727152ebfbb 1318
coreyharris 0:6727152ebfbb 1319 /// 0x4a r/o adc_data_port_10 PIXI port 10 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1320 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1321 #define adc_data_port_10_adccode 0x0fff
coreyharris 0:6727152ebfbb 1322
coreyharris 0:6727152ebfbb 1323 /// 0x4b r/o adc_data_port_11 PIXI port 11 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1324 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1325 #define adc_data_port_11_adccode 0x0fff
coreyharris 0:6727152ebfbb 1326
coreyharris 0:6727152ebfbb 1327 /// 0x4c r/o adc_data_port_12 PIXI port 12 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1328 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1329 #define adc_data_port_12_adccode 0x0fff
coreyharris 0:6727152ebfbb 1330
coreyharris 0:6727152ebfbb 1331 /// 0x4d r/o adc_data_port_13 PIXI port 13 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1332 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1333 #define adc_data_port_13_adccode 0x0fff
coreyharris 0:6727152ebfbb 1334
coreyharris 0:6727152ebfbb 1335 /// 0x4e r/o adc_data_port_14 PIXI port 14 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1336 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1337 #define adc_data_port_14_adccode 0x0fff
coreyharris 0:6727152ebfbb 1338
coreyharris 0:6727152ebfbb 1339 /// 0x4f r/o adc_data_port_15 PIXI port 15 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1340 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1341 #define adc_data_port_15_adccode 0x0fff
coreyharris 0:6727152ebfbb 1342
coreyharris 0:6727152ebfbb 1343 /// 0x50 r/o adc_data_port_16 PIXI port 16 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1344 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1345 #define adc_data_port_16_adccode 0x0fff
coreyharris 0:6727152ebfbb 1346
coreyharris 0:6727152ebfbb 1347 /// 0x51 r/o adc_data_port_17 PIXI port 17 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1348 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1349 #define adc_data_port_17_adccode 0x0fff
coreyharris 0:6727152ebfbb 1350
coreyharris 0:6727152ebfbb 1351 /// 0x52 r/o adc_data_port_18 PIXI port 18 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1352 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1353 #define adc_data_port_18_adccode 0x0fff
coreyharris 0:6727152ebfbb 1354
coreyharris 0:6727152ebfbb 1355 /// 0x53 r/o adc_data_port_19 PIXI port 19 Analog to Digital Converter register
coreyharris 0:6727152ebfbb 1356 /// <code>xxxx111111111111</code> adccode 12-bit ADC code
coreyharris 0:6727152ebfbb 1357 #define adc_data_port_19_adccode 0x0fff
coreyharris 0:6727152ebfbb 1358
coreyharris 0:6727152ebfbb 1359 /// 0x60 r/w dac_data_port_00 PIXI port 0 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1360 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1361 #define dac_data_port_00_daccode 0x0fff
coreyharris 0:6727152ebfbb 1362 #define dac_data_port_00_DESIGNVALUE 0x0666
coreyharris 0:6727152ebfbb 1363
coreyharris 0:6727152ebfbb 1364 /// 0x61 r/w dac_data_port_01 PIXI port 1 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1365 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1366 #define dac_data_port_01_daccode 0x0fff
coreyharris 0:6727152ebfbb 1367 #define dac_data_port_01_DESIGNVALUE 0x0666
coreyharris 0:6727152ebfbb 1368
coreyharris 0:6727152ebfbb 1369 /// 0x62 r/w dac_data_port_02 PIXI port 2 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1370 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1371 #define dac_data_port_02_daccode 0x0fff
coreyharris 0:6727152ebfbb 1372 #define dac_data_port_02_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1373
coreyharris 0:6727152ebfbb 1374 /// 0x63 r/w dac_data_port_03 PIXI port 3 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1375 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1376 #define dac_data_port_03_daccode 0x0fff
coreyharris 0:6727152ebfbb 1377 #define dac_data_port_03_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1378
coreyharris 0:6727152ebfbb 1379 /// 0x64 r/w dac_data_port_04 PIXI port 4 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1380 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1381 #define dac_data_port_04_daccode 0x0fff
coreyharris 0:6727152ebfbb 1382 #define dac_data_port_04_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1383
coreyharris 0:6727152ebfbb 1384 /// 0x65 r/w dac_data_port_05 PIXI port 5 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1385 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1386 #define dac_data_port_05_daccode 0x0fff
coreyharris 0:6727152ebfbb 1387 #define dac_data_port_05_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1388
coreyharris 0:6727152ebfbb 1389 /// 0x66 r/w dac_data_port_06 PIXI port 6 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1390 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1391 #define dac_data_port_06_daccode 0x0fff
coreyharris 0:6727152ebfbb 1392 #define dac_data_port_06_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1393
coreyharris 0:6727152ebfbb 1394 /// 0x67 r/w dac_data_port_07 PIXI port 7 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1395 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1396 #define dac_data_port_07_daccode 0x0fff
coreyharris 0:6727152ebfbb 1397 #define dac_data_port_07_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1398
coreyharris 0:6727152ebfbb 1399 /// 0x68 r/w dac_data_port_08 PIXI port 8 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1400 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1401 #define dac_data_port_08_daccode 0x0fff
coreyharris 0:6727152ebfbb 1402 #define dac_data_port_08_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1403
coreyharris 0:6727152ebfbb 1404 /// 0x69 r/w dac_data_port_09 PIXI port 9 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1405 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1406 #define dac_data_port_09_daccode 0x0fff
coreyharris 0:6727152ebfbb 1407 #define dac_data_port_09_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1408
coreyharris 0:6727152ebfbb 1409 /// 0x6a r/w dac_data_port_10 PIXI port 10 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1410 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1411 #define dac_data_port_10_daccode 0x0fff
coreyharris 0:6727152ebfbb 1412 #define dac_data_port_10_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1413
coreyharris 0:6727152ebfbb 1414 /// 0x6b r/w dac_data_port_11 PIXI port 11 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1415 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1416 #define dac_data_port_11_daccode 0x0fff
coreyharris 0:6727152ebfbb 1417 #define dac_data_port_11_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1418
coreyharris 0:6727152ebfbb 1419 /// 0x6c r/w dac_data_port_12 PIXI port 12 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1420 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1421 #define dac_data_port_12_daccode 0x0fff
coreyharris 0:6727152ebfbb 1422 #define dac_data_port_12_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1423
coreyharris 0:6727152ebfbb 1424 /// 0x6d r/w dac_data_port_13 PIXI port 13 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1425 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1426 #define dac_data_port_13_daccode 0x0fff
coreyharris 0:6727152ebfbb 1427 #define dac_data_port_13_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1428
coreyharris 0:6727152ebfbb 1429 /// 0x6e r/w dac_data_port_14 PIXI port 14 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1430 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1431 #define dac_data_port_14_daccode 0x0fff
coreyharris 0:6727152ebfbb 1432 #define dac_data_port_14_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1433
coreyharris 0:6727152ebfbb 1434 /// 0x6f r/w dac_data_port_15 PIXI port 15 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1435 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1436 #define dac_data_port_15_daccode 0x0fff
coreyharris 0:6727152ebfbb 1437 #define dac_data_port_15_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1438
coreyharris 0:6727152ebfbb 1439 /// 0x70 r/w dac_data_port_16 PIXI port 16 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1440 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1441 #define dac_data_port_16_daccode 0x0fff
coreyharris 0:6727152ebfbb 1442 #define dac_data_port_16_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1443
coreyharris 0:6727152ebfbb 1444 /// 0x71 r/w dac_data_port_17 PIXI port 17 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1445 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1446 #define dac_data_port_17_daccode 0x0fff
coreyharris 0:6727152ebfbb 1447 #define dac_data_port_17_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1448
coreyharris 0:6727152ebfbb 1449 /// 0x72 r/w dac_data_port_18 PIXI port 18 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1450 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1451 #define dac_data_port_18_daccode 0x0fff
coreyharris 0:6727152ebfbb 1452 #define dac_data_port_18_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1453
coreyharris 0:6727152ebfbb 1454 /// 0x73 r/w dac_data_port_19 PIXI port 19 Digital to Analog Converter register
coreyharris 0:6727152ebfbb 1455 /// <code>xxxx111111111111</code> daccode 12-bit DAC code
coreyharris 0:6727152ebfbb 1456 #define dac_data_port_19_daccode 0x0fff
coreyharris 0:6727152ebfbb 1457 #define dac_data_port_19_DESIGNVALUE 0x0000
coreyharris 0:6727152ebfbb 1458
coreyharris 0:6727152ebfbb 1459 /// Initialize registers in sequence recommended by PIXI Port Configuration Flow Chart.
coreyharris 0:6727152ebfbb 1460 /// Requires user-provided function MAX11300regWrite(regAddress8, regData16)
coreyharris 0:6727152ebfbb 1461 /// Requires user-provided function MAX11300initDelayus(delay_us)
coreyharris 0:6727152ebfbb 1462 ///
coreyharris 0:6727152ebfbb 1463 /// PIXI ports to configure as Mode 0 HighImpedance:
coreyharris 0:6727152ebfbb 1464 /// portIndex 2 PIXI port P2
coreyharris 0:6727152ebfbb 1465 /// portIndex 3 PIXI port P3
coreyharris 0:6727152ebfbb 1466 /// portIndex 4 PIXI port P4
coreyharris 0:6727152ebfbb 1467 /// portIndex 5 PIXI port P5
coreyharris 0:6727152ebfbb 1468 /// portIndex 6 PIXI port P6
coreyharris 0:6727152ebfbb 1469 /// portIndex 7 PIXI port P7
coreyharris 0:6727152ebfbb 1470 /// portIndex 8 PIXI port P8
coreyharris 0:6727152ebfbb 1471 /// portIndex 10 PIXI port P10
coreyharris 0:6727152ebfbb 1472 /// portIndex 11 PIXI port P11
coreyharris 0:6727152ebfbb 1473 /// portIndex 12 PIXI port P12
coreyharris 0:6727152ebfbb 1474 /// portIndex 13 PIXI port P13
coreyharris 0:6727152ebfbb 1475 /// portIndex 14 PIXI port P14
coreyharris 0:6727152ebfbb 1476 /// portIndex 15 PIXI port P15
coreyharris 0:6727152ebfbb 1477 /// portIndex 16 PIXI port P16
coreyharris 0:6727152ebfbb 1478 /// portIndex 17 PIXI port P17
coreyharris 0:6727152ebfbb 1479 /// portIndex 18 PIXI port P18
coreyharris 0:6727152ebfbb 1480 /// portIndex 19 PIXI port P19
coreyharris 0:6727152ebfbb 1481 /// PIXI ports to configure as Mode 1 GPIOinPgmThreshold:
coreyharris 0:6727152ebfbb 1482 /// none
coreyharris 0:6727152ebfbb 1483 /// PIXI ports to configure as Mode 2 GPIOinOutBidirLevelTrans:
coreyharris 0:6727152ebfbb 1484 /// none
coreyharris 0:6727152ebfbb 1485 /// PIXI ports to configure as Mode 3 GPIOoutRegDrivenOutputDAClevel:
coreyharris 0:6727152ebfbb 1486 /// none
coreyharris 0:6727152ebfbb 1487 /// PIXI ports to configure as Mode 4 GPIOoutUnidirOutputDAClevel:
coreyharris 0:6727152ebfbb 1488 /// none
coreyharris 0:6727152ebfbb 1489 /// PIXI ports to configure as Mode 5 DACout:
coreyharris 0:6727152ebfbb 1490 /// portIndex 0 PIXI port P0
coreyharris 0:6727152ebfbb 1491 /// portIndex 1 PIXI port P1
coreyharris 0:6727152ebfbb 1492 /// PIXI ports to configure as Mode 6 DACoutWithADCmonitor:
coreyharris 0:6727152ebfbb 1493 /// none
coreyharris 0:6727152ebfbb 1494 /// PIXI ports to configure as Mode 7 ADCinPosSingleEnded:
coreyharris 0:6727152ebfbb 1495 /// portIndex 9 PIXI port P9
coreyharris 0:6727152ebfbb 1496 /// PIXI ports to configure as Mode 8 ADCinPosDifferential:
coreyharris 0:6727152ebfbb 1497 /// none
coreyharris 0:6727152ebfbb 1498 /// PIXI ports to configure as Mode 9 ADCinNegDifferential:
coreyharris 0:6727152ebfbb 1499 /// none
coreyharris 0:6727152ebfbb 1500 /// PIXI ports to configure as Mode 10 DACoutADCinNegDifferential:
coreyharris 0:6727152ebfbb 1501 /// none
coreyharris 0:6727152ebfbb 1502 /// PIXI ports to configure as Mode 11 GPIOBidirAnalogSwitchExtControlled:
coreyharris 0:6727152ebfbb 1503 /// none
coreyharris 0:6727152ebfbb 1504 /// PIXI ports to configure as Mode 12 GPIOBidirAnalogSwitch:
coreyharris 0:6727152ebfbb 1505 /// none
coreyharris 0:6727152ebfbb 1506 /// PIXI ports to configure as Mode 13 Reserved13:
coreyharris 0:6727152ebfbb 1507 /// none
coreyharris 0:6727152ebfbb 1508 /// PIXI ports to configure as Mode 14 Reserved14:
coreyharris 0:6727152ebfbb 1509 /// none
coreyharris 0:6727152ebfbb 1510 /// PIXI ports to configure as Mode 15 Reserved15:
coreyharris 0:6727152ebfbb 1511 /// none
coreyharris 0:6727152ebfbb 1512 ///
coreyharris 0:6727152ebfbb 1513 //inline void MAX11301init()
coreyharris 0:6727152ebfbb 1514 //{
coreyharris 0:6727152ebfbb 1515 // extern bool MAX11301regWrite(int regAddress8, int regData16);
coreyharris 0:6727152ebfbb 1516 // extern void MAX11301initDelayus(int delay_us);
coreyharris 0:6727152ebfbb 1517 //
coreyharris 0:6727152ebfbb 1518 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1519 // // Soft Reset device registers by device_control 8000_RESET
coreyharris 0:6727152ebfbb 1520 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1521 // MAX11300regWrite(device_control, 0x8000); // 1xxx xxxx xxxx xxxx RESET Soft reset command
coreyharris 0:6727152ebfbb 1522 //
coreyharris 0:6727152ebfbb 1523 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1524 // // FLOWCHART: "Configure device_control 4000_BRST, 0080_THSHDN, 0030_ADCCONV"
coreyharris 0:6727152ebfbb 1525 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1526 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40B0));
coreyharris 0:6727152ebfbb 1527 //
coreyharris 0:6727152ebfbb 1528 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1529 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?"
coreyharris 0:6727152ebfbb 1530 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1531 // // PIXI ports to configure as Mode 1 GPIOinPgmThreshold:
coreyharris 0:6727152ebfbb 1532 // // none
coreyharris 0:6727152ebfbb 1533 // // PIXI ports to configure as Mode 3 GPIOoutRegDrivenOutputDAClevel:
coreyharris 0:6727152ebfbb 1534 // // none
coreyharris 0:6727152ebfbb 1535 // // PIXI ports to configure as Mode 4 GPIOoutUnidirOutputDAClevel:
coreyharris 0:6727152ebfbb 1536 // // none
coreyharris 0:6727152ebfbb 1537 // // PIXI ports to configure as Mode 5 DACout:
coreyharris 0:6727152ebfbb 1538 // // portIndex 0 PIXI port P0
coreyharris 0:6727152ebfbb 1539 // // portIndex 1 PIXI port P1
coreyharris 0:6727152ebfbb 1540 // // PIXI ports to configure as Mode 6 DACoutWithADCmonitor:
coreyharris 0:6727152ebfbb 1541 // // none
coreyharris 0:6727152ebfbb 1542 // // PIXI ports to configure as Mode 10 DACoutADCinNegDifferential:
coreyharris 0:6727152ebfbb 1543 // // none
coreyharris 0:6727152ebfbb 1544 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1545 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1546 // // FLOWCHART: "Configure device_control 0040_DACREF, 000C_DACCTL"
coreyharris 0:6727152ebfbb 1547 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1548 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40FC));
coreyharris 0:6727152ebfbb 1549 //
coreyharris 0:6727152ebfbb 1550 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1551 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1552 // // FLOWCHART: "Wait 200us"
coreyharris 0:6727152ebfbb 1553 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1554 // MAX11300initDelayus(200);
coreyharris 0:6727152ebfbb 1555 //
coreyharris 0:6727152ebfbb 1556 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1557 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1558 // // Configure DACDAT[i] for ports in mode 5 DACout:
coreyharris 0:6727152ebfbb 1559 // // portIndex 0 PIXI port P0
coreyharris 0:6727152ebfbb 1560 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1561 // MAX11300regWrite(dac_data_port_00, dac_data_port_00_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1562 //
coreyharris 0:6727152ebfbb 1563 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1564 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1565 // // FLOWCHART: "Wait 1ms"
coreyharris 0:6727152ebfbb 1566 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1567 // MAX11300initDelayus(1000);
coreyharris 0:6727152ebfbb 1568 //
coreyharris 0:6727152ebfbb 1569 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1570 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1571 // // Configure DACDAT[i] for ports in mode 5 DACout:
coreyharris 0:6727152ebfbb 1572 // // portIndex 1 PIXI port P1
coreyharris 0:6727152ebfbb 1573 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1574 // MAX11300regWrite(dac_data_port_01, dac_data_port_01_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1575 //
coreyharris 0:6727152ebfbb 1576 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1577 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1578 // // FLOWCHART: "Wait 1ms"
coreyharris 0:6727152ebfbb 1579 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1580 // MAX11300initDelayus(1000);
coreyharris 0:6727152ebfbb 1581 //
coreyharris 0:6727152ebfbb 1582 //
coreyharris 0:6727152ebfbb 1583 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1584 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1585 // // FLOWCHART: "Enter DACPRSTDAT1 or DACPRSTDAT2"
coreyharris 0:6727152ebfbb 1586 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1587 // MAX11300regWrite(dac_preset_data_1, dac_preset_data_1_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1588 // MAX11300regWrite(dac_preset_data_2, dac_preset_data_2_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1589 //
coreyharris 0:6727152ebfbb 1590 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1591 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1592 // // FLOWCHART: "Wait 200us x number of ports in mode 1"
coreyharris 0:6727152ebfbb 1593 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1594 //
coreyharris 0:6727152ebfbb 1595 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1596 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1597 // // FLOWCHART: "Configure GPODAT[i] for ports in mode 3"
coreyharris 0:6727152ebfbb 1598 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1599 //
coreyharris 0:6727152ebfbb 1600 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1601 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1602 // // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
coreyharris 0:6727152ebfbb 1603 // // portIndex 0 PIXI port P0
coreyharris 0:6727152ebfbb 1604 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1605 // MAX11300regWrite(port_cfg_00, port_cfg_00_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1606 //
coreyharris 0:6727152ebfbb 1607 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1608 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1609 // // FLOWCHART: "Wait 1ms"
coreyharris 0:6727152ebfbb 1610 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1611 // MAX11300initDelayus(1000);
coreyharris 0:6727152ebfbb 1612 //
coreyharris 0:6727152ebfbb 1613 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1614 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1615 // // Configure FUNCID[i] FUNCPRM[i] for ports in mode 5 DACout:
coreyharris 0:6727152ebfbb 1616 // // portIndex 1 PIXI port P1
coreyharris 0:6727152ebfbb 1617 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1618 // MAX11300regWrite(port_cfg_01, port_cfg_01_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1619 //
coreyharris 0:6727152ebfbb 1620 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1621 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1622 // // FLOWCHART: "Wait 1ms"
coreyharris 0:6727152ebfbb 1623 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1624 // MAX11300initDelayus(1000);
coreyharris 0:6727152ebfbb 1625 //
coreyharris 0:6727152ebfbb 1626 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1627 // // FLOWCHART: decision "Is mode 1, 3, 4, 5, 6, or 10 used?" branch "Y"
coreyharris 0:6727152ebfbb 1628 // // FLOWCHART: "Configure GPIMD[i] for ports in mode 1"
coreyharris 0:6727152ebfbb 1629 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1630 // MAX11300regWrite(gpi_irqmode_7_to_0, gpi_irqmode_7_to_0_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1631 // MAX11300regWrite(gpi_irqmode_15_to_8, gpi_irqmode_15_to_8_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1632 // MAX11300regWrite(gpi_irqmode_19_to_16, gpi_irqmode_19_to_16_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1633 //
coreyharris 0:6727152ebfbb 1634 //
coreyharris 0:6727152ebfbb 1635 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1636 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?"
coreyharris 0:6727152ebfbb 1637 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1638 // // PIXI ports to configure as Mode 7 ADCinPosSingleEnded:
coreyharris 0:6727152ebfbb 1639 // // portIndex 9 PIXI port P9
coreyharris 0:6727152ebfbb 1640 // // PIXI ports to configure as Mode 8 ADCinPosDifferential:
coreyharris 0:6727152ebfbb 1641 // // none
coreyharris 0:6727152ebfbb 1642 // // PIXI ports to configure as Mode 9 ADCinNegDifferential:
coreyharris 0:6727152ebfbb 1643 // // none
coreyharris 0:6727152ebfbb 1644 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1645 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
coreyharris 0:6727152ebfbb 1646 // // Configure FUNCID[i] FUNCPRM[i] for ports in mode 7 ADCinPosSingleEnded:
coreyharris 0:6727152ebfbb 1647 // // portIndex 9 PIXI port P9
coreyharris 0:6727152ebfbb 1648 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1649 // MAX11300regWrite(port_cfg_09, port_cfg_09_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1650 //
coreyharris 0:6727152ebfbb 1651 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1652 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
coreyharris 0:6727152ebfbb 1653 // // FLOWCHART: "Wait 100us"
coreyharris 0:6727152ebfbb 1654 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1655 // MAX11300initDelayus(100);
coreyharris 0:6727152ebfbb 1656 //
coreyharris 0:6727152ebfbb 1657 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1658 // // FLOWCHART: decision "Is mode 7, 8, or 9 used?" branch "Y"
coreyharris 0:6727152ebfbb 1659 // // FLOWCHART: "Configure device_control 0003_ADCCTL"
coreyharris 0:6727152ebfbb 1660 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1661 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE & 0x40FF));
coreyharris 0:6727152ebfbb 1662 //
coreyharris 0:6727152ebfbb 1663 //
coreyharris 0:6727152ebfbb 1664 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1665 // // FLOWCHART: decision "Is mode 2, 11, or 12 used?"
coreyharris 0:6727152ebfbb 1666 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1667 //
coreyharris 0:6727152ebfbb 1668 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1669 // // FLOWCHART: decision "Are temperature sensors used?"
coreyharris 0:6727152ebfbb 1670 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1671 //
coreyharris 0:6727152ebfbb 1672 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1673 // // Configure final device_control design value 2000_LPEN
coreyharris 0:6727152ebfbb 1674 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1675 // MAX11300regWrite(device_control, (device_control_DESIGNVALUE));
coreyharris 0:6727152ebfbb 1676 //
coreyharris 0:6727152ebfbb 1677 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1678 // // FLOWCHART: Configure Interrupt Masks
coreyharris 0:6727152ebfbb 1679 // // ------------------------------------------------------
coreyharris 0:6727152ebfbb 1680 // MAX11300regWrite(interrupt_mask, interrupt_mask_DESIGNVALUE);
coreyharris 0:6727152ebfbb 1681 //
coreyharris 0:6727152ebfbb 1682 //
coreyharris 0:6727152ebfbb 1683 //}
coreyharris 0:6727152ebfbb 1684
coreyharris 0:6727152ebfbb 1685
coreyharris 0:6727152ebfbb 1686 #endif /* _MAX11300_DESIGNVALUE_H_ */
coreyharris 0:6727152ebfbb 1687
coreyharris 0:6727152ebfbb 1688 // End of file
coreyharris 0:6727152ebfbb 1689