Maxim Integrated / MAX11300

Library for the MAX11300

Dependents:   MAXREFDES130_131_Demo MAXREFDES130_Demo MAX11300_test

MAX11300.h@6:09a5c5c8081c, 2016-07-31 (annotated)

Committer:
j3
Date:
Sun Jul 31 22:00:30 2016 +0000
Revision:
6:09a5c5c8081c
Parent:
5:c75c615f95b2 
added counter for num samples in read adc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:bfae6930d2ff 1 /**********************************************************************
j3 0:bfae6930d2ff 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:bfae6930d2ff 3 *
j3 0:bfae6930d2ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:bfae6930d2ff 5 * copy of this software and associated documentation files (the "Software"),
j3 0:bfae6930d2ff 6 * to deal in the Software without restriction, including without limitation
j3 0:bfae6930d2ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:bfae6930d2ff 8 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:bfae6930d2ff 9 * Software is furnished to do so, subject to the following conditions:
j3 0:bfae6930d2ff 10 *
j3 0:bfae6930d2ff 11 * The above copyright notice and this permission notice shall be included
j3 0:bfae6930d2ff 12 * in all copies or substantial portions of the Software.
j3 0:bfae6930d2ff 13 *
j3 0:bfae6930d2ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:bfae6930d2ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:bfae6930d2ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:bfae6930d2ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:bfae6930d2ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:bfae6930d2ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:bfae6930d2ff 20 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:bfae6930d2ff 21 *
j3 0:bfae6930d2ff 22 * Except as contained in this notice, the name of Maxim Integrated
j3 0:bfae6930d2ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:bfae6930d2ff 24 * Products, Inc. Branding Policy.
j3 0:bfae6930d2ff 25 *
j3 0:bfae6930d2ff 26 * The mere transfer of this software does not imply any licenses
j3 0:bfae6930d2ff 27 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:bfae6930d2ff 28 * trademarks, maskwork rights, or any other form of intellectual
j3 0:bfae6930d2ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:bfae6930d2ff 30 * ownership rights.
j3 0:bfae6930d2ff 31 **********************************************************************/
j3 0:bfae6930d2ff 32
j3 0:bfae6930d2ff 33
j3 0:bfae6930d2ff 34 #ifndef MAX11300_H
j3 0:bfae6930d2ff 35 #define MAX11300_H
j3 0:bfae6930d2ff 36
j3 0:bfae6930d2ff 37 #include "mbed.h"
j3 0:bfae6930d2ff 38 #include "MAX11300Hex.h"
j3 0:bfae6930d2ff 39
j3 0:bfae6930d2ff 40 /**
j3 0:bfae6930d2ff 41 @brief MAX11300 - PIXI, 20-Port Programmable Mixed-Signal I/O with
j3 0:bfae6930d2ff 42 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
j3 0:bfae6930d2ff 43
j3 0:bfae6930d2ff 44 The MAX11300 integrates a PIXI™, 12-bit, multichannel, analog-to-digital
j3 0:bfae6930d2ff 45 converter (ADC) and a 12-bit, multichannel, buffered digital-to-analog
j3 0:bfae6930d2ff 46 converter (DAC) in a single integrated circuit (IC). This device offers
j3 0:bfae6930d2ff 47 20 mixed-signal high-voltage, bipolar ports, which are configurable as an
j3 0:bfae6930d2ff 48 ADC analog input, a DAC analog output, a general-purpose input port (GPI),
j3 0:bfae6930d2ff 49 a general-purpose output port (GPO), or an analog switch terminal.
j3 0:bfae6930d2ff 50 One internal and two external temperature sensors track junction and
j3 0:bfae6930d2ff 51 environmental temperature, respectively. Adjacent pairs of ports are
j3 0:bfae6930d2ff 52 configurable as a logic-level translator for open-drain devices or an
j3 0:bfae6930d2ff 53 analog switch.
j3 0:bfae6930d2ff 54
j3 0:bfae6930d2ff 55 Use configuration software found at
j3 0:bfae6930d2ff 56 https://www.maximintegrated.com/en/products/analog/data-converters/analog-to-digital-converters/MAX11300.html/tb_tab2
j3 0:bfae6930d2ff 57 to generate MAX11300hex.h file
j3 0:bfae6930d2ff 58 */
j3 0:bfae6930d2ff 59 class MAX11300
j3 0:bfae6930d2ff 60 {
j3 0:bfae6930d2ff 61 public:
j3 0:bfae6930d2ff 62
j3 0:bfae6930d2ff 63 ///MAX11300 Ports
j3 0:bfae6930d2ff 64 enum MAX11300_Ports
j3 0:bfae6930d2ff 65 {
j3 0:bfae6930d2ff 66 PORT0,
j3 0:bfae6930d2ff 67 PORT1,
j3 0:bfae6930d2ff 68 PORT2,
j3 0:bfae6930d2ff 69 PORT3,
j3 0:bfae6930d2ff 70 PORT4,
j3 0:bfae6930d2ff 71 PORT5,
j3 0:bfae6930d2ff 72 PORT6,
j3 0:bfae6930d2ff 73 PORT7,
j3 0:bfae6930d2ff 74 PORT8,
j3 0:bfae6930d2ff 75 PORT9,
j3 0:bfae6930d2ff 76 PORT10,
j3 0:bfae6930d2ff 77 PORT11,
j3 0:bfae6930d2ff 78 PORT12,
j3 0:bfae6930d2ff 79 PORT13,
j3 0:bfae6930d2ff 80 PORT14,
j3 0:bfae6930d2ff 81 PORT15,
j3 0:bfae6930d2ff 82 PORT16,
j3 0:bfae6930d2ff 83 PORT17,
j3 0:bfae6930d2ff 84 PORT18,
j3 0:bfae6930d2ff 85 PORT19
j3 0:bfae6930d2ff 86 };
j3 0:bfae6930d2ff 87
j3 0:bfae6930d2ff 88 ///MAX11300 Port Modes
j3 0:bfae6930d2ff 89 enum MAX11300_Port_Modes
j3 0:bfae6930d2ff 90 {
j3 0:bfae6930d2ff 91 ///HIGH_Z
j3 0:bfae6930d2ff 92 MODE_0,
j3 0:bfae6930d2ff 93 ///Digital input with programmable threshold, GPI
j3 0:bfae6930d2ff 94 MODE_1,
j3 0:bfae6930d2ff 95 ///Bidirectional level translator terminal
j3 0:bfae6930d2ff 96 MODE_2,
j3 0:bfae6930d2ff 97 ///Register-driven digital output with DAC-controlled level, GPO
j3 0:bfae6930d2ff 98 MODE_3,
j3 0:bfae6930d2ff 99 ///Unidirectional path output with DAC-controlled level, GPO
j3 0:bfae6930d2ff 100 MODE_4,
j3 0:bfae6930d2ff 101 ///Analog output for DAC
j3 0:bfae6930d2ff 102 MODE_5,
j3 0:bfae6930d2ff 103 ///Analog output for DAC with ADC monitoring
j3 0:bfae6930d2ff 104 MODE_6,
j3 0:bfae6930d2ff 105 ///Positive analog input to single-ended ADC
j3 0:bfae6930d2ff 106 MODE_7,
j3 0:bfae6930d2ff 107 ///Positive analog input to differential ADC
j3 0:bfae6930d2ff 108 MODE_8,
j3 0:bfae6930d2ff 109 ///Negative analog input to differential ADC
j3 0:bfae6930d2ff 110 MODE_9,
j3 0:bfae6930d2ff 111 ///Analog output for DAC and negative analog input to differential ADC
j3 0:bfae6930d2ff 112 MODE_10,
j3 0:bfae6930d2ff 113 ///Terminal to GPI-controlled analog switch
j3 0:bfae6930d2ff 114 MODE_11,
j3 0:bfae6930d2ff 115 ///Terminal to register-controlled analog switch
j3 0:bfae6930d2ff 116 MODE_12
j3 0:bfae6930d2ff 117 };
j3 0:bfae6930d2ff 118
j3 0:bfae6930d2ff 119 enum CmdResult
j3 0:bfae6930d2ff 120 {
j3 0:bfae6930d2ff 121 ///Failed operation
j3 0:bfae6930d2ff 122 OpFailure,
j3 0:bfae6930d2ff 123 ///Successful operation
j3 0:bfae6930d2ff 124 Success
j3 0:bfae6930d2ff 125 };
j3 0:bfae6930d2ff 126
j3 1:90e0ff21a740 127 static const uint16_t MODE_BITMASK_PROCESS_1 = 0x047A;
j3 1:90e0ff21a740 128
j3 1:90e0ff21a740 129 static const uint16_t MODE_BITMASK_PROCESS_2 = 0x0380;
j3 1:90e0ff21a740 130
j3 1:90e0ff21a740 131 static const uint16_t MODE_BITMASK_PROCESS_3 = 0x1804;
j3 1:90e0ff21a740 132
j3 0:bfae6930d2ff 133 ///@brief MAX11300 Constructor
j3 0:bfae6930d2ff 134 ///@param[in] spi_bus - reference to SPI bus for this device
j3 0:bfae6930d2ff 135 ///@param[in] cs - pin to be used for chip select
j3 0:bfae6930d2ff 136 ///@param[in] interrupt - pin to be used as interrupt input, default = NC
j3 0:bfae6930d2ff 137 ///@param[in] cnvrt - pin to be used for convert, default = NC
j3 0:bfae6930d2ff 138 MAX11300(SPI & spi_bus, PinName cs, PinName interrupt = NC, PinName cnvt = NC);
j3 0:bfae6930d2ff 139
j3 0:bfae6930d2ff 140 ///@brief MAX11300 Destructor
j3 0:bfae6930d2ff 141 ~MAX11300();
j3 0:bfae6930d2ff 142
j3 4:feb3df5409d4 143 ///@brief Writes given register with data
j3 4:feb3df5409d4 144 ///@param[in] reg - register to be written
j3 4:feb3df5409d4 145 ///@param[in] data - data to write
j3 4:feb3df5409d4 146 ///@return none
j3 0:bfae6930d2ff 147 void write_register(MAX11300RegAddress_t reg, uint16_t data);
j3 0:bfae6930d2ff 148
j3 4:feb3df5409d4 149 ///@brief Reads given register
j3 4:feb3df5409d4 150 ///@param[in] reg - register to read
j3 4:feb3df5409d4 151 ///@return contents of register
j3 0:bfae6930d2ff 152 uint16_t read_register(MAX11300RegAddress_t reg);
j3 0:bfae6930d2ff 153
j3 4:feb3df5409d4 154 ///@brief Writes a block of data starting at given register
j3 4:feb3df5409d4 155 ///@param[in] reg - register to start writing at
j3 4:feb3df5409d4 156 ///@param[in] data - pointer to data buffer
j3 4:feb3df5409d4 157 ///@param[in] num_reg - number of registers to be written
j3 4:feb3df5409d4 158 ///@return none
j3 4:feb3df5409d4 159 void block_write(MAX11300RegAddress_t reg, uint16_t * data, uint8_t num_reg);
j3 0:bfae6930d2ff 160
j3 4:feb3df5409d4 161 ///@brief Reads a block of data starting at given register
j3 4:feb3df5409d4 162 ///@param[in] reg - register to start reading at
j3 4:feb3df5409d4 163 ///@param[in] data - pointer to data buffer
j3 4:feb3df5409d4 164 ///@param[in] num_reg - number of registers to be read
j3 4:feb3df5409d4 165 ///@return none
j3 4:feb3df5409d4 166 void block_read(MAX11300RegAddress_t reg, uint16_t * data, uint8_t num_reg);
j3 0:bfae6930d2ff 167
j3 4:feb3df5409d4 168 ///@brief Writes gpo configured port with lsb of state
j3 4:feb3df5409d4 169 ///@param[in] port - gpo congigured port to be written
j3 4:feb3df5409d4 170 ///@param[in] state - lsb of state is written to port
j3 4:feb3df5409d4 171 ///@return Result of operation
j3 0:bfae6930d2ff 172 CmdResult gpio_write(MAX11300_Ports port, uint8_t state);
j3 0:bfae6930d2ff 173
j3 4:feb3df5409d4 174 ///@brief Reads gpi configured port
j3 4:feb3df5409d4 175 ///@param[in] port - gpi congigured port to be read
j3 4:feb3df5409d4 176 ///@param[out] state - lsb of state matches port state
j3 4:feb3df5409d4 177 ///@return Result of operation
j3 0:bfae6930d2ff 178 CmdResult gpio_read(MAX11300_Ports port, uint8_t & state);
j3 0:bfae6930d2ff 179
j3 4:feb3df5409d4 180 ///@brief Read single ended ADC configured port
j3 4:feb3df5409d4 181 ///@param[in] port - single ended ADC configured port
j3 4:feb3df5409d4 182 ///@param[out] data - contents of ADC data register
j3 4:feb3df5409d4 183 ///@return Result of operation
j3 1:90e0ff21a740 184 CmdResult single_ended_adc_read(MAX11300_Ports port, uint16_t & data);
j3 0:bfae6930d2ff 185
j3 4:feb3df5409d4 186 ///@brief Write single ended DAC configured port
j3 4:feb3df5409d4 187 ///@param[in] port - single ended DAC configured port
j3 5:c75c615f95b2 188 ///@param[in] data - value to be written to DAC data register
j3 4:feb3df5409d4 189 ///@return Result of operation
j3 1:90e0ff21a740 190 CmdResult single_ended_dac_write(MAX11300_Ports port, uint16_t data);
j3 0:bfae6930d2ff 191
j3 0:bfae6930d2ff 192 private:
j3 0:bfae6930d2ff 193
j3 0:bfae6930d2ff 194 SPI & m_spi_bus;
j3 0:bfae6930d2ff 195 DigitalOut m_cs;
j3 0:bfae6930d2ff 196 DigitalIn m_int;
j3 0:bfae6930d2ff 197 DigitalOut m_cnvt;
j3 0:bfae6930d2ff 198
j3 0:bfae6930d2ff 199 void init(void);
j3 1:90e0ff21a740 200 void config_process_1(uint16_t & device_control_local);
j3 1:90e0ff21a740 201 void config_process_2(uint16_t & device_control_local);
j3 0:bfae6930d2ff 202 void config_process_3(void);
j3 0:bfae6930d2ff 203 };
j3 0:bfae6930d2ff 204
j3 0:bfae6930d2ff 205 #endif /* MAX11300_H */