MSS / FXOS8700CQ

FXOS8700CQ, 6-Axis Sensor with Integrated Linear Accelerometer and Magnetometer

Dependents:   test_FXOS8700CQ testSensor

FXOS8700CQ.cpp@0:08ed32d49eca, 2015-12-25 (annotated)

Committer:
Rhyme
Date:
Fri Dec 25 05:41:05 2015 +0000
Revision:
0:08ed32d49eca
First working version. Only init and read from the data sheet implemented.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:08ed32d49eca 1 #include "mbed.h"
Rhyme 0:08ed32d49eca 2 #include "FXOS8700CQ.h"
Rhyme 0:08ed32d49eca 3
Rhyme 0:08ed32d49eca 4 /* Register Address definitions */
Rhyme 0:08ed32d49eca 5 #define REG_STATUS 0x00
Rhyme 0:08ed32d49eca 6 #define REG_OUT_X_MSB 0x01
Rhyme 0:08ed32d49eca 7 #define REG_OUT_X_LSB 0x02
Rhyme 0:08ed32d49eca 8 #define REG_OUT_Y_MSB 0x03
Rhyme 0:08ed32d49eca 9 #define REG_OUT_Y_LSB 0x04
Rhyme 0:08ed32d49eca 10 #define REG_OUT_Z_MSB 0x05
Rhyme 0:08ed32d49eca 11 #define REG_OUT_Z_LSB 0x06
Rhyme 0:08ed32d49eca 12 /* RESERVED 0x07 */
Rhyme 0:08ed32d49eca 13 /* RESERVED 0x08 */
Rhyme 0:08ed32d49eca 14 #define REG_F_SETUP 0x09
Rhyme 0:08ed32d49eca 15 #define REG_TRIG_CFG 0x0A
Rhyme 0:08ed32d49eca 16 #define REG_SYSMOD 0x0B
Rhyme 0:08ed32d49eca 17 #define REG_INT_SOURCE 0x0C
Rhyme 0:08ed32d49eca 18 #define REG_WHO_AM_I 0x0D
Rhyme 0:08ed32d49eca 19 #define REG_XYZ_DATA_CFG 0x0E
Rhyme 0:08ed32d49eca 20 #define REG_HP_FILTER_CUTOFF 0x0F
Rhyme 0:08ed32d49eca 21 #define REG_PL_STATUS 0x10
Rhyme 0:08ed32d49eca 22 #define REG_PL_CFG 0x11
Rhyme 0:08ed32d49eca 23 #define REG_PL_COUNT 0x12
Rhyme 0:08ed32d49eca 24 #define REG_PL_BF_ZCOMP 0x13
Rhyme 0:08ed32d49eca 25 #define REG_PL_THS_REG 0x14
Rhyme 0:08ed32d49eca 26 #define REG_A_FFMT_CFG 0x15
Rhyme 0:08ed32d49eca 27 #define REG_A_FFMT_SRC 0x16
Rhyme 0:08ed32d49eca 28 #define REG_A_FFMT_THS 0x17
Rhyme 0:08ed32d49eca 29 #define REG_A_FFMT_COUNT 0x18
Rhyme 0:08ed32d49eca 30 /* RESERVED 0x19 */
Rhyme 0:08ed32d49eca 31 /* RESERVED 0x1A */
Rhyme 0:08ed32d49eca 32 /* RESERVED 0x1B */
Rhyme 0:08ed32d49eca 33 /* RESERVED 0x1C */
Rhyme 0:08ed32d49eca 34 #define REG_TRANSIENT_CFG 0x1D
Rhyme 0:08ed32d49eca 35 #define REG_TRANSIENT_SRC 0x1E
Rhyme 0:08ed32d49eca 36 #define REG_TRANSIENT_THS 0x1F
Rhyme 0:08ed32d49eca 37 #define REG_TRANSIENT_COUNT 0x20
Rhyme 0:08ed32d49eca 38 #define REG_PULSE_CFG 0x21
Rhyme 0:08ed32d49eca 39 #define REG_PULSE_SRC 0x22
Rhyme 0:08ed32d49eca 40 #define REG_PULSE_THSX 0x23
Rhyme 0:08ed32d49eca 41 #define REG_PULSE_THSY 0x24
Rhyme 0:08ed32d49eca 42 #define REG_PULSE_THSZ 0x25
Rhyme 0:08ed32d49eca 43 #define REG_PULSE_TMLT 0x26
Rhyme 0:08ed32d49eca 44 #define REG_PULSE_LTCY 0x27
Rhyme 0:08ed32d49eca 45 #define REG_PULSE_WIND 0x28
Rhyme 0:08ed32d49eca 46 #define REG_ASLP_COUNT 0x29
Rhyme 0:08ed32d49eca 47 #define REG_CTRL_REG1 0x2A
Rhyme 0:08ed32d49eca 48 #define REG_CTRL_REG2 0x2B
Rhyme 0:08ed32d49eca 49 #define REG_CTRL_REG3 0x2C
Rhyme 0:08ed32d49eca 50 #define REG_CTRL_REG4 0x2D
Rhyme 0:08ed32d49eca 51 #define REG_CTRL_REG5 0x2E
Rhyme 0:08ed32d49eca 52 #define REG_OFF_X 0x2F
Rhyme 0:08ed32d49eca 53 #define REG_OFF_Y 0x30
Rhyme 0:08ed32d49eca 54 #define REG_OFF_Z 0x31
Rhyme 0:08ed32d49eca 55 #define REG_M_DR_STATUS 0x32
Rhyme 0:08ed32d49eca 56 #define REG_M_OUT_X_MSB 0x33
Rhyme 0:08ed32d49eca 57 #define REG_M_OUT_X_LSB 0x34
Rhyme 0:08ed32d49eca 58 #define REG_M_OUT_Y_MSB 0x35
Rhyme 0:08ed32d49eca 59 #define REG_M_OUT_Y_LSB 0x36
Rhyme 0:08ed32d49eca 60 #define REG_M_OUT_Z_MSB 0x37
Rhyme 0:08ed32d49eca 61 #define REG_M_OUT_Z_LSB 0x38
Rhyme 0:08ed32d49eca 62 #define REG_CMP_X_MSB 0x39
Rhyme 0:08ed32d49eca 63 #define REG_CMP_X_LSB 0x3A
Rhyme 0:08ed32d49eca 64 #define REG_CMP_Y_MSB 0x3B
Rhyme 0:08ed32d49eca 65 #define REG_CMP_Y_LSB 0x3C
Rhyme 0:08ed32d49eca 66 #define REG_CMP_Z_MSB 0x3D
Rhyme 0:08ed32d49eca 67 #define REG_CMP_Z_LSB 0x3E
Rhyme 0:08ed32d49eca 68 #define REG_M_OFF_X_MSB 0x3F
Rhyme 0:08ed32d49eca 69 #define REG_M_OFF_X_LSB 0x40
Rhyme 0:08ed32d49eca 70 #define REG_M_OFF_Y_MSB 0x41
Rhyme 0:08ed32d49eca 71 #define REG_M_OFF_Y_LSB 0x42
Rhyme 0:08ed32d49eca 72 #define REG_M_OFF_Z_MSB 0x43
Rhyme 0:08ed32d49eca 73 #define REG_M_OFF_Z_LSB 0x44
Rhyme 0:08ed32d49eca 74 #define REG_MAX_X_MSB 0x45
Rhyme 0:08ed32d49eca 75 #define REG_MAX_X_LSB 0x46
Rhyme 0:08ed32d49eca 76 #define REG_MAX_Y_MSB 0x47
Rhyme 0:08ed32d49eca 77 #define REG_MAX_Y_LSB 0x48
Rhyme 0:08ed32d49eca 78 #define REG_MAX_Z_MSB 0x49
Rhyme 0:08ed32d49eca 79 #define REG_MAX_Z_LSB 0x4A
Rhyme 0:08ed32d49eca 80 #define REG_MIN_X_MSB 0x4B
Rhyme 0:08ed32d49eca 81 #define REG_MIN_X_LSB 0x4C
Rhyme 0:08ed32d49eca 82 #define REG_MIN_Y_MSB 0x4D
Rhyme 0:08ed32d49eca 83 #define REG_MIN_Y_LSB 0x4E
Rhyme 0:08ed32d49eca 84 #define REG_MIN_Z_MSB 0x4F
Rhyme 0:08ed32d49eca 85 #define REG_MIN_Z_LSB 0x50
Rhyme 0:08ed32d49eca 86 #define REG_TEMP 0x51
Rhyme 0:08ed32d49eca 87 #define REG_M_THS_CFG 0x52
Rhyme 0:08ed32d49eca 88 #define REG_M_THS_SRC 0x53
Rhyme 0:08ed32d49eca 89 #define REG_M_THS_X_MSB 0x54
Rhyme 0:08ed32d49eca 90 #define REG_M_THS_X_LSB 0x55
Rhyme 0:08ed32d49eca 91 #define REG_M_THS_Y_MSB 0x56
Rhyme 0:08ed32d49eca 92 #define REG_M_THS_Y_LSB 0x57
Rhyme 0:08ed32d49eca 93 #define REG_M_THS_Z_MSB 0x58
Rhyme 0:08ed32d49eca 94 #define REG_M_THS_Z_LSB 0x59
Rhyme 0:08ed32d49eca 95 #define REG_M_THS_COUNT 0x5A
Rhyme 0:08ed32d49eca 96 #define REG_M_CTRL_REG1 0x5B
Rhyme 0:08ed32d49eca 97 #define REG_M_CTRL_REG2 0x5C
Rhyme 0:08ed32d49eca 98 #define REG_M_CTRL_REG3 0x5D
Rhyme 0:08ed32d49eca 99 #define REG_M_INT_SRC 0x5E
Rhyme 0:08ed32d49eca 100 #define REG_A_VECM_CFG 0x5F
Rhyme 0:08ed32d49eca 101 #define REG_A_VECM_THS_MSB 0x60
Rhyme 0:08ed32d49eca 102 #define REG_A_VECM_THS_LSB 0x61
Rhyme 0:08ed32d49eca 103 #define REG_A_VECM_CNT 0x62
Rhyme 0:08ed32d49eca 104 #define REG_A_VECM_INITX_MSB 0x63
Rhyme 0:08ed32d49eca 105 #define REG_A_VECM_INITX_LSB 0x64
Rhyme 0:08ed32d49eca 106 #define REG_A_VECM_INITY_MSB 0x65
Rhyme 0:08ed32d49eca 107 #define REG_A_VECM_INITY_LSB 0x66
Rhyme 0:08ed32d49eca 108 #define REG_A_VECM_INITZ_MSB 0x67
Rhyme 0:08ed32d49eca 109 #define REG_A_VECM_INITZ_LSB 0x68
Rhyme 0:08ed32d49eca 110 #define REG_M_VECM_CFG 0x69
Rhyme 0:08ed32d49eca 111 #define REG_M_VECM_THS_MSB 0x6A
Rhyme 0:08ed32d49eca 112 #define REG_M_VECM_THS_LSB 0x6B
Rhyme 0:08ed32d49eca 113 #define REG_M_VECM_CNT 0x6C
Rhyme 0:08ed32d49eca 114 #define REG_M_VECM_INITX_MSB 0x6D
Rhyme 0:08ed32d49eca 115 #define REG_M_VECM_INITX_LSB 0x6E
Rhyme 0:08ed32d49eca 116 #define REG_M_VECM_INITY_MSB 0x6F
Rhyme 0:08ed32d49eca 117 #define REG_M_VECM_INITY_LSB 0x70
Rhyme 0:08ed32d49eca 118 #define REG_M_VECM_INITZ_MSB 0x71
Rhyme 0:08ed32d49eca 119 #define REG_M_VECM_INITZ_LSB 0x72
Rhyme 0:08ed32d49eca 120 #define REG_A_FFMT_THS_X_MSB 0x73
Rhyme 0:08ed32d49eca 121 #define REG_A_FFMT_THS_X_LSB 0x74
Rhyme 0:08ed32d49eca 122 #define REG_A_FFMT_THS_Y_MSB 0x75
Rhyme 0:08ed32d49eca 123 #define REG_A_FFMT_THS_Y_LSB 0x76
Rhyme 0:08ed32d49eca 124 #define REG_A_FFMT_THS_Z_MSB 0x77
Rhyme 0:08ed32d49eca 125 #define REG_A_FFMT_THS_Z_LSB 0x78
Rhyme 0:08ed32d49eca 126 /* RESERVED 0x79 */
Rhyme 0:08ed32d49eca 127
Rhyme 0:08ed32d49eca 128 #define FXOS8700CQ_WHO_AM_I 0xC7
Rhyme 0:08ed32d49eca 129
Rhyme 0:08ed32d49eca 130 FXOS8700CQ::FXOS8700CQ(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr<<1)
Rhyme 0:08ed32d49eca 131 {
Rhyme 0:08ed32d49eca 132 // activate the peripheral
Rhyme 0:08ed32d49eca 133 }
Rhyme 0:08ed32d49eca 134
Rhyme 0:08ed32d49eca 135 FXOS8700CQ::~FXOS8700CQ() { }
Rhyme 0:08ed32d49eca 136
Rhyme 0:08ed32d49eca 137 void FXOS8700CQ::readRegs(int addr, uint8_t * data, int len)
Rhyme 0:08ed32d49eca 138 {
Rhyme 0:08ed32d49eca 139 char t[1] = {addr} ;
Rhyme 0:08ed32d49eca 140 m_i2c.write(m_addr, t, 1, true) ;
Rhyme 0:08ed32d49eca 141 m_i2c.read(m_addr, (char*)data, len) ;
Rhyme 0:08ed32d49eca 142 }
Rhyme 0:08ed32d49eca 143
Rhyme 0:08ed32d49eca 144 void FXOS8700CQ::writeRegs(uint8_t * data, int len)
Rhyme 0:08ed32d49eca 145 {
Rhyme 0:08ed32d49eca 146 m_i2c.write(m_addr, (char *)data, len) ;
Rhyme 0:08ed32d49eca 147 }
Rhyme 0:08ed32d49eca 148
Rhyme 0:08ed32d49eca 149 void FXOS8700CQ::standby(void)
Rhyme 0:08ed32d49eca 150 {
Rhyme 0:08ed32d49eca 151 uint8_t data[2] ;
Rhyme 0:08ed32d49eca 152 data[0] = REG_CTRL_REG1 ;
Rhyme 0:08ed32d49eca 153 data[1] = 0x00 ;
Rhyme 0:08ed32d49eca 154 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 155 }
Rhyme 0:08ed32d49eca 156
Rhyme 0:08ed32d49eca 157 void FXOS8700CQ::activate(void)
Rhyme 0:08ed32d49eca 158 {
Rhyme 0:08ed32d49eca 159 uint8_t data[2] ;
Rhyme 0:08ed32d49eca 160 data[0] = REG_CTRL_REG1 ;
Rhyme 0:08ed32d49eca 161 data[1] = 0x01 ;
Rhyme 0:08ed32d49eca 162 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 163 }
Rhyme 0:08ed32d49eca 164
Rhyme 0:08ed32d49eca 165 void FXOS8700CQ::init(void)
Rhyme 0:08ed32d49eca 166 {
Rhyme 0:08ed32d49eca 167 uint8_t data[2] ;
Rhyme 0:08ed32d49eca 168 readRegs(REG_WHO_AM_I, data, 1) ;
Rhyme 0:08ed32d49eca 169 if (data[0] != FXOS8700CQ_WHO_AM_I) {
Rhyme 0:08ed32d49eca 170 printf("Wrong FXOS8700CQ id[0x%02X], 0x%02X expected\n",
Rhyme 0:08ed32d49eca 171 data[0], FXOS8700CQ_WHO_AM_I ) ;
Rhyme 0:08ed32d49eca 172 }
Rhyme 0:08ed32d49eca 173 /* write 0000_0000 = 0x00 to CTRL_REG1 => standby */
Rhyme 0:08ed32d49eca 174 data[0] = REG_CTRL_REG1 ;
Rhyme 0:08ed32d49eca 175 data[1] = 0x00 ;
Rhyme 0:08ed32d49eca 176 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 177 /* write 0001_1111 = 0x1F to M_CTRL_REG1 */
Rhyme 0:08ed32d49eca 178 data[0] = REG_M_CTRL_REG1 ;
Rhyme 0:08ed32d49eca 179 data[1] = 0x1F ;
Rhyme 0:08ed32d49eca 180 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 181 /* write 0010_0000 = 0x20 to M_CTRL_REG2 */
Rhyme 0:08ed32d49eca 182 data[0] = REG_M_CTRL_REG2 ;
Rhyme 0:08ed32d49eca 183 data[1] = 0x20 ;
Rhyme 0:08ed32d49eca 184 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 185 /* write 0000_0001 = 0x01 to XYZ_DATA_CFG */
Rhyme 0:08ed32d49eca 186 data[0] = REG_XYZ_DATA_CFG ;
Rhyme 0:08ed32d49eca 187 data[1] = 0x01 ;
Rhyme 0:08ed32d49eca 188 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 189 /* write 0000_1101 = 0x0D to CTRL_REG1 */
Rhyme 0:08ed32d49eca 190 data[0] = REG_CTRL_REG1 ;
Rhyme 0:08ed32d49eca 191 data[1] = 0x0D ;
Rhyme 0:08ed32d49eca 192 writeRegs(data, 2) ;
Rhyme 0:08ed32d49eca 193 }
Rhyme 0:08ed32d49eca 194
Rhyme 0:08ed32d49eca 195 void FXOS8700CQ::readAccMgnData(int16_t *accData, int16_t *mgnData)
Rhyme 0:08ed32d49eca 196 {
Rhyme 0:08ed32d49eca 197 uint8_t buf[13] ; /* status + acc (6bytes) + mgn (6bytes) */
Rhyme 0:08ed32d49eca 198 readRegs(REG_STATUS, buf, 13) ;
Rhyme 0:08ed32d49eca 199 // copy the 14 bit accelerometer byte data into 16 bit words
Rhyme 0:08ed32d49eca 200 accData[0] = (int16_t)((buf[1] << 8) | buf[2]) >> 2 ;
Rhyme 0:08ed32d49eca 201 accData[1] = (int16_t)((buf[3] << 8) | buf[4]) >> 2 ;
Rhyme 0:08ed32d49eca 202 accData[2] = (int16_t)((buf[5] << 8) | buf[6]) >> 2 ;
Rhyme 0:08ed32d49eca 203 // copy the magnetometer byte data into 16 bit words
Rhyme 0:08ed32d49eca 204 mgnData[0] = (buf[ 7] << 8) | buf[ 8] ;
Rhyme 0:08ed32d49eca 205 mgnData[1] = (buf[ 9] << 8) | buf[10] ;
Rhyme 0:08ed32d49eca 206 mgnData[2] = (buf[11] << 8) | buf[12] ;
Rhyme 0:08ed32d49eca 207 }