MH / Mbed OS MAX30003WING_monitorhealth_beta_test1_6172021

RTC_MUX_3Channel_Working

Dependencies:   MAX30003 max32630fthr DS1307

main.cpp@5:f8d1f651bef5, 2017-08-28 (annotated)

Committer:
coreyharris
Date:
Mon Aug 28 20:57:10 2017 +0000
Revision:
5:f8d1f651bef5
Parent:
4:06e258ff0b97
Child:
6:86ac850c718d
update the FIFO interrupt flag

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 0:38c49bc37c7c 1 #include "mbed.h"
coreyharris 0:38c49bc37c7c 2 #include "max32630fthr.h"
coreyharris 0:38c49bc37c7c 3 #include "MAX30003.h"
coreyharris 0:38c49bc37c7c 4
coreyharris 0:38c49bc37c7c 5 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
coreyharris 0:38c49bc37c7c 6
coreyharris 0:38c49bc37c7c 7 void ecg_config(MAX30003 &ecgAFE);
coreyharris 0:38c49bc37c7c 8
coreyharris 0:38c49bc37c7c 9 /* ECG FIFO nearly full callback */
coreyharris 0:38c49bc37c7c 10 volatile bool ecgFIFOIntFlag = 0;
coreyharris 0:38c49bc37c7c 11 void ecgFIFO_callback() {
coreyharris 0:38c49bc37c7c 12
coreyharris 0:38c49bc37c7c 13 ecgFIFOIntFlag = 1;
coreyharris 0:38c49bc37c7c 14
coreyharris 0:38c49bc37c7c 15 }
coreyharris 0:38c49bc37c7c 16
coreyharris 0:38c49bc37c7c 17 int main()
coreyharris 3:420d5efbd967 18 {
coreyharris 4:06e258ff0b97 19 const int EINT_STATUS_MASK = 1 << 23;
coreyharris 3:420d5efbd967 20
coreyharris 1:86843c27cc81 21 Serial pc(USBTX, USBRX); // Use USB debug probe for serial link
coreyharris 1:86843c27cc81 22 pc.baud(115200); // Baud rate = 115200
coreyharris 1:86843c27cc81 23
coreyharris 1:86843c27cc81 24 DigitalOut rLed(LED1, LED_OFF); // Debug LEDs
coreyharris 0:38c49bc37c7c 25 DigitalOut gLed(LED2, LED_OFF);
coreyharris 0:38c49bc37c7c 26 DigitalOut bLed(LED3, LED_OFF);
coreyharris 0:38c49bc37c7c 27
coreyharris 1:86843c27cc81 28 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
coreyharris 1:86843c27cc81 29 ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
coreyharris 0:38c49bc37c7c 30
coreyharris 1:86843c27cc81 31 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
coreyharris 1:86843c27cc81 32 // P5_2 = MISO, P5_0 = SCK
coreyharris 0:38c49bc37c7c 33
coreyharris 4:06e258ff0b97 34 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
coreyharris 4:06e258ff0b97 35 ecg_config(ecgAFE); // Config ECG
coreyharris 1:86843c27cc81 36
coreyharris 0:38c49bc37c7c 37
coreyharris 4:06e258ff0b97 38 ecgAFE.writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 39
coreyharris 4:06e258ff0b97 40 uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
coreyharris 1:86843c27cc81 41 int16_t ecgSample[32];
coreyharris 2:812d40f1853d 42
coreyharris 1:86843c27cc81 43 while(1) {
coreyharris 1:86843c27cc81 44
coreyharris 4:06e258ff0b97 45 // Read back ECG samples from the FIFO
coreyharris 0:38c49bc37c7c 46 if( ecgFIFOIntFlag ) {
coreyharris 2:812d40f1853d 47
coreyharris 5:f8d1f651bef5 48 ecgFIFOIntFlag = 0;
coreyharris 4:06e258ff0b97 49 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 2:812d40f1853d 50
coreyharris 3:420d5efbd967 51 // Check if EINT interrupt asserted
coreyharris 3:420d5efbd967 52 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
coreyharris 3:420d5efbd967 53
coreyharris 4:06e258ff0b97 54 readECGSamples = 0; // Reset sample counter
coreyharris 3:420d5efbd967 55
coreyharris 2:812d40f1853d 56 do {
coreyharris 4:06e258ff0b97 57 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 4:06e258ff0b97 58 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
coreyharris 4:06e258ff0b97 59 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & 0b111; // Isolate ETAG
coreyharris 4:06e258ff0b97 60 readECGSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 61
coreyharris 3:420d5efbd967 62 // Check that sample is not last sample in FIFO
coreyharris 4:06e258ff0b97 63 } while ( ETAG[readECGSamples-1] == 0x0 ||
coreyharris 4:06e258ff0b97 64 ETAG[readECGSamples-1] == 0x1 );
coreyharris 2:812d40f1853d 65
coreyharris 3:420d5efbd967 66 // Check if FIFO has overflowed
coreyharris 3:420d5efbd967 67 if( ETAG[readECGSamples - 1] == 0x7 ){
coreyharris 3:420d5efbd967 68 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
coreyharris 3:420d5efbd967 69 }
coreyharris 3:420d5efbd967 70
coreyharris 4:06e258ff0b97 71 // Print results
coreyharris 4:06e258ff0b97 72 for( idx = 0; idx < readECGSamples; idx++ ) {
coreyharris 4:06e258ff0b97 73 pc.printf("Sample : %6d\r\n", ecgSample[idx]);
coreyharris 4:06e258ff0b97 74 }
coreyharris 0:38c49bc37c7c 75 }
coreyharris 0:38c49bc37c7c 76 }
coreyharris 0:38c49bc37c7c 77 }
coreyharris 0:38c49bc37c7c 78 }
coreyharris 0:38c49bc37c7c 79
coreyharris 0:38c49bc37c7c 80
coreyharris 0:38c49bc37c7c 81
coreyharris 0:38c49bc37c7c 82
coreyharris 0:38c49bc37c7c 83 void ecg_config(MAX30003& ecgAFE) {
coreyharris 0:38c49bc37c7c 84
coreyharris 1:86843c27cc81 85 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 86 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 87
coreyharris 1:86843c27cc81 88 // General config register setting
coreyharris 1:86843c27cc81 89 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 90 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 91 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 92 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 93 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 3:420d5efbd967 94 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 95 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 96 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 97
coreyharris 1:86843c27cc81 98
coreyharris 1:86843c27cc81 99 // ECG Config register setting
coreyharris 1:86843c27cc81 100 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 3:420d5efbd967 101 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 3:420d5efbd967 102 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 3:420d5efbd967 103 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 3:420d5efbd967 104 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 105 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 106
coreyharris 1:86843c27cc81 107
coreyharris 1:86843c27cc81 108 //R-to-R configuration
coreyharris 1:86843c27cc81 109 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 3:420d5efbd967 110 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 111 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 112
coreyharris 1:86843c27cc81 113
coreyharris 1:86843c27cc81 114 //Manage interrupts register setting
coreyharris 1:86843c27cc81 115 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 116 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 117 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 118 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 119
coreyharris 0:38c49bc37c7c 120
coreyharris 1:86843c27cc81 121 //Enable interrupts register setting
coreyharris 1:86843c27cc81 122 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 5:f8d1f651bef5 123 EN_INT_r.all = 0;
coreyharris 3:420d5efbd967 124 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 4:06e258ff0b97 125 EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt
coreyharris 3:420d5efbd967 126 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 127 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 128
coreyharris 1:86843c27cc81 129
coreyharris 1:86843c27cc81 130 //Dyanmic modes config
coreyharris 1:86843c27cc81 131 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 132 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 133 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 5:f8d1f651bef5 134
coreyharris 5:f8d1f651bef5 135 // MUX Config
coreyharris 5:f8d1f651bef5 136 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 5:f8d1f651bef5 137 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
coreyharris 5:f8d1f651bef5 138 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
coreyharris 5:f8d1f651bef5 139 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 1:86843c27cc81 140
coreyharris 1:86843c27cc81 141 return;
coreyharris 0:38c49bc37c7c 142 }
coreyharris 0:38c49bc37c7c 143