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Test2
Dependencies: MAX30003 max32630fthr DS1307
main.cpp
- Committer:
- parthsagar2010
- Date:
- 2020-08-19
- Revision:
- 9:24ecf16eab0f
- Parent:
- 8:6b9359f81cc0
- Child:
- 10:54aa50490b15
File content as of revision 9:24ecf16eab0f:
#include "MAX30003.h" #include "mbed.h" #include "max32630fthr.h" #include "ds1307.h" Timer timer_fast; MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3); void task_fast(void); DigitalOut ledA(LED2); void ecg_config(MAX30003 &ecgAFE); volatile bool ecgFIFOIntFlag = 0; volatile int16_t onesec_counter = 0; volatile bool timerflag = 0; void ecgFIFO_callback_1() { // Triggered when the ECG FIFO is about to be full ecgFIFOIntFlag = 1; } int main() { // Constants const int EINT_STATUS_MASK = 1 << 23; const int FIFO_OVF_MASK = 0x7; const int FIFO_VALID_SAMPLE_MASK = 0x0; const int FIFO_FAST_SAMPLE_MASK = 0x1; const int ETAG_BITS_MASK = 0x7; timer_fast.start(); DigitalOut rLed(LED1, LED_OFF); Serial pc(USBTX, USBRX); // Use USB debug probe for serial link pc.baud(115200); // Baud rate = 115200 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the ecgFIFO_int.fall(&ecgFIFO_callback_1); // ecg FIFO interrupt at falling edge SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI, // P5_2 = MISO, P5_0 = SCK MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3 ecg_config(ecgAFE); // Config ECG ecgAFE.writeRegister( MAX30003::SYNCH , 0); uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status; int16_t ecgSample[32]; //bool timerflag = false; int16_t ecgSample_1sec[700]; int16_t onesec_counter = 0; int16_t sample = 300; while(1) { if (timer_fast.read() > 1) { //timerflag = 1; ledA = !ledA; timer_fast.reset(); int8_t header_device_id[3] = {0,0,210}; int8_t header_packet_type[2] = {0,2}; int8_t header_packet_id[4] = {0,0,0,0}; int8_t header_ecg_datalen[2] = {0,onesec_counter}; int8_t header_ecg_checksum[2] = {0,0}; //pc.printf("%6d\r\n", sample); //pc.printf("%6d\r\n", onesec_counter); onesec_counter = 0; } // Read back ECG samples from the FIFO else if( (ecgFIFOIntFlag==1))// && (timerflag == 0)) { ecgFIFOIntFlag = 0; status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register // Check if EINT interrupt asserted if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) { readECGSamples = 0; // Reset sample counter do { ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG readECGSamples++; // Increment sample counter // Check that sample is not last sample in FIFO } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK || ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK ); // Check if FIFO has overflowed if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ) { ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO rLed = 1;//notifies the user that an over flow occured } // Print results for( idx = 0; idx < readECGSamples; idx++ ) { //pc.printf("%6d\r\n", ecgSample[idx]); ecgSample_1sec[onesec_counter] = ecgSample[idx]; onesec_counter++; } } // else // { // timerflag = 0; // } //else if (timerflag == 1) //{ //timerflag = 0; //pc.printf("1 sec ends :\n"); //onesec_counter = 0; //timer_fast.reset(); //timer_fast.start(); //delete[] ecgSample_1sec; //} } } } void ecg_config(MAX30003& ecgAFE) { // Reset ECG to clear registers ecgAFE.writeRegister( MAX30003::SW_RST , 0); // General config register setting MAX30003::GeneralConfiguration_u CNFG_GEN_r; CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all); // ECG Config register setting MAX30003::ECGConfiguration_u CNFG_ECG_r; CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all); //R-to-R configuration MAX30003::RtoR1Configuration_u CNFG_RTOR_r; CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all); //Manage interrupts register setting MAX30003::ManageInterrupts_u MNG_INT_r; MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all); //Enable interrupts register setting MAX30003::EnableInterrupts_u EN_INT_r; EN_INT_r.all = 0; EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all); //Dyanmic modes config MAX30003::ManageDynamicModes_u MNG_DYN_r; MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all); // MUX Config MAX30003::MuxConfiguration_u CNFG_MUX_r; CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all); return; }