File content as of revision 12:2f1730e0e638:

#include "mbed.h"
#include "max32630fthr.h"
#include "MAX30003.h"
 
MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
 
void ecg_config(MAX30003 &ecgAFE);
DigitalOut led1(P2_0,LED_ON); 



/* ECG FIFO nearly full callback */
volatile bool ecgFIFOIntFlag = 0; 
void ecgFIFO_callback()  {
    
    ecgFIFOIntFlag = 1;
 
}  
Timer timer1;
//void MUX()
//{
DigitalOut EN(P1_7);
DigitalOut A0(P1_4);
DigitalOut A1(P7_2);
//}
 bool mux1= false ;
 bool mux2= false ;
 bool mux3= false ;

 
int main()
{   

    // Constants
    const int EINT_STATUS_MASK =  1 << 23;
    const int FIFO_OVF_MASK =  0x7;
    const int FIFO_VALID_SAMPLE_MASK =  0x0;
    const int FIFO_FAST_SAMPLE_MASK =  0x1;
    const int ETAG_BITS_MASK = 0x7;
    
    
 
  //  EN=0; 
  //  EN=1;
  //  A0=0;
   // A1=0;
    
    // Ports and serial connections
    Serial pc(P0_0,P0_1);            // Use USB debug probe for serial link
    pc.baud(230400);                    // Baud rate = 115200
    DigitalOut bLed(LED3, LED_ON);
    DigitalOut gLed(LED2, LED_ON);
    DigitalOut rLed(LED1, LED_ON);
         // Debug LEDs
    
    InterruptIn ecgFIFO_int(P5_4);          // Config P5_4 as int. in for the
    ecgFIFO_int.fall(&ecgFIFO_callback);    // ecg FIFO almost full interrupt
    
   //SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK);     // SPI bus, P5_1 = MOSI, 
                                                    // P5_2 = MISO, P5_0 = SCK
    
    
   SPI spiBus(P5_1, P5_2, P5_0);
    
    MAX30003 ecgAFE(spiBus, P5_3);          // New MAX30003 on spiBus, CS = P5_3 
    ecg_config(ecgAFE);                    // Config ECG 
     
    
    ecgAFE.writeRegister( MAX30003::SYNCH , 0);
    
    uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
    int16_t ecgSample[32];
    int x=0;
    while(1) {
       
   while (x<100 && mux1==false)   
       {
        // if (0<x<=1000 && mux1==false)
      // { 
       
       EN = 0; 
       EN = 1;
       A0 = 0;
       A1 = 0;
       mux1= true ;
       }
     while (101<x<=200 && mux2==false)
       { 
       gLed = 1 ;
       EN = 0;
       EN = 1;
       A0 = 1;
       A1 = 0;
         mux2=true ;
       }
       
   while (201<x<=300 && mux3==false)
       {
     rLed = 1 ;  
       EN = 0 ;      
       EN = 1;
       A0 = 0;
       A1 = 1;
       mux3=true;
       } 
         
            
        // Read back ECG samples from the FIFO 
        if( ecgFIFOIntFlag ) {
            timer1.start();
            
            ecgFIFOIntFlag = 0; 
            status = ecgAFE.readRegister( MAX30003::STATUS );      // Read the STATUS register
             
            // Check if EINT interrupt asserted
            if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {     
            
                readECGSamples = 0;                        // Reset sample counter
                
                do {
                    ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO );       // Read FIFO
                    ecgSample[readECGSamples] = ecgFIFO >> 8;                  // Isolate voltage data
                    ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK;  // Isolate ETAG
                    readECGSamples++;                                          // Increment sample counter
                
                // Check that sample is not last sample in FIFO                                              
                } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK || 
                          ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK ); 
                
                // Check if FIFO has overflowed
                if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){                  
                    ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
                    bLed = 1;//notifies the user that an over flow occured
                }
                
                // Print results 
                for( idx = 0; idx < readECGSamples; idx++ ) {
                    pc.printf("%6d\r\n", ecgSample[idx]);           
                  //   pc.printf("Hello\n");    
                } 
             //   bLed = ! bLed;
             //   gLed = ! gLed;
             //   rLed = ! rLed;
                
             
                     x++;   
                      if (x>300) 
                      
                      {x=0;}     
            }           
        }
        
        
   }
}
 
 
 
 
void ecg_config(MAX30003& ecgAFE) { 
 
    // Reset ECG to clear registers
    ecgAFE.writeRegister( MAX30003::SW_RST , 0);
    
    // General config register setting
    MAX30003::GeneralConfiguration_u CNFG_GEN_r;
    CNFG_GEN_r.bits.en_ecg = 1;     // Enable ECG channel
    CNFG_GEN_r.bits.rbiasn = 1;     // Enable resistive bias on negative input
    CNFG_GEN_r.bits.rbiasp = 1;     // Enable resistive bias on positive input
    CNFG_GEN_r.bits.en_rbias = 1;   // Enable resistive bias
    CNFG_GEN_r.bits.imag = 2;       // Current magnitude = 10nA
    CNFG_GEN_r.bits.en_dcloff = 1;  // Enable DC lead-off detection   
    ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
        
    
    // ECG Config register setting
    MAX30003::ECGConfiguration_u CNFG_ECG_r;
    CNFG_ECG_r.bits.dlpf = 1;       // Digital LPF cutoff = 40Hz
    CNFG_ECG_r.bits.dhpf = 1;       // Digital HPF cutoff = 0.5Hz
    CNFG_ECG_r.bits.gain = 3;       // ECG gain = 160V/V
    CNFG_ECG_r.bits.rate = 2;       // Sample rate = 128 sps
    ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
      
    
    //R-to-R configuration
    MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
    CNFG_RTOR_r.bits.en_rtor = 1;           // Enable R-to-R detection
    ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
       
        
    //Manage interrupts register setting
    MAX30003::ManageInterrupts_u MNG_INT_r;
    MNG_INT_r.bits.efit = 0b00011;          // Assert EINT w/ 4 unread samples
    MNG_INT_r.bits.clr_rrint = 0b01;        // Clear R-to-R on RTOR reg. read back
    ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
    
    
    //Enable interrupts register setting
    MAX30003::EnableInterrupts_u EN_INT_r;
    EN_INT_r.all = 0;
    EN_INT_r.bits.en_eint = 1;              // Enable EINT interrupt
    EN_INT_r.bits.en_rrint = 0;             // Disable R-to-R interrupt
    EN_INT_r.bits.intb_type = 3;            // Open-drain NMOS with internal pullup
    ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
       
       
    //Dyanmic modes config
    MAX30003::ManageDynamicModes_u MNG_DYN_r;
    MNG_DYN_r.bits.fast = 0;                // Fast recovery mode disabled
    ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
    
    // MUX Config
    MAX30003::MuxConfiguration_u CNFG_MUX_r;
    CNFG_MUX_r.bits.openn = 0;          // Connect ECGN to AFE channel
    CNFG_MUX_r.bits.openp = 0;          // Connect ECGP to AFE channel
    ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
       
    return;
}