MH
MUX
Dependencies: MAX30003 max32630fthr
Diff: main.cpp
- Revision:
- 8:67ba6d185fe0
- Parent:
- 7:cf0855a0450a
--- a/main.cpp Thu Dec 14 21:42:36 2017 +0000
+++ b/main.cpp Sat May 22 19:19:45 2021 +0000
@@ -31,8 +31,6 @@
*******************************************************************************
*/
-
-
#include "mbed.h"
#include "max32630fthr.h"
#include "MAX30003.h"
@@ -40,18 +38,23 @@
MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
void ecg_config(MAX30003 &ecgAFE);
+void ecg_config_off(MAX30003& ecgAFE);
+
+DigitalOut EN(P1_7);
+DigitalOut A0(P1_4);
+DigitalOut A1(P7_2);
+
/* ECG FIFO nearly full callback */
volatile bool ecgFIFOIntFlag = 0;
-void ecgFIFO_callback() {
-
+bool flag = 1;
+void ecgFIFO_callback()
+{
ecgFIFOIntFlag = 1;
-
}
int main()
{
-
// Constants
const int EINT_STATUS_MASK = 1 << 23;
const int FIFO_OVF_MASK = 0x7;
@@ -60,44 +63,55 @@
const int ETAG_BITS_MASK = 0x7;
// Ports and serial connections
- Serial pc(USBTX, USBRX); // Use USB debug probe for serial link
- pc.baud(115200); // Baud rate = 115200
+ Serial pc(P3_0,P3_1); // Use USB debug probe for serial link
+ pc.baud(230400); // Baud rate = 115200
- DigitalOut rLed(LED1, LED_OFF); // Debug LEDs
+ DigitalOut bLed(LED3); // Debug LEDs
- InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
- ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
+ InterruptIn ecgFIFO_1_int(P5_4); // Config P5_4 as int. in for the
+ ecgFIFO_1_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
- SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
+ SPI spiBus(P5_1,P5_2,P5_0); // SPI bus, P5_1 = MOSI,
// P5_2 = MISO, P5_0 = SCK
- MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
- ecg_config(ecgAFE); // Config ECG
+ MAX30003 ecgAFE_1(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
+ ecg_config(ecgAFE_1); // Config ECG
- ecgAFE.writeRegister( MAX30003::SYNCH , 0);
+ ecgAFE_1.writeRegister( MAX30003::SYNCH , 0);
uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
- int16_t ecgSample[32];
+ int16_t ecgSample[32], x = 0;
+
+
- while(1) {
-
+ while(1)
+ {
+ EN = 1;
+ A0 = 0;
+ A1 = 0;
+
+ do
+ {
// Read back ECG samples from the FIFO
if( ecgFIFOIntFlag ) {
- ecgFIFOIntFlag = 0;
- status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
+ //ecgFIFOIntFlag = 0;
+ status = ecgAFE_1.readRegister( MAX30003::STATUS ); // Read the STATUS register
// Check if EINT interrupt asserted
if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
- readECGSamples = 0; // Reset sample counter
+ readECGSamples = 0; // Reset sample counter
do {
- ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
+ ecgFIFO = ecgAFE_1.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
+ pc.printf("%d samples read from FIFO \r\n", readECGSamples);
+ // pc.printf("%d samples read from FIFO \r\n", readECGSamples);
ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
- readECGSamples++; // Increment sample counter
+ readECGSamples++;
+ // Increment sample counter
// Check that sample is not last sample in FIFO
} while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
@@ -105,7 +119,109 @@
// Check if FIFO has overflowed
if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){
- ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
+ ecgAFE_1.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
+ bLed = 1;//notifies the user that an over flow occured
+ }
+
+ // Print results
+ for( idx = 0; idx < readECGSamples; idx++ ) {
+ pc.printf("%6d\r\n", ecgSample[idx]);
+ }
+ //rLed = 1;
+ bLed = ! bLed;
+ x++;
+ }
+ }
+ }while(x<20);
+ //ecg_config_off(ecgAFE_1);
+ bLed = ~bLed;
+ x=0;
+
+
+
+
+ DigitalOut gLed(LED2);
+ A0 = 1;
+ do
+ {
+ // Read back ECG samples from the FIFO
+ if( ecgFIFOIntFlag ) {
+
+ // ecgFIFOIntFlag = 0;
+ status = ecgAFE_1.readRegister( MAX30003::STATUS ); // Read the STATUS register
+
+ // Check if EINT interrupt asserted
+ if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
+
+ readECGSamples = 0; // Reset sample counter
+
+ do {
+ ecgFIFO = ecgAFE_1.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
+ pc.printf("%d samples read from FIFO \r\n", readECGSamples);
+ // pc.printf("%d samples read from FIFO \r\n", readECGSamples);
+ ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
+ ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
+ readECGSamples++;
+ // Increment sample counter
+
+ // Check that sample is not last sample in FIFO
+ } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
+ ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK );
+
+ // Check if FIFO has overflowed
+ if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){
+ ecgAFE_1.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
+ gLed = 1;//notifies the user that an over flow occured
+ }
+
+ // Print results
+ for( idx = 0; idx < readECGSamples; idx++ ) {
+ pc.printf("%6d\r\n", ecgSample[idx]);
+ }
+ //rLed = 1;
+ gLed = ! gLed;
+ x++;
+ }
+ }
+ }while(x<20);
+ //ecg_config_off(ecgAFE_1);
+ gLed = ~gLed;
+ x=0;
+
+
+
+
+ DigitalOut rLed(LED1);
+ A0 = 1;
+ do
+ {
+ // Read back ECG samples from the FIFO
+ if( ecgFIFOIntFlag ) {
+
+ // ecgFIFOIntFlag = 0;
+ status = ecgAFE_1.readRegister( MAX30003::STATUS ); // Read the STATUS register
+
+ // Check if EINT interrupt asserted
+ if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
+
+ readECGSamples = 0; // Reset sample counter
+
+ do {
+ ecgFIFO = ecgAFE_1.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
+ pc.printf("%d samples read from FIFO \r\n", readECGSamples);
+ // pc.printf("%d samples read from FIFO \r\n", readECGSamples);
+ ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
+ ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
+ readECGSamples++;
+ // Increment sample counter
+
+ // Check that sample is not last sample in FIFO
+ } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
+ ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK );
+
+ // Check if FIFO has overflowed
+ if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){
+ ecgAFE_1.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
rLed = 1;//notifies the user that an over flow occured
}
@@ -113,15 +229,19 @@
for( idx = 0; idx < readECGSamples; idx++ ) {
pc.printf("%6d\r\n", ecgSample[idx]);
}
-
+ //rLed = 1;
+ rLed = ! rLed;
+ x++;
+ }
}
- }
+ }while(x<20);
+ //ecg_config_off(ecgAFE_1);
+ rLed = ~rLed;
+ x=0;
+
}
}
-
-
-
void ecg_config(MAX30003& ecgAFE) {
// Reset ECG to clear registers
@@ -179,7 +299,19 @@
CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
-
+
return;
}
+void ecg_config_off(MAX30003& ecgAFE)
+{
+ // General config register setting
+ MAX30003::GeneralConfiguration_u CNFG_GEN_r;
+ CNFG_GEN_r.bits.en_ecg = 0; // Enable ECG channel
+ // CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
+ // CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
+ // CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
+ // CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
+ // CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
+ ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
+}
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