Test program for master controller
Dependencies: Controller_Master mbed
Controller_Master.h
- Committer:
- AndreaAndreoli
- Date:
- 2016-06-04
- Revision:
- 0:ae1df001727e
File content as of revision 0:ae1df001727e:
/* * Academic License - for use in teaching, academic research, and meeting * course requirements at degree granting institutions only. Not for * government, commercial, or other organizational use. * * File: Controller_Master.h * * Code generated for Simulink model 'Controller_Master'. * * Model version : 1.0 * Simulink Coder version : 8.10 (R2016a) 10-Feb-2016 * C/C++ source code generated on : Sat Jun 04 17:59:52 2016 * * Target selection: ert.tlc * Embedded hardware selection: NXP->Cortex-M4 * Code generation objectives: Unspecified * Validation result: Not run */ #ifndef RTW_HEADER_Controller_Master_h_ #define RTW_HEADER_Controller_Master_h_ #include <math.h> #include <string.h> #ifndef Controller_Master_COMMON_INCLUDES_ # define Controller_Master_COMMON_INCLUDES_ #include "rtwtypes.h" #endif /* Controller_Master_COMMON_INCLUDES_ */ /* Macros for accessing real-time model data structure */ #ifndef rtmGetErrorStatus # define rtmGetErrorStatus(rtm) ((rtm)->errorStatus) #endif #ifndef rtmSetErrorStatus # define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val)) #endif /* Forward declaration for rtModel */ typedef struct tag_RTM_Controller_Master_T RT_MODEL_Controller_Master_T; /* Block signals (auto storage) */ typedef struct { real_T Led_Blue; /* '<S1>/AEB' */ } B_Controller_Master_T; /* Block states (auto storage) for system '<Root>' */ typedef struct { uint32_T temporalCounter_i1; /* '<S1>/select_command' */ uint8_T Memory_PreviousInput; /* '<S1>/Memory' */ uint8_T is_active_c2_Controller_Master;/* '<S1>/select_command' */ uint8_T is_c2_Controller_Master; /* '<S1>/select_command' */ uint8_T is_BLINK; /* '<S1>/select_command' */ uint8_T is_active_c3_Controller_Master;/* '<S1>/AEB' */ uint8_T is_ERRORS_CHECK_THREAD; /* '<S1>/AEB' */ uint8_T is_APPLICATION_THREAD; /* '<S1>/AEB' */ uint8_T is_ACTIVE; /* '<S1>/AEB' */ boolean_T En; /* '<S1>/AEB' */ } DW_Controller_Master_T; /* Real-time Model Data Structure */ struct tag_RTM_Controller_Master_T { const char_T * volatile errorStatus; /* * ModelData: * The following substructure contains information regarding * the data used in the model. */ struct { B_Controller_Master_T *blockIO; DW_Controller_Master_T *dwork; } ModelData; }; /* Model entry point functions */ extern void Controller_Master_initialize(RT_MODEL_Controller_Master_T *const Controller_Master_M, real_T *Controller_Master_U_V, real_T *Controller_Master_U_D_M, uint8_T *Controller_Master_U_Slave, uint8_T *Controller_Master_Y_BRAKE, uint8_T *Controller_Master_Y_LED_BLUE, uint8_T *Controller_Master_Y_LED_RED, uint8_T *Controller_Master_Y_MASTER); extern void Controller_Master_step(RT_MODEL_Controller_Master_T *const Controller_Master_M, real_T Controller_Master_U_V, real_T Controller_Master_U_D_M, uint8_T Controller_Master_U_Slave, uint8_T *Controller_Master_Y_BRAKE, uint8_T *Controller_Master_Y_LED_BLUE, uint8_T *Controller_Master_Y_LED_RED, uint8_T *Controller_Master_Y_MASTER); extern void Controller_Master_terminate(RT_MODEL_Controller_Master_T *const Controller_Master_M); /*- * The generated code includes comments that allow you to trace directly * back to the appropriate location in the model. The basic format * is <system>/block_name, where system is the system number (uniquely * assigned by Simulink) and block_name is the name of the block. * * Note that this particular code originates from a subsystem build, * and has its own system numbers different from the parent model. * Refer to the system hierarchy for this subsystem below, and use the * MATLAB hilite_system command to trace the generated code back * to the parent model. For example, * * hilite_system('untitled/Controller/Controller_Master') - opens subsystem untitled/Controller/Controller_Master * hilite_system('untitled/Controller/Controller_Master/Kp') - opens and selects block Kp * * Here is the system hierarchy for this model * * '<Root>' : 'untitled/Controller' * '<S1>' : 'untitled/Controller/Controller_Master' * '<S2>' : 'untitled/Controller/Controller_Master/AEB' * '<S3>' : 'untitled/Controller/Controller_Master/select_command' */ #endif /* RTW_HEADER_Controller_Master_h_ */ /* * File trailer for generated code. * * [EOF] */