Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/core_caFunc.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
0:e1a608bb55e8 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /**************************************************************************//**
jamesadevine 0:e1a608bb55e8 2 * @file core_caFunc.h
jamesadevine 0:e1a608bb55e8 3 * @brief CMSIS Cortex-A Core Function Access Header File
jamesadevine 0:e1a608bb55e8 4 * @version V3.10
jamesadevine 0:e1a608bb55e8 5 * @date 9 May 2013
jamesadevine 0:e1a608bb55e8 6 *
jamesadevine 0:e1a608bb55e8 7 * @note
jamesadevine 0:e1a608bb55e8 8 *
jamesadevine 0:e1a608bb55e8 9 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
jamesadevine 0:e1a608bb55e8 11
jamesadevine 0:e1a608bb55e8 12 All rights reserved.
jamesadevine 0:e1a608bb55e8 13 Redistribution and use in source and binary forms, with or without
jamesadevine 0:e1a608bb55e8 14 modification, are permitted provided that the following conditions are met:
jamesadevine 0:e1a608bb55e8 15 - Redistributions of source code must retain the above copyright
jamesadevine 0:e1a608bb55e8 16 notice, this list of conditions and the following disclaimer.
jamesadevine 0:e1a608bb55e8 17 - Redistributions in binary form must reproduce the above copyright
jamesadevine 0:e1a608bb55e8 18 notice, this list of conditions and the following disclaimer in the
jamesadevine 0:e1a608bb55e8 19 documentation and/or other materials provided with the distribution.
jamesadevine 0:e1a608bb55e8 20 - Neither the name of ARM nor the names of its contributors may be used
jamesadevine 0:e1a608bb55e8 21 to endorse or promote products derived from this software without
jamesadevine 0:e1a608bb55e8 22 specific prior written permission.
jamesadevine 0:e1a608bb55e8 23 *
jamesadevine 0:e1a608bb55e8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine 0:e1a608bb55e8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine 0:e1a608bb55e8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine 0:e1a608bb55e8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine 0:e1a608bb55e8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine 0:e1a608bb55e8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine 0:e1a608bb55e8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine 0:e1a608bb55e8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine 0:e1a608bb55e8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine 0:e1a608bb55e8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine 0:e1a608bb55e8 34 POSSIBILITY OF SUCH DAMAGE.
jamesadevine 0:e1a608bb55e8 35 ---------------------------------------------------------------------------*/
jamesadevine 0:e1a608bb55e8 36
jamesadevine 0:e1a608bb55e8 37
jamesadevine 0:e1a608bb55e8 38 #ifndef __CORE_CAFUNC_H__
jamesadevine 0:e1a608bb55e8 39 #define __CORE_CAFUNC_H__
jamesadevine 0:e1a608bb55e8 40
jamesadevine 0:e1a608bb55e8 41
jamesadevine 0:e1a608bb55e8 42 /* ########################### Core Function Access ########################### */
jamesadevine 0:e1a608bb55e8 43 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
jamesadevine 0:e1a608bb55e8 45 @{
jamesadevine 0:e1a608bb55e8 46 */
jamesadevine 0:e1a608bb55e8 47
jamesadevine 0:e1a608bb55e8 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jamesadevine 0:e1a608bb55e8 49 /* ARM armcc specific functions */
jamesadevine 0:e1a608bb55e8 50
jamesadevine 0:e1a608bb55e8 51 #if (__ARMCC_VERSION < 400677)
jamesadevine 0:e1a608bb55e8 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jamesadevine 0:e1a608bb55e8 53 #endif
jamesadevine 0:e1a608bb55e8 54
jamesadevine 0:e1a608bb55e8 55 #define MODE_USR 0x10
jamesadevine 0:e1a608bb55e8 56 #define MODE_FIQ 0x11
jamesadevine 0:e1a608bb55e8 57 #define MODE_IRQ 0x12
jamesadevine 0:e1a608bb55e8 58 #define MODE_SVC 0x13
jamesadevine 0:e1a608bb55e8 59 #define MODE_MON 0x16
jamesadevine 0:e1a608bb55e8 60 #define MODE_ABT 0x17
jamesadevine 0:e1a608bb55e8 61 #define MODE_HYP 0x1A
jamesadevine 0:e1a608bb55e8 62 #define MODE_UND 0x1B
jamesadevine 0:e1a608bb55e8 63 #define MODE_SYS 0x1F
jamesadevine 0:e1a608bb55e8 64
jamesadevine 0:e1a608bb55e8 65 /** \brief Get APSR Register
jamesadevine 0:e1a608bb55e8 66
jamesadevine 0:e1a608bb55e8 67 This function returns the content of the APSR Register.
jamesadevine 0:e1a608bb55e8 68
jamesadevine 0:e1a608bb55e8 69 \return APSR Register value
jamesadevine 0:e1a608bb55e8 70 */
jamesadevine 0:e1a608bb55e8 71 __STATIC_INLINE uint32_t __get_APSR(void)
jamesadevine 0:e1a608bb55e8 72 {
jamesadevine 0:e1a608bb55e8 73 register uint32_t __regAPSR __ASM("apsr");
jamesadevine 0:e1a608bb55e8 74 return(__regAPSR);
jamesadevine 0:e1a608bb55e8 75 }
jamesadevine 0:e1a608bb55e8 76
jamesadevine 0:e1a608bb55e8 77
jamesadevine 0:e1a608bb55e8 78 /** \brief Get CPSR Register
jamesadevine 0:e1a608bb55e8 79
jamesadevine 0:e1a608bb55e8 80 This function returns the content of the CPSR Register.
jamesadevine 0:e1a608bb55e8 81
jamesadevine 0:e1a608bb55e8 82 \return CPSR Register value
jamesadevine 0:e1a608bb55e8 83 */
jamesadevine 0:e1a608bb55e8 84 __STATIC_INLINE uint32_t __get_CPSR(void)
jamesadevine 0:e1a608bb55e8 85 {
jamesadevine 0:e1a608bb55e8 86 register uint32_t __regCPSR __ASM("cpsr");
jamesadevine 0:e1a608bb55e8 87 return(__regCPSR);
jamesadevine 0:e1a608bb55e8 88 }
jamesadevine 0:e1a608bb55e8 89
jamesadevine 0:e1a608bb55e8 90 /** \brief Set Stack Pointer
jamesadevine 0:e1a608bb55e8 91
jamesadevine 0:e1a608bb55e8 92 This function assigns the given value to the current stack pointer.
jamesadevine 0:e1a608bb55e8 93
jamesadevine 0:e1a608bb55e8 94 \param [in] topOfStack Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 95 */
jamesadevine 0:e1a608bb55e8 96 register uint32_t __regSP __ASM("sp");
jamesadevine 0:e1a608bb55e8 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jamesadevine 0:e1a608bb55e8 98 {
jamesadevine 0:e1a608bb55e8 99 __regSP = topOfStack;
jamesadevine 0:e1a608bb55e8 100 }
jamesadevine 0:e1a608bb55e8 101
jamesadevine 0:e1a608bb55e8 102
jamesadevine 0:e1a608bb55e8 103 /** \brief Get link register
jamesadevine 0:e1a608bb55e8 104
jamesadevine 0:e1a608bb55e8 105 This function returns the value of the link register
jamesadevine 0:e1a608bb55e8 106
jamesadevine 0:e1a608bb55e8 107 \return Value of link register
jamesadevine 0:e1a608bb55e8 108 */
jamesadevine 0:e1a608bb55e8 109 register uint32_t __reglr __ASM("lr");
jamesadevine 0:e1a608bb55e8 110 __STATIC_INLINE uint32_t __get_LR(void)
jamesadevine 0:e1a608bb55e8 111 {
jamesadevine 0:e1a608bb55e8 112 return(__reglr);
jamesadevine 0:e1a608bb55e8 113 }
jamesadevine 0:e1a608bb55e8 114
jamesadevine 0:e1a608bb55e8 115 /** \brief Set link register
jamesadevine 0:e1a608bb55e8 116
jamesadevine 0:e1a608bb55e8 117 This function sets the value of the link register
jamesadevine 0:e1a608bb55e8 118
jamesadevine 0:e1a608bb55e8 119 \param [in] lr LR value to set
jamesadevine 0:e1a608bb55e8 120 */
jamesadevine 0:e1a608bb55e8 121 __STATIC_INLINE void __set_LR(uint32_t lr)
jamesadevine 0:e1a608bb55e8 122 {
jamesadevine 0:e1a608bb55e8 123 __reglr = lr;
jamesadevine 0:e1a608bb55e8 124 }
jamesadevine 0:e1a608bb55e8 125
jamesadevine 0:e1a608bb55e8 126 /** \brief Set Process Stack Pointer
jamesadevine 0:e1a608bb55e8 127
jamesadevine 0:e1a608bb55e8 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jamesadevine 0:e1a608bb55e8 129
jamesadevine 0:e1a608bb55e8 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 131 */
jamesadevine 0:e1a608bb55e8 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
jamesadevine 0:e1a608bb55e8 133 {
jamesadevine 0:e1a608bb55e8 134 ARM
jamesadevine 0:e1a608bb55e8 135 PRESERVE8
jamesadevine 0:e1a608bb55e8 136
jamesadevine 0:e1a608bb55e8 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
jamesadevine 0:e1a608bb55e8 138 MRS R1, CPSR
jamesadevine 0:e1a608bb55e8 139 CPS #MODE_SYS ;no effect in USR mode
jamesadevine 0:e1a608bb55e8 140 MOV SP, R0
jamesadevine 0:e1a608bb55e8 141 MSR CPSR_c, R1 ;no effect in USR mode
jamesadevine 0:e1a608bb55e8 142 ISB
jamesadevine 0:e1a608bb55e8 143 BX LR
jamesadevine 0:e1a608bb55e8 144
jamesadevine 0:e1a608bb55e8 145 }
jamesadevine 0:e1a608bb55e8 146
jamesadevine 0:e1a608bb55e8 147 /** \brief Set User Mode
jamesadevine 0:e1a608bb55e8 148
jamesadevine 0:e1a608bb55e8 149 This function changes the processor state to User Mode
jamesadevine 0:e1a608bb55e8 150
jamesadevine 0:e1a608bb55e8 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 152 */
jamesadevine 0:e1a608bb55e8 153 __STATIC_ASM void __set_CPS_USR(void)
jamesadevine 0:e1a608bb55e8 154 {
jamesadevine 0:e1a608bb55e8 155 ARM
jamesadevine 0:e1a608bb55e8 156
jamesadevine 0:e1a608bb55e8 157 CPS #MODE_USR
jamesadevine 0:e1a608bb55e8 158 BX LR
jamesadevine 0:e1a608bb55e8 159 }
jamesadevine 0:e1a608bb55e8 160
jamesadevine 0:e1a608bb55e8 161
jamesadevine 0:e1a608bb55e8 162 /** \brief Enable FIQ
jamesadevine 0:e1a608bb55e8 163
jamesadevine 0:e1a608bb55e8 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 165 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 166 */
jamesadevine 0:e1a608bb55e8 167 #define __enable_fault_irq __enable_fiq
jamesadevine 0:e1a608bb55e8 168
jamesadevine 0:e1a608bb55e8 169
jamesadevine 0:e1a608bb55e8 170 /** \brief Disable FIQ
jamesadevine 0:e1a608bb55e8 171
jamesadevine 0:e1a608bb55e8 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 173 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 174 */
jamesadevine 0:e1a608bb55e8 175 #define __disable_fault_irq __disable_fiq
jamesadevine 0:e1a608bb55e8 176
jamesadevine 0:e1a608bb55e8 177
jamesadevine 0:e1a608bb55e8 178 /** \brief Get FPSCR
jamesadevine 0:e1a608bb55e8 179
jamesadevine 0:e1a608bb55e8 180 This function returns the current value of the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 181
jamesadevine 0:e1a608bb55e8 182 \return Floating Point Status/Control register value
jamesadevine 0:e1a608bb55e8 183 */
jamesadevine 0:e1a608bb55e8 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
jamesadevine 0:e1a608bb55e8 185 {
jamesadevine 0:e1a608bb55e8 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 187 register uint32_t __regfpscr __ASM("fpscr");
jamesadevine 0:e1a608bb55e8 188 return(__regfpscr);
jamesadevine 0:e1a608bb55e8 189 #else
jamesadevine 0:e1a608bb55e8 190 return(0);
jamesadevine 0:e1a608bb55e8 191 #endif
jamesadevine 0:e1a608bb55e8 192 }
jamesadevine 0:e1a608bb55e8 193
jamesadevine 0:e1a608bb55e8 194
jamesadevine 0:e1a608bb55e8 195 /** \brief Set FPSCR
jamesadevine 0:e1a608bb55e8 196
jamesadevine 0:e1a608bb55e8 197 This function assigns the given value to the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 198
jamesadevine 0:e1a608bb55e8 199 \param [in] fpscr Floating Point Status/Control value to set
jamesadevine 0:e1a608bb55e8 200 */
jamesadevine 0:e1a608bb55e8 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jamesadevine 0:e1a608bb55e8 202 {
jamesadevine 0:e1a608bb55e8 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 204 register uint32_t __regfpscr __ASM("fpscr");
jamesadevine 0:e1a608bb55e8 205 __regfpscr = (fpscr);
jamesadevine 0:e1a608bb55e8 206 #endif
jamesadevine 0:e1a608bb55e8 207 }
jamesadevine 0:e1a608bb55e8 208
jamesadevine 0:e1a608bb55e8 209 /** \brief Get FPEXC
jamesadevine 0:e1a608bb55e8 210
jamesadevine 0:e1a608bb55e8 211 This function returns the current value of the Floating Point Exception Control register.
jamesadevine 0:e1a608bb55e8 212
jamesadevine 0:e1a608bb55e8 213 \return Floating Point Exception Control register value
jamesadevine 0:e1a608bb55e8 214 */
jamesadevine 0:e1a608bb55e8 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
jamesadevine 0:e1a608bb55e8 216 {
jamesadevine 0:e1a608bb55e8 217 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 218 register uint32_t __regfpexc __ASM("fpexc");
jamesadevine 0:e1a608bb55e8 219 return(__regfpexc);
jamesadevine 0:e1a608bb55e8 220 #else
jamesadevine 0:e1a608bb55e8 221 return(0);
jamesadevine 0:e1a608bb55e8 222 #endif
jamesadevine 0:e1a608bb55e8 223 }
jamesadevine 0:e1a608bb55e8 224
jamesadevine 0:e1a608bb55e8 225
jamesadevine 0:e1a608bb55e8 226 /** \brief Set FPEXC
jamesadevine 0:e1a608bb55e8 227
jamesadevine 0:e1a608bb55e8 228 This function assigns the given value to the Floating Point Exception Control register.
jamesadevine 0:e1a608bb55e8 229
jamesadevine 0:e1a608bb55e8 230 \param [in] fpscr Floating Point Exception Control value to set
jamesadevine 0:e1a608bb55e8 231 */
jamesadevine 0:e1a608bb55e8 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jamesadevine 0:e1a608bb55e8 233 {
jamesadevine 0:e1a608bb55e8 234 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 235 register uint32_t __regfpexc __ASM("fpexc");
jamesadevine 0:e1a608bb55e8 236 __regfpexc = (fpexc);
jamesadevine 0:e1a608bb55e8 237 #endif
jamesadevine 0:e1a608bb55e8 238 }
jamesadevine 0:e1a608bb55e8 239
jamesadevine 0:e1a608bb55e8 240 /** \brief Get CPACR
jamesadevine 0:e1a608bb55e8 241
jamesadevine 0:e1a608bb55e8 242 This function returns the current value of the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 243
jamesadevine 0:e1a608bb55e8 244 \return Coprocessor Access Control register value
jamesadevine 0:e1a608bb55e8 245 */
jamesadevine 0:e1a608bb55e8 246 __STATIC_INLINE uint32_t __get_CPACR(void)
jamesadevine 0:e1a608bb55e8 247 {
jamesadevine 0:e1a608bb55e8 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jamesadevine 0:e1a608bb55e8 249 return __regCPACR;
jamesadevine 0:e1a608bb55e8 250 }
jamesadevine 0:e1a608bb55e8 251
jamesadevine 0:e1a608bb55e8 252 /** \brief Set CPACR
jamesadevine 0:e1a608bb55e8 253
jamesadevine 0:e1a608bb55e8 254 This function assigns the given value to the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 255
jamesadevine 0:e1a608bb55e8 256 \param [in] cpacr Coporcessor Acccess Control value to set
jamesadevine 0:e1a608bb55e8 257 */
jamesadevine 0:e1a608bb55e8 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jamesadevine 0:e1a608bb55e8 259 {
jamesadevine 0:e1a608bb55e8 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jamesadevine 0:e1a608bb55e8 261 __regCPACR = cpacr;
jamesadevine 0:e1a608bb55e8 262 __ISB();
jamesadevine 0:e1a608bb55e8 263 }
jamesadevine 0:e1a608bb55e8 264
jamesadevine 0:e1a608bb55e8 265 /** \brief Get CBAR
jamesadevine 0:e1a608bb55e8 266
jamesadevine 0:e1a608bb55e8 267 This function returns the value of the Configuration Base Address register.
jamesadevine 0:e1a608bb55e8 268
jamesadevine 0:e1a608bb55e8 269 \return Configuration Base Address register value
jamesadevine 0:e1a608bb55e8 270 */
jamesadevine 0:e1a608bb55e8 271 __STATIC_INLINE uint32_t __get_CBAR() {
jamesadevine 0:e1a608bb55e8 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jamesadevine 0:e1a608bb55e8 273 return(__regCBAR);
jamesadevine 0:e1a608bb55e8 274 }
jamesadevine 0:e1a608bb55e8 275
jamesadevine 0:e1a608bb55e8 276 /** \brief Get TTBR0
jamesadevine 0:e1a608bb55e8 277
jamesadevine 0:e1a608bb55e8 278 This function returns the value of the Configuration Base Address register.
jamesadevine 0:e1a608bb55e8 279
jamesadevine 0:e1a608bb55e8 280 \return Translation Table Base Register 0 value
jamesadevine 0:e1a608bb55e8 281 */
jamesadevine 0:e1a608bb55e8 282 __STATIC_INLINE uint32_t __get_TTBR0() {
jamesadevine 0:e1a608bb55e8 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jamesadevine 0:e1a608bb55e8 284 return(__regTTBR0);
jamesadevine 0:e1a608bb55e8 285 }
jamesadevine 0:e1a608bb55e8 286
jamesadevine 0:e1a608bb55e8 287 /** \brief Set TTBR0
jamesadevine 0:e1a608bb55e8 288
jamesadevine 0:e1a608bb55e8 289 This function assigns the given value to the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 290
jamesadevine 0:e1a608bb55e8 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
jamesadevine 0:e1a608bb55e8 292 */
jamesadevine 0:e1a608bb55e8 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jamesadevine 0:e1a608bb55e8 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jamesadevine 0:e1a608bb55e8 295 __regTTBR0 = ttbr0;
jamesadevine 0:e1a608bb55e8 296 __ISB();
jamesadevine 0:e1a608bb55e8 297 }
jamesadevine 0:e1a608bb55e8 298
jamesadevine 0:e1a608bb55e8 299 /** \brief Get DACR
jamesadevine 0:e1a608bb55e8 300
jamesadevine 0:e1a608bb55e8 301 This function returns the value of the Domain Access Control Register.
jamesadevine 0:e1a608bb55e8 302
jamesadevine 0:e1a608bb55e8 303 \return Domain Access Control Register value
jamesadevine 0:e1a608bb55e8 304 */
jamesadevine 0:e1a608bb55e8 305 __STATIC_INLINE uint32_t __get_DACR() {
jamesadevine 0:e1a608bb55e8 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jamesadevine 0:e1a608bb55e8 307 return(__regDACR);
jamesadevine 0:e1a608bb55e8 308 }
jamesadevine 0:e1a608bb55e8 309
jamesadevine 0:e1a608bb55e8 310 /** \brief Set DACR
jamesadevine 0:e1a608bb55e8 311
jamesadevine 0:e1a608bb55e8 312 This function assigns the given value to the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 313
jamesadevine 0:e1a608bb55e8 314 \param [in] dacr Domain Access Control Register value to set
jamesadevine 0:e1a608bb55e8 315 */
jamesadevine 0:e1a608bb55e8 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jamesadevine 0:e1a608bb55e8 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jamesadevine 0:e1a608bb55e8 318 __regDACR = dacr;
jamesadevine 0:e1a608bb55e8 319 __ISB();
jamesadevine 0:e1a608bb55e8 320 }
jamesadevine 0:e1a608bb55e8 321
jamesadevine 0:e1a608bb55e8 322 /******************************** Cache and BTAC enable ****************************************************/
jamesadevine 0:e1a608bb55e8 323
jamesadevine 0:e1a608bb55e8 324 /** \brief Set SCTLR
jamesadevine 0:e1a608bb55e8 325
jamesadevine 0:e1a608bb55e8 326 This function assigns the given value to the System Control Register.
jamesadevine 0:e1a608bb55e8 327
jamesadevine 0:e1a608bb55e8 328 \param [in] sctlr System Control Register, value to set
jamesadevine 0:e1a608bb55e8 329 */
jamesadevine 0:e1a608bb55e8 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jamesadevine 0:e1a608bb55e8 331 {
jamesadevine 0:e1a608bb55e8 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jamesadevine 0:e1a608bb55e8 333 __regSCTLR = sctlr;
jamesadevine 0:e1a608bb55e8 334 }
jamesadevine 0:e1a608bb55e8 335
jamesadevine 0:e1a608bb55e8 336 /** \brief Get SCTLR
jamesadevine 0:e1a608bb55e8 337
jamesadevine 0:e1a608bb55e8 338 This function returns the value of the System Control Register.
jamesadevine 0:e1a608bb55e8 339
jamesadevine 0:e1a608bb55e8 340 \return System Control Register value
jamesadevine 0:e1a608bb55e8 341 */
jamesadevine 0:e1a608bb55e8 342 __STATIC_INLINE uint32_t __get_SCTLR() {
jamesadevine 0:e1a608bb55e8 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jamesadevine 0:e1a608bb55e8 344 return(__regSCTLR);
jamesadevine 0:e1a608bb55e8 345 }
jamesadevine 0:e1a608bb55e8 346
jamesadevine 0:e1a608bb55e8 347 /** \brief Enable Caches
jamesadevine 0:e1a608bb55e8 348
jamesadevine 0:e1a608bb55e8 349 Enable Caches
jamesadevine 0:e1a608bb55e8 350 */
jamesadevine 0:e1a608bb55e8 351 __STATIC_INLINE void __enable_caches(void) {
jamesadevine 0:e1a608bb55e8 352 // Set I bit 12 to enable I Cache
jamesadevine 0:e1a608bb55e8 353 // Set C bit 2 to enable D Cache
jamesadevine 0:e1a608bb55e8 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jamesadevine 0:e1a608bb55e8 355 }
jamesadevine 0:e1a608bb55e8 356
jamesadevine 0:e1a608bb55e8 357 /** \brief Disable Caches
jamesadevine 0:e1a608bb55e8 358
jamesadevine 0:e1a608bb55e8 359 Disable Caches
jamesadevine 0:e1a608bb55e8 360 */
jamesadevine 0:e1a608bb55e8 361 __STATIC_INLINE void __disable_caches(void) {
jamesadevine 0:e1a608bb55e8 362 // Clear I bit 12 to disable I Cache
jamesadevine 0:e1a608bb55e8 363 // Clear C bit 2 to disable D Cache
jamesadevine 0:e1a608bb55e8 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jamesadevine 0:e1a608bb55e8 365 __ISB();
jamesadevine 0:e1a608bb55e8 366 }
jamesadevine 0:e1a608bb55e8 367
jamesadevine 0:e1a608bb55e8 368 /** \brief Enable BTAC
jamesadevine 0:e1a608bb55e8 369
jamesadevine 0:e1a608bb55e8 370 Enable BTAC
jamesadevine 0:e1a608bb55e8 371 */
jamesadevine 0:e1a608bb55e8 372 __STATIC_INLINE void __enable_btac(void) {
jamesadevine 0:e1a608bb55e8 373 // Set Z bit 11 to enable branch prediction
jamesadevine 0:e1a608bb55e8 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
jamesadevine 0:e1a608bb55e8 375 __ISB();
jamesadevine 0:e1a608bb55e8 376 }
jamesadevine 0:e1a608bb55e8 377
jamesadevine 0:e1a608bb55e8 378 /** \brief Disable BTAC
jamesadevine 0:e1a608bb55e8 379
jamesadevine 0:e1a608bb55e8 380 Disable BTAC
jamesadevine 0:e1a608bb55e8 381 */
jamesadevine 0:e1a608bb55e8 382 __STATIC_INLINE void __disable_btac(void) {
jamesadevine 0:e1a608bb55e8 383 // Clear Z bit 11 to disable branch prediction
jamesadevine 0:e1a608bb55e8 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jamesadevine 0:e1a608bb55e8 385 }
jamesadevine 0:e1a608bb55e8 386
jamesadevine 0:e1a608bb55e8 387
jamesadevine 0:e1a608bb55e8 388 /** \brief Enable MMU
jamesadevine 0:e1a608bb55e8 389
jamesadevine 0:e1a608bb55e8 390 Enable MMU
jamesadevine 0:e1a608bb55e8 391 */
jamesadevine 0:e1a608bb55e8 392 __STATIC_INLINE void __enable_mmu(void) {
jamesadevine 0:e1a608bb55e8 393 // Set M bit 0 to enable the MMU
jamesadevine 0:e1a608bb55e8 394 // Set AFE bit to enable simplified access permissions model
jamesadevine 0:e1a608bb55e8 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jamesadevine 0:e1a608bb55e8 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jamesadevine 0:e1a608bb55e8 397 __ISB();
jamesadevine 0:e1a608bb55e8 398 }
jamesadevine 0:e1a608bb55e8 399
jamesadevine 0:e1a608bb55e8 400 /** \brief Enable MMU
jamesadevine 0:e1a608bb55e8 401
jamesadevine 0:e1a608bb55e8 402 Enable MMU
jamesadevine 0:e1a608bb55e8 403 */
jamesadevine 0:e1a608bb55e8 404 __STATIC_INLINE void __disable_mmu(void) {
jamesadevine 0:e1a608bb55e8 405 // Clear M bit 0 to disable the MMU
jamesadevine 0:e1a608bb55e8 406 __set_SCTLR( __get_SCTLR() & ~1);
jamesadevine 0:e1a608bb55e8 407 __ISB();
jamesadevine 0:e1a608bb55e8 408 }
jamesadevine 0:e1a608bb55e8 409
jamesadevine 0:e1a608bb55e8 410 /******************************** TLB maintenance operations ************************************************/
jamesadevine 0:e1a608bb55e8 411 /** \brief Invalidate the whole tlb
jamesadevine 0:e1a608bb55e8 412
jamesadevine 0:e1a608bb55e8 413 TLBIALL. Invalidate the whole tlb
jamesadevine 0:e1a608bb55e8 414 */
jamesadevine 0:e1a608bb55e8 415
jamesadevine 0:e1a608bb55e8 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jamesadevine 0:e1a608bb55e8 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jamesadevine 0:e1a608bb55e8 418 __TLBIALL = 0;
jamesadevine 0:e1a608bb55e8 419 __DSB();
jamesadevine 0:e1a608bb55e8 420 __ISB();
jamesadevine 0:e1a608bb55e8 421 }
jamesadevine 0:e1a608bb55e8 422
jamesadevine 0:e1a608bb55e8 423 /******************************** BTB maintenance operations ************************************************/
jamesadevine 0:e1a608bb55e8 424 /** \brief Invalidate entire branch predictor array
jamesadevine 0:e1a608bb55e8 425
jamesadevine 0:e1a608bb55e8 426 BPIALL. Branch Predictor Invalidate All.
jamesadevine 0:e1a608bb55e8 427 */
jamesadevine 0:e1a608bb55e8 428
jamesadevine 0:e1a608bb55e8 429 __STATIC_INLINE void __v7_inv_btac(void) {
jamesadevine 0:e1a608bb55e8 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jamesadevine 0:e1a608bb55e8 431 __BPIALL = 0;
jamesadevine 0:e1a608bb55e8 432 __DSB(); //ensure completion of the invalidation
jamesadevine 0:e1a608bb55e8 433 __ISB(); //ensure instruction fetch path sees new state
jamesadevine 0:e1a608bb55e8 434 }
jamesadevine 0:e1a608bb55e8 435
jamesadevine 0:e1a608bb55e8 436
jamesadevine 0:e1a608bb55e8 437 /******************************** L1 cache operations ******************************************************/
jamesadevine 0:e1a608bb55e8 438
jamesadevine 0:e1a608bb55e8 439 /** \brief Invalidate the whole I$
jamesadevine 0:e1a608bb55e8 440
jamesadevine 0:e1a608bb55e8 441 ICIALLU. Instruction Cache Invalidate All to PoU
jamesadevine 0:e1a608bb55e8 442 */
jamesadevine 0:e1a608bb55e8 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
jamesadevine 0:e1a608bb55e8 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jamesadevine 0:e1a608bb55e8 445 __ICIALLU = 0;
jamesadevine 0:e1a608bb55e8 446 __DSB(); //ensure completion of the invalidation
jamesadevine 0:e1a608bb55e8 447 __ISB(); //ensure instruction fetch path sees new I cache state
jamesadevine 0:e1a608bb55e8 448 }
jamesadevine 0:e1a608bb55e8 449
jamesadevine 0:e1a608bb55e8 450 /** \brief Clean D$ by MVA
jamesadevine 0:e1a608bb55e8 451
jamesadevine 0:e1a608bb55e8 452 DCCMVAC. Data cache clean by MVA to PoC
jamesadevine 0:e1a608bb55e8 453 */
jamesadevine 0:e1a608bb55e8 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jamesadevine 0:e1a608bb55e8 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jamesadevine 0:e1a608bb55e8 456 __DCCMVAC = (uint32_t)va;
jamesadevine 0:e1a608bb55e8 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jamesadevine 0:e1a608bb55e8 458 }
jamesadevine 0:e1a608bb55e8 459
jamesadevine 0:e1a608bb55e8 460 /** \brief Invalidate D$ by MVA
jamesadevine 0:e1a608bb55e8 461
jamesadevine 0:e1a608bb55e8 462 DCIMVAC. Data cache invalidate by MVA to PoC
jamesadevine 0:e1a608bb55e8 463 */
jamesadevine 0:e1a608bb55e8 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jamesadevine 0:e1a608bb55e8 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jamesadevine 0:e1a608bb55e8 466 __DCIMVAC = (uint32_t)va;
jamesadevine 0:e1a608bb55e8 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jamesadevine 0:e1a608bb55e8 468 }
jamesadevine 0:e1a608bb55e8 469
jamesadevine 0:e1a608bb55e8 470 /** \brief Clean and Invalidate D$ by MVA
jamesadevine 0:e1a608bb55e8 471
jamesadevine 0:e1a608bb55e8 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jamesadevine 0:e1a608bb55e8 473 */
jamesadevine 0:e1a608bb55e8 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jamesadevine 0:e1a608bb55e8 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jamesadevine 0:e1a608bb55e8 476 __DCCIMVAC = (uint32_t)va;
jamesadevine 0:e1a608bb55e8 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jamesadevine 0:e1a608bb55e8 478 }
jamesadevine 0:e1a608bb55e8 479
jamesadevine 0:e1a608bb55e8 480 /** \brief
jamesadevine 0:e1a608bb55e8 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jamesadevine 0:e1a608bb55e8 482 */
jamesadevine 0:e1a608bb55e8 483 #pragma push
jamesadevine 0:e1a608bb55e8 484 #pragma arm
jamesadevine 0:e1a608bb55e8 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
jamesadevine 0:e1a608bb55e8 486 ARM
jamesadevine 0:e1a608bb55e8 487
jamesadevine 0:e1a608bb55e8 488 PUSH {R4-R11}
jamesadevine 0:e1a608bb55e8 489
jamesadevine 0:e1a608bb55e8 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
jamesadevine 0:e1a608bb55e8 491 ANDS R3, R6, #0x07000000 // Extract coherency level
jamesadevine 0:e1a608bb55e8 492 MOV R3, R3, LSR #23 // Total cache levels << 1
jamesadevine 0:e1a608bb55e8 493 BEQ Finished // If 0, no need to clean
jamesadevine 0:e1a608bb55e8 494
jamesadevine 0:e1a608bb55e8 495 MOV R10, #0 // R10 holds current cache level << 1
jamesadevine 0:e1a608bb55e8 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
jamesadevine 0:e1a608bb55e8 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
jamesadevine 0:e1a608bb55e8 498 AND R1, R1, #7 // Isolate those lower 3 bits
jamesadevine 0:e1a608bb55e8 499 CMP R1, #2
jamesadevine 0:e1a608bb55e8 500 BLT Skip // No cache or only instruction cache at this level
jamesadevine 0:e1a608bb55e8 501
jamesadevine 0:e1a608bb55e8 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
jamesadevine 0:e1a608bb55e8 503 ISB // ISB to sync the change to the CacheSizeID reg
jamesadevine 0:e1a608bb55e8 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
jamesadevine 0:e1a608bb55e8 505 AND R2, R1, #7 // Extract the line length field
jamesadevine 0:e1a608bb55e8 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
jamesadevine 0:e1a608bb55e8 507 LDR R4, =0x3FF
jamesadevine 0:e1a608bb55e8 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
jamesadevine 0:e1a608bb55e8 509 CLZ R5, R4 // R5 is the bit position of the way size increment
jamesadevine 0:e1a608bb55e8 510 LDR R7, =0x7FFF
jamesadevine 0:e1a608bb55e8 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
jamesadevine 0:e1a608bb55e8 512
jamesadevine 0:e1a608bb55e8 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
jamesadevine 0:e1a608bb55e8 514
jamesadevine 0:e1a608bb55e8 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
jamesadevine 0:e1a608bb55e8 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
jamesadevine 0:e1a608bb55e8 517 CMP R0, #0
jamesadevine 0:e1a608bb55e8 518 BNE Dccsw
jamesadevine 0:e1a608bb55e8 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
jamesadevine 0:e1a608bb55e8 520 B cont
jamesadevine 0:e1a608bb55e8 521 Dccsw CMP R0, #1
jamesadevine 0:e1a608bb55e8 522 BNE Dccisw
jamesadevine 0:e1a608bb55e8 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
jamesadevine 0:e1a608bb55e8 524 B cont
jamesadevine 0:e1a608bb55e8 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
jamesadevine 0:e1a608bb55e8 526 cont SUBS R9, R9, #1 // Decrement the Way number
jamesadevine 0:e1a608bb55e8 527 BGE Loop3
jamesadevine 0:e1a608bb55e8 528 SUBS R7, R7, #1 // Decrement the Set number
jamesadevine 0:e1a608bb55e8 529 BGE Loop2
jamesadevine 0:e1a608bb55e8 530 Skip ADD R10, R10, #2 // increment the cache number
jamesadevine 0:e1a608bb55e8 531 CMP R3, R10
jamesadevine 0:e1a608bb55e8 532 BGT Loop1
jamesadevine 0:e1a608bb55e8 533
jamesadevine 0:e1a608bb55e8 534 Finished
jamesadevine 0:e1a608bb55e8 535 DSB
jamesadevine 0:e1a608bb55e8 536 POP {R4-R11}
jamesadevine 0:e1a608bb55e8 537 BX lr
jamesadevine 0:e1a608bb55e8 538
jamesadevine 0:e1a608bb55e8 539 }
jamesadevine 0:e1a608bb55e8 540 #pragma pop
jamesadevine 0:e1a608bb55e8 541
jamesadevine 0:e1a608bb55e8 542 /** \brief __v7_all_cache - helper function
jamesadevine 0:e1a608bb55e8 543
jamesadevine 0:e1a608bb55e8 544 */
jamesadevine 0:e1a608bb55e8 545
jamesadevine 0:e1a608bb55e8 546 /** \brief Invalidate the whole D$
jamesadevine 0:e1a608bb55e8 547
jamesadevine 0:e1a608bb55e8 548 DCISW. Invalidate by Set/Way
jamesadevine 0:e1a608bb55e8 549 */
jamesadevine 0:e1a608bb55e8 550
jamesadevine 0:e1a608bb55e8 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
jamesadevine 0:e1a608bb55e8 552 __v7_all_cache(0);
jamesadevine 0:e1a608bb55e8 553 }
jamesadevine 0:e1a608bb55e8 554
jamesadevine 0:e1a608bb55e8 555 /** \brief Clean the whole D$
jamesadevine 0:e1a608bb55e8 556
jamesadevine 0:e1a608bb55e8 557 DCCSW. Clean by Set/Way
jamesadevine 0:e1a608bb55e8 558 */
jamesadevine 0:e1a608bb55e8 559
jamesadevine 0:e1a608bb55e8 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
jamesadevine 0:e1a608bb55e8 561 __v7_all_cache(1);
jamesadevine 0:e1a608bb55e8 562 }
jamesadevine 0:e1a608bb55e8 563
jamesadevine 0:e1a608bb55e8 564 /** \brief Clean and invalidate the whole D$
jamesadevine 0:e1a608bb55e8 565
jamesadevine 0:e1a608bb55e8 566 DCCISW. Clean and Invalidate by Set/Way
jamesadevine 0:e1a608bb55e8 567 */
jamesadevine 0:e1a608bb55e8 568
jamesadevine 0:e1a608bb55e8 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jamesadevine 0:e1a608bb55e8 570 __v7_all_cache(2);
jamesadevine 0:e1a608bb55e8 571 }
jamesadevine 0:e1a608bb55e8 572
jamesadevine 0:e1a608bb55e8 573 #include "core_ca_mmu.h"
jamesadevine 0:e1a608bb55e8 574
jamesadevine 0:e1a608bb55e8 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
jamesadevine 0:e1a608bb55e8 576
jamesadevine 0:e1a608bb55e8 577 #error IAR Compiler support not implemented for Cortex-A
jamesadevine 0:e1a608bb55e8 578
jamesadevine 0:e1a608bb55e8 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
jamesadevine 0:e1a608bb55e8 580
jamesadevine 0:e1a608bb55e8 581 /* GNU gcc specific functions */
jamesadevine 0:e1a608bb55e8 582
jamesadevine 0:e1a608bb55e8 583 #define MODE_USR 0x10
jamesadevine 0:e1a608bb55e8 584 #define MODE_FIQ 0x11
jamesadevine 0:e1a608bb55e8 585 #define MODE_IRQ 0x12
jamesadevine 0:e1a608bb55e8 586 #define MODE_SVC 0x13
jamesadevine 0:e1a608bb55e8 587 #define MODE_MON 0x16
jamesadevine 0:e1a608bb55e8 588 #define MODE_ABT 0x17
jamesadevine 0:e1a608bb55e8 589 #define MODE_HYP 0x1A
jamesadevine 0:e1a608bb55e8 590 #define MODE_UND 0x1B
jamesadevine 0:e1a608bb55e8 591 #define MODE_SYS 0x1F
jamesadevine 0:e1a608bb55e8 592
jamesadevine 0:e1a608bb55e8 593
jamesadevine 0:e1a608bb55e8 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
jamesadevine 0:e1a608bb55e8 595 {
jamesadevine 0:e1a608bb55e8 596 __ASM volatile ("cpsie i");
jamesadevine 0:e1a608bb55e8 597 }
jamesadevine 0:e1a608bb55e8 598
jamesadevine 0:e1a608bb55e8 599 /** \brief Disable IRQ Interrupts
jamesadevine 0:e1a608bb55e8 600
jamesadevine 0:e1a608bb55e8 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 602 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 603 */
jamesadevine 0:e1a608bb55e8 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
jamesadevine 0:e1a608bb55e8 605 {
jamesadevine 0:e1a608bb55e8 606 uint32_t result;
jamesadevine 0:e1a608bb55e8 607
jamesadevine 0:e1a608bb55e8 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
jamesadevine 0:e1a608bb55e8 609 __ASM volatile ("cpsid i");
jamesadevine 0:e1a608bb55e8 610 return(result & 0x80);
jamesadevine 0:e1a608bb55e8 611 }
jamesadevine 0:e1a608bb55e8 612
jamesadevine 0:e1a608bb55e8 613
jamesadevine 0:e1a608bb55e8 614 /** \brief Get APSR Register
jamesadevine 0:e1a608bb55e8 615
jamesadevine 0:e1a608bb55e8 616 This function returns the content of the APSR Register.
jamesadevine 0:e1a608bb55e8 617
jamesadevine 0:e1a608bb55e8 618 \return APSR Register value
jamesadevine 0:e1a608bb55e8 619 */
jamesadevine 0:e1a608bb55e8 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
jamesadevine 0:e1a608bb55e8 621 {
jamesadevine 0:e1a608bb55e8 622 #if 1
jamesadevine 0:e1a608bb55e8 623 uint32_t result;
jamesadevine 0:e1a608bb55e8 624
jamesadevine 0:e1a608bb55e8 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 626 return (result);
jamesadevine 0:e1a608bb55e8 627 #else
jamesadevine 0:e1a608bb55e8 628 register uint32_t __regAPSR __ASM("apsr");
jamesadevine 0:e1a608bb55e8 629 return(__regAPSR);
jamesadevine 0:e1a608bb55e8 630 #endif
jamesadevine 0:e1a608bb55e8 631 }
jamesadevine 0:e1a608bb55e8 632
jamesadevine 0:e1a608bb55e8 633
jamesadevine 0:e1a608bb55e8 634 /** \brief Get CPSR Register
jamesadevine 0:e1a608bb55e8 635
jamesadevine 0:e1a608bb55e8 636 This function returns the content of the CPSR Register.
jamesadevine 0:e1a608bb55e8 637
jamesadevine 0:e1a608bb55e8 638 \return CPSR Register value
jamesadevine 0:e1a608bb55e8 639 */
jamesadevine 0:e1a608bb55e8 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
jamesadevine 0:e1a608bb55e8 641 {
jamesadevine 0:e1a608bb55e8 642 #if 1
jamesadevine 0:e1a608bb55e8 643 register uint32_t __regCPSR;
jamesadevine 0:e1a608bb55e8 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
jamesadevine 0:e1a608bb55e8 645 #else
jamesadevine 0:e1a608bb55e8 646 register uint32_t __regCPSR __ASM("cpsr");
jamesadevine 0:e1a608bb55e8 647 #endif
jamesadevine 0:e1a608bb55e8 648 return(__regCPSR);
jamesadevine 0:e1a608bb55e8 649 }
jamesadevine 0:e1a608bb55e8 650
jamesadevine 0:e1a608bb55e8 651 #if 0
jamesadevine 0:e1a608bb55e8 652 /** \brief Set Stack Pointer
jamesadevine 0:e1a608bb55e8 653
jamesadevine 0:e1a608bb55e8 654 This function assigns the given value to the current stack pointer.
jamesadevine 0:e1a608bb55e8 655
jamesadevine 0:e1a608bb55e8 656 \param [in] topOfStack Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 657 */
jamesadevine 0:e1a608bb55e8 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jamesadevine 0:e1a608bb55e8 659 {
jamesadevine 0:e1a608bb55e8 660 register uint32_t __regSP __ASM("sp");
jamesadevine 0:e1a608bb55e8 661 __regSP = topOfStack;
jamesadevine 0:e1a608bb55e8 662 }
jamesadevine 0:e1a608bb55e8 663 #endif
jamesadevine 0:e1a608bb55e8 664
jamesadevine 0:e1a608bb55e8 665 /** \brief Get link register
jamesadevine 0:e1a608bb55e8 666
jamesadevine 0:e1a608bb55e8 667 This function returns the value of the link register
jamesadevine 0:e1a608bb55e8 668
jamesadevine 0:e1a608bb55e8 669 \return Value of link register
jamesadevine 0:e1a608bb55e8 670 */
jamesadevine 0:e1a608bb55e8 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
jamesadevine 0:e1a608bb55e8 672 {
jamesadevine 0:e1a608bb55e8 673 register uint32_t __reglr __ASM("lr");
jamesadevine 0:e1a608bb55e8 674 return(__reglr);
jamesadevine 0:e1a608bb55e8 675 }
jamesadevine 0:e1a608bb55e8 676
jamesadevine 0:e1a608bb55e8 677 #if 0
jamesadevine 0:e1a608bb55e8 678 /** \brief Set link register
jamesadevine 0:e1a608bb55e8 679
jamesadevine 0:e1a608bb55e8 680 This function sets the value of the link register
jamesadevine 0:e1a608bb55e8 681
jamesadevine 0:e1a608bb55e8 682 \param [in] lr LR value to set
jamesadevine 0:e1a608bb55e8 683 */
jamesadevine 0:e1a608bb55e8 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
jamesadevine 0:e1a608bb55e8 685 {
jamesadevine 0:e1a608bb55e8 686 register uint32_t __reglr __ASM("lr");
jamesadevine 0:e1a608bb55e8 687 __reglr = lr;
jamesadevine 0:e1a608bb55e8 688 }
jamesadevine 0:e1a608bb55e8 689 #endif
jamesadevine 0:e1a608bb55e8 690
jamesadevine 0:e1a608bb55e8 691 /** \brief Set Process Stack Pointer
jamesadevine 0:e1a608bb55e8 692
jamesadevine 0:e1a608bb55e8 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jamesadevine 0:e1a608bb55e8 694
jamesadevine 0:e1a608bb55e8 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 696 */
jamesadevine 0:e1a608bb55e8 697 extern void __set_PSP(uint32_t topOfProcStack);
jamesadevine 0:e1a608bb55e8 698
jamesadevine 0:e1a608bb55e8 699 /** \brief Set User Mode
jamesadevine 0:e1a608bb55e8 700
jamesadevine 0:e1a608bb55e8 701 This function changes the processor state to User Mode
jamesadevine 0:e1a608bb55e8 702
jamesadevine 0:e1a608bb55e8 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 704 */
jamesadevine 0:e1a608bb55e8 705 extern void __set_CPS_USR(void);
jamesadevine 0:e1a608bb55e8 706
jamesadevine 0:e1a608bb55e8 707 /** \brief Enable FIQ
jamesadevine 0:e1a608bb55e8 708
jamesadevine 0:e1a608bb55e8 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 710 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 711 */
jamesadevine 0:e1a608bb55e8 712 #define __enable_fault_irq __enable_fiq
jamesadevine 0:e1a608bb55e8 713
jamesadevine 0:e1a608bb55e8 714
jamesadevine 0:e1a608bb55e8 715 /** \brief Disable FIQ
jamesadevine 0:e1a608bb55e8 716
jamesadevine 0:e1a608bb55e8 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 718 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 719 */
jamesadevine 0:e1a608bb55e8 720 #define __disable_fault_irq __disable_fiq
jamesadevine 0:e1a608bb55e8 721
jamesadevine 0:e1a608bb55e8 722
jamesadevine 0:e1a608bb55e8 723 /** \brief Get FPSCR
jamesadevine 0:e1a608bb55e8 724
jamesadevine 0:e1a608bb55e8 725 This function returns the current value of the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 726
jamesadevine 0:e1a608bb55e8 727 \return Floating Point Status/Control register value
jamesadevine 0:e1a608bb55e8 728 */
jamesadevine 0:e1a608bb55e8 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
jamesadevine 0:e1a608bb55e8 730 {
jamesadevine 0:e1a608bb55e8 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 732 #if 1
jamesadevine 0:e1a608bb55e8 733 uint32_t result;
jamesadevine 0:e1a608bb55e8 734
jamesadevine 0:e1a608bb55e8 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 736 return (result);
jamesadevine 0:e1a608bb55e8 737 #else
jamesadevine 0:e1a608bb55e8 738 register uint32_t __regfpscr __ASM("fpscr");
jamesadevine 0:e1a608bb55e8 739 return(__regfpscr);
jamesadevine 0:e1a608bb55e8 740 #endif
jamesadevine 0:e1a608bb55e8 741 #else
jamesadevine 0:e1a608bb55e8 742 return(0);
jamesadevine 0:e1a608bb55e8 743 #endif
jamesadevine 0:e1a608bb55e8 744 }
jamesadevine 0:e1a608bb55e8 745
jamesadevine 0:e1a608bb55e8 746
jamesadevine 0:e1a608bb55e8 747 /** \brief Set FPSCR
jamesadevine 0:e1a608bb55e8 748
jamesadevine 0:e1a608bb55e8 749 This function assigns the given value to the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 750
jamesadevine 0:e1a608bb55e8 751 \param [in] fpscr Floating Point Status/Control value to set
jamesadevine 0:e1a608bb55e8 752 */
jamesadevine 0:e1a608bb55e8 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jamesadevine 0:e1a608bb55e8 754 {
jamesadevine 0:e1a608bb55e8 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 756 #if 1
jamesadevine 0:e1a608bb55e8 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
jamesadevine 0:e1a608bb55e8 758 #else
jamesadevine 0:e1a608bb55e8 759 register uint32_t __regfpscr __ASM("fpscr");
jamesadevine 0:e1a608bb55e8 760 __regfpscr = (fpscr);
jamesadevine 0:e1a608bb55e8 761 #endif
jamesadevine 0:e1a608bb55e8 762 #endif
jamesadevine 0:e1a608bb55e8 763 }
jamesadevine 0:e1a608bb55e8 764
jamesadevine 0:e1a608bb55e8 765 /** \brief Get FPEXC
jamesadevine 0:e1a608bb55e8 766
jamesadevine 0:e1a608bb55e8 767 This function returns the current value of the Floating Point Exception Control register.
jamesadevine 0:e1a608bb55e8 768
jamesadevine 0:e1a608bb55e8 769 \return Floating Point Exception Control register value
jamesadevine 0:e1a608bb55e8 770 */
jamesadevine 0:e1a608bb55e8 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
jamesadevine 0:e1a608bb55e8 772 {
jamesadevine 0:e1a608bb55e8 773 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 774 #if 1
jamesadevine 0:e1a608bb55e8 775 uint32_t result;
jamesadevine 0:e1a608bb55e8 776
jamesadevine 0:e1a608bb55e8 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
jamesadevine 0:e1a608bb55e8 778 return (result);
jamesadevine 0:e1a608bb55e8 779 #else
jamesadevine 0:e1a608bb55e8 780 register uint32_t __regfpexc __ASM("fpexc");
jamesadevine 0:e1a608bb55e8 781 return(__regfpexc);
jamesadevine 0:e1a608bb55e8 782 #endif
jamesadevine 0:e1a608bb55e8 783 #else
jamesadevine 0:e1a608bb55e8 784 return(0);
jamesadevine 0:e1a608bb55e8 785 #endif
jamesadevine 0:e1a608bb55e8 786 }
jamesadevine 0:e1a608bb55e8 787
jamesadevine 0:e1a608bb55e8 788
jamesadevine 0:e1a608bb55e8 789 /** \brief Set FPEXC
jamesadevine 0:e1a608bb55e8 790
jamesadevine 0:e1a608bb55e8 791 This function assigns the given value to the Floating Point Exception Control register.
jamesadevine 0:e1a608bb55e8 792
jamesadevine 0:e1a608bb55e8 793 \param [in] fpscr Floating Point Exception Control value to set
jamesadevine 0:e1a608bb55e8 794 */
jamesadevine 0:e1a608bb55e8 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jamesadevine 0:e1a608bb55e8 796 {
jamesadevine 0:e1a608bb55e8 797 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 798 #if 1
jamesadevine 0:e1a608bb55e8 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
jamesadevine 0:e1a608bb55e8 800 #else
jamesadevine 0:e1a608bb55e8 801 register uint32_t __regfpexc __ASM("fpexc");
jamesadevine 0:e1a608bb55e8 802 __regfpexc = (fpexc);
jamesadevine 0:e1a608bb55e8 803 #endif
jamesadevine 0:e1a608bb55e8 804 #endif
jamesadevine 0:e1a608bb55e8 805 }
jamesadevine 0:e1a608bb55e8 806
jamesadevine 0:e1a608bb55e8 807 /** \brief Get CPACR
jamesadevine 0:e1a608bb55e8 808
jamesadevine 0:e1a608bb55e8 809 This function returns the current value of the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 810
jamesadevine 0:e1a608bb55e8 811 \return Coprocessor Access Control register value
jamesadevine 0:e1a608bb55e8 812 */
jamesadevine 0:e1a608bb55e8 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
jamesadevine 0:e1a608bb55e8 814 {
jamesadevine 0:e1a608bb55e8 815 #if 1
jamesadevine 0:e1a608bb55e8 816 register uint32_t __regCPACR;
jamesadevine 0:e1a608bb55e8 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
jamesadevine 0:e1a608bb55e8 818 #else
jamesadevine 0:e1a608bb55e8 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jamesadevine 0:e1a608bb55e8 820 #endif
jamesadevine 0:e1a608bb55e8 821 return __regCPACR;
jamesadevine 0:e1a608bb55e8 822 }
jamesadevine 0:e1a608bb55e8 823
jamesadevine 0:e1a608bb55e8 824 /** \brief Set CPACR
jamesadevine 0:e1a608bb55e8 825
jamesadevine 0:e1a608bb55e8 826 This function assigns the given value to the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 827
jamesadevine 0:e1a608bb55e8 828 \param [in] cpacr Coporcessor Acccess Control value to set
jamesadevine 0:e1a608bb55e8 829 */
jamesadevine 0:e1a608bb55e8 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jamesadevine 0:e1a608bb55e8 831 {
jamesadevine 0:e1a608bb55e8 832 #if 1
jamesadevine 0:e1a608bb55e8 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
jamesadevine 0:e1a608bb55e8 834 #else
jamesadevine 0:e1a608bb55e8 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jamesadevine 0:e1a608bb55e8 836 __regCPACR = cpacr;
jamesadevine 0:e1a608bb55e8 837 #endif
jamesadevine 0:e1a608bb55e8 838 __ISB();
jamesadevine 0:e1a608bb55e8 839 }
jamesadevine 0:e1a608bb55e8 840
jamesadevine 0:e1a608bb55e8 841 /** \brief Get CBAR
jamesadevine 0:e1a608bb55e8 842
jamesadevine 0:e1a608bb55e8 843 This function returns the value of the Configuration Base Address register.
jamesadevine 0:e1a608bb55e8 844
jamesadevine 0:e1a608bb55e8 845 \return Configuration Base Address register value
jamesadevine 0:e1a608bb55e8 846 */
jamesadevine 0:e1a608bb55e8 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
jamesadevine 0:e1a608bb55e8 848 #if 1
jamesadevine 0:e1a608bb55e8 849 register uint32_t __regCBAR;
jamesadevine 0:e1a608bb55e8 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
jamesadevine 0:e1a608bb55e8 851 #else
jamesadevine 0:e1a608bb55e8 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jamesadevine 0:e1a608bb55e8 853 #endif
jamesadevine 0:e1a608bb55e8 854 return(__regCBAR);
jamesadevine 0:e1a608bb55e8 855 }
jamesadevine 0:e1a608bb55e8 856
jamesadevine 0:e1a608bb55e8 857 /** \brief Get TTBR0
jamesadevine 0:e1a608bb55e8 858
jamesadevine 0:e1a608bb55e8 859 This function returns the value of the Configuration Base Address register.
jamesadevine 0:e1a608bb55e8 860
jamesadevine 0:e1a608bb55e8 861 \return Translation Table Base Register 0 value
jamesadevine 0:e1a608bb55e8 862 */
jamesadevine 0:e1a608bb55e8 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
jamesadevine 0:e1a608bb55e8 864 #if 1
jamesadevine 0:e1a608bb55e8 865 register uint32_t __regTTBR0;
jamesadevine 0:e1a608bb55e8 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
jamesadevine 0:e1a608bb55e8 867 #else
jamesadevine 0:e1a608bb55e8 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jamesadevine 0:e1a608bb55e8 869 #endif
jamesadevine 0:e1a608bb55e8 870 return(__regTTBR0);
jamesadevine 0:e1a608bb55e8 871 }
jamesadevine 0:e1a608bb55e8 872
jamesadevine 0:e1a608bb55e8 873 /** \brief Set TTBR0
jamesadevine 0:e1a608bb55e8 874
jamesadevine 0:e1a608bb55e8 875 This function assigns the given value to the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 876
jamesadevine 0:e1a608bb55e8 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
jamesadevine 0:e1a608bb55e8 878 */
jamesadevine 0:e1a608bb55e8 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jamesadevine 0:e1a608bb55e8 880 #if 1
jamesadevine 0:e1a608bb55e8 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
jamesadevine 0:e1a608bb55e8 882 #else
jamesadevine 0:e1a608bb55e8 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jamesadevine 0:e1a608bb55e8 884 __regTTBR0 = ttbr0;
jamesadevine 0:e1a608bb55e8 885 #endif
jamesadevine 0:e1a608bb55e8 886 __ISB();
jamesadevine 0:e1a608bb55e8 887 }
jamesadevine 0:e1a608bb55e8 888
jamesadevine 0:e1a608bb55e8 889 /** \brief Get DACR
jamesadevine 0:e1a608bb55e8 890
jamesadevine 0:e1a608bb55e8 891 This function returns the value of the Domain Access Control Register.
jamesadevine 0:e1a608bb55e8 892
jamesadevine 0:e1a608bb55e8 893 \return Domain Access Control Register value
jamesadevine 0:e1a608bb55e8 894 */
jamesadevine 0:e1a608bb55e8 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
jamesadevine 0:e1a608bb55e8 896 #if 1
jamesadevine 0:e1a608bb55e8 897 register uint32_t __regDACR;
jamesadevine 0:e1a608bb55e8 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
jamesadevine 0:e1a608bb55e8 899 #else
jamesadevine 0:e1a608bb55e8 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jamesadevine 0:e1a608bb55e8 901 #endif
jamesadevine 0:e1a608bb55e8 902 return(__regDACR);
jamesadevine 0:e1a608bb55e8 903 }
jamesadevine 0:e1a608bb55e8 904
jamesadevine 0:e1a608bb55e8 905 /** \brief Set DACR
jamesadevine 0:e1a608bb55e8 906
jamesadevine 0:e1a608bb55e8 907 This function assigns the given value to the Coprocessor Access Control register.
jamesadevine 0:e1a608bb55e8 908
jamesadevine 0:e1a608bb55e8 909 \param [in] dacr Domain Access Control Register value to set
jamesadevine 0:e1a608bb55e8 910 */
jamesadevine 0:e1a608bb55e8 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jamesadevine 0:e1a608bb55e8 912 #if 1
jamesadevine 0:e1a608bb55e8 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
jamesadevine 0:e1a608bb55e8 914 #else
jamesadevine 0:e1a608bb55e8 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jamesadevine 0:e1a608bb55e8 916 __regDACR = dacr;
jamesadevine 0:e1a608bb55e8 917 #endif
jamesadevine 0:e1a608bb55e8 918 __ISB();
jamesadevine 0:e1a608bb55e8 919 }
jamesadevine 0:e1a608bb55e8 920
jamesadevine 0:e1a608bb55e8 921 /******************************** Cache and BTAC enable ****************************************************/
jamesadevine 0:e1a608bb55e8 922
jamesadevine 0:e1a608bb55e8 923 /** \brief Set SCTLR
jamesadevine 0:e1a608bb55e8 924
jamesadevine 0:e1a608bb55e8 925 This function assigns the given value to the System Control Register.
jamesadevine 0:e1a608bb55e8 926
jamesadevine 0:e1a608bb55e8 927 \param [in] sctlr System Control Register, value to set
jamesadevine 0:e1a608bb55e8 928 */
jamesadevine 0:e1a608bb55e8 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jamesadevine 0:e1a608bb55e8 930 {
jamesadevine 0:e1a608bb55e8 931 #if 1
jamesadevine 0:e1a608bb55e8 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
jamesadevine 0:e1a608bb55e8 933 #else
jamesadevine 0:e1a608bb55e8 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jamesadevine 0:e1a608bb55e8 935 __regSCTLR = sctlr;
jamesadevine 0:e1a608bb55e8 936 #endif
jamesadevine 0:e1a608bb55e8 937 }
jamesadevine 0:e1a608bb55e8 938
jamesadevine 0:e1a608bb55e8 939 /** \brief Get SCTLR
jamesadevine 0:e1a608bb55e8 940
jamesadevine 0:e1a608bb55e8 941 This function returns the value of the System Control Register.
jamesadevine 0:e1a608bb55e8 942
jamesadevine 0:e1a608bb55e8 943 \return System Control Register value
jamesadevine 0:e1a608bb55e8 944 */
jamesadevine 0:e1a608bb55e8 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
jamesadevine 0:e1a608bb55e8 946 #if 1
jamesadevine 0:e1a608bb55e8 947 register uint32_t __regSCTLR;
jamesadevine 0:e1a608bb55e8 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
jamesadevine 0:e1a608bb55e8 949 #else
jamesadevine 0:e1a608bb55e8 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jamesadevine 0:e1a608bb55e8 951 #endif
jamesadevine 0:e1a608bb55e8 952 return(__regSCTLR);
jamesadevine 0:e1a608bb55e8 953 }
jamesadevine 0:e1a608bb55e8 954
jamesadevine 0:e1a608bb55e8 955 /** \brief Enable Caches
jamesadevine 0:e1a608bb55e8 956
jamesadevine 0:e1a608bb55e8 957 Enable Caches
jamesadevine 0:e1a608bb55e8 958 */
jamesadevine 0:e1a608bb55e8 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
jamesadevine 0:e1a608bb55e8 960 // Set I bit 12 to enable I Cache
jamesadevine 0:e1a608bb55e8 961 // Set C bit 2 to enable D Cache
jamesadevine 0:e1a608bb55e8 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jamesadevine 0:e1a608bb55e8 963 }
jamesadevine 0:e1a608bb55e8 964
jamesadevine 0:e1a608bb55e8 965 /** \brief Disable Caches
jamesadevine 0:e1a608bb55e8 966
jamesadevine 0:e1a608bb55e8 967 Disable Caches
jamesadevine 0:e1a608bb55e8 968 */
jamesadevine 0:e1a608bb55e8 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
jamesadevine 0:e1a608bb55e8 970 // Clear I bit 12 to disable I Cache
jamesadevine 0:e1a608bb55e8 971 // Clear C bit 2 to disable D Cache
jamesadevine 0:e1a608bb55e8 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jamesadevine 0:e1a608bb55e8 973 __ISB();
jamesadevine 0:e1a608bb55e8 974 }
jamesadevine 0:e1a608bb55e8 975
jamesadevine 0:e1a608bb55e8 976 /** \brief Enable BTAC
jamesadevine 0:e1a608bb55e8 977
jamesadevine 0:e1a608bb55e8 978 Enable BTAC
jamesadevine 0:e1a608bb55e8 979 */
jamesadevine 0:e1a608bb55e8 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
jamesadevine 0:e1a608bb55e8 981 // Set Z bit 11 to enable branch prediction
jamesadevine 0:e1a608bb55e8 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
jamesadevine 0:e1a608bb55e8 983 __ISB();
jamesadevine 0:e1a608bb55e8 984 }
jamesadevine 0:e1a608bb55e8 985
jamesadevine 0:e1a608bb55e8 986 /** \brief Disable BTAC
jamesadevine 0:e1a608bb55e8 987
jamesadevine 0:e1a608bb55e8 988 Disable BTAC
jamesadevine 0:e1a608bb55e8 989 */
jamesadevine 0:e1a608bb55e8 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
jamesadevine 0:e1a608bb55e8 991 // Clear Z bit 11 to disable branch prediction
jamesadevine 0:e1a608bb55e8 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jamesadevine 0:e1a608bb55e8 993 }
jamesadevine 0:e1a608bb55e8 994
jamesadevine 0:e1a608bb55e8 995
jamesadevine 0:e1a608bb55e8 996 /** \brief Enable MMU
jamesadevine 0:e1a608bb55e8 997
jamesadevine 0:e1a608bb55e8 998 Enable MMU
jamesadevine 0:e1a608bb55e8 999 */
jamesadevine 0:e1a608bb55e8 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
jamesadevine 0:e1a608bb55e8 1001 // Set M bit 0 to enable the MMU
jamesadevine 0:e1a608bb55e8 1002 // Set AFE bit to enable simplified access permissions model
jamesadevine 0:e1a608bb55e8 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jamesadevine 0:e1a608bb55e8 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jamesadevine 0:e1a608bb55e8 1005 __ISB();
jamesadevine 0:e1a608bb55e8 1006 }
jamesadevine 0:e1a608bb55e8 1007
jamesadevine 0:e1a608bb55e8 1008 /** \brief Enable MMU
jamesadevine 0:e1a608bb55e8 1009
jamesadevine 0:e1a608bb55e8 1010 Enable MMU
jamesadevine 0:e1a608bb55e8 1011 */
jamesadevine 0:e1a608bb55e8 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
jamesadevine 0:e1a608bb55e8 1013 // Clear M bit 0 to disable the MMU
jamesadevine 0:e1a608bb55e8 1014 __set_SCTLR( __get_SCTLR() & ~1);
jamesadevine 0:e1a608bb55e8 1015 __ISB();
jamesadevine 0:e1a608bb55e8 1016 }
jamesadevine 0:e1a608bb55e8 1017
jamesadevine 0:e1a608bb55e8 1018 /******************************** TLB maintenance operations ************************************************/
jamesadevine 0:e1a608bb55e8 1019 /** \brief Invalidate the whole tlb
jamesadevine 0:e1a608bb55e8 1020
jamesadevine 0:e1a608bb55e8 1021 TLBIALL. Invalidate the whole tlb
jamesadevine 0:e1a608bb55e8 1022 */
jamesadevine 0:e1a608bb55e8 1023
jamesadevine 0:e1a608bb55e8 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jamesadevine 0:e1a608bb55e8 1025 #if 1
jamesadevine 0:e1a608bb55e8 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
jamesadevine 0:e1a608bb55e8 1027 #else
jamesadevine 0:e1a608bb55e8 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jamesadevine 0:e1a608bb55e8 1029 __TLBIALL = 0;
jamesadevine 0:e1a608bb55e8 1030 #endif
jamesadevine 0:e1a608bb55e8 1031 __DSB();
jamesadevine 0:e1a608bb55e8 1032 __ISB();
jamesadevine 0:e1a608bb55e8 1033 }
jamesadevine 0:e1a608bb55e8 1034
jamesadevine 0:e1a608bb55e8 1035 /******************************** BTB maintenance operations ************************************************/
jamesadevine 0:e1a608bb55e8 1036 /** \brief Invalidate entire branch predictor array
jamesadevine 0:e1a608bb55e8 1037
jamesadevine 0:e1a608bb55e8 1038 BPIALL. Branch Predictor Invalidate All.
jamesadevine 0:e1a608bb55e8 1039 */
jamesadevine 0:e1a608bb55e8 1040
jamesadevine 0:e1a608bb55e8 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
jamesadevine 0:e1a608bb55e8 1042 #if 1
jamesadevine 0:e1a608bb55e8 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
jamesadevine 0:e1a608bb55e8 1044 #else
jamesadevine 0:e1a608bb55e8 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jamesadevine 0:e1a608bb55e8 1046 __BPIALL = 0;
jamesadevine 0:e1a608bb55e8 1047 #endif
jamesadevine 0:e1a608bb55e8 1048 __DSB(); //ensure completion of the invalidation
jamesadevine 0:e1a608bb55e8 1049 __ISB(); //ensure instruction fetch path sees new state
jamesadevine 0:e1a608bb55e8 1050 }
jamesadevine 0:e1a608bb55e8 1051
jamesadevine 0:e1a608bb55e8 1052
jamesadevine 0:e1a608bb55e8 1053 /******************************** L1 cache operations ******************************************************/
jamesadevine 0:e1a608bb55e8 1054
jamesadevine 0:e1a608bb55e8 1055 /** \brief Invalidate the whole I$
jamesadevine 0:e1a608bb55e8 1056
jamesadevine 0:e1a608bb55e8 1057 ICIALLU. Instruction Cache Invalidate All to PoU
jamesadevine 0:e1a608bb55e8 1058 */
jamesadevine 0:e1a608bb55e8 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
jamesadevine 0:e1a608bb55e8 1060 #if 1
jamesadevine 0:e1a608bb55e8 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
jamesadevine 0:e1a608bb55e8 1062 #else
jamesadevine 0:e1a608bb55e8 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jamesadevine 0:e1a608bb55e8 1064 __ICIALLU = 0;
jamesadevine 0:e1a608bb55e8 1065 #endif
jamesadevine 0:e1a608bb55e8 1066 __DSB(); //ensure completion of the invalidation
jamesadevine 0:e1a608bb55e8 1067 __ISB(); //ensure instruction fetch path sees new I cache state
jamesadevine 0:e1a608bb55e8 1068 }
jamesadevine 0:e1a608bb55e8 1069
jamesadevine 0:e1a608bb55e8 1070 /** \brief Clean D$ by MVA
jamesadevine 0:e1a608bb55e8 1071
jamesadevine 0:e1a608bb55e8 1072 DCCMVAC. Data cache clean by MVA to PoC
jamesadevine 0:e1a608bb55e8 1073 */
jamesadevine 0:e1a608bb55e8 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jamesadevine 0:e1a608bb55e8 1075 #if 1
jamesadevine 0:e1a608bb55e8 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
jamesadevine 0:e1a608bb55e8 1077 #else
jamesadevine 0:e1a608bb55e8 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jamesadevine 0:e1a608bb55e8 1079 __DCCMVAC = (uint32_t)va;
jamesadevine 0:e1a608bb55e8 1080 #endif
jamesadevine 0:e1a608bb55e8 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jamesadevine 0:e1a608bb55e8 1082 }
jamesadevine 0:e1a608bb55e8 1083
jamesadevine 0:e1a608bb55e8 1084 /** \brief Invalidate D$ by MVA
jamesadevine 0:e1a608bb55e8 1085
jamesadevine 0:e1a608bb55e8 1086 DCIMVAC. Data cache invalidate by MVA to PoC
jamesadevine 0:e1a608bb55e8 1087 */
jamesadevine 0:e1a608bb55e8 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jamesadevine 0:e1a608bb55e8 1089 #if 1
jamesadevine 0:e1a608bb55e8 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
jamesadevine 0:e1a608bb55e8 1091 #else
jamesadevine 0:e1a608bb55e8 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jamesadevine 0:e1a608bb55e8 1093 __DCIMVAC = (uint32_t)va;
jamesadevine 0:e1a608bb55e8 1094 #endif
jamesadevine 0:e1a608bb55e8 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jamesadevine 0:e1a608bb55e8 1096 }
jamesadevine 0:e1a608bb55e8 1097
jamesadevine 0:e1a608bb55e8 1098 /** \brief Clean and Invalidate D$ by MVA
jamesadevine 0:e1a608bb55e8 1099
jamesadevine 0:e1a608bb55e8 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jamesadevine 0:e1a608bb55e8 1101 */
jamesadevine 0:e1a608bb55e8 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jamesadevine 0:e1a608bb55e8 1103 #if 1
jamesadevine 0:e1a608bb55e8 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
jamesadevine 0:e1a608bb55e8 1105 #else
jamesadevine 0:e1a608bb55e8 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jamesadevine 0:e1a608bb55e8 1107 __DCCIMVAC = (uint32_t)va;
jamesadevine 0:e1a608bb55e8 1108 #endif
jamesadevine 0:e1a608bb55e8 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jamesadevine 0:e1a608bb55e8 1110 }
jamesadevine 0:e1a608bb55e8 1111
jamesadevine 0:e1a608bb55e8 1112 /** \brief
jamesadevine 0:e1a608bb55e8 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jamesadevine 0:e1a608bb55e8 1114 */
jamesadevine 0:e1a608bb55e8 1115
jamesadevine 0:e1a608bb55e8 1116 /** \brief __v7_all_cache - helper function
jamesadevine 0:e1a608bb55e8 1117
jamesadevine 0:e1a608bb55e8 1118 */
jamesadevine 0:e1a608bb55e8 1119
jamesadevine 0:e1a608bb55e8 1120 extern void __v7_all_cache(uint32_t op);
jamesadevine 0:e1a608bb55e8 1121
jamesadevine 0:e1a608bb55e8 1122
jamesadevine 0:e1a608bb55e8 1123 /** \brief Invalidate the whole D$
jamesadevine 0:e1a608bb55e8 1124
jamesadevine 0:e1a608bb55e8 1125 DCISW. Invalidate by Set/Way
jamesadevine 0:e1a608bb55e8 1126 */
jamesadevine 0:e1a608bb55e8 1127
jamesadevine 0:e1a608bb55e8 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
jamesadevine 0:e1a608bb55e8 1129 __v7_all_cache(0);
jamesadevine 0:e1a608bb55e8 1130 }
jamesadevine 0:e1a608bb55e8 1131
jamesadevine 0:e1a608bb55e8 1132 /** \brief Clean the whole D$
jamesadevine 0:e1a608bb55e8 1133
jamesadevine 0:e1a608bb55e8 1134 DCCSW. Clean by Set/Way
jamesadevine 0:e1a608bb55e8 1135 */
jamesadevine 0:e1a608bb55e8 1136
jamesadevine 0:e1a608bb55e8 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
jamesadevine 0:e1a608bb55e8 1138 __v7_all_cache(1);
jamesadevine 0:e1a608bb55e8 1139 }
jamesadevine 0:e1a608bb55e8 1140
jamesadevine 0:e1a608bb55e8 1141 /** \brief Clean and invalidate the whole D$
jamesadevine 0:e1a608bb55e8 1142
jamesadevine 0:e1a608bb55e8 1143 DCCISW. Clean and Invalidate by Set/Way
jamesadevine 0:e1a608bb55e8 1144 */
jamesadevine 0:e1a608bb55e8 1145
jamesadevine 0:e1a608bb55e8 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jamesadevine 0:e1a608bb55e8 1147 __v7_all_cache(2);
jamesadevine 0:e1a608bb55e8 1148 }
jamesadevine 0:e1a608bb55e8 1149
jamesadevine 0:e1a608bb55e8 1150 #include "core_ca_mmu.h"
jamesadevine 0:e1a608bb55e8 1151
jamesadevine 0:e1a608bb55e8 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
jamesadevine 0:e1a608bb55e8 1153
jamesadevine 0:e1a608bb55e8 1154 #error TASKING Compiler support not implemented for Cortex-A
jamesadevine 0:e1a608bb55e8 1155
jamesadevine 0:e1a608bb55e8 1156 #endif
jamesadevine 0:e1a608bb55e8 1157
jamesadevine 0:e1a608bb55e8 1158 /*@} end of CMSIS_Core_RegAccFunctions */
jamesadevine 0:e1a608bb55e8 1159
jamesadevine 0:e1a608bb55e8 1160
jamesadevine 0:e1a608bb55e8 1161 #endif /* __CORE_CAFUNC_H__ */