La Suno / Mbed 2 deprecated afero_poc15_180403

I2C hang recover function added

Dependencies:   UniGraphic mbed vt100

In this version, check_i2c_pins function was added in edge_mgr.cpp.

プログラムの起動時、I2Cモジュールを初期化する前に、I2Cに使用するピンの電位を確認し
もし一方でも Low に張り付いていた場合、SCL を GPIO 出力に設定して　
所定回数 (I2C_UNLOCK_TRIAL_CYCLE) 反転させることにより、疑似リセットクロックを生成します。

その後は、通常の起動手順に復帰し、以降はこれまでと同様の動作をします。

edge_utils/edge_reset_mgr.cpp@0:d895cd1cd897, 2018-04-03 (annotated)

Committer:
Rhyme
Date:
Tue Apr 03 08:30:29 2018 +0000
Revision:
0:d895cd1cd897
Initial I2C Pin force reset function added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:d895cd1cd897 1 #include "mbed.h"
Rhyme 0:d895cd1cd897 2 #include "edge_reset_mgr.h"
Rhyme 0:d895cd1cd897 3
Rhyme 0:d895cd1cd897 4 /**
Rhyme 0:d895cd1cd897 5 * System Reset Status Register 0 (RCM_SRS0) 0x4007_F000
Rhyme 0:d895cd1cd897 6 *
Rhyme 0:d895cd1cd897 7 * bit[7] : POR Power-On Reset
Rhyme 0:d895cd1cd897 8 * bit[6] : PIN External Reset Pin
Rhyme 0:d895cd1cd897 9 * bit[5] : WDOG Watchdog
Rhyme 0:d895cd1cd897 10 * bit[4] : (Reserved)
Rhyme 0:d895cd1cd897 11 * bit[3] : LOL Loss-of-Lock Reset
Rhyme 0:d895cd1cd897 12 * bit[2] : LOC Loss-of-Clock Reset
Rhyme 0:d895cd1cd897 13 * bit[1] : LVD Low-Voltage Detect Reset
Rhyme 0:d895cd1cd897 14 * bit[0] : WAKEUP Low Leakage Wakeup Reset
Rhyme 0:d895cd1cd897 15 */
Rhyme 0:d895cd1cd897 16 #define REG_RCM_SRS0 (uint8_t *)0x4007F000
Rhyme 0:d895cd1cd897 17 #define POR_RESET_BIT 0x80
Rhyme 0:d895cd1cd897 18 #define PIN_RESET_BIT 0x40
Rhyme 0:d895cd1cd897 19 #define WDG_RESET_BIT 0x20
Rhyme 0:d895cd1cd897 20 #define LOL_RESET_BIT 0x08
Rhyme 0:d895cd1cd897 21 #define LOC_RESET_BIT 0x04
Rhyme 0:d895cd1cd897 22 #define LVD_RESET_BIT 0x02
Rhyme 0:d895cd1cd897 23 #define WUP_RESET_BIT 0x01
Rhyme 0:d895cd1cd897 24
Rhyme 0:d895cd1cd897 25 /**
Rhyme 0:d895cd1cd897 26 * System Reset Status Register 1 (RCM_SRS1) 0x4007_F001
Rhyme 0:d895cd1cd897 27 *
Rhyme 0:d895cd1cd897 28 * bit[7:6] (Reserved)
Rhyme 0:d895cd1cd897 29 * bit[5] : SACKERR Stop Mode Acknowledge Error Reset
Rhyme 0:d895cd1cd897 30 * bit[4] : (Reserved)
Rhyme 0:d895cd1cd897 31 * bit[3] : MDM_AP MDM-AP System Reset Request
Rhyme 0:d895cd1cd897 32 * bit[2] : SW Software Reset
Rhyme 0:d895cd1cd897 33 * bit[1] : LOCKUP Core Lockup
Rhyme 0:d895cd1cd897 34 * bit[0] : (Reserved)
Rhyme 0:d895cd1cd897 35 */
Rhyme 0:d895cd1cd897 36 #define REG_RCM_SRS1 (uint8_t *)0x4007F001
Rhyme 0:d895cd1cd897 37 #define SACK_RESET_BIT 0x20
Rhyme 0:d895cd1cd897 38 #define MDM_RESET_BIT 0x08
Rhyme 0:d895cd1cd897 39 #define SW_RESET_BIT 0x04
Rhyme 0:d895cd1cd897 40 #define LOCKUP_RESET_BIT 0x02
Rhyme 0:d895cd1cd897 41
Rhyme 0:d895cd1cd897 42 #define IDX_POR_RESET 0
Rhyme 0:d895cd1cd897 43 #define IDX_PIN_RESET 1
Rhyme 0:d895cd1cd897 44 #define IDX_WDG_RESET 2
Rhyme 0:d895cd1cd897 45 #define IDX_LOL_RESET 3
Rhyme 0:d895cd1cd897 46 #define IDX_LOC_RESET 4
Rhyme 0:d895cd1cd897 47 #define IDX_LVD_RESET 5
Rhyme 0:d895cd1cd897 48 #define IDX_WUP_RESET 6
Rhyme 0:d895cd1cd897 49 #define IDX_SACK_RESET 7
Rhyme 0:d895cd1cd897 50 #define IDX_MDM_RESET 8
Rhyme 0:d895cd1cd897 51 #define IDX_SW_RESET 9
Rhyme 0:d895cd1cd897 52 #define IDX_LOCKUP_RESET 10
Rhyme 0:d895cd1cd897 53
Rhyme 0:d895cd1cd897 54 const char *reset_reason[] = {
Rhyme 0:d895cd1cd897 55 "Power On Reset",
Rhyme 0:d895cd1cd897 56 "Reset Pin Asserted",
Rhyme 0:d895cd1cd897 57 "Watch Dog Reset",
Rhyme 0:d895cd1cd897 58 "Loss of Lock Reset",
Rhyme 0:d895cd1cd897 59 "Loss of Clock Reset",
Rhyme 0:d895cd1cd897 60 "Low Voltage Detect Reset",
Rhyme 0:d895cd1cd897 61 "Low Leakage Wakeup Reset",
Rhyme 0:d895cd1cd897 62 "Stop Mode Acknowledge Error Reset",
Rhyme 0:d895cd1cd897 63 "MDM-AP System Reset Request",
Rhyme 0:d895cd1cd897 64 "Software Reset",
Rhyme 0:d895cd1cd897 65 "Core Lockup Reset",
Rhyme 0:d895cd1cd897 66 0
Rhyme 0:d895cd1cd897 67 } ;
Rhyme 0:d895cd1cd897 68
Rhyme 0:d895cd1cd897 69 void print_reset_reason(void)
Rhyme 0:d895cd1cd897 70 {
Rhyme 0:d895cd1cd897 71 extern char *reset_reason_str ;
Rhyme 0:d895cd1cd897 72 int idx = 0 ;
Rhyme 0:d895cd1cd897 73 uint8_t *data = REG_RCM_SRS0 ;
Rhyme 0:d895cd1cd897 74 if (*data & POR_RESET_BIT) {
Rhyme 0:d895cd1cd897 75 idx = IDX_POR_RESET ;
Rhyme 0:d895cd1cd897 76 }
Rhyme 0:d895cd1cd897 77 if (*data & PIN_RESET_BIT) {
Rhyme 0:d895cd1cd897 78 idx = IDX_PIN_RESET ;
Rhyme 0:d895cd1cd897 79 }
Rhyme 0:d895cd1cd897 80 if (*data & WDG_RESET_BIT) {
Rhyme 0:d895cd1cd897 81 idx = IDX_WDG_RESET ;
Rhyme 0:d895cd1cd897 82 }
Rhyme 0:d895cd1cd897 83 if (*data & LOL_RESET_BIT) {
Rhyme 0:d895cd1cd897 84 idx = IDX_LOL_RESET ;
Rhyme 0:d895cd1cd897 85 }
Rhyme 0:d895cd1cd897 86 if (*data & LVD_RESET_BIT) {
Rhyme 0:d895cd1cd897 87 idx = IDX_LVD_RESET ;
Rhyme 0:d895cd1cd897 88 }
Rhyme 0:d895cd1cd897 89 if (*data & LOC_RESET_BIT) {
Rhyme 0:d895cd1cd897 90 idx = IDX_LOC_RESET ;
Rhyme 0:d895cd1cd897 91 }
Rhyme 0:d895cd1cd897 92 if (*data & WUP_RESET_BIT) {
Rhyme 0:d895cd1cd897 93 idx = IDX_WUP_RESET ;
Rhyme 0:d895cd1cd897 94 }
Rhyme 0:d895cd1cd897 95 data = REG_RCM_SRS1 ;
Rhyme 0:d895cd1cd897 96 if (*data & SACK_RESET_BIT) {
Rhyme 0:d895cd1cd897 97 idx = IDX_SACK_RESET ;
Rhyme 0:d895cd1cd897 98 }
Rhyme 0:d895cd1cd897 99 if (*data & MDM_RESET_BIT) {
Rhyme 0:d895cd1cd897 100 idx = IDX_MDM_RESET ;
Rhyme 0:d895cd1cd897 101 }
Rhyme 0:d895cd1cd897 102 if (*data & SW_RESET_BIT) {
Rhyme 0:d895cd1cd897 103 idx = IDX_SW_RESET ;
Rhyme 0:d895cd1cd897 104 }
Rhyme 0:d895cd1cd897 105 if (*data & LOCKUP_RESET_BIT) {
Rhyme 0:d895cd1cd897 106 idx = IDX_LOCKUP_RESET ;
Rhyme 0:d895cd1cd897 107 }
Rhyme 0:d895cd1cd897 108 printf("%s\n", reset_reason[idx]) ;
Rhyme 0:d895cd1cd897 109 reset_reason_str = (char *)reset_reason[idx] ;
Rhyme 0:d895cd1cd897 110 }
Rhyme 0:d895cd1cd897 111
Rhyme 0:d895cd1cd897 112 /**
Rhyme 0:d895cd1cd897 113 * Software Reset
Rhyme 0:d895cd1cd897 114 *
Rhyme 0:d895cd1cd897 115 * From Cortex-M0 Devices Generic User Guide
Rhyme 0:d895cd1cd897 116 * 4.3.4 Application Interrupt and Reset Control Register
Rhyme 0:d895cd1cd897 117 *
Rhyme 0:d895cd1cd897 118 * Bit[31:16] : VECTCKEY
Rhyme 0:d895cd1cd897 119 * Bit[15] : ENDIANESS
Rhyme 0:d895cd1cd897 120 * Bit[14:3] : (Reserved)
Rhyme 0:d895cd1cd897 121 * Bit[2] : SYSRESETREQ
Rhyme 0:d895cd1cd897 122 * Bit[1] : VECTCLRACTIVE (reserved for debug use)
Rhyme 0:d895cd1cd897 123 * Bit[0] : (Reserved)
Rhyme 0:d895cd1cd897 124 *
Rhyme 0:d895cd1cd897 125 * Note: To trigger software reset, both VECTKEY=0x05FA and SYSRESETREQ
Rhyme 0:d895cd1cd897 126 * must be written at once, therefore the value will be
Rhyme 0:d895cd1cd897 127 * 0x05FA0004
Rhyme 0:d895cd1cd897 128 */
Rhyme 0:d895cd1cd897 129
Rhyme 0:d895cd1cd897 130 void software_reset(void)
Rhyme 0:d895cd1cd897 131 {
Rhyme 0:d895cd1cd897 132 SCB->AIRCR = 0x05FA0004 ;
Rhyme 0:d895cd1cd897 133 }
Rhyme 0:d895cd1cd897 134
Rhyme 0:d895cd1cd897 135 /**
Rhyme 0:d895cd1cd897 136 * reset_watch_dog
Rhyme 0:d895cd1cd897 137 * reset the watch dog counter
Rhyme 0:d895cd1cd897 138 * this function must be called within the limit (1sec)
Rhyme 0:d895cd1cd897 139 */
Rhyme 0:d895cd1cd897 140
Rhyme 0:d895cd1cd897 141 void reset_watch_dog(void)
Rhyme 0:d895cd1cd897 142 {
Rhyme 0:d895cd1cd897 143 SIM->SRVCOP = (uint32_t)0x55u;
Rhyme 0:d895cd1cd897 144 SIM->SRVCOP = (uint32_t)0xAAu;
Rhyme 0:d895cd1cd897 145 }