La Suno / Mbed 2 deprecated afero_poc15_180302

Release candidate version. The pointer in GAS Pressure display is changed to a triangle.

Dependencies:   UniGraphic mbed vt100

Please note, at 2-Mar-2018 the current version of mbed-lib has a defect in Ticker.
https://os.mbed.com/forum/bugs-suggestions/topic/29287/

So, mbed lib version 157 is intentionally being used.
Please do not update mbed library until the problem in the above URL is fixed.

In this version, format of GAS Pressure Display has been changed.
/media/uploads/Rhyme/low.jpg

/media/uploads/Rhyme/good.jpg

/media/uploads/Rhyme/high.jpg

moto

edge_utils/KL25Z_SystemInit.c@0:774324cbc5a6, 2018-03-02 (annotated)

Committer:
Rhyme
Date:
Fri Mar 02 07:56:09 2018 +0000
Revision:
0:774324cbc5a6
Release candidate version. GAS Pressure pointer is now a triangle.; Some source file clean-up was done.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:774324cbc5a6 1 #if defined (TARGET_KL25Z)
Rhyme 0:774324cbc5a6 2 /*
Rhyme 0:774324cbc5a6 3 ** ###################################################################
Rhyme 0:774324cbc5a6 4 ** Processor: MKL25Z128VLK4
Rhyme 0:774324cbc5a6 5 ** Compilers: ARM Compiler
Rhyme 0:774324cbc5a6 6 ** Freescale C/C++ for Embedded ARM
Rhyme 0:774324cbc5a6 7 ** GNU C Compiler
Rhyme 0:774324cbc5a6 8 ** IAR ANSI C/C++ Compiler for ARM
Rhyme 0:774324cbc5a6 9 **
Rhyme 0:774324cbc5a6 10 ** Reference manual: KL25RM, Rev.1, Jun 2012
Rhyme 0:774324cbc5a6 11 ** Version: rev. 1.1, 2012-06-21
Rhyme 0:774324cbc5a6 12 **
Rhyme 0:774324cbc5a6 13 ** Abstract:
Rhyme 0:774324cbc5a6 14 ** Provides a system configuration function and a global variable that
Rhyme 0:774324cbc5a6 15 ** contains the system frequency. It configures the device and initializes
Rhyme 0:774324cbc5a6 16 ** the oscillator (PLL) that is part of the microcontroller device.
Rhyme 0:774324cbc5a6 17 **
Rhyme 0:774324cbc5a6 18 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
Rhyme 0:774324cbc5a6 19 **
Rhyme 0:774324cbc5a6 20 ** http: www.freescale.com
Rhyme 0:774324cbc5a6 21 ** mail: support@freescale.com
Rhyme 0:774324cbc5a6 22 **
Rhyme 0:774324cbc5a6 23 ** Revisions:
Rhyme 0:774324cbc5a6 24 ** - rev. 1.0 (2012-06-13)
Rhyme 0:774324cbc5a6 25 ** Initial version.
Rhyme 0:774324cbc5a6 26 ** - rev. 1.1 (2012-06-21)
Rhyme 0:774324cbc5a6 27 ** Update according to reference manual rev. 1.
Rhyme 0:774324cbc5a6 28 **
Rhyme 0:774324cbc5a6 29 ** ###################################################################
Rhyme 0:774324cbc5a6 30 */
Rhyme 0:774324cbc5a6 31
Rhyme 0:774324cbc5a6 32 /**
Rhyme 0:774324cbc5a6 33 * @file MKL25Z4
Rhyme 0:774324cbc5a6 34 * @version 1.1
Rhyme 0:774324cbc5a6 35 * @date 2012-06-21
Rhyme 0:774324cbc5a6 36 * @brief Device specific configuration file for MKL25Z4 (implementation file)
Rhyme 0:774324cbc5a6 37 *
Rhyme 0:774324cbc5a6 38 * Provides a system configuration function and a global variable that contains
Rhyme 0:774324cbc5a6 39 * the system frequency. It configures the device and initializes the oscillator
Rhyme 0:774324cbc5a6 40 * (PLL) that is part of the microcontroller device.
Rhyme 0:774324cbc5a6 41 */
Rhyme 0:774324cbc5a6 42
Rhyme 0:774324cbc5a6 43 #include <stdint.h>
Rhyme 0:774324cbc5a6 44 #include "MKL25Z4.h"
Rhyme 0:774324cbc5a6 45
Rhyme 0:774324cbc5a6 46 //MODIFICATION: We DO want watchdog, uC default after reset is enabled with timeout=1024ms (2^10*LPO=1KHz)
Rhyme 0:774324cbc5a6 47 //#define DISABLE_WDOG 1
Rhyme 0:774324cbc5a6 48
Rhyme 0:774324cbc5a6 49 #define CLOCK_SETUP 1
Rhyme 0:774324cbc5a6 50 /* Predefined clock setups
Rhyme 0:774324cbc5a6 51 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Rhyme 0:774324cbc5a6 52 Reference clock source for MCG module is the slow internal clock source 32.768kHz
Rhyme 0:774324cbc5a6 53 Core clock = 41.94MHz, BusClock = 13.98MHz
Rhyme 0:774324cbc5a6 54 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Rhyme 0:774324cbc5a6 55 Reference clock source for MCG module is an external crystal 8MHz
Rhyme 0:774324cbc5a6 56 Core clock = 48MHz, BusClock = 24MHz
Rhyme 0:774324cbc5a6 57 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Rhyme 0:774324cbc5a6 58 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Rhyme 0:774324cbc5a6 59 Core clock = 8MHz, BusClock = 8MHz
Rhyme 0:774324cbc5a6 60 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
Rhyme 0:774324cbc5a6 61 Reference clock source for MCG module is an external crystal 32.768kHz
Rhyme 0:774324cbc5a6 62 Core clock = 47.97MHz, BusClock = 23.98MHz
Rhyme 0:774324cbc5a6 63 This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
Rhyme 0:774324cbc5a6 64 RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
Rhyme 0:774324cbc5a6 65 accuracy durring the reset period. RTC will reset on power down.
Rhyme 0:774324cbc5a6 66 */
Rhyme 0:774324cbc5a6 67
Rhyme 0:774324cbc5a6 68 /*----------------------------------------------------------------------------
Rhyme 0:774324cbc5a6 69 Define clock source values
Rhyme 0:774324cbc5a6 70 *----------------------------------------------------------------------------*/
Rhyme 0:774324cbc5a6 71 #if (CLOCK_SETUP == 0)
Rhyme 0:774324cbc5a6 72 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 73 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 74 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 75 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
Rhyme 0:774324cbc5a6 76 #elif (CLOCK_SETUP == 1)
Rhyme 0:774324cbc5a6 77 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 78 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 79 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 80 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
Rhyme 0:774324cbc5a6 81 #elif (CLOCK_SETUP == 2)
Rhyme 0:774324cbc5a6 82 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 83 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 84 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 85 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
Rhyme 0:774324cbc5a6 86 #elif (CLOCK_SETUP == 3)
Rhyme 0:774324cbc5a6 87 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 88 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 89 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:774324cbc5a6 90 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
Rhyme 0:774324cbc5a6 91 #endif /* (CLOCK_SETUP == 3) */
Rhyme 0:774324cbc5a6 92
Rhyme 0:774324cbc5a6 93 /* ----------------------------------------------------------------------------
Rhyme 0:774324cbc5a6 94 -- Core clock
Rhyme 0:774324cbc5a6 95 ---------------------------------------------------------------------------- */
Rhyme 0:774324cbc5a6 96
Rhyme 0:774324cbc5a6 97 //MODIFICATION: That vartiable already exists
Rhyme 0:774324cbc5a6 98 // uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
Rhyme 0:774324cbc5a6 99
Rhyme 0:774324cbc5a6 100 /* ----------------------------------------------------------------------------
Rhyme 0:774324cbc5a6 101 -- SystemInit()
Rhyme 0:774324cbc5a6 102 ---------------------------------------------------------------------------- */
Rhyme 0:774324cbc5a6 103
Rhyme 0:774324cbc5a6 104 void $Sub$$SystemInit (void) {
Rhyme 0:774324cbc5a6 105
Rhyme 0:774324cbc5a6 106 //MODIFICATION:
Rhyme 0:774324cbc5a6 107 // That variable already exists, we set it here
Rhyme 0:774324cbc5a6 108 SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
Rhyme 0:774324cbc5a6 109 // We want visual indication of boot time with red LED on
Rhyme 0:774324cbc5a6 110 //TODO
Rhyme 0:774324cbc5a6 111
Rhyme 0:774324cbc5a6 112 #if (DISABLE_WDOG)
Rhyme 0:774324cbc5a6 113 /* Disable the WDOG module */
Rhyme 0:774324cbc5a6 114 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
Rhyme 0:774324cbc5a6 115 SIM->COPC = (uint32_t)0x00u;
Rhyme 0:774324cbc5a6 116 #endif /* (DISABLE_WDOG) */
Rhyme 0:774324cbc5a6 117 #if (CLOCK_SETUP == 0)
Rhyme 0:774324cbc5a6 118 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:774324cbc5a6 119 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
Rhyme 0:774324cbc5a6 120 /* Switch to FEI Mode */
Rhyme 0:774324cbc5a6 121 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:774324cbc5a6 122 MCG->C1 = (uint8_t)0x06U;
Rhyme 0:774324cbc5a6 123 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
Rhyme 0:774324cbc5a6 124 MCG->C2 = (uint8_t)0x00U;
Rhyme 0:774324cbc5a6 125 /* MCG->C4: DMX32=0,DRST_DRS=1 */
Rhyme 0:774324cbc5a6 126 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
Rhyme 0:774324cbc5a6 127 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Rhyme 0:774324cbc5a6 128 OSC0->CR = (uint8_t)0x80U;
Rhyme 0:774324cbc5a6 129 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Rhyme 0:774324cbc5a6 130 MCG->C5 = (uint8_t)0x00U;
Rhyme 0:774324cbc5a6 131 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Rhyme 0:774324cbc5a6 132 MCG->C6 = (uint8_t)0x00U;
Rhyme 0:774324cbc5a6 133 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
Rhyme 0:774324cbc5a6 134 }
Rhyme 0:774324cbc5a6 135 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
Rhyme 0:774324cbc5a6 136 }
Rhyme 0:774324cbc5a6 137 #elif (CLOCK_SETUP == 1)
Rhyme 0:774324cbc5a6 138 /* SIM->SCGC5: PORTA=1 */
Rhyme 0:774324cbc5a6 139 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
Rhyme 0:774324cbc5a6 140 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:774324cbc5a6 141 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
Rhyme 0:774324cbc5a6 142 /* PORTA->PCR18: ISF=0,MUX=0 */
Rhyme 0:774324cbc5a6 143 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
Rhyme 0:774324cbc5a6 144 /* PORTA->PCR19: ISF=0,MUX=0 */
Rhyme 0:774324cbc5a6 145 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
Rhyme 0:774324cbc5a6 146 /* Switch to FBE Mode */
Rhyme 0:774324cbc5a6 147 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
Rhyme 0:774324cbc5a6 148 OSC0->CR = (uint8_t)0x89U;
Rhyme 0:774324cbc5a6 149 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
Rhyme 0:774324cbc5a6 150 MCG->C2 = (uint8_t)0x24U;
Rhyme 0:774324cbc5a6 151 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:774324cbc5a6 152 MCG->C1 = (uint8_t)0x9AU;
Rhyme 0:774324cbc5a6 153 /* MCG->C4: DMX32=0,DRST_DRS=0 */
Rhyme 0:774324cbc5a6 154 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
Rhyme 0:774324cbc5a6 155 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
Rhyme 0:774324cbc5a6 156 MCG->C5 = (uint8_t)0x01U;
Rhyme 0:774324cbc5a6 157 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Rhyme 0:774324cbc5a6 158 MCG->C6 = (uint8_t)0x00U;
Rhyme 0:774324cbc5a6 159 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
Rhyme 0:774324cbc5a6 160 }
Rhyme 0:774324cbc5a6 161 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:774324cbc5a6 162 }
Rhyme 0:774324cbc5a6 163 /* Switch to PBE Mode */
Rhyme 0:774324cbc5a6 164 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
Rhyme 0:774324cbc5a6 165 MCG->C6 = (uint8_t)0x40U;
Rhyme 0:774324cbc5a6 166 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:774324cbc5a6 167 }
Rhyme 0:774324cbc5a6 168 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
Rhyme 0:774324cbc5a6 169 }
Rhyme 0:774324cbc5a6 170 /* Switch to PEE Mode */
Rhyme 0:774324cbc5a6 171 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:774324cbc5a6 172 MCG->C1 = (uint8_t)0x1AU;
Rhyme 0:774324cbc5a6 173 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
Rhyme 0:774324cbc5a6 174 }
Rhyme 0:774324cbc5a6 175 #elif (CLOCK_SETUP == 2)
Rhyme 0:774324cbc5a6 176 /* SIM->SCGC5: PORTA=1 */
Rhyme 0:774324cbc5a6 177 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
Rhyme 0:774324cbc5a6 178 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:774324cbc5a6 179 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
Rhyme 0:774324cbc5a6 180 /* PORTA->PCR18: ISF=0,MUX=0 */
Rhyme 0:774324cbc5a6 181 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
Rhyme 0:774324cbc5a6 182 /* PORTA->PCR19: ISF=0,MUX=0 */
Rhyme 0:774324cbc5a6 183 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
Rhyme 0:774324cbc5a6 184 /* Switch to FBE Mode */
Rhyme 0:774324cbc5a6 185 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
Rhyme 0:774324cbc5a6 186 OSC0->CR = (uint8_t)0x89U;
Rhyme 0:774324cbc5a6 187 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
Rhyme 0:774324cbc5a6 188 MCG->C2 = (uint8_t)0x24U;
Rhyme 0:774324cbc5a6 189 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:774324cbc5a6 190 MCG->C1 = (uint8_t)0x9AU;
Rhyme 0:774324cbc5a6 191 /* MCG->C4: DMX32=0,DRST_DRS=0 */
Rhyme 0:774324cbc5a6 192 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
Rhyme 0:774324cbc5a6 193 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Rhyme 0:774324cbc5a6 194 MCG->C5 = (uint8_t)0x00U;
Rhyme 0:774324cbc5a6 195 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Rhyme 0:774324cbc5a6 196 MCG->C6 = (uint8_t)0x00U;
Rhyme 0:774324cbc5a6 197 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
Rhyme 0:774324cbc5a6 198 }
Rhyme 0:774324cbc5a6 199 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:774324cbc5a6 200 }
Rhyme 0:774324cbc5a6 201 /* Switch to BLPE Mode */
Rhyme 0:774324cbc5a6 202 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
Rhyme 0:774324cbc5a6 203 MCG->C2 = (uint8_t)0x26U;
Rhyme 0:774324cbc5a6 204 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:774324cbc5a6 205 }
Rhyme 0:774324cbc5a6 206 #elif (CLOCK_SETUP == 3)
Rhyme 0:774324cbc5a6 207 /* SIM->SCGC5: PORTA=1 */
Rhyme 0:774324cbc5a6 208 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
Rhyme 0:774324cbc5a6 209 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:774324cbc5a6 210 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
Rhyme 0:774324cbc5a6 211 /* PORTA->PCR[3]: ISF=0,MUX=0 */
Rhyme 0:774324cbc5a6 212 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
Rhyme 0:774324cbc5a6 213 /* PORTA->PCR[4]: ISF=0,MUX=0 */
Rhyme 0:774324cbc5a6 214 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
Rhyme 0:774324cbc5a6 215 /* Switch to FEE Mode */
Rhyme 0:774324cbc5a6 216 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
Rhyme 0:774324cbc5a6 217 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
Rhyme 0:774324cbc5a6 218 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Rhyme 0:774324cbc5a6 219 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
Rhyme 0:774324cbc5a6 220 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:774324cbc5a6 221 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
Rhyme 0:774324cbc5a6 222 /* MCG->C4: DMX32=1,DRST_DRS=1 */
Rhyme 0:774324cbc5a6 223 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
Rhyme 0:774324cbc5a6 224 MCG_C4_DRST_DRS(0x02)
Rhyme 0:774324cbc5a6 225 )) | (uint8_t)(
Rhyme 0:774324cbc5a6 226 MCG_C4_DMX32_MASK |
Rhyme 0:774324cbc5a6 227 MCG_C4_DRST_DRS(0x01)
Rhyme 0:774324cbc5a6 228 ));
Rhyme 0:774324cbc5a6 229 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
Rhyme 0:774324cbc5a6 230 }
Rhyme 0:774324cbc5a6 231 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
Rhyme 0:774324cbc5a6 232 }
Rhyme 0:774324cbc5a6 233 #endif /* (CLOCK_SETUP == 3) */
Rhyme 0:774324cbc5a6 234 }
Rhyme 0:774324cbc5a6 235 #endif // TARGET_KL25Z