La Suno / Mbed 2 deprecated afero_poc15_180223

Color sensor reset at the end of calibration added. sensor id auto assignment was changed to be a fixed value assignment to avoid sensor id shift when some sensor is absent.

Dependencies:   UniGraphic mbed vt100

edge_utils/edge_reset_mgr.cpp@0:ce97f6d34336, 2018-02-23 (annotated)

Committer:
Rhyme
Date:
Fri Feb 23 05:40:22 2018 +0000
Revision:
0:ce97f6d34336
color sensor reset was added at the end of calibration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:ce97f6d34336 1 #include "mbed.h"
Rhyme 0:ce97f6d34336 2 #include "edge_reset_mgr.h"
Rhyme 0:ce97f6d34336 3
Rhyme 0:ce97f6d34336 4 /**
Rhyme 0:ce97f6d34336 5 * System Reset Status Register 0 (RCM_SRS0) 0x4007_F000
Rhyme 0:ce97f6d34336 6 *
Rhyme 0:ce97f6d34336 7 * bit[7] : POR Power-On Reset
Rhyme 0:ce97f6d34336 8 * bit[6] : PIN External Reset Pin
Rhyme 0:ce97f6d34336 9 * bit[5] : WDOG Watchdog
Rhyme 0:ce97f6d34336 10 * bit[4] : (Reserved)
Rhyme 0:ce97f6d34336 11 * bit[3] : LOL Loss-of-Lock Reset
Rhyme 0:ce97f6d34336 12 * bit[2] : LOC Loss-of-Clock Reset
Rhyme 0:ce97f6d34336 13 * bit[1] : LVD Low-Voltage Detect Reset
Rhyme 0:ce97f6d34336 14 * bit[0] : WAKEUP Low Leakage Wakeup Reset
Rhyme 0:ce97f6d34336 15 */
Rhyme 0:ce97f6d34336 16 #define REG_RCM_SRS0 (uint8_t *)0x4007F000
Rhyme 0:ce97f6d34336 17 #define POR_RESET_BIT 0x80
Rhyme 0:ce97f6d34336 18 #define PIN_RESET_BIT 0x40
Rhyme 0:ce97f6d34336 19 #define WDG_RESET_BIT 0x20
Rhyme 0:ce97f6d34336 20 #define LOL_RESET_BIT 0x08
Rhyme 0:ce97f6d34336 21 #define LOC_RESET_BIT 0x04
Rhyme 0:ce97f6d34336 22 #define LVD_RESET_BIT 0x02
Rhyme 0:ce97f6d34336 23 #define WUP_RESET_BIT 0x01
Rhyme 0:ce97f6d34336 24
Rhyme 0:ce97f6d34336 25 /**
Rhyme 0:ce97f6d34336 26 * System Reset Status Register 1 (RCM_SRS1) 0x4007_F001
Rhyme 0:ce97f6d34336 27 *
Rhyme 0:ce97f6d34336 28 * bit[7:6] (Reserved)
Rhyme 0:ce97f6d34336 29 * bit[5] : SACKERR Stop Mode Acknowledge Error Reset
Rhyme 0:ce97f6d34336 30 * bit[4] : (Reserved)
Rhyme 0:ce97f6d34336 31 * bit[3] : MDM_AP MDM-AP System Reset Request
Rhyme 0:ce97f6d34336 32 * bit[2] : SW Software Reset
Rhyme 0:ce97f6d34336 33 * bit[1] : LOCKUP Core Lockup
Rhyme 0:ce97f6d34336 34 * bit[0] : (Reserved)
Rhyme 0:ce97f6d34336 35 */
Rhyme 0:ce97f6d34336 36 #define REG_RCM_SRS1 (uint8_t *)0x4007F001
Rhyme 0:ce97f6d34336 37 #define SACK_RESET_BIT 0x20
Rhyme 0:ce97f6d34336 38 #define MDM_RESET_BIT 0x08
Rhyme 0:ce97f6d34336 39 #define SW_RESET_BIT 0x04
Rhyme 0:ce97f6d34336 40 #define LOCKUP_RESET_BIT 0x02
Rhyme 0:ce97f6d34336 41
Rhyme 0:ce97f6d34336 42 #define IDX_POR_RESET 0
Rhyme 0:ce97f6d34336 43 #define IDX_PIN_RESET 1
Rhyme 0:ce97f6d34336 44 #define IDX_WDG_RESET 2
Rhyme 0:ce97f6d34336 45 #define IDX_LOL_RESET 3
Rhyme 0:ce97f6d34336 46 #define IDX_LOC_RESET 4
Rhyme 0:ce97f6d34336 47 #define IDX_LVD_RESET 5
Rhyme 0:ce97f6d34336 48 #define IDX_WUP_RESET 6
Rhyme 0:ce97f6d34336 49 #define IDX_SACK_RESET 7
Rhyme 0:ce97f6d34336 50 #define IDX_MDM_RESET 8
Rhyme 0:ce97f6d34336 51 #define IDX_SW_RESET 9
Rhyme 0:ce97f6d34336 52 #define IDX_LOCKUP_RESET 10
Rhyme 0:ce97f6d34336 53
Rhyme 0:ce97f6d34336 54 const char *reset_reason[] = {
Rhyme 0:ce97f6d34336 55 "Power On Reset",
Rhyme 0:ce97f6d34336 56 "Reset Pin Asserted",
Rhyme 0:ce97f6d34336 57 "Watch Dog Reset",
Rhyme 0:ce97f6d34336 58 "Loss of Lock Reset",
Rhyme 0:ce97f6d34336 59 "Loss of Clock Reset",
Rhyme 0:ce97f6d34336 60 "Low Voltage Detect Reset",
Rhyme 0:ce97f6d34336 61 "Low Leakage Wakeup Reset",
Rhyme 0:ce97f6d34336 62 "Stop Mode Acknowledge Error Reset",
Rhyme 0:ce97f6d34336 63 "MDM-AP System Reset Request",
Rhyme 0:ce97f6d34336 64 "Software Reset",
Rhyme 0:ce97f6d34336 65 "Core Lockup Reset",
Rhyme 0:ce97f6d34336 66 0
Rhyme 0:ce97f6d34336 67 } ;
Rhyme 0:ce97f6d34336 68
Rhyme 0:ce97f6d34336 69 void print_reset_reason(void)
Rhyme 0:ce97f6d34336 70 {
Rhyme 0:ce97f6d34336 71 extern char *reset_reason_str ;
Rhyme 0:ce97f6d34336 72 int idx = 0 ;
Rhyme 0:ce97f6d34336 73 uint8_t *data = REG_RCM_SRS0 ;
Rhyme 0:ce97f6d34336 74 if (*data & POR_RESET_BIT) {
Rhyme 0:ce97f6d34336 75 idx = IDX_POR_RESET ;
Rhyme 0:ce97f6d34336 76 }
Rhyme 0:ce97f6d34336 77 if (*data & PIN_RESET_BIT) {
Rhyme 0:ce97f6d34336 78 idx = IDX_PIN_RESET ;
Rhyme 0:ce97f6d34336 79 }
Rhyme 0:ce97f6d34336 80 if (*data & WDG_RESET_BIT) {
Rhyme 0:ce97f6d34336 81 idx = IDX_WDG_RESET ;
Rhyme 0:ce97f6d34336 82 }
Rhyme 0:ce97f6d34336 83 if (*data & LOL_RESET_BIT) {
Rhyme 0:ce97f6d34336 84 idx = IDX_LOL_RESET ;
Rhyme 0:ce97f6d34336 85 }
Rhyme 0:ce97f6d34336 86 if (*data & LVD_RESET_BIT) {
Rhyme 0:ce97f6d34336 87 idx = IDX_LVD_RESET ;
Rhyme 0:ce97f6d34336 88 }
Rhyme 0:ce97f6d34336 89 if (*data & LOC_RESET_BIT) {
Rhyme 0:ce97f6d34336 90 idx = IDX_LOC_RESET ;
Rhyme 0:ce97f6d34336 91 }
Rhyme 0:ce97f6d34336 92 if (*data & WUP_RESET_BIT) {
Rhyme 0:ce97f6d34336 93 idx = IDX_WUP_RESET ;
Rhyme 0:ce97f6d34336 94 }
Rhyme 0:ce97f6d34336 95 data = REG_RCM_SRS1 ;
Rhyme 0:ce97f6d34336 96 if (*data & SACK_RESET_BIT) {
Rhyme 0:ce97f6d34336 97 idx = IDX_SACK_RESET ;
Rhyme 0:ce97f6d34336 98 }
Rhyme 0:ce97f6d34336 99 if (*data & MDM_RESET_BIT) {
Rhyme 0:ce97f6d34336 100 idx = IDX_MDM_RESET ;
Rhyme 0:ce97f6d34336 101 }
Rhyme 0:ce97f6d34336 102 if (*data & SW_RESET_BIT) {
Rhyme 0:ce97f6d34336 103 idx = IDX_SW_RESET ;
Rhyme 0:ce97f6d34336 104 }
Rhyme 0:ce97f6d34336 105 if (*data & LOCKUP_RESET_BIT) {
Rhyme 0:ce97f6d34336 106 idx = IDX_LOCKUP_RESET ;
Rhyme 0:ce97f6d34336 107 }
Rhyme 0:ce97f6d34336 108 printf("%s\n", reset_reason[idx]) ;
Rhyme 0:ce97f6d34336 109 reset_reason_str = (char *)reset_reason[idx] ;
Rhyme 0:ce97f6d34336 110 }
Rhyme 0:ce97f6d34336 111
Rhyme 0:ce97f6d34336 112 /**
Rhyme 0:ce97f6d34336 113 * Software Reset
Rhyme 0:ce97f6d34336 114 *
Rhyme 0:ce97f6d34336 115 * From Cortex-M0 Devices Generic User Guide
Rhyme 0:ce97f6d34336 116 * 4.3.4 Application Interrupt and Reset Control Register
Rhyme 0:ce97f6d34336 117 *
Rhyme 0:ce97f6d34336 118 * Bit[31:16] : VECTCKEY
Rhyme 0:ce97f6d34336 119 * Bit[15] : ENDIANESS
Rhyme 0:ce97f6d34336 120 * Bit[14:3] : (Reserved)
Rhyme 0:ce97f6d34336 121 * Bit[2] : SYSRESETREQ
Rhyme 0:ce97f6d34336 122 * Bit[1] : VECTCLRACTIVE (reserved for debug use)
Rhyme 0:ce97f6d34336 123 * Bit[0] : (Reserved)
Rhyme 0:ce97f6d34336 124 *
Rhyme 0:ce97f6d34336 125 * Note: To trigger software reset, both VECTKEY=0x05FA and SYSRESETREQ
Rhyme 0:ce97f6d34336 126 * must be written at once, therefore the value will be
Rhyme 0:ce97f6d34336 127 * 0x05FA0004
Rhyme 0:ce97f6d34336 128 */
Rhyme 0:ce97f6d34336 129
Rhyme 0:ce97f6d34336 130 void software_reset(void)
Rhyme 0:ce97f6d34336 131 {
Rhyme 0:ce97f6d34336 132 SCB->AIRCR = 0x05FA0004 ;
Rhyme 0:ce97f6d34336 133 }
Rhyme 0:ce97f6d34336 134
Rhyme 0:ce97f6d34336 135 /**
Rhyme 0:ce97f6d34336 136 * reset_watch_dog
Rhyme 0:ce97f6d34336 137 * reset the watch dog counter
Rhyme 0:ce97f6d34336 138 * this function must be called within the limit (1sec)
Rhyme 0:ce97f6d34336 139 */
Rhyme 0:ce97f6d34336 140
Rhyme 0:ce97f6d34336 141 void reset_watch_dog(void)
Rhyme 0:ce97f6d34336 142 {
Rhyme 0:ce97f6d34336 143 SIM->SRVCOP = (uint32_t)0x55u;
Rhyme 0:ce97f6d34336 144 SIM->SRVCOP = (uint32_t)0xAAu;
Rhyme 0:ce97f6d34336 145 }