La Suno / Mbed 2 deprecated afero_poc15_180223

Color sensor reset at the end of calibration added. sensor id auto assignment was changed to be a fixed value assignment to avoid sensor id shift when some sensor is absent.

Dependencies:   UniGraphic mbed vt100

edge_utils/KL25Z_SystemInit.c@0:ce97f6d34336, 2018-02-23 (annotated)

Committer:
Rhyme
Date:
Fri Feb 23 05:40:22 2018 +0000
Revision:
0:ce97f6d34336
color sensor reset was added at the end of calibration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:ce97f6d34336 1 #if defined (TARGET_KL25Z)
Rhyme 0:ce97f6d34336 2 /*
Rhyme 0:ce97f6d34336 3 ** ###################################################################
Rhyme 0:ce97f6d34336 4 ** Processor: MKL25Z128VLK4
Rhyme 0:ce97f6d34336 5 ** Compilers: ARM Compiler
Rhyme 0:ce97f6d34336 6 ** Freescale C/C++ for Embedded ARM
Rhyme 0:ce97f6d34336 7 ** GNU C Compiler
Rhyme 0:ce97f6d34336 8 ** IAR ANSI C/C++ Compiler for ARM
Rhyme 0:ce97f6d34336 9 **
Rhyme 0:ce97f6d34336 10 ** Reference manual: KL25RM, Rev.1, Jun 2012
Rhyme 0:ce97f6d34336 11 ** Version: rev. 1.1, 2012-06-21
Rhyme 0:ce97f6d34336 12 **
Rhyme 0:ce97f6d34336 13 ** Abstract:
Rhyme 0:ce97f6d34336 14 ** Provides a system configuration function and a global variable that
Rhyme 0:ce97f6d34336 15 ** contains the system frequency. It configures the device and initializes
Rhyme 0:ce97f6d34336 16 ** the oscillator (PLL) that is part of the microcontroller device.
Rhyme 0:ce97f6d34336 17 **
Rhyme 0:ce97f6d34336 18 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
Rhyme 0:ce97f6d34336 19 **
Rhyme 0:ce97f6d34336 20 ** http: www.freescale.com
Rhyme 0:ce97f6d34336 21 ** mail: support@freescale.com
Rhyme 0:ce97f6d34336 22 **
Rhyme 0:ce97f6d34336 23 ** Revisions:
Rhyme 0:ce97f6d34336 24 ** - rev. 1.0 (2012-06-13)
Rhyme 0:ce97f6d34336 25 ** Initial version.
Rhyme 0:ce97f6d34336 26 ** - rev. 1.1 (2012-06-21)
Rhyme 0:ce97f6d34336 27 ** Update according to reference manual rev. 1.
Rhyme 0:ce97f6d34336 28 **
Rhyme 0:ce97f6d34336 29 ** ###################################################################
Rhyme 0:ce97f6d34336 30 */
Rhyme 0:ce97f6d34336 31
Rhyme 0:ce97f6d34336 32 /**
Rhyme 0:ce97f6d34336 33 * @file MKL25Z4
Rhyme 0:ce97f6d34336 34 * @version 1.1
Rhyme 0:ce97f6d34336 35 * @date 2012-06-21
Rhyme 0:ce97f6d34336 36 * @brief Device specific configuration file for MKL25Z4 (implementation file)
Rhyme 0:ce97f6d34336 37 *
Rhyme 0:ce97f6d34336 38 * Provides a system configuration function and a global variable that contains
Rhyme 0:ce97f6d34336 39 * the system frequency. It configures the device and initializes the oscillator
Rhyme 0:ce97f6d34336 40 * (PLL) that is part of the microcontroller device.
Rhyme 0:ce97f6d34336 41 */
Rhyme 0:ce97f6d34336 42
Rhyme 0:ce97f6d34336 43 #include <stdint.h>
Rhyme 0:ce97f6d34336 44 #include "MKL25Z4.h"
Rhyme 0:ce97f6d34336 45
Rhyme 0:ce97f6d34336 46 //MODIFICATION: We DO want watchdog, uC default after reset is enabled with timeout=1024ms (2^10*LPO=1KHz)
Rhyme 0:ce97f6d34336 47 //#define DISABLE_WDOG 1
Rhyme 0:ce97f6d34336 48
Rhyme 0:ce97f6d34336 49 #define CLOCK_SETUP 1
Rhyme 0:ce97f6d34336 50 /* Predefined clock setups
Rhyme 0:ce97f6d34336 51 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Rhyme 0:ce97f6d34336 52 Reference clock source for MCG module is the slow internal clock source 32.768kHz
Rhyme 0:ce97f6d34336 53 Core clock = 41.94MHz, BusClock = 13.98MHz
Rhyme 0:ce97f6d34336 54 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Rhyme 0:ce97f6d34336 55 Reference clock source for MCG module is an external crystal 8MHz
Rhyme 0:ce97f6d34336 56 Core clock = 48MHz, BusClock = 24MHz
Rhyme 0:ce97f6d34336 57 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Rhyme 0:ce97f6d34336 58 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Rhyme 0:ce97f6d34336 59 Core clock = 8MHz, BusClock = 8MHz
Rhyme 0:ce97f6d34336 60 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
Rhyme 0:ce97f6d34336 61 Reference clock source for MCG module is an external crystal 32.768kHz
Rhyme 0:ce97f6d34336 62 Core clock = 47.97MHz, BusClock = 23.98MHz
Rhyme 0:ce97f6d34336 63 This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
Rhyme 0:ce97f6d34336 64 RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
Rhyme 0:ce97f6d34336 65 accuracy durring the reset period. RTC will reset on power down.
Rhyme 0:ce97f6d34336 66 */
Rhyme 0:ce97f6d34336 67
Rhyme 0:ce97f6d34336 68 /*----------------------------------------------------------------------------
Rhyme 0:ce97f6d34336 69 Define clock source values
Rhyme 0:ce97f6d34336 70 *----------------------------------------------------------------------------*/
Rhyme 0:ce97f6d34336 71 #if (CLOCK_SETUP == 0)
Rhyme 0:ce97f6d34336 72 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 73 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 74 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 75 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
Rhyme 0:ce97f6d34336 76 #elif (CLOCK_SETUP == 1)
Rhyme 0:ce97f6d34336 77 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 78 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 79 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 80 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
Rhyme 0:ce97f6d34336 81 #elif (CLOCK_SETUP == 2)
Rhyme 0:ce97f6d34336 82 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 83 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 84 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 85 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
Rhyme 0:ce97f6d34336 86 #elif (CLOCK_SETUP == 3)
Rhyme 0:ce97f6d34336 87 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 88 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 89 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Rhyme 0:ce97f6d34336 90 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
Rhyme 0:ce97f6d34336 91 #endif /* (CLOCK_SETUP == 3) */
Rhyme 0:ce97f6d34336 92
Rhyme 0:ce97f6d34336 93 /* ----------------------------------------------------------------------------
Rhyme 0:ce97f6d34336 94 -- Core clock
Rhyme 0:ce97f6d34336 95 ---------------------------------------------------------------------------- */
Rhyme 0:ce97f6d34336 96
Rhyme 0:ce97f6d34336 97 //MODIFICATION: That vartiable already exists
Rhyme 0:ce97f6d34336 98 // uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
Rhyme 0:ce97f6d34336 99
Rhyme 0:ce97f6d34336 100 /* ----------------------------------------------------------------------------
Rhyme 0:ce97f6d34336 101 -- SystemInit()
Rhyme 0:ce97f6d34336 102 ---------------------------------------------------------------------------- */
Rhyme 0:ce97f6d34336 103
Rhyme 0:ce97f6d34336 104 void $Sub$$SystemInit (void) {
Rhyme 0:ce97f6d34336 105
Rhyme 0:ce97f6d34336 106 //MODIFICATION:
Rhyme 0:ce97f6d34336 107 // That variable already exists, we set it here
Rhyme 0:ce97f6d34336 108 SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
Rhyme 0:ce97f6d34336 109 // We want visual indication of boot time with red LED on
Rhyme 0:ce97f6d34336 110 //TODO
Rhyme 0:ce97f6d34336 111
Rhyme 0:ce97f6d34336 112 #if (DISABLE_WDOG)
Rhyme 0:ce97f6d34336 113 /* Disable the WDOG module */
Rhyme 0:ce97f6d34336 114 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
Rhyme 0:ce97f6d34336 115 SIM->COPC = (uint32_t)0x00u;
Rhyme 0:ce97f6d34336 116 #endif /* (DISABLE_WDOG) */
Rhyme 0:ce97f6d34336 117 #if (CLOCK_SETUP == 0)
Rhyme 0:ce97f6d34336 118 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:ce97f6d34336 119 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
Rhyme 0:ce97f6d34336 120 /* Switch to FEI Mode */
Rhyme 0:ce97f6d34336 121 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:ce97f6d34336 122 MCG->C1 = (uint8_t)0x06U;
Rhyme 0:ce97f6d34336 123 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
Rhyme 0:ce97f6d34336 124 MCG->C2 = (uint8_t)0x00U;
Rhyme 0:ce97f6d34336 125 /* MCG->C4: DMX32=0,DRST_DRS=1 */
Rhyme 0:ce97f6d34336 126 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
Rhyme 0:ce97f6d34336 127 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Rhyme 0:ce97f6d34336 128 OSC0->CR = (uint8_t)0x80U;
Rhyme 0:ce97f6d34336 129 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Rhyme 0:ce97f6d34336 130 MCG->C5 = (uint8_t)0x00U;
Rhyme 0:ce97f6d34336 131 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Rhyme 0:ce97f6d34336 132 MCG->C6 = (uint8_t)0x00U;
Rhyme 0:ce97f6d34336 133 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
Rhyme 0:ce97f6d34336 134 }
Rhyme 0:ce97f6d34336 135 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
Rhyme 0:ce97f6d34336 136 }
Rhyme 0:ce97f6d34336 137 #elif (CLOCK_SETUP == 1)
Rhyme 0:ce97f6d34336 138 /* SIM->SCGC5: PORTA=1 */
Rhyme 0:ce97f6d34336 139 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
Rhyme 0:ce97f6d34336 140 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:ce97f6d34336 141 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
Rhyme 0:ce97f6d34336 142 /* PORTA->PCR18: ISF=0,MUX=0 */
Rhyme 0:ce97f6d34336 143 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
Rhyme 0:ce97f6d34336 144 /* PORTA->PCR19: ISF=0,MUX=0 */
Rhyme 0:ce97f6d34336 145 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
Rhyme 0:ce97f6d34336 146 /* Switch to FBE Mode */
Rhyme 0:ce97f6d34336 147 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
Rhyme 0:ce97f6d34336 148 OSC0->CR = (uint8_t)0x89U;
Rhyme 0:ce97f6d34336 149 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
Rhyme 0:ce97f6d34336 150 MCG->C2 = (uint8_t)0x24U;
Rhyme 0:ce97f6d34336 151 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:ce97f6d34336 152 MCG->C1 = (uint8_t)0x9AU;
Rhyme 0:ce97f6d34336 153 /* MCG->C4: DMX32=0,DRST_DRS=0 */
Rhyme 0:ce97f6d34336 154 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
Rhyme 0:ce97f6d34336 155 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
Rhyme 0:ce97f6d34336 156 MCG->C5 = (uint8_t)0x01U;
Rhyme 0:ce97f6d34336 157 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Rhyme 0:ce97f6d34336 158 MCG->C6 = (uint8_t)0x00U;
Rhyme 0:ce97f6d34336 159 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
Rhyme 0:ce97f6d34336 160 }
Rhyme 0:ce97f6d34336 161 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:ce97f6d34336 162 }
Rhyme 0:ce97f6d34336 163 /* Switch to PBE Mode */
Rhyme 0:ce97f6d34336 164 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
Rhyme 0:ce97f6d34336 165 MCG->C6 = (uint8_t)0x40U;
Rhyme 0:ce97f6d34336 166 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:ce97f6d34336 167 }
Rhyme 0:ce97f6d34336 168 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
Rhyme 0:ce97f6d34336 169 }
Rhyme 0:ce97f6d34336 170 /* Switch to PEE Mode */
Rhyme 0:ce97f6d34336 171 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:ce97f6d34336 172 MCG->C1 = (uint8_t)0x1AU;
Rhyme 0:ce97f6d34336 173 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
Rhyme 0:ce97f6d34336 174 }
Rhyme 0:ce97f6d34336 175 #elif (CLOCK_SETUP == 2)
Rhyme 0:ce97f6d34336 176 /* SIM->SCGC5: PORTA=1 */
Rhyme 0:ce97f6d34336 177 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
Rhyme 0:ce97f6d34336 178 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:ce97f6d34336 179 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
Rhyme 0:ce97f6d34336 180 /* PORTA->PCR18: ISF=0,MUX=0 */
Rhyme 0:ce97f6d34336 181 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
Rhyme 0:ce97f6d34336 182 /* PORTA->PCR19: ISF=0,MUX=0 */
Rhyme 0:ce97f6d34336 183 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
Rhyme 0:ce97f6d34336 184 /* Switch to FBE Mode */
Rhyme 0:ce97f6d34336 185 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
Rhyme 0:ce97f6d34336 186 OSC0->CR = (uint8_t)0x89U;
Rhyme 0:ce97f6d34336 187 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
Rhyme 0:ce97f6d34336 188 MCG->C2 = (uint8_t)0x24U;
Rhyme 0:ce97f6d34336 189 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:ce97f6d34336 190 MCG->C1 = (uint8_t)0x9AU;
Rhyme 0:ce97f6d34336 191 /* MCG->C4: DMX32=0,DRST_DRS=0 */
Rhyme 0:ce97f6d34336 192 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
Rhyme 0:ce97f6d34336 193 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Rhyme 0:ce97f6d34336 194 MCG->C5 = (uint8_t)0x00U;
Rhyme 0:ce97f6d34336 195 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Rhyme 0:ce97f6d34336 196 MCG->C6 = (uint8_t)0x00U;
Rhyme 0:ce97f6d34336 197 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
Rhyme 0:ce97f6d34336 198 }
Rhyme 0:ce97f6d34336 199 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:ce97f6d34336 200 }
Rhyme 0:ce97f6d34336 201 /* Switch to BLPE Mode */
Rhyme 0:ce97f6d34336 202 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
Rhyme 0:ce97f6d34336 203 MCG->C2 = (uint8_t)0x26U;
Rhyme 0:ce97f6d34336 204 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
Rhyme 0:ce97f6d34336 205 }
Rhyme 0:ce97f6d34336 206 #elif (CLOCK_SETUP == 3)
Rhyme 0:ce97f6d34336 207 /* SIM->SCGC5: PORTA=1 */
Rhyme 0:ce97f6d34336 208 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
Rhyme 0:ce97f6d34336 209 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
Rhyme 0:ce97f6d34336 210 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
Rhyme 0:ce97f6d34336 211 /* PORTA->PCR[3]: ISF=0,MUX=0 */
Rhyme 0:ce97f6d34336 212 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
Rhyme 0:ce97f6d34336 213 /* PORTA->PCR[4]: ISF=0,MUX=0 */
Rhyme 0:ce97f6d34336 214 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
Rhyme 0:ce97f6d34336 215 /* Switch to FEE Mode */
Rhyme 0:ce97f6d34336 216 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
Rhyme 0:ce97f6d34336 217 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
Rhyme 0:ce97f6d34336 218 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Rhyme 0:ce97f6d34336 219 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
Rhyme 0:ce97f6d34336 220 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Rhyme 0:ce97f6d34336 221 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
Rhyme 0:ce97f6d34336 222 /* MCG->C4: DMX32=1,DRST_DRS=1 */
Rhyme 0:ce97f6d34336 223 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
Rhyme 0:ce97f6d34336 224 MCG_C4_DRST_DRS(0x02)
Rhyme 0:ce97f6d34336 225 )) | (uint8_t)(
Rhyme 0:ce97f6d34336 226 MCG_C4_DMX32_MASK |
Rhyme 0:ce97f6d34336 227 MCG_C4_DRST_DRS(0x01)
Rhyme 0:ce97f6d34336 228 ));
Rhyme 0:ce97f6d34336 229 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
Rhyme 0:ce97f6d34336 230 }
Rhyme 0:ce97f6d34336 231 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
Rhyme 0:ce97f6d34336 232 }
Rhyme 0:ce97f6d34336 233 #endif /* (CLOCK_SETUP == 3) */
Rhyme 0:ce97f6d34336 234 }
Rhyme 0:ce97f6d34336 235 #endif // TARGET_KL25Z