La Suno / Mbed 2 deprecated afero_poc15_180223

Color sensor reset at the end of calibration added. sensor id auto assignment was changed to be a fixed value assignment to avoid sensor id shift when some sensor is absent.

Dependencies:   UniGraphic mbed vt100

sensors/MMA8451Q.cpp@1:8818b793d147, 2018-02-23 (annotated)

Committer:
Rhyme
Date:
Fri Feb 23 07:51:55 2018 +0000
Revision:
1:8818b793d147
Parent:
0:ce97f6d34336 
Wrong behavior when one of color sensor is missing has been fixed.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:ce97f6d34336 1 /**
Rhyme 0:ce97f6d34336 2 * MMA8451Q 3-Axis, 14-bit/8-bit Digital Accelerometer
Rhyme 0:ce97f6d34336 3 */
Rhyme 0:ce97f6d34336 4
Rhyme 0:ce97f6d34336 5 #include "mbed.h"
Rhyme 0:ce97f6d34336 6 #include "MMA8451Q.h"
Rhyme 0:ce97f6d34336 7 #include "af_mgr.h"
Rhyme 0:ce97f6d34336 8
Rhyme 0:ce97f6d34336 9 #define REG_STATUS 0x00 // when F_MODE = 00
Rhyme 0:ce97f6d34336 10 #define REG_FIFO_STATUS 0x00 // when F_MODE > 0
Rhyme 0:ce97f6d34336 11 #define REG_XYZ_FIFO 0x01 // Root pointer to XYZ FIFO data
Rhyme 0:ce97f6d34336 12 #define REG_OUT_X_MSB 0x01 // 8 MSBs of 14-bit sample
Rhyme 0:ce97f6d34336 13 #define REG_OUT_X_LSB 0x02 // 6 LSBs of 14-bit sample
Rhyme 0:ce97f6d34336 14 #define REG_OUT_Y_MSB 0x03
Rhyme 0:ce97f6d34336 15 #define REG_OUT_Y_LSB 0x04
Rhyme 0:ce97f6d34336 16 #define REG_OUT_Z_MSB 0x05
Rhyme 0:ce97f6d34336 17 #define REG_OUT_Z_LSB 0x06
Rhyme 0:ce97f6d34336 18 #define REG_F_SETUP 0x09 // FIFO setup
Rhyme 0:ce97f6d34336 19 #define REG_TRIG_CFG 0x0A // Map of FIFO daa capture events
Rhyme 0:ce97f6d34336 20 #define REG_SYSMOD 0x0B // Current System Mode
Rhyme 0:ce97f6d34336 21 #define REG_INT_SOURCE 0x0C // Interrupt status
Rhyme 0:ce97f6d34336 22 #define REG_WHO_AM_I 0x0D // Device ID (0x1A)
Rhyme 0:ce97f6d34336 23 #define REG_XYZ_DATA_CFG 0x0E // Dynamic Range Settings
Rhyme 0:ce97f6d34336 24 #define REG_HP_FILTER_CUTOFF 0x0F // Cutoff freq is set to 16Hz@800Hz
Rhyme 0:ce97f6d34336 25 #define REG_PL_STATUS 0x10 // Landscape/Portrait orientation status
Rhyme 0:ce97f6d34336 26 #define REG_PL_CFG 0x11 // Landscape/Portrait configuration
Rhyme 0:ce97f6d34336 27 #define REG_PL_COUNT 0x12 // Landscape/Portrait debounce counter
Rhyme 0:ce97f6d34336 28 #define REG_PL_BF_ZCOMP 0x13 // Back/Front, Z-Lock Trip threshold
Rhyme 0:ce97f6d34336 29 #define REG_P_L_THS_REG 0x14 // Portrait to Landscape Trip Angle is 29 degree
Rhyme 0:ce97f6d34336 30 #define REG_FF_MT_CFG 0x15 // Freefall/Motion function block configuration
Rhyme 0:ce97f6d34336 31 #define REG_FF_MT_SRC 0x16 // Freefall/Motion event source register
Rhyme 0:ce97f6d34336 32 #define REG_FF_MT_THS 0x17 // Freefall/Motion threshold register
Rhyme 0:ce97f6d34336 33 #define REG_FF_MT_COUNT 0x18 // Freefall/Motion debounce counter
Rhyme 0:ce97f6d34336 34 // TRANSIENT
Rhyme 0:ce97f6d34336 35 #define REG_TRANSIENT_CFG 0x1D // Transient functional block configuration
Rhyme 0:ce97f6d34336 36 #define REG_TRANSIENT_SRC 0x1E // Transient event status register
Rhyme 0:ce97f6d34336 37 #define REG_TRANSIENT_THS 0x1F // Transient event threshold
Rhyme 0:ce97f6d34336 38 #define REG_TRANSIENT_COUNT 0x20 // Transient debounce counter
Rhyme 0:ce97f6d34336 39 // PULSE
Rhyme 0:ce97f6d34336 40 #define REG_PULSE_CFG 0x21 // ELE, Double_XYZ or Single_XYZ
Rhyme 0:ce97f6d34336 41 #define REG_PULSE_SRC 0x22 // EA, Double_XYZ or Single_XYZ
Rhyme 0:ce97f6d34336 42 #define REG_PULSE_THSX 0x23 // X pulse threshold
Rhyme 0:ce97f6d34336 43 #define REG_PULSE_THSY 0x24 // Y pulse threshold
Rhyme 0:ce97f6d34336 44 #define REG_PULSE_THSZ 0x25 // Z pulse threshold
Rhyme 0:ce97f6d34336 45 #define REG_PULSE_TMLT 0x26 // Time limit for pulse
Rhyme 0:ce97f6d34336 46 #define REG_PULSE_LTCY 0x27 // Latency time for 2nd pulse
Rhyme 0:ce97f6d34336 47 #define REG_PULSE_WIND 0x28 // Window time for 2nd pulse
Rhyme 0:ce97f6d34336 48 #define REG_ASLP_COUNT 0x29 // Counter setting for Auto-SLEEP
Rhyme 0:ce97f6d34336 49 // Control Registers
Rhyme 0:ce97f6d34336 50 #define REG_CTRL_REG1 0x2A // ODR = 800Hz, STANDBY Mode
Rhyme 0:ce97f6d34336 51 #define REG_CTRL_REG2 0x2B // Sleep Enable, OS Modes, RST, ST
Rhyme 0:ce97f6d34336 52 #define REG_CTRL_REG3 0x2C // Wake from Sleep, IPOL, PP_OD
Rhyme 0:ce97f6d34336 53 #define REG_CTRL_REG4 0x2D // Interrupt enable register
Rhyme 0:ce97f6d34336 54 #define REG_CTRL_REG5 0x2E // Interrupt pin (INT1/INT2) map
Rhyme 0:ce97f6d34336 55 // User Offset
Rhyme 0:ce97f6d34336 56 #define REG_OFF_X 0x2F // X-axis offset adjust
Rhyme 0:ce97f6d34336 57 #define REG_OFF_Y 0x30 // Y-axis offset adjust
Rhyme 0:ce97f6d34336 58 #define REG_OFF_Z 0x31 // Z-axis offset adjust
Rhyme 0:ce97f6d34336 59
Rhyme 0:ce97f6d34336 60 // Value definitions
Rhyme 0:ce97f6d34336 61 #define BIT_TRIG_TRANS 0x20 // Transient interrupt trigger bit
Rhyme 0:ce97f6d34336 62 #define BIT_TRIG_LNDPRT 0x10 // Landscape/Portrati Orientation
Rhyme 0:ce97f6d34336 63 #define BIT_TRIG_PULSE 0x08 // Pulse interrupt trigger bit
Rhyme 0:ce97f6d34336 64 #define BIT_TRIG_FF_MT 0x04 // Freefall/Motion trigger bit
Rhyme 0:ce97f6d34336 65
Rhyme 0:ce97f6d34336 66 MMA8451Q::MMA8451Q(I2C *i2c, int addr) : m_addr(addr<<1) {
Rhyme 0:ce97f6d34336 67 // activate the peripheral
Rhyme 0:ce97f6d34336 68 p_i2c = i2c ;
Rhyme 0:ce97f6d34336 69 uint8_t data[2] = {REG_CTRL_REG1, 0x01};
Rhyme 0:ce97f6d34336 70 writeRegs(data, 2);
Rhyme 0:ce97f6d34336 71 }
Rhyme 0:ce97f6d34336 72
Rhyme 0:ce97f6d34336 73 MMA8451Q::~MMA8451Q() { }
Rhyme 0:ce97f6d34336 74
Rhyme 0:ce97f6d34336 75 int MMA8451Q::readRegs(int addr, uint8_t * data, int len)
Rhyme 0:ce97f6d34336 76 {
Rhyme 0:ce97f6d34336 77 char t[1] = {addr};
Rhyme 0:ce97f6d34336 78 int result ;
Rhyme 0:ce97f6d34336 79 __disable_irq() ; // Disable Interrupts
Rhyme 0:ce97f6d34336 80 result = p_i2c->write(m_addr, t, 1, true);
Rhyme 0:ce97f6d34336 81 if (result == 0) {
Rhyme 0:ce97f6d34336 82 result = p_i2c->read(m_addr, (char *)data, len);
Rhyme 0:ce97f6d34336 83 }
Rhyme 0:ce97f6d34336 84 __enable_irq() ; // Enable Interrupts
Rhyme 0:ce97f6d34336 85 return( result ) ;
Rhyme 0:ce97f6d34336 86 }
Rhyme 0:ce97f6d34336 87
Rhyme 0:ce97f6d34336 88 int MMA8451Q::writeRegs(uint8_t * data, int len)
Rhyme 0:ce97f6d34336 89 {
Rhyme 0:ce97f6d34336 90 int result ;
Rhyme 0:ce97f6d34336 91 __disable_irq() ; // Disable Interrupts
Rhyme 0:ce97f6d34336 92 result = p_i2c->write(m_addr, (char *)data, len);
Rhyme 0:ce97f6d34336 93 __enable_irq() ; // Enable Interrupts
Rhyme 0:ce97f6d34336 94 return( result ) ;
Rhyme 0:ce97f6d34336 95 }
Rhyme 0:ce97f6d34336 96
Rhyme 0:ce97f6d34336 97 int MMA8451Q::getAllRawData(int16_t value[])
Rhyme 0:ce97f6d34336 98 {
Rhyme 0:ce97f6d34336 99 int result ;
Rhyme 0:ce97f6d34336 100 uint8_t data[6] ;
Rhyme 0:ce97f6d34336 101 result = readRegs(REG_OUT_X_MSB, data, 6) ;
Rhyme 0:ce97f6d34336 102 if (result == 0) {
Rhyme 0:ce97f6d34336 103 value[0] = ((int16_t)((data[0] << 8) | data[1])) >> 2 ;
Rhyme 0:ce97f6d34336 104 value[1] = ((int16_t)((data[2] << 8) | data[3])) >> 2 ;
Rhyme 0:ce97f6d34336 105 value[2] = ((int16_t)((data[4] << 8) | data[5])) >> 2 ;
Rhyme 0:ce97f6d34336 106 }
Rhyme 0:ce97f6d34336 107 return( result ) ;
Rhyme 0:ce97f6d34336 108 }
Rhyme 0:ce97f6d34336 109
Rhyme 0:ce97f6d34336 110 int MMA8451Q::getAllData(float fvalue[])
Rhyme 0:ce97f6d34336 111 {
Rhyme 0:ce97f6d34336 112 int result ;
Rhyme 0:ce97f6d34336 113 uint8_t data[6] ;
Rhyme 0:ce97f6d34336 114 result = readRegs(REG_OUT_X_MSB, data, 6) ;
Rhyme 0:ce97f6d34336 115 if (result == 0) {
Rhyme 0:ce97f6d34336 116 fvalue[0] = (float)((int16_t)((data[0] << 8) | data[1])) / 16384.0 ;
Rhyme 0:ce97f6d34336 117 fvalue[1] = (float)((int16_t)((data[2] << 8) | data[3])) / 16384.0 ;
Rhyme 0:ce97f6d34336 118 fvalue[2] = (float)((int16_t)((data[4] << 8) | data[5])) / 16384.0 ;
Rhyme 0:ce97f6d34336 119 }
Rhyme 0:ce97f6d34336 120 return( result ) ;
Rhyme 0:ce97f6d34336 121 }
Rhyme 0:ce97f6d34336 122
Rhyme 0:ce97f6d34336 123 int16_t MMA8451Q::getRawData(uint8_t addr)
Rhyme 0:ce97f6d34336 124 {
Rhyme 0:ce97f6d34336 125 int16_t value ;
Rhyme 0:ce97f6d34336 126 uint8_t data[2] ;
Rhyme 0:ce97f6d34336 127 readRegs(addr, data, 2) ;
Rhyme 0:ce97f6d34336 128 value = ((int16_t)((data[0] << 8) | data[1])) >> 2 ;
Rhyme 0:ce97f6d34336 129 return( value ) ;
Rhyme 0:ce97f6d34336 130 }
Rhyme 0:ce97f6d34336 131
Rhyme 0:ce97f6d34336 132 int16_t MMA8451Q::getRawX(void)
Rhyme 0:ce97f6d34336 133 {
Rhyme 0:ce97f6d34336 134 int16_t value ;
Rhyme 0:ce97f6d34336 135 value = getRawData(REG_OUT_X_MSB) ;
Rhyme 0:ce97f6d34336 136 return( value ) ;
Rhyme 0:ce97f6d34336 137 }
Rhyme 0:ce97f6d34336 138
Rhyme 0:ce97f6d34336 139 int16_t MMA8451Q::getRawY(void)
Rhyme 0:ce97f6d34336 140 {
Rhyme 0:ce97f6d34336 141 int16_t value ;
Rhyme 0:ce97f6d34336 142 value = getRawData(REG_OUT_Y_MSB) ;
Rhyme 0:ce97f6d34336 143 return( value ) ;
Rhyme 0:ce97f6d34336 144 }
Rhyme 0:ce97f6d34336 145
Rhyme 0:ce97f6d34336 146 int16_t MMA8451Q::getRawZ(void)
Rhyme 0:ce97f6d34336 147 {
Rhyme 0:ce97f6d34336 148 int16_t value ;
Rhyme 0:ce97f6d34336 149 value = getRawData(REG_OUT_Z_MSB) ;
Rhyme 0:ce97f6d34336 150 return( value ) ;
Rhyme 0:ce97f6d34336 151 }
Rhyme 0:ce97f6d34336 152
Rhyme 0:ce97f6d34336 153 float MMA8451Q::getAccX(void)
Rhyme 0:ce97f6d34336 154 {
Rhyme 0:ce97f6d34336 155 return(((float)getRawX())/4096.0) ;
Rhyme 0:ce97f6d34336 156 }
Rhyme 0:ce97f6d34336 157
Rhyme 0:ce97f6d34336 158 float MMA8451Q::getAccY(void)
Rhyme 0:ce97f6d34336 159 {
Rhyme 0:ce97f6d34336 160 return(((float)getRawY())/4096.0) ;
Rhyme 0:ce97f6d34336 161 }
Rhyme 0:ce97f6d34336 162
Rhyme 0:ce97f6d34336 163 float MMA8451Q::getAccZ(void)
Rhyme 0:ce97f6d34336 164 {
Rhyme 0:ce97f6d34336 165 return(((float)getRawZ())/4096.0) ;
Rhyme 0:ce97f6d34336 166 }