Color sensor reset at the end of calibration added. sensor id auto assignment was changed to be a fixed value assignment to avoid sensor id shift when some sensor is absent.

Dependencies:   UniGraphic mbed vt100

Committer:
Rhyme
Date:
Fri Feb 23 07:51:55 2018 +0000
Revision:
1:8818b793d147
Parent:
0:ce97f6d34336
Wrong behavior when one of color sensor is missing has been fixed.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:ce97f6d34336 1 #include "mbed.h"
Rhyme 0:ce97f6d34336 2 #include "LM75B.h"
Rhyme 0:ce97f6d34336 3 #include "af_mgr.h"
Rhyme 0:ce97f6d34336 4
Rhyme 0:ce97f6d34336 5 /* Register list */
Rhyme 0:ce97f6d34336 6 #define PTR_CONF 0x01
Rhyme 0:ce97f6d34336 7 #define PTR_TEMP 0x00
Rhyme 0:ce97f6d34336 8 #define PTR_TOS 0x03
Rhyme 0:ce97f6d34336 9 #define PTR_THYST 0x02
Rhyme 0:ce97f6d34336 10
Rhyme 0:ce97f6d34336 11 /* Configuration register */
Rhyme 0:ce97f6d34336 12 /* B[7:5] : Reserved */
Rhyme 0:ce97f6d34336 13 /* B[4:3] : OS_F_QUE[1:0] OS fault queue value */
Rhyme 0:ce97f6d34336 14 #define CONFIG_QUE_1 0x00
Rhyme 0:ce97f6d34336 15 #define CONFIG_QUE_2 (0x01 << 3)
Rhyme 0:ce97f6d34336 16 #define CONFIG_QUE_4 (0x10 << 3)
Rhyme 0:ce97f6d34336 17 #define CONFIG_QUE_6 (0x11 << 3)
Rhyme 0:ce97f6d34336 18 /* B[2] : OS_POL 0 = OS active LOW, 1 = OS active HIGH */
Rhyme 0:ce97f6d34336 19 #define CONFIG_OS_POL_L 0x00
Rhyme 0:ce97f6d34336 20 #define CONFIG_OS_POL_H (0x01 << 2)
Rhyme 0:ce97f6d34336 21 /* B[1] : OS_COMP_INT 0 = OS comparator, 1 = OS interrupt */
Rhyme 0:ce97f6d34336 22 #define CONFIG_OS_COMP 0x00
Rhyme 0:ce97f6d34336 23 #define CONFIG_OS_INT (0x01 << 1)
Rhyme 0:ce97f6d34336 24 /* B[0] : SHUTDOWN 0 = normal, 1 = shutdown */
Rhyme 0:ce97f6d34336 25 #define CONFIG_NORMARL 0x00
Rhyme 0:ce97f6d34336 26 #define CONFIG_SHUTDOWN 0x01
Rhyme 0:ce97f6d34336 27
Rhyme 0:ce97f6d34336 28 /* Temperature register */
Rhyme 0:ce97f6d34336 29 /* D[15:5] = 11 bit data 0.125 * temp data */
Rhyme 0:ce97f6d34336 30 /* D[4:0] : reserved */
Rhyme 0:ce97f6d34336 31
Rhyme 0:ce97f6d34336 32 /* Tos register */
Rhyme 0:ce97f6d34336 33 /* D[15:7] = 9 bit data */
Rhyme 0:ce97f6d34336 34 /* D[6:0] : reserved */
Rhyme 0:ce97f6d34336 35
Rhyme 0:ce97f6d34336 36 /* Thyst register */
Rhyme 0:ce97f6d34336 37 /* D[15:7] = 9 ibt data */
Rhyme 0:ce97f6d34336 38 /* D[6:0] : reserved */
Rhyme 0:ce97f6d34336 39
Rhyme 0:ce97f6d34336 40 LM75B::LM75B(I2C *i2c, int addr) : m_addr(addr<<1) {
Rhyme 0:ce97f6d34336 41 p_i2c = i2c ;
Rhyme 0:ce97f6d34336 42 p_i2c->frequency(100000); /* 100kHz */
Rhyme 0:ce97f6d34336 43 // activate the peripheral
Rhyme 0:ce97f6d34336 44 }
Rhyme 0:ce97f6d34336 45
Rhyme 0:ce97f6d34336 46 LM75B::~LM75B() { }
Rhyme 0:ce97f6d34336 47
Rhyme 0:ce97f6d34336 48 int LM75B::temp(int8_t *temp)
Rhyme 0:ce97f6d34336 49 {
Rhyme 0:ce97f6d34336 50 int result ;
Rhyme 0:ce97f6d34336 51 char t[1] = { 0x00 } ;
Rhyme 0:ce97f6d34336 52 result = p_i2c->write(m_addr, t, 1, true) ;
Rhyme 0:ce97f6d34336 53 if (result == 0) {
Rhyme 0:ce97f6d34336 54 result = p_i2c->read(m_addr, t, 1) ;
Rhyme 0:ce97f6d34336 55 }
Rhyme 0:ce97f6d34336 56 if (result == 0) {
Rhyme 0:ce97f6d34336 57 *temp = (int8_t)t[0] ;
Rhyme 0:ce97f6d34336 58 }
Rhyme 0:ce97f6d34336 59 return( result ) ;
Rhyme 0:ce97f6d34336 60 }
Rhyme 0:ce97f6d34336 61
Rhyme 0:ce97f6d34336 62 int LM75B::getTemp(float *temp)
Rhyme 0:ce97f6d34336 63 {
Rhyme 0:ce97f6d34336 64 int result ;
Rhyme 0:ce97f6d34336 65 char t[2] = { 0, 0 } ;
Rhyme 0:ce97f6d34336 66 int16_t iTemp = 0 ;
Rhyme 0:ce97f6d34336 67 result = p_i2c->write(m_addr, t, 1) ; /* write pointer byte 0x00 */
Rhyme 0:ce97f6d34336 68 if (result == 0) {
Rhyme 0:ce97f6d34336 69 result = p_i2c->read(m_addr, t, 2) ; /* read MSB, LSB */
Rhyme 0:ce97f6d34336 70 }
Rhyme 0:ce97f6d34336 71 if (result == 0) {
Rhyme 0:ce97f6d34336 72 iTemp = (t[0] << 8) | t[1] ;
Rhyme 0:ce97f6d34336 73 iTemp >>= 5 ;
Rhyme 0:ce97f6d34336 74 *temp = 0.125 * iTemp ;
Rhyme 0:ce97f6d34336 75 }
Rhyme 0:ce97f6d34336 76 return( result ) ;
Rhyme 0:ce97f6d34336 77 }
Rhyme 0:ce97f6d34336 78
Rhyme 0:ce97f6d34336 79 int LM75B::getConfig(uint8_t ptr_byte, uint8_t *config_data)
Rhyme 0:ce97f6d34336 80 {
Rhyme 0:ce97f6d34336 81 int result ;
Rhyme 0:ce97f6d34336 82 char config = 0x00 ; /* default value */
Rhyme 0:ce97f6d34336 83 result = p_i2c->write(m_addr, (char*)(&ptr_byte), 1, true) ;
Rhyme 0:ce97f6d34336 84 if (result == 0) {
Rhyme 0:ce97f6d34336 85 result = p_i2c->read(m_addr, &config, 1) ;
Rhyme 0:ce97f6d34336 86 }
Rhyme 0:ce97f6d34336 87 if (result == 0) {
Rhyme 0:ce97f6d34336 88 *config_data = config ;
Rhyme 0:ce97f6d34336 89 }
Rhyme 0:ce97f6d34336 90 return( result ) ;
Rhyme 0:ce97f6d34336 91 }
Rhyme 0:ce97f6d34336 92
Rhyme 0:ce97f6d34336 93 int LM75B::setConfig(uint8_t ptr_byte, uint8_t config_data)
Rhyme 0:ce97f6d34336 94 {
Rhyme 0:ce97f6d34336 95 int result ;
Rhyme 0:ce97f6d34336 96 char t[2] ;
Rhyme 0:ce97f6d34336 97 t[0] = ptr_byte ;
Rhyme 0:ce97f6d34336 98 t[1] = config_data ;
Rhyme 0:ce97f6d34336 99 result = p_i2c->write(m_addr, t, 2, true) ;
Rhyme 0:ce97f6d34336 100 return( result ) ;
Rhyme 0:ce97f6d34336 101 }
Rhyme 0:ce97f6d34336 102
Rhyme 0:ce97f6d34336 103 int LM75B::readRegs(int addr, uint8_t * data, int len)
Rhyme 0:ce97f6d34336 104 {
Rhyme 0:ce97f6d34336 105 int result ;
Rhyme 0:ce97f6d34336 106 char t[1] = {addr};
Rhyme 0:ce97f6d34336 107 __disable_irq() ; // Disable Interrupts
Rhyme 0:ce97f6d34336 108 result = p_i2c->write(m_addr, t, 1, true);
Rhyme 0:ce97f6d34336 109 if (result == 0) {
Rhyme 0:ce97f6d34336 110 result = p_i2c->read(m_addr, (char *)data, len);
Rhyme 0:ce97f6d34336 111 }
Rhyme 0:ce97f6d34336 112 __enable_irq() ; // Enable Interrupts
Rhyme 0:ce97f6d34336 113 return( result ) ;
Rhyme 0:ce97f6d34336 114 }
Rhyme 0:ce97f6d34336 115
Rhyme 0:ce97f6d34336 116 int LM75B::writeRegs(uint8_t * data, int len) {
Rhyme 0:ce97f6d34336 117 int result ;
Rhyme 0:ce97f6d34336 118 __disable_irq() ; // Disable Interrupts
Rhyme 0:ce97f6d34336 119 result = p_i2c->write(m_addr, (char *)data, len);
Rhyme 0:ce97f6d34336 120 __enable_irq() ; // Enable Interrupts
Rhyme 0:ce97f6d34336 121 return( result ) ;
Rhyme 0:ce97f6d34336 122 }