Basically i glued Peter Drescher and Simon Ford libs in a GraphicsDisplay class, then derived TFT or LCD class (which inherits Protocols class), then the most derived ones (Inits), which are per-display and are the only part needed to be adapted to diff hw.

Dependents:   afero_poc15_180216 afero_poc15_180223 afero_poc15_180302 afero_poc15_180403R ... more

Fork of UniGraphic by GraphicsDisplay

UniGraphic for La Suno Version.
To go with La Suno, WatchDog Reset functions were added in ILI9341.

Committer:
dreschpe
Date:
Sun Feb 22 00:05:34 2015 +0000
Revision:
12:9c8f3076347c
Child:
13:d8c593fa7705
Add SSD1306 OLED Driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 12:9c8f3076347c 1 /* mbed UniGraphic library - Device specific class
dreschpe 12:9c8f3076347c 2 * Copyright (c) 2015 Peter Drescher
dreschpe 12:9c8f3076347c 3 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 12:9c8f3076347c 4 */
dreschpe 12:9c8f3076347c 5
dreschpe 12:9c8f3076347c 6 #include "Protocols.h"
dreschpe 12:9c8f3076347c 7 #include "SSD1306.h"
dreschpe 12:9c8f3076347c 8
dreschpe 12:9c8f3076347c 9 //////////////////////////////////////////////////////////////////////////////////
dreschpe 12:9c8f3076347c 10 // display settings ///////////////////////////////////////////////////////
dreschpe 12:9c8f3076347c 11 /////////////////////////////////////////////////////////////////////////
dreschpe 12:9c8f3076347c 12
dreschpe 12:9c8f3076347c 13
dreschpe 12:9c8f3076347c 14 #define IC_X_SEGS 128 // UC1608 SEG has range 0-239 (239-0 if MX=1), check your datasheet, important for the orientation
dreschpe 12:9c8f3076347c 15 #define IC_Y_COMS 64 // UC1608 COM has range 0-127 (127-0 if MY=1), check your datasheet, important for the orientation
dreschpe 12:9c8f3076347c 16
dreschpe 12:9c8f3076347c 17 #define SSD1306_SETCONTRAST 0x81
dreschpe 12:9c8f3076347c 18 #define SSD1306_DISPLAYALLON_RESUME 0xA4
dreschpe 12:9c8f3076347c 19 #define SSD1306_DISPLAYALLON 0xA5
dreschpe 12:9c8f3076347c 20 #define SSD1306_NORMALDISPLAY 0xA6
dreschpe 12:9c8f3076347c 21 #define SSD1306_INVERTDISPLAY 0xA7
dreschpe 12:9c8f3076347c 22 #define SSD1306_DISPLAYOFF 0xAE
dreschpe 12:9c8f3076347c 23 #define SSD1306_DISPLAYON 0xAF
dreschpe 12:9c8f3076347c 24 #define SSD1306_SETDISPLAYOFFSET 0xD3
dreschpe 12:9c8f3076347c 25 #define SSD1306_SETCOMPINS 0xDA
dreschpe 12:9c8f3076347c 26 #define SSD1306_SETVCOMDETECT 0xDB
dreschpe 12:9c8f3076347c 27 #define SSD1306_SETDISPLAYCLOCKDIV 0xD5
dreschpe 12:9c8f3076347c 28 #define SSD1306_SETPRECHARGE 0xD9
dreschpe 12:9c8f3076347c 29 #define SSD1306_SETMULTIPLEX 0xA8
dreschpe 12:9c8f3076347c 30 #define SSD1306_SETLOWCOLUMN 0x00
dreschpe 12:9c8f3076347c 31 #define SSD1306_SETHIGHCOLUMN 0x10
dreschpe 12:9c8f3076347c 32 #define SSD1306_SETSTARTLINE 0x40
dreschpe 12:9c8f3076347c 33 #define SSD1306_MEMORYMODE 0x20
dreschpe 12:9c8f3076347c 34 #define SSD1306_COMSCANINC 0xC0
dreschpe 12:9c8f3076347c 35 #define SSD1306_COMSCANDEC 0xC8
dreschpe 12:9c8f3076347c 36 #define SSD1306_SEGREMAP 0xA0
dreschpe 12:9c8f3076347c 37 #define SSD1306_CHARGEPUMP 0x8D
dreschpe 12:9c8f3076347c 38
dreschpe 12:9c8f3076347c 39 SSD1306::SSD1306(proto_t displayproto, PortName port, PinName CS, PinName reset, PinName DC, PinName WR, PinName RD, const char *name , unsigned int LCDSIZE_X, unsigned int LCDSIZE_Y)
dreschpe 12:9c8f3076347c 40 : LCD(displayproto, port, CS, reset, DC, WR, RD, LCDSIZE_X, LCDSIZE_Y, IC_X_SEGS, IC_Y_COMS, name)
dreschpe 12:9c8f3076347c 41 {
dreschpe 12:9c8f3076347c 42 hw_reset();
dreschpe 12:9c8f3076347c 43 BusEnable(true);
dreschpe 12:9c8f3076347c 44 init();
dreschpe 12:9c8f3076347c 45 cls();
dreschpe 12:9c8f3076347c 46 set_orientation(1);
dreschpe 12:9c8f3076347c 47 locate(0,0);
dreschpe 12:9c8f3076347c 48 }
dreschpe 12:9c8f3076347c 49 SSD1306::SSD1306(proto_t displayproto, int Hz, PinName mosi, PinName miso, PinName sclk, PinName CS, PinName reset, PinName DC, const char *name, unsigned int LCDSIZE_X, unsigned int LCDSIZE_Y)
dreschpe 12:9c8f3076347c 50 : LCD(displayproto, Hz, mosi, miso, sclk, CS, reset, DC, LCDSIZE_X, LCDSIZE_Y, IC_X_SEGS, IC_Y_COMS, name)
dreschpe 12:9c8f3076347c 51 {
dreschpe 12:9c8f3076347c 52 hw_reset();
dreschpe 12:9c8f3076347c 53 BusEnable(true);
dreschpe 12:9c8f3076347c 54 init();
dreschpe 12:9c8f3076347c 55 cls();
dreschpe 12:9c8f3076347c 56 set_orientation(1);
dreschpe 12:9c8f3076347c 57 locate(0,0);
dreschpe 12:9c8f3076347c 58 }
dreschpe 12:9c8f3076347c 59 // reset and init the lcd controller
dreschpe 12:9c8f3076347c 60 void SSD1306::init()
dreschpe 12:9c8f3076347c 61 {
dreschpe 12:9c8f3076347c 62 /* Start Initial Sequence ----------------------------------------------------*/
dreschpe 12:9c8f3076347c 63
dreschpe 12:9c8f3076347c 64 // wr_cmd8(0xE2); // sw reset
dreschpe 12:9c8f3076347c 65 wait_ms(15);
dreschpe 12:9c8f3076347c 66
dreschpe 12:9c8f3076347c 67 wr_cmd8(SSD1306_DISPLAYOFF);
dreschpe 12:9c8f3076347c 68 wr_cmd8(SSD1306_SETDISPLAYCLOCKDIV);
dreschpe 12:9c8f3076347c 69 wr_cmd8(0x80);
dreschpe 12:9c8f3076347c 70 wr_cmd8(SSD1306_SETMULTIPLEX);
dreschpe 12:9c8f3076347c 71 wr_cmd8(63);
dreschpe 12:9c8f3076347c 72
dreschpe 12:9c8f3076347c 73 wr_cmd8(SSD1306_SETDISPLAYOFFSET);
dreschpe 12:9c8f3076347c 74 wr_cmd8(0x0);
dreschpe 12:9c8f3076347c 75
dreschpe 12:9c8f3076347c 76 wr_cmd8(SSD1306_SETSTARTLINE | 0x0); // line #0
dreschpe 12:9c8f3076347c 77
dreschpe 12:9c8f3076347c 78 wr_cmd8(SSD1306_CHARGEPUMP);
dreschpe 12:9c8f3076347c 79 wr_cmd8(0x14); // 0x10
dreschpe 12:9c8f3076347c 80
dreschpe 12:9c8f3076347c 81 wr_cmd8(SSD1306_MEMORYMODE);
dreschpe 12:9c8f3076347c 82 wr_cmd8(0x00); // 0x0 act like ks0108
dreschpe 12:9c8f3076347c 83
dreschpe 12:9c8f3076347c 84 wr_cmd8(SSD1306_SEGREMAP ); //| 0x1);
dreschpe 12:9c8f3076347c 85
dreschpe 12:9c8f3076347c 86 wr_cmd8(SSD1306_COMSCANDEC);
dreschpe 12:9c8f3076347c 87
dreschpe 12:9c8f3076347c 88 wr_cmd8(SSD1306_SETCOMPINS);
dreschpe 12:9c8f3076347c 89 wr_cmd8(0x12); // LCDSIZE_Y == 32 ? 0x02 : 0x12);
dreschpe 12:9c8f3076347c 90
dreschpe 12:9c8f3076347c 91 wr_cmd8(SSD1306_SETCONTRAST);
dreschpe 12:9c8f3076347c 92 wr_cmd8(0xCF); // _rawHeight == 32 ? 0x8F : ((vccstate == SSD1306_EXTERNALVCC) ? 0x9F : 0xCF) );
dreschpe 12:9c8f3076347c 93
dreschpe 12:9c8f3076347c 94 wr_cmd8(SSD1306_SETPRECHARGE);
dreschpe 12:9c8f3076347c 95 wr_cmd8(0xF1); // : 0x22);
dreschpe 12:9c8f3076347c 96
dreschpe 12:9c8f3076347c 97 wr_cmd8(SSD1306_SETVCOMDETECT);
dreschpe 12:9c8f3076347c 98 wr_cmd8(0x40);
dreschpe 12:9c8f3076347c 99
dreschpe 12:9c8f3076347c 100 wr_cmd8(SSD1306_DISPLAYALLON_RESUME);
dreschpe 12:9c8f3076347c 101
dreschpe 12:9c8f3076347c 102 //wr_cmd8(SSD1306_NORMALDISPLAY);
dreschpe 12:9c8f3076347c 103 wr_cmd8(SSD1306_INVERTDISPLAY);
dreschpe 12:9c8f3076347c 104
dreschpe 12:9c8f3076347c 105 wr_cmd8(SSD1306_DISPLAYON);
dreschpe 12:9c8f3076347c 106 }
dreschpe 12:9c8f3076347c 107
dreschpe 12:9c8f3076347c 108 ////////////////////////////////////////////////////////////////////
dreschpe 12:9c8f3076347c 109 // functions that overrides the standard ones implemented in LCD.cpp
dreschpe 12:9c8f3076347c 110 ////////////////////////////////////////////////////////////////////
dreschpe 12:9c8f3076347c 111
dreschpe 12:9c8f3076347c 112 void SSD1306::mirrorXY(mirror_t mode)
dreschpe 12:9c8f3076347c 113 {
dreschpe 12:9c8f3076347c 114 switch (mode)
dreschpe 12:9c8f3076347c 115 {
dreschpe 12:9c8f3076347c 116 case(NONE):
dreschpe 12:9c8f3076347c 117 wr_cmd16(0xA0C0);
dreschpe 12:9c8f3076347c 118 break;
dreschpe 12:9c8f3076347c 119 case(X):
dreschpe 12:9c8f3076347c 120 wr_cmd16(0xA1C0);
dreschpe 12:9c8f3076347c 121 break;
dreschpe 12:9c8f3076347c 122 case(Y):
dreschpe 12:9c8f3076347c 123 wr_cmd16(0xA0C8);
dreschpe 12:9c8f3076347c 124 break;
dreschpe 12:9c8f3076347c 125 case(XY):
dreschpe 12:9c8f3076347c 126 wr_cmd16(0xA1C8);
dreschpe 12:9c8f3076347c 127 break;
dreschpe 12:9c8f3076347c 128 }
dreschpe 12:9c8f3076347c 129 }
dreschpe 12:9c8f3076347c 130
dreschpe 12:9c8f3076347c 131 void SSD1306::set_contrast(int o)
dreschpe 12:9c8f3076347c 132 {
dreschpe 12:9c8f3076347c 133 contrast = o;
dreschpe 12:9c8f3076347c 134
dreschpe 12:9c8f3076347c 135 wr_cmd16(0x8100|(o));
dreschpe 12:9c8f3076347c 136 }