Interactive Device Design / Mbed 2 deprecated air_zuma

Control the wondrous spinning-frog game of Zuma's Revenge with a rotating chair and an Airzooka. Maps compass rotation, flex sensor and push button input to USB actions to control Zuma's Revenge (http://www.popcap.com/games/zumas-revenge/online)

Dependencies:   LSM303DLHC mbed

Note that content for USB HID and USB Device is actually from the USBDevice mbed library. However, we made a couple of small changes to this library (allowing USB clicks at a particular location) that required us to break it off from the main project if we wanted to publish without pushing upstream.

USBDevice/USBHAL_LPC11U.cpp@0:4df415dde990, 2014-09-29 (annotated)

Committer:
andrewhead
Date:
Mon Sep 29 01:12:20 2014 +0000
Revision:
0:4df415dde990
Initial Commit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrewhead 0:4df415dde990 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
andrewhead 0:4df415dde990 2 *
andrewhead 0:4df415dde990 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
andrewhead 0:4df415dde990 4 * and associated documentation files (the "Software"), to deal in the Software without
andrewhead 0:4df415dde990 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
andrewhead 0:4df415dde990 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
andrewhead 0:4df415dde990 7 * Software is furnished to do so, subject to the following conditions:
andrewhead 0:4df415dde990 8 *
andrewhead 0:4df415dde990 9 * The above copyright notice and this permission notice shall be included in all copies or
andrewhead 0:4df415dde990 10 * substantial portions of the Software.
andrewhead 0:4df415dde990 11 *
andrewhead 0:4df415dde990 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
andrewhead 0:4df415dde990 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
andrewhead 0:4df415dde990 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
andrewhead 0:4df415dde990 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
andrewhead 0:4df415dde990 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
andrewhead 0:4df415dde990 17 */
andrewhead 0:4df415dde990 18
andrewhead 0:4df415dde990 19 #ifdef TARGET_LPC11U24
andrewhead 0:4df415dde990 20
andrewhead 0:4df415dde990 21 #include "USBHAL.h"
andrewhead 0:4df415dde990 22
andrewhead 0:4df415dde990 23 USBHAL * USBHAL::instance;
andrewhead 0:4df415dde990 24
andrewhead 0:4df415dde990 25 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
andrewhead 0:4df415dde990 26 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
andrewhead 0:4df415dde990 27
andrewhead 0:4df415dde990 28 // Convert physical endpoint number to register bit
andrewhead 0:4df415dde990 29 #define EP(endpoint) (1UL<<endpoint)
andrewhead 0:4df415dde990 30
andrewhead 0:4df415dde990 31 // Convert physical to logical
andrewhead 0:4df415dde990 32 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
andrewhead 0:4df415dde990 33
andrewhead 0:4df415dde990 34 // Get endpoint direction
andrewhead 0:4df415dde990 35 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
andrewhead 0:4df415dde990 36 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
andrewhead 0:4df415dde990 37
andrewhead 0:4df415dde990 38 // USB RAM
andrewhead 0:4df415dde990 39 #define USB_RAM_START (0x20004000)
andrewhead 0:4df415dde990 40 #define USB_RAM_SIZE (0x00000800)
andrewhead 0:4df415dde990 41
andrewhead 0:4df415dde990 42 // SYSAHBCLKCTRL
andrewhead 0:4df415dde990 43 #define CLK_USB (1UL<<14)
andrewhead 0:4df415dde990 44 #define CLK_USBRAM (1UL<<27)
andrewhead 0:4df415dde990 45
andrewhead 0:4df415dde990 46 // USB Information register
andrewhead 0:4df415dde990 47 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
andrewhead 0:4df415dde990 48
andrewhead 0:4df415dde990 49 // USB Device Command/Status register
andrewhead 0:4df415dde990 50 #define DEV_ADDR_MASK (0x7f) // Device address
andrewhead 0:4df415dde990 51 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
andrewhead 0:4df415dde990 52 #define DEV_EN (1UL<<7) // Device enable
andrewhead 0:4df415dde990 53 #define SETUP (1UL<<8) // SETUP token received
andrewhead 0:4df415dde990 54 #define PLL_ON (1UL<<9) // PLL enabled in suspend
andrewhead 0:4df415dde990 55 #define DCON (1UL<<16) // Device status - connect
andrewhead 0:4df415dde990 56 #define DSUS (1UL<<17) // Device status - suspend
andrewhead 0:4df415dde990 57 #define DCON_C (1UL<<24) // Connect change
andrewhead 0:4df415dde990 58 #define DSUS_C (1UL<<25) // Suspend change
andrewhead 0:4df415dde990 59 #define DRES_C (1UL<<26) // Reset change
andrewhead 0:4df415dde990 60 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
andrewhead 0:4df415dde990 61
andrewhead 0:4df415dde990 62 // Endpoint Command/Status list
andrewhead 0:4df415dde990 63 #define CMDSTS_A (1UL<<31) // Active
andrewhead 0:4df415dde990 64 #define CMDSTS_D (1UL<<30) // Disable
andrewhead 0:4df415dde990 65 #define CMDSTS_S (1UL<<29) // Stall
andrewhead 0:4df415dde990 66 #define CMDSTS_TR (1UL<<28) // Toggle Reset
andrewhead 0:4df415dde990 67 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
andrewhead 0:4df415dde990 68 #define CMDSTS_TV (1UL<<27) // Toggle Value
andrewhead 0:4df415dde990 69 #define CMDSTS_T (1UL<<26) // Endpoint Type
andrewhead 0:4df415dde990 70 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
andrewhead 0:4df415dde990 71 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
andrewhead 0:4df415dde990 72
andrewhead 0:4df415dde990 73 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
andrewhead 0:4df415dde990 74
andrewhead 0:4df415dde990 75 // USB Non-endpoint interrupt sources
andrewhead 0:4df415dde990 76 #define FRAME_INT (1UL<<30)
andrewhead 0:4df415dde990 77 #define DEV_INT (1UL<<31)
andrewhead 0:4df415dde990 78
andrewhead 0:4df415dde990 79 static volatile int epComplete = 0;
andrewhead 0:4df415dde990 80
andrewhead 0:4df415dde990 81 // One entry for a double-buffered logical endpoint in the endpoint
andrewhead 0:4df415dde990 82 // command/status list. Endpoint 0 is single buffered, out[1] is used
andrewhead 0:4df415dde990 83 // for the SETUP packet and in[1] is not used
andrewhead 0:4df415dde990 84 typedef __packed struct {
andrewhead 0:4df415dde990 85 uint32_t out[2];
andrewhead 0:4df415dde990 86 uint32_t in[2];
andrewhead 0:4df415dde990 87 } EP_COMMAND_STATUS;
andrewhead 0:4df415dde990 88
andrewhead 0:4df415dde990 89 typedef __packed struct {
andrewhead 0:4df415dde990 90 uint8_t out[MAX_PACKET_SIZE_EP0];
andrewhead 0:4df415dde990 91 uint8_t in[MAX_PACKET_SIZE_EP0];
andrewhead 0:4df415dde990 92 uint8_t setup[SETUP_PACKET_SIZE];
andrewhead 0:4df415dde990 93 } CONTROL_TRANSFER;
andrewhead 0:4df415dde990 94
andrewhead 0:4df415dde990 95 typedef __packed struct {
andrewhead 0:4df415dde990 96 uint32_t maxPacket;
andrewhead 0:4df415dde990 97 uint32_t buffer[2];
andrewhead 0:4df415dde990 98 uint32_t options;
andrewhead 0:4df415dde990 99 } EP_STATE;
andrewhead 0:4df415dde990 100
andrewhead 0:4df415dde990 101 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
andrewhead 0:4df415dde990 102
andrewhead 0:4df415dde990 103 // Pointer to the endpoint command/status list
andrewhead 0:4df415dde990 104 static EP_COMMAND_STATUS *ep = NULL;
andrewhead 0:4df415dde990 105
andrewhead 0:4df415dde990 106 // Pointer to endpoint 0 data (IN/OUT and SETUP)
andrewhead 0:4df415dde990 107 static CONTROL_TRANSFER *ct = NULL;
andrewhead 0:4df415dde990 108
andrewhead 0:4df415dde990 109 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
andrewhead 0:4df415dde990 110 // initiating a remote wakeup event.
andrewhead 0:4df415dde990 111 static volatile uint32_t devCmdStat;
andrewhead 0:4df415dde990 112
andrewhead 0:4df415dde990 113 // Pointers used to allocate USB RAM
andrewhead 0:4df415dde990 114 static uint32_t usbRamPtr = USB_RAM_START;
andrewhead 0:4df415dde990 115 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
andrewhead 0:4df415dde990 116
andrewhead 0:4df415dde990 117 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
andrewhead 0:4df415dde990 118
andrewhead 0:4df415dde990 119 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
andrewhead 0:4df415dde990 120 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
andrewhead 0:4df415dde990 121 if (size > 0) {
andrewhead 0:4df415dde990 122 do {
andrewhead 0:4df415dde990 123 *dst++ = *src++;
andrewhead 0:4df415dde990 124 } while (--size > 0);
andrewhead 0:4df415dde990 125 }
andrewhead 0:4df415dde990 126 }
andrewhead 0:4df415dde990 127
andrewhead 0:4df415dde990 128
andrewhead 0:4df415dde990 129 USBHAL::USBHAL(void) {
andrewhead 0:4df415dde990 130 NVIC_DisableIRQ(USB_IRQn);
andrewhead 0:4df415dde990 131
andrewhead 0:4df415dde990 132 // fill in callback array
andrewhead 0:4df415dde990 133 epCallback[0] = &USBHAL::EP1_OUT_callback;
andrewhead 0:4df415dde990 134 epCallback[1] = &USBHAL::EP1_IN_callback;
andrewhead 0:4df415dde990 135 epCallback[2] = &USBHAL::EP2_OUT_callback;
andrewhead 0:4df415dde990 136 epCallback[3] = &USBHAL::EP2_IN_callback;
andrewhead 0:4df415dde990 137 epCallback[4] = &USBHAL::EP3_OUT_callback;
andrewhead 0:4df415dde990 138 epCallback[5] = &USBHAL::EP3_IN_callback;
andrewhead 0:4df415dde990 139 epCallback[6] = &USBHAL::EP4_OUT_callback;
andrewhead 0:4df415dde990 140 epCallback[7] = &USBHAL::EP4_IN_callback;
andrewhead 0:4df415dde990 141
andrewhead 0:4df415dde990 142 // nUSB_CONNECT output
andrewhead 0:4df415dde990 143 LPC_IOCON->PIO0_6 = 0x00000001;
andrewhead 0:4df415dde990 144
andrewhead 0:4df415dde990 145 // Enable clocks (USB registers, USB RAM)
andrewhead 0:4df415dde990 146 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
andrewhead 0:4df415dde990 147
andrewhead 0:4df415dde990 148 // Ensure device disconnected (DCON not set)
andrewhead 0:4df415dde990 149 LPC_USB->DEVCMDSTAT = 0;
andrewhead 0:4df415dde990 150
andrewhead 0:4df415dde990 151 // to ensure that the USB host sees the device as
andrewhead 0:4df415dde990 152 // disconnected if the target CPU is reset.
andrewhead 0:4df415dde990 153 wait(0.3);
andrewhead 0:4df415dde990 154
andrewhead 0:4df415dde990 155 // Reserve space in USB RAM for endpoint command/status list
andrewhead 0:4df415dde990 156 // Must be 256 byte aligned
andrewhead 0:4df415dde990 157 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
andrewhead 0:4df415dde990 158 ep = (EP_COMMAND_STATUS *)usbRamPtr;
andrewhead 0:4df415dde990 159 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
andrewhead 0:4df415dde990 160 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
andrewhead 0:4df415dde990 161
andrewhead 0:4df415dde990 162 // Reserve space in USB RAM for Endpoint 0
andrewhead 0:4df415dde990 163 // Must be 64 byte aligned
andrewhead 0:4df415dde990 164 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
andrewhead 0:4df415dde990 165 ct = (CONTROL_TRANSFER *)usbRamPtr;
andrewhead 0:4df415dde990 166 usbRamPtr += sizeof(CONTROL_TRANSFER);
andrewhead 0:4df415dde990 167 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
andrewhead 0:4df415dde990 168
andrewhead 0:4df415dde990 169 // Setup command/status list for EP0
andrewhead 0:4df415dde990 170 ep[0].out[0] = 0;
andrewhead 0:4df415dde990 171 ep[0].in[0] = 0;
andrewhead 0:4df415dde990 172 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
andrewhead 0:4df415dde990 173
andrewhead 0:4df415dde990 174 // Route all interrupts to IRQ, some can be routed to
andrewhead 0:4df415dde990 175 // USB_FIQ if you wish.
andrewhead 0:4df415dde990 176 LPC_USB->INTROUTING = 0;
andrewhead 0:4df415dde990 177
andrewhead 0:4df415dde990 178 // Set device address 0, enable USB device, no remote wakeup
andrewhead 0:4df415dde990 179 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
andrewhead 0:4df415dde990 180 LPC_USB->DEVCMDSTAT = devCmdStat;
andrewhead 0:4df415dde990 181
andrewhead 0:4df415dde990 182 // Enable interrupts for device events and EP0
andrewhead 0:4df415dde990 183 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
andrewhead 0:4df415dde990 184 instance = this;
andrewhead 0:4df415dde990 185
andrewhead 0:4df415dde990 186 //attach IRQ handler and enable interrupts
andrewhead 0:4df415dde990 187 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
andrewhead 0:4df415dde990 188 }
andrewhead 0:4df415dde990 189
andrewhead 0:4df415dde990 190 USBHAL::~USBHAL(void) {
andrewhead 0:4df415dde990 191 // Ensure device disconnected (DCON not set)
andrewhead 0:4df415dde990 192 LPC_USB->DEVCMDSTAT = 0;
andrewhead 0:4df415dde990 193 // Disable USB interrupts
andrewhead 0:4df415dde990 194 NVIC_DisableIRQ(USB_IRQn);
andrewhead 0:4df415dde990 195 }
andrewhead 0:4df415dde990 196
andrewhead 0:4df415dde990 197 void USBHAL::connect(void) {
andrewhead 0:4df415dde990 198 NVIC_EnableIRQ(USB_IRQn);
andrewhead 0:4df415dde990 199 devCmdStat |= DCON;
andrewhead 0:4df415dde990 200 LPC_USB->DEVCMDSTAT = devCmdStat;
andrewhead 0:4df415dde990 201 }
andrewhead 0:4df415dde990 202
andrewhead 0:4df415dde990 203 void USBHAL::disconnect(void) {
andrewhead 0:4df415dde990 204 NVIC_DisableIRQ(USB_IRQn);
andrewhead 0:4df415dde990 205 devCmdStat &= ~DCON;
andrewhead 0:4df415dde990 206 LPC_USB->DEVCMDSTAT = devCmdStat;
andrewhead 0:4df415dde990 207 }
andrewhead 0:4df415dde990 208
andrewhead 0:4df415dde990 209 void USBHAL::configureDevice(void) {
andrewhead 0:4df415dde990 210 // Not required
andrewhead 0:4df415dde990 211 }
andrewhead 0:4df415dde990 212
andrewhead 0:4df415dde990 213 void USBHAL::unconfigureDevice(void) {
andrewhead 0:4df415dde990 214 // Not required
andrewhead 0:4df415dde990 215 }
andrewhead 0:4df415dde990 216
andrewhead 0:4df415dde990 217 void USBHAL::EP0setup(uint8_t *buffer) {
andrewhead 0:4df415dde990 218 // Copy setup packet data
andrewhead 0:4df415dde990 219 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
andrewhead 0:4df415dde990 220 }
andrewhead 0:4df415dde990 221
andrewhead 0:4df415dde990 222 void USBHAL::EP0read(void) {
andrewhead 0:4df415dde990 223 // Start an endpoint 0 read
andrewhead 0:4df415dde990 224
andrewhead 0:4df415dde990 225 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
andrewhead 0:4df415dde990 226 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
andrewhead 0:4df415dde990 227 // read the data.
andrewhead 0:4df415dde990 228
andrewhead 0:4df415dde990 229 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
andrewhead 0:4df415dde990 230 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
andrewhead 0:4df415dde990 231 }
andrewhead 0:4df415dde990 232
andrewhead 0:4df415dde990 233 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
andrewhead 0:4df415dde990 234 // Complete an endpoint 0 read
andrewhead 0:4df415dde990 235 uint32_t bytesRead;
andrewhead 0:4df415dde990 236
andrewhead 0:4df415dde990 237 // Find how many bytes were read
andrewhead 0:4df415dde990 238 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
andrewhead 0:4df415dde990 239
andrewhead 0:4df415dde990 240 // Copy data
andrewhead 0:4df415dde990 241 USBMemCopy(buffer, ct->out, bytesRead);
andrewhead 0:4df415dde990 242 return bytesRead;
andrewhead 0:4df415dde990 243 }
andrewhead 0:4df415dde990 244
andrewhead 0:4df415dde990 245
andrewhead 0:4df415dde990 246 void USBHAL::EP0readStage(void) {
andrewhead 0:4df415dde990 247 // Not required
andrewhead 0:4df415dde990 248 }
andrewhead 0:4df415dde990 249
andrewhead 0:4df415dde990 250 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
andrewhead 0:4df415dde990 251 // Start and endpoint 0 write
andrewhead 0:4df415dde990 252
andrewhead 0:4df415dde990 253 // The USB ISR will call USBDevice_EP0in() when the data has
andrewhead 0:4df415dde990 254 // been written, the USBDevice layer then calls
andrewhead 0:4df415dde990 255 // USBBusInterface_EP0getWriteResult() to complete the transaction.
andrewhead 0:4df415dde990 256
andrewhead 0:4df415dde990 257 // Copy data
andrewhead 0:4df415dde990 258 USBMemCopy(ct->in, buffer, size);
andrewhead 0:4df415dde990 259
andrewhead 0:4df415dde990 260 // Start transfer
andrewhead 0:4df415dde990 261 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
andrewhead 0:4df415dde990 262 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
andrewhead 0:4df415dde990 263 }
andrewhead 0:4df415dde990 264
andrewhead 0:4df415dde990 265
andrewhead 0:4df415dde990 266 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
andrewhead 0:4df415dde990 267 uint8_t bf = 0;
andrewhead 0:4df415dde990 268 uint32_t flags = 0;
andrewhead 0:4df415dde990 269
andrewhead 0:4df415dde990 270 //check which buffer must be filled
andrewhead 0:4df415dde990 271 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
andrewhead 0:4df415dde990 272 // Double buffered
andrewhead 0:4df415dde990 273 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 274 bf = 1;
andrewhead 0:4df415dde990 275 } else {
andrewhead 0:4df415dde990 276 bf = 0;
andrewhead 0:4df415dde990 277 }
andrewhead 0:4df415dde990 278 }
andrewhead 0:4df415dde990 279
andrewhead 0:4df415dde990 280 // if isochronous endpoint, T = 1
andrewhead 0:4df415dde990 281 if(endpointState[endpoint].options & ISOCHRONOUS)
andrewhead 0:4df415dde990 282 {
andrewhead 0:4df415dde990 283 flags |= CMDSTS_T;
andrewhead 0:4df415dde990 284 }
andrewhead 0:4df415dde990 285
andrewhead 0:4df415dde990 286 //Active the endpoint for reading
andrewhead 0:4df415dde990 287 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
andrewhead 0:4df415dde990 288 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
andrewhead 0:4df415dde990 289 return EP_PENDING;
andrewhead 0:4df415dde990 290 }
andrewhead 0:4df415dde990 291
andrewhead 0:4df415dde990 292 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
andrewhead 0:4df415dde990 293
andrewhead 0:4df415dde990 294 uint8_t bf = 0;
andrewhead 0:4df415dde990 295
andrewhead 0:4df415dde990 296 if (!(epComplete & EP(endpoint)))
andrewhead 0:4df415dde990 297 return EP_PENDING;
andrewhead 0:4df415dde990 298 else {
andrewhead 0:4df415dde990 299 epComplete &= ~EP(endpoint);
andrewhead 0:4df415dde990 300
andrewhead 0:4df415dde990 301 //check which buffer has been filled
andrewhead 0:4df415dde990 302 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
andrewhead 0:4df415dde990 303 // Double buffered (here we read the previous buffer which was used)
andrewhead 0:4df415dde990 304 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 305 bf = 0;
andrewhead 0:4df415dde990 306 } else {
andrewhead 0:4df415dde990 307 bf = 1;
andrewhead 0:4df415dde990 308 }
andrewhead 0:4df415dde990 309 }
andrewhead 0:4df415dde990 310
andrewhead 0:4df415dde990 311 // Find how many bytes were read
andrewhead 0:4df415dde990 312 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
andrewhead 0:4df415dde990 313
andrewhead 0:4df415dde990 314 // Copy data
andrewhead 0:4df415dde990 315 USBMemCopy(data, ct->out, *bytesRead);
andrewhead 0:4df415dde990 316 return EP_COMPLETED;
andrewhead 0:4df415dde990 317 }
andrewhead 0:4df415dde990 318 }
andrewhead 0:4df415dde990 319
andrewhead 0:4df415dde990 320 void USBHAL::EP0getWriteResult(void) {
andrewhead 0:4df415dde990 321 // Not required
andrewhead 0:4df415dde990 322 }
andrewhead 0:4df415dde990 323
andrewhead 0:4df415dde990 324 void USBHAL::EP0stall(void) {
andrewhead 0:4df415dde990 325 ep[0].in[0] = CMDSTS_S;
andrewhead 0:4df415dde990 326 ep[0].out[0] = CMDSTS_S;
andrewhead 0:4df415dde990 327 }
andrewhead 0:4df415dde990 328
andrewhead 0:4df415dde990 329 void USBHAL::setAddress(uint8_t address) {
andrewhead 0:4df415dde990 330 devCmdStat &= ~DEV_ADDR_MASK;
andrewhead 0:4df415dde990 331 devCmdStat |= DEV_ADDR(address);
andrewhead 0:4df415dde990 332 LPC_USB->DEVCMDSTAT = devCmdStat;
andrewhead 0:4df415dde990 333 }
andrewhead 0:4df415dde990 334
andrewhead 0:4df415dde990 335 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
andrewhead 0:4df415dde990 336 uint32_t flags = 0;
andrewhead 0:4df415dde990 337 uint32_t bf;
andrewhead 0:4df415dde990 338
andrewhead 0:4df415dde990 339 // Validate parameters
andrewhead 0:4df415dde990 340 if (data == NULL) {
andrewhead 0:4df415dde990 341 return EP_INVALID;
andrewhead 0:4df415dde990 342 }
andrewhead 0:4df415dde990 343
andrewhead 0:4df415dde990 344 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
andrewhead 0:4df415dde990 345 return EP_INVALID;
andrewhead 0:4df415dde990 346 }
andrewhead 0:4df415dde990 347
andrewhead 0:4df415dde990 348 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
andrewhead 0:4df415dde990 349 return EP_INVALID;
andrewhead 0:4df415dde990 350 }
andrewhead 0:4df415dde990 351
andrewhead 0:4df415dde990 352 if (size > endpointState[endpoint].maxPacket) {
andrewhead 0:4df415dde990 353 return EP_INVALID;
andrewhead 0:4df415dde990 354 }
andrewhead 0:4df415dde990 355
andrewhead 0:4df415dde990 356 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
andrewhead 0:4df415dde990 357 // Double buffered
andrewhead 0:4df415dde990 358 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 359 bf = 1;
andrewhead 0:4df415dde990 360 } else {
andrewhead 0:4df415dde990 361 bf = 0;
andrewhead 0:4df415dde990 362 }
andrewhead 0:4df415dde990 363 } else {
andrewhead 0:4df415dde990 364 // Single buffered
andrewhead 0:4df415dde990 365 bf = 0;
andrewhead 0:4df415dde990 366 }
andrewhead 0:4df415dde990 367
andrewhead 0:4df415dde990 368 // Check if already active
andrewhead 0:4df415dde990 369 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
andrewhead 0:4df415dde990 370 return EP_INVALID;
andrewhead 0:4df415dde990 371 }
andrewhead 0:4df415dde990 372
andrewhead 0:4df415dde990 373 // Check if stalled
andrewhead 0:4df415dde990 374 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
andrewhead 0:4df415dde990 375 return EP_STALLED;
andrewhead 0:4df415dde990 376 }
andrewhead 0:4df415dde990 377
andrewhead 0:4df415dde990 378 // Copy data to USB RAM
andrewhead 0:4df415dde990 379 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
andrewhead 0:4df415dde990 380
andrewhead 0:4df415dde990 381 // Add options
andrewhead 0:4df415dde990 382 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
andrewhead 0:4df415dde990 383 flags |= CMDSTS_RF;
andrewhead 0:4df415dde990 384 }
andrewhead 0:4df415dde990 385
andrewhead 0:4df415dde990 386 if (endpointState[endpoint].options & ISOCHRONOUS) {
andrewhead 0:4df415dde990 387 flags |= CMDSTS_T;
andrewhead 0:4df415dde990 388 }
andrewhead 0:4df415dde990 389
andrewhead 0:4df415dde990 390 // Add transfer
andrewhead 0:4df415dde990 391 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
andrewhead 0:4df415dde990 392 endpointState[endpoint].buffer[bf]) \
andrewhead 0:4df415dde990 393 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
andrewhead 0:4df415dde990 394
andrewhead 0:4df415dde990 395 return EP_PENDING;
andrewhead 0:4df415dde990 396 }
andrewhead 0:4df415dde990 397
andrewhead 0:4df415dde990 398 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
andrewhead 0:4df415dde990 399 uint32_t bf;
andrewhead 0:4df415dde990 400
andrewhead 0:4df415dde990 401 // Validate parameters
andrewhead 0:4df415dde990 402 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
andrewhead 0:4df415dde990 403 return EP_INVALID;
andrewhead 0:4df415dde990 404 }
andrewhead 0:4df415dde990 405
andrewhead 0:4df415dde990 406 if (OUT_EP(endpoint)) {
andrewhead 0:4df415dde990 407 return EP_INVALID;
andrewhead 0:4df415dde990 408 }
andrewhead 0:4df415dde990 409
andrewhead 0:4df415dde990 410 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
andrewhead 0:4df415dde990 411 // Double buffered // TODO: FIX THIS
andrewhead 0:4df415dde990 412 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 413 bf = 1;
andrewhead 0:4df415dde990 414 } else {
andrewhead 0:4df415dde990 415 bf = 0;
andrewhead 0:4df415dde990 416 }
andrewhead 0:4df415dde990 417 } else {
andrewhead 0:4df415dde990 418 // Single buffered
andrewhead 0:4df415dde990 419 bf = 0;
andrewhead 0:4df415dde990 420 }
andrewhead 0:4df415dde990 421
andrewhead 0:4df415dde990 422 // Check if endpoint still active
andrewhead 0:4df415dde990 423 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
andrewhead 0:4df415dde990 424 return EP_PENDING;
andrewhead 0:4df415dde990 425 }
andrewhead 0:4df415dde990 426
andrewhead 0:4df415dde990 427 // Check if stalled
andrewhead 0:4df415dde990 428 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
andrewhead 0:4df415dde990 429 return EP_STALLED;
andrewhead 0:4df415dde990 430 }
andrewhead 0:4df415dde990 431
andrewhead 0:4df415dde990 432 return EP_COMPLETED;
andrewhead 0:4df415dde990 433 }
andrewhead 0:4df415dde990 434
andrewhead 0:4df415dde990 435 void USBHAL::stallEndpoint(uint8_t endpoint) {
andrewhead 0:4df415dde990 436
andrewhead 0:4df415dde990 437 // FIX: should this clear active bit?
andrewhead 0:4df415dde990 438 if (IN_EP(endpoint)) {
andrewhead 0:4df415dde990 439 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
andrewhead 0:4df415dde990 440 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
andrewhead 0:4df415dde990 441 } else {
andrewhead 0:4df415dde990 442 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
andrewhead 0:4df415dde990 443 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
andrewhead 0:4df415dde990 444 }
andrewhead 0:4df415dde990 445 }
andrewhead 0:4df415dde990 446
andrewhead 0:4df415dde990 447 void USBHAL::unstallEndpoint(uint8_t endpoint) {
andrewhead 0:4df415dde990 448 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
andrewhead 0:4df415dde990 449 // Double buffered
andrewhead 0:4df415dde990 450 if (IN_EP(endpoint)) {
andrewhead 0:4df415dde990 451 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
andrewhead 0:4df415dde990 452 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
andrewhead 0:4df415dde990 453
andrewhead 0:4df415dde990 454 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 455 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
andrewhead 0:4df415dde990 456 } else {
andrewhead 0:4df415dde990 457 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
andrewhead 0:4df415dde990 458 }
andrewhead 0:4df415dde990 459 } else {
andrewhead 0:4df415dde990 460 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
andrewhead 0:4df415dde990 461 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
andrewhead 0:4df415dde990 462
andrewhead 0:4df415dde990 463 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 464 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
andrewhead 0:4df415dde990 465 } else {
andrewhead 0:4df415dde990 466 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
andrewhead 0:4df415dde990 467 }
andrewhead 0:4df415dde990 468 }
andrewhead 0:4df415dde990 469 } else {
andrewhead 0:4df415dde990 470 // Single buffered
andrewhead 0:4df415dde990 471 if (IN_EP(endpoint)) {
andrewhead 0:4df415dde990 472 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
andrewhead 0:4df415dde990 473 } else {
andrewhead 0:4df415dde990 474 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
andrewhead 0:4df415dde990 475 }
andrewhead 0:4df415dde990 476 }
andrewhead 0:4df415dde990 477 }
andrewhead 0:4df415dde990 478
andrewhead 0:4df415dde990 479 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
andrewhead 0:4df415dde990 480 if (IN_EP(endpoint)) {
andrewhead 0:4df415dde990 481 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 482 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
andrewhead 0:4df415dde990 483 return true;
andrewhead 0:4df415dde990 484 }
andrewhead 0:4df415dde990 485 } else {
andrewhead 0:4df415dde990 486 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
andrewhead 0:4df415dde990 487 return true;
andrewhead 0:4df415dde990 488 }
andrewhead 0:4df415dde990 489 }
andrewhead 0:4df415dde990 490 } else {
andrewhead 0:4df415dde990 491 if (LPC_USB->EPINUSE & EP(endpoint)) {
andrewhead 0:4df415dde990 492 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
andrewhead 0:4df415dde990 493 return true;
andrewhead 0:4df415dde990 494 }
andrewhead 0:4df415dde990 495 } else {
andrewhead 0:4df415dde990 496 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
andrewhead 0:4df415dde990 497 return true;
andrewhead 0:4df415dde990 498 }
andrewhead 0:4df415dde990 499 }
andrewhead 0:4df415dde990 500 }
andrewhead 0:4df415dde990 501
andrewhead 0:4df415dde990 502 return false;
andrewhead 0:4df415dde990 503 }
andrewhead 0:4df415dde990 504
andrewhead 0:4df415dde990 505 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
andrewhead 0:4df415dde990 506 uint32_t tmpEpRamPtr;
andrewhead 0:4df415dde990 507
andrewhead 0:4df415dde990 508 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
andrewhead 0:4df415dde990 509 return false;
andrewhead 0:4df415dde990 510 }
andrewhead 0:4df415dde990 511
andrewhead 0:4df415dde990 512 // Not applicable to the control endpoints
andrewhead 0:4df415dde990 513 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
andrewhead 0:4df415dde990 514 return false;
andrewhead 0:4df415dde990 515 }
andrewhead 0:4df415dde990 516
andrewhead 0:4df415dde990 517 // Allocate buffers in USB RAM
andrewhead 0:4df415dde990 518 tmpEpRamPtr = epRamPtr;
andrewhead 0:4df415dde990 519
andrewhead 0:4df415dde990 520 // Must be 64 byte aligned
andrewhead 0:4df415dde990 521 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
andrewhead 0:4df415dde990 522
andrewhead 0:4df415dde990 523 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
andrewhead 0:4df415dde990 524 // Out of memory
andrewhead 0:4df415dde990 525 return false;
andrewhead 0:4df415dde990 526 }
andrewhead 0:4df415dde990 527
andrewhead 0:4df415dde990 528 // Allocate first buffer
andrewhead 0:4df415dde990 529 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
andrewhead 0:4df415dde990 530 tmpEpRamPtr += maxPacket;
andrewhead 0:4df415dde990 531
andrewhead 0:4df415dde990 532 if (!(options & SINGLE_BUFFERED)) {
andrewhead 0:4df415dde990 533 // Must be 64 byte aligned
andrewhead 0:4df415dde990 534 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
andrewhead 0:4df415dde990 535
andrewhead 0:4df415dde990 536 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
andrewhead 0:4df415dde990 537 // Out of memory
andrewhead 0:4df415dde990 538 return false;
andrewhead 0:4df415dde990 539 }
andrewhead 0:4df415dde990 540
andrewhead 0:4df415dde990 541 // Allocate second buffer
andrewhead 0:4df415dde990 542 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
andrewhead 0:4df415dde990 543 tmpEpRamPtr += maxPacket;
andrewhead 0:4df415dde990 544 }
andrewhead 0:4df415dde990 545
andrewhead 0:4df415dde990 546 // Commit to this USB RAM allocation
andrewhead 0:4df415dde990 547 epRamPtr = tmpEpRamPtr;
andrewhead 0:4df415dde990 548
andrewhead 0:4df415dde990 549 // Remaining endpoint state values
andrewhead 0:4df415dde990 550 endpointState[endpoint].maxPacket = maxPacket;
andrewhead 0:4df415dde990 551 endpointState[endpoint].options = options;
andrewhead 0:4df415dde990 552
andrewhead 0:4df415dde990 553 // Enable double buffering if required
andrewhead 0:4df415dde990 554 if (options & SINGLE_BUFFERED) {
andrewhead 0:4df415dde990 555 LPC_USB->EPBUFCFG &= ~EP(endpoint);
andrewhead 0:4df415dde990 556 } else {
andrewhead 0:4df415dde990 557 // Double buffered
andrewhead 0:4df415dde990 558 LPC_USB->EPBUFCFG |= EP(endpoint);
andrewhead 0:4df415dde990 559 }
andrewhead 0:4df415dde990 560
andrewhead 0:4df415dde990 561 // Enable interrupt
andrewhead 0:4df415dde990 562 LPC_USB->INTEN |= EP(endpoint);
andrewhead 0:4df415dde990 563
andrewhead 0:4df415dde990 564 // Enable endpoint
andrewhead 0:4df415dde990 565 unstallEndpoint(endpoint);
andrewhead 0:4df415dde990 566 return true;
andrewhead 0:4df415dde990 567 }
andrewhead 0:4df415dde990 568
andrewhead 0:4df415dde990 569 void USBHAL::remoteWakeup(void) {
andrewhead 0:4df415dde990 570 // Clearing DSUS bit initiates a remote wakeup if the
andrewhead 0:4df415dde990 571 // device is currently enabled and suspended - otherwise
andrewhead 0:4df415dde990 572 // it has no effect.
andrewhead 0:4df415dde990 573 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
andrewhead 0:4df415dde990 574 }
andrewhead 0:4df415dde990 575
andrewhead 0:4df415dde990 576
andrewhead 0:4df415dde990 577 static void disableEndpoints(void) {
andrewhead 0:4df415dde990 578 uint32_t logEp;
andrewhead 0:4df415dde990 579
andrewhead 0:4df415dde990 580 // Ref. Table 158 "When a bus reset is received, software
andrewhead 0:4df415dde990 581 // must set the disable bit of all endpoints to 1".
andrewhead 0:4df415dde990 582
andrewhead 0:4df415dde990 583 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
andrewhead 0:4df415dde990 584 ep[logEp].out[0] = CMDSTS_D;
andrewhead 0:4df415dde990 585 ep[logEp].out[1] = CMDSTS_D;
andrewhead 0:4df415dde990 586 ep[logEp].in[0] = CMDSTS_D;
andrewhead 0:4df415dde990 587 ep[logEp].in[1] = CMDSTS_D;
andrewhead 0:4df415dde990 588 }
andrewhead 0:4df415dde990 589
andrewhead 0:4df415dde990 590 // Start of USB RAM for endpoints > 0
andrewhead 0:4df415dde990 591 epRamPtr = usbRamPtr;
andrewhead 0:4df415dde990 592 }
andrewhead 0:4df415dde990 593
andrewhead 0:4df415dde990 594
andrewhead 0:4df415dde990 595
andrewhead 0:4df415dde990 596 void USBHAL::_usbisr(void) {
andrewhead 0:4df415dde990 597 instance->usbisr();
andrewhead 0:4df415dde990 598 }
andrewhead 0:4df415dde990 599
andrewhead 0:4df415dde990 600 void USBHAL::usbisr(void) {
andrewhead 0:4df415dde990 601 // Start of frame
andrewhead 0:4df415dde990 602 if (LPC_USB->INTSTAT & FRAME_INT) {
andrewhead 0:4df415dde990 603 // Clear SOF interrupt
andrewhead 0:4df415dde990 604 LPC_USB->INTSTAT = FRAME_INT;
andrewhead 0:4df415dde990 605
andrewhead 0:4df415dde990 606 // SOF event, read frame number
andrewhead 0:4df415dde990 607 SOF(FRAME_NR(LPC_USB->INFO));
andrewhead 0:4df415dde990 608 }
andrewhead 0:4df415dde990 609
andrewhead 0:4df415dde990 610 // Device state
andrewhead 0:4df415dde990 611 if (LPC_USB->INTSTAT & DEV_INT) {
andrewhead 0:4df415dde990 612 LPC_USB->INTSTAT = DEV_INT;
andrewhead 0:4df415dde990 613
andrewhead 0:4df415dde990 614 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
andrewhead 0:4df415dde990 615 // Suspend status changed
andrewhead 0:4df415dde990 616 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
andrewhead 0:4df415dde990 617 if((LPC_USB->DEVCMDSTAT & DSUS) != 0) {
andrewhead 0:4df415dde990 618 suspendStateChanged(1);
andrewhead 0:4df415dde990 619 }
andrewhead 0:4df415dde990 620 }
andrewhead 0:4df415dde990 621
andrewhead 0:4df415dde990 622 if (LPC_USB->DEVCMDSTAT & DRES_C) {
andrewhead 0:4df415dde990 623 // Bus reset
andrewhead 0:4df415dde990 624 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
andrewhead 0:4df415dde990 625
andrewhead 0:4df415dde990 626 suspendStateChanged(0);
andrewhead 0:4df415dde990 627
andrewhead 0:4df415dde990 628 // Disable endpoints > 0
andrewhead 0:4df415dde990 629 disableEndpoints();
andrewhead 0:4df415dde990 630
andrewhead 0:4df415dde990 631 // Bus reset event
andrewhead 0:4df415dde990 632 busReset();
andrewhead 0:4df415dde990 633 }
andrewhead 0:4df415dde990 634 }
andrewhead 0:4df415dde990 635
andrewhead 0:4df415dde990 636 // Endpoint 0
andrewhead 0:4df415dde990 637 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
andrewhead 0:4df415dde990 638 // Clear EP0OUT/SETUP interrupt
andrewhead 0:4df415dde990 639 LPC_USB->INTSTAT = EP(EP0OUT);
andrewhead 0:4df415dde990 640
andrewhead 0:4df415dde990 641 // Check if SETUP
andrewhead 0:4df415dde990 642 if (LPC_USB->DEVCMDSTAT & SETUP) {
andrewhead 0:4df415dde990 643 // Clear Active and Stall bits for EP0
andrewhead 0:4df415dde990 644 // Documentation does not make it clear if we must use the
andrewhead 0:4df415dde990 645 // EPSKIP register to achieve this, Fig. 16 and NXP reference
andrewhead 0:4df415dde990 646 // code suggests we can just clear the Active bits - check with
andrewhead 0:4df415dde990 647 // NXP to be sure.
andrewhead 0:4df415dde990 648 ep[0].in[0] = 0;
andrewhead 0:4df415dde990 649 ep[0].out[0] = 0;
andrewhead 0:4df415dde990 650
andrewhead 0:4df415dde990 651 // Clear EP0IN interrupt
andrewhead 0:4df415dde990 652 LPC_USB->INTSTAT = EP(EP0IN);
andrewhead 0:4df415dde990 653
andrewhead 0:4df415dde990 654 // Clear SETUP (and INTONNAK_CI/O) in device status register
andrewhead 0:4df415dde990 655 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
andrewhead 0:4df415dde990 656
andrewhead 0:4df415dde990 657 // EP0 SETUP event (SETUP data received)
andrewhead 0:4df415dde990 658 EP0setupCallback();
andrewhead 0:4df415dde990 659 } else {
andrewhead 0:4df415dde990 660 // EP0OUT ACK event (OUT data received)
andrewhead 0:4df415dde990 661 EP0out();
andrewhead 0:4df415dde990 662 }
andrewhead 0:4df415dde990 663 }
andrewhead 0:4df415dde990 664
andrewhead 0:4df415dde990 665 if (LPC_USB->INTSTAT & EP(EP0IN)) {
andrewhead 0:4df415dde990 666 // Clear EP0IN interrupt
andrewhead 0:4df415dde990 667 LPC_USB->INTSTAT = EP(EP0IN);
andrewhead 0:4df415dde990 668
andrewhead 0:4df415dde990 669 // EP0IN ACK event (IN data sent)
andrewhead 0:4df415dde990 670 EP0in();
andrewhead 0:4df415dde990 671 }
andrewhead 0:4df415dde990 672
andrewhead 0:4df415dde990 673 for (uint8_t num = 2; num < 5*2; num++) {
andrewhead 0:4df415dde990 674 if (LPC_USB->INTSTAT & EP(num)) {
andrewhead 0:4df415dde990 675 LPC_USB->INTSTAT = EP(num);
andrewhead 0:4df415dde990 676 epComplete |= EP(num);
andrewhead 0:4df415dde990 677 if ((instance->*(epCallback[num - 2]))()) {
andrewhead 0:4df415dde990 678 epComplete &= ~EP(num);
andrewhead 0:4df415dde990 679 }
andrewhead 0:4df415dde990 680 }
andrewhead 0:4df415dde990 681 }
andrewhead 0:4df415dde990 682 }
andrewhead 0:4df415dde990 683
andrewhead 0:4df415dde990 684 #endif