Basic fram test for spi connectivity
Dependencies: mbed
main.cpp@2:d11473ce92d6, 2015-01-30 (annotated)
- Committer:
- smigielski
- Date:
- Fri Jan 30 22:38:04 2015 +0000
- Revision:
- 2:d11473ce92d6
- Parent:
- 1:711a282f7332
- Child:
- 3:f71a526212cc
Make cs switch after each command
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
smigielski | 0:94b74988d717 | 1 | #include "mbed.h" |
smigielski | 0:94b74988d717 | 2 | |
smigielski | 1:711a282f7332 | 3 | SPI spi(P0_02, P0_03, P0_04); // mosi, miso, sclk |
smigielski | 1:711a282f7332 | 4 | DigitalOut cs(P0_30); |
smigielski | 1:711a282f7332 | 5 | DigitalOut hold(P0_01); |
smigielski | 0:94b74988d717 | 6 | |
smigielski | 0:94b74988d717 | 7 | |
smigielski | 0:94b74988d717 | 8 | // ACC Registers |
smigielski | 0:94b74988d717 | 9 | #define FM25CL_WREN 0x06 |
smigielski | 0:94b74988d717 | 10 | #define FM25CL_WRDI 0x04 |
smigielski | 0:94b74988d717 | 11 | #define FM25CL_RDSR 0x05 |
smigielski | 0:94b74988d717 | 12 | #define FM25CL_WRSR 0x01 |
smigielski | 0:94b74988d717 | 13 | #define FM25CL_READ 0x03 |
smigielski | 0:94b74988d717 | 14 | #define FM25CL_WRITE 0x02 |
smigielski | 0:94b74988d717 | 15 | |
smigielski | 0:94b74988d717 | 16 | #define TEST_LENGTH 4 |
smigielski | 0:94b74988d717 | 17 | |
smigielski | 2:d11473ce92d6 | 18 | void readRegister(){ |
smigielski | 0:94b74988d717 | 19 | cs = 0; |
smigielski | 0:94b74988d717 | 20 | spi.write(FM25CL_RDSR); |
smigielski | 0:94b74988d717 | 21 | //should be 0x00 |
smigielski | 0:94b74988d717 | 22 | uint8_t val_register = spi.write(0x00); |
smigielski | 2:d11473ce92d6 | 23 | cs = 1; |
smigielski | 2:d11473ce92d6 | 24 | } |
smigielski | 2:d11473ce92d6 | 25 | void enableWrite(){ |
smigielski | 2:d11473ce92d6 | 26 | cs = 0; |
smigielski | 0:94b74988d717 | 27 | spi.write(FM25CL_WREN); |
smigielski | 2:d11473ce92d6 | 28 | cs = 1; |
smigielski | 2:d11473ce92d6 | 29 | } |
smigielski | 2:d11473ce92d6 | 30 | void writeMemory(){ |
smigielski | 2:d11473ce92d6 | 31 | cs = 0; |
smigielski | 0:94b74988d717 | 32 | spi.write(FM25CL_WRITE); |
smigielski | 0:94b74988d717 | 33 | spi.write(0x00); |
smigielski | 0:94b74988d717 | 34 | spi.write(0x00); |
smigielski | 0:94b74988d717 | 35 | for (uint8_t i=0;i<TEST_LENGTH;i++){ |
smigielski | 0:94b74988d717 | 36 | spi.write(i); |
smigielski | 0:94b74988d717 | 37 | } |
smigielski | 0:94b74988d717 | 38 | cs = 1; |
smigielski | 0:94b74988d717 | 39 | } |
smigielski | 0:94b74988d717 | 40 | void readMemory(){ |
smigielski | 0:94b74988d717 | 41 | cs = 0; |
smigielski | 0:94b74988d717 | 42 | spi.write(FM25CL_READ); |
smigielski | 0:94b74988d717 | 43 | spi.write(0x00); |
smigielski | 0:94b74988d717 | 44 | spi.write(0x00); |
smigielski | 0:94b74988d717 | 45 | //should be next increments up to test_length |
smigielski | 0:94b74988d717 | 46 | for (uint8_t i=0;i<TEST_LENGTH;i++){ |
smigielski | 0:94b74988d717 | 47 | uint8_t data = spi.write(0x00); |
smigielski | 0:94b74988d717 | 48 | } |
smigielski | 0:94b74988d717 | 49 | cs = 1; |
smigielski | 0:94b74988d717 | 50 | } |
smigielski | 0:94b74988d717 | 51 | |
smigielski | 0:94b74988d717 | 52 | //Test that spi is working with fram FM25CL memory |
smigielski | 0:94b74988d717 | 53 | int main() { |
smigielski | 0:94b74988d717 | 54 | hold=1; |
smigielski | 0:94b74988d717 | 55 | cs=1; |
smigielski | 0:94b74988d717 | 56 | while(1) { |
smigielski | 2:d11473ce92d6 | 57 | readRegister(); |
smigielski | 2:d11473ce92d6 | 58 | enableWrite(); |
smigielski | 2:d11473ce92d6 | 59 | readRegister(); |
smigielski | 2:d11473ce92d6 | 60 | writeMemory(); |
smigielski | 2:d11473ce92d6 | 61 | readRegister(); |
smigielski | 0:94b74988d717 | 62 | readMemory(); |
smigielski | 0:94b74988d717 | 63 | wait(0.5); |
smigielski | 0:94b74988d717 | 64 | } |
smigielski | 0:94b74988d717 | 65 | } |
smigielski | 0:94b74988d717 | 66 |