Diff: Nucleo_Encoder_16_bits.cpp

Revision:

1:e82009479b5c

Parent:

0:ebd170807e11

Child:

2:916d277f09a1

--- a/Nucleo_Encoder_16_bits.cpp	Sun May 22 19:59:18 2016 +0000
+++ b/Nucleo_Encoder_16_bits.cpp	Thu May 26 16:21:43 2016 +0000
@@ -54,6 +54,51 @@
 
 namespace mbed
 {   
+
+    Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM)
+    {
+        TIM = _TIM;
+        // Initialisation of the TIM module as an encoder counter
+        EncoderInit(&encoder, &timer, _TIM, 0xffff, TIM_ENCODERMODE_TI12);
+
+        // Update (aka over- and underflow) interrupt enabled
+        TIM->DIER |= 0x0001;
+        // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
+        TIM->SR &= 0xfffe;
+
+        // Setting the ISR for the corresponding interrupt vector
+        switch((uint32_t)TIM)
+        {
+            case TIM2_BASE :
+            NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
+            NVIC_EnableIRQ(TIM2_IRQn);
+            Soft_32_Counter_TIM2 = 0;
+            break;
+            
+            case TIM3_BASE :
+            NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
+            NVIC_EnableIRQ(TIM3_IRQn);
+            Soft_32_Counter_TIM3 = 0;
+            break;
+            
+            case TIM4_BASE :
+            NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
+            NVIC_EnableIRQ(TIM4_IRQn);
+            Soft_32_Counter_TIM4 = 0;
+            break;
+            
+            case TIM5_BASE :
+            NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
+            NVIC_EnableIRQ(TIM5_IRQn);
+            Soft_32_Counter_TIM5 = 0;
+            break;
+            
+            default :
+            
+            break;
+        }
+        
+    }
     Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
     {
         TIM = _TIM;