IUT DE CACHAN GE1 / Encoder_Nucleo_16_bits

Modification du la bibliothèque de base

Fork of Encoder_Nucleo_32_bits by Pierre David

Nucleo_Encoder_16_bits.cpp@0:ebd170807e11, 2016-05-22 (annotated)

Committer:
kkoichy
Date:
Sun May 22 19:59:18 2016 +0000
Revision:
0:ebd170807e11
Child:
1:e82009479b5c
V1.0 :; - Objet Encoder_Nucleo_16_bits created, allowing 32bits encoder counting operation, based on a software 32bits counter, using a 16bits TIM with interrupt.; Based on the work of David Lowe

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kkoichy 0:ebd170807e11 1 #include "Nucleo_Encoder_16_bits.h"
kkoichy 0:ebd170807e11 2
kkoichy 0:ebd170807e11 3 int32_t Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
kkoichy 0:ebd170807e11 4
kkoichy 0:ebd170807e11 5 void Overflow_Routine_TIM2()
kkoichy 0:ebd170807e11 6 {
kkoichy 0:ebd170807e11 7 if(TIM2->SR & 0x0001)
kkoichy 0:ebd170807e11 8 {
kkoichy 0:ebd170807e11 9 printf("Overflow Routine");
kkoichy 0:ebd170807e11 10 TIM2->SR &= 0xfffe;
kkoichy 0:ebd170807e11 11 if(!(TIM2->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 12 Soft_32_Counter_TIM2 += 0xffff;
kkoichy 0:ebd170807e11 13 else
kkoichy 0:ebd170807e11 14 Soft_32_Counter_TIM2 -= 0xffff;
kkoichy 0:ebd170807e11 15 }
kkoichy 0:ebd170807e11 16 }
kkoichy 0:ebd170807e11 17
kkoichy 0:ebd170807e11 18 void Overflow_Routine_TIM3()
kkoichy 0:ebd170807e11 19 {
kkoichy 0:ebd170807e11 20 if(TIM3->SR & 0x0001)
kkoichy 0:ebd170807e11 21 {
kkoichy 0:ebd170807e11 22 printf("Overflow Routine");
kkoichy 0:ebd170807e11 23 TIM3->SR &= 0xfffe;
kkoichy 0:ebd170807e11 24 if(!(TIM3->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 25 Soft_32_Counter_TIM3 += 0xffff;
kkoichy 0:ebd170807e11 26 else
kkoichy 0:ebd170807e11 27 Soft_32_Counter_TIM3 -= 0xffff;
kkoichy 0:ebd170807e11 28 }
kkoichy 0:ebd170807e11 29 }
kkoichy 0:ebd170807e11 30 void Overflow_Routine_TIM4()
kkoichy 0:ebd170807e11 31 {
kkoichy 0:ebd170807e11 32 if(TIM4->SR & 0x0001)
kkoichy 0:ebd170807e11 33 {
kkoichy 0:ebd170807e11 34 printf("Overflow Routine");
kkoichy 0:ebd170807e11 35 TIM4->SR &= 0xfffe;
kkoichy 0:ebd170807e11 36 if(!(TIM4->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 37 Soft_32_Counter_TIM4 += 0xffff;
kkoichy 0:ebd170807e11 38 else
kkoichy 0:ebd170807e11 39 Soft_32_Counter_TIM4 -= 0xffff;
kkoichy 0:ebd170807e11 40 }
kkoichy 0:ebd170807e11 41 }
kkoichy 0:ebd170807e11 42 void Overflow_Routine_TIM5()
kkoichy 0:ebd170807e11 43 {
kkoichy 0:ebd170807e11 44 if(TIM5->SR & 0x0001)
kkoichy 0:ebd170807e11 45 {
kkoichy 0:ebd170807e11 46 printf("Overflow Routine");
kkoichy 0:ebd170807e11 47 TIM5->SR &= 0xfffe;
kkoichy 0:ebd170807e11 48 if(!(TIM5->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 49 Soft_32_Counter_TIM5 += 0xffff;
kkoichy 0:ebd170807e11 50 else
kkoichy 0:ebd170807e11 51 Soft_32_Counter_TIM5 -= 0xffff;
kkoichy 0:ebd170807e11 52 }
kkoichy 0:ebd170807e11 53 }
kkoichy 0:ebd170807e11 54
kkoichy 0:ebd170807e11 55 namespace mbed
kkoichy 0:ebd170807e11 56 {
kkoichy 0:ebd170807e11 57 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 58 {
kkoichy 0:ebd170807e11 59 TIM = _TIM;
kkoichy 0:ebd170807e11 60 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 61 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 62
kkoichy 0:ebd170807e11 63 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 64 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 65 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 66 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 67
kkoichy 0:ebd170807e11 68 // Setting the ISR for the corresponding interrupt vector
kkoichy 0:ebd170807e11 69 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 70 {
kkoichy 0:ebd170807e11 71 case TIM2_BASE :
kkoichy 0:ebd170807e11 72 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 0:ebd170807e11 73 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 0:ebd170807e11 74 Soft_32_Counter_TIM2 = 0;
kkoichy 0:ebd170807e11 75 break;
kkoichy 0:ebd170807e11 76
kkoichy 0:ebd170807e11 77 case TIM3_BASE :
kkoichy 0:ebd170807e11 78 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 0:ebd170807e11 79 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 0:ebd170807e11 80 Soft_32_Counter_TIM3 = 0;
kkoichy 0:ebd170807e11 81 break;
kkoichy 0:ebd170807e11 82
kkoichy 0:ebd170807e11 83 case TIM4_BASE :
kkoichy 0:ebd170807e11 84 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 0:ebd170807e11 85 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 0:ebd170807e11 86 Soft_32_Counter_TIM4 = 0;
kkoichy 0:ebd170807e11 87 break;
kkoichy 0:ebd170807e11 88
kkoichy 0:ebd170807e11 89 case TIM5_BASE :
kkoichy 0:ebd170807e11 90 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 0:ebd170807e11 91 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 0:ebd170807e11 92 Soft_32_Counter_TIM5 = 0;
kkoichy 0:ebd170807e11 93 break;
kkoichy 0:ebd170807e11 94
kkoichy 0:ebd170807e11 95 default :
kkoichy 0:ebd170807e11 96
kkoichy 0:ebd170807e11 97 break;
kkoichy 0:ebd170807e11 98 }
kkoichy 0:ebd170807e11 99
kkoichy 0:ebd170807e11 100 }
kkoichy 0:ebd170807e11 101
kkoichy 0:ebd170807e11 102 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_Encoder_InitTypeDef * _encoder, TIM_HandleTypeDef * _timer, TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 103 {
kkoichy 0:ebd170807e11 104 timer = *_timer;
kkoichy 0:ebd170807e11 105 encoder = *_encoder;
kkoichy 0:ebd170807e11 106 TIM = _TIM;
kkoichy 0:ebd170807e11 107 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 108 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 109
kkoichy 0:ebd170807e11 110 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 111 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 112 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 113 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 114
kkoichy 0:ebd170807e11 115 // Setting the ISR for the corresponding interrupt vector
kkoichy 0:ebd170807e11 116 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 117 {
kkoichy 0:ebd170807e11 118 case TIM2_BASE :
kkoichy 0:ebd170807e11 119 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 0:ebd170807e11 120 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 0:ebd170807e11 121 Soft_32_Counter_TIM2 = 0;
kkoichy 0:ebd170807e11 122 break;
kkoichy 0:ebd170807e11 123
kkoichy 0:ebd170807e11 124 case TIM3_BASE :
kkoichy 0:ebd170807e11 125 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 0:ebd170807e11 126 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 0:ebd170807e11 127 Soft_32_Counter_TIM3 = 0;
kkoichy 0:ebd170807e11 128 break;
kkoichy 0:ebd170807e11 129
kkoichy 0:ebd170807e11 130 case TIM4_BASE :
kkoichy 0:ebd170807e11 131 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 0:ebd170807e11 132 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 0:ebd170807e11 133 Soft_32_Counter_TIM4 = 0;
kkoichy 0:ebd170807e11 134 break;
kkoichy 0:ebd170807e11 135
kkoichy 0:ebd170807e11 136 case TIM5_BASE :
kkoichy 0:ebd170807e11 137 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 0:ebd170807e11 138 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 0:ebd170807e11 139 Soft_32_Counter_TIM5 = 0;
kkoichy 0:ebd170807e11 140 break;
kkoichy 0:ebd170807e11 141
kkoichy 0:ebd170807e11 142 default :
kkoichy 0:ebd170807e11 143
kkoichy 0:ebd170807e11 144 break;
kkoichy 0:ebd170807e11 145 }
kkoichy 0:ebd170807e11 146
kkoichy 0:ebd170807e11 147 }
kkoichy 0:ebd170807e11 148
kkoichy 0:ebd170807e11 149
kkoichy 0:ebd170807e11 150 int32_t Nucleo_Encoder_16_bits::GetCounter()
kkoichy 0:ebd170807e11 151 {
kkoichy 0:ebd170807e11 152 uint16_t count = TIM->CNT;
kkoichy 0:ebd170807e11 153 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 154 {
kkoichy 0:ebd170807e11 155 case TIM2_BASE :
kkoichy 0:ebd170807e11 156 return (int32_t)count + Soft_32_Counter_TIM2;
kkoichy 0:ebd170807e11 157 break;
kkoichy 0:ebd170807e11 158
kkoichy 0:ebd170807e11 159 case TIM3_BASE :
kkoichy 0:ebd170807e11 160 return (int32_t)count + Soft_32_Counter_TIM3;
kkoichy 0:ebd170807e11 161 break;
kkoichy 0:ebd170807e11 162
kkoichy 0:ebd170807e11 163 case TIM4_BASE :
kkoichy 0:ebd170807e11 164 return (int32_t)count + Soft_32_Counter_TIM4;
kkoichy 0:ebd170807e11 165 break;
kkoichy 0:ebd170807e11 166
kkoichy 0:ebd170807e11 167 case TIM5_BASE :
kkoichy 0:ebd170807e11 168 return (int32_t)count + Soft_32_Counter_TIM5;
kkoichy 0:ebd170807e11 169 break;
kkoichy 0:ebd170807e11 170 }
kkoichy 0:ebd170807e11 171
kkoichy 0:ebd170807e11 172 return (int32_t)count;
kkoichy 0:ebd170807e11 173 }
kkoichy 0:ebd170807e11 174
kkoichy 0:ebd170807e11 175 TIM_HandleTypeDef* Nucleo_Encoder_16_bits::GetTimer()
kkoichy 0:ebd170807e11 176 {
kkoichy 0:ebd170807e11 177 return &timer;
kkoichy 0:ebd170807e11 178 }
kkoichy 0:ebd170807e11 179
kkoichy 0:ebd170807e11 180
kkoichy 0:ebd170807e11 181
kkoichy 0:ebd170807e11 182
kkoichy 0:ebd170807e11 183
kkoichy 0:ebd170807e11 184
kkoichy 0:ebd170807e11 185 }