RF24 - no modif

ISEN Nimes CSI3 » Code » RF24

no modif

Dependents: ISEN_RF24Network_Node_01 ISEN_RF24Network_Node_02

RF24.cpp@6:5cc7136648d1, 2016-04-21 (annotated)

Committer:: akashvibhute
Date:: Thu Apr 21 04:10:58 2016 +0000
Revision:: 6:5cc7136648d1
Parent:: 5:ee34c2837c4c
Child:: 8:b70b1d82f1d7

Library re-ported with all the latest and greatest stuff from Manicbug; Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20

Who changed what in which revision?

User	Revision	Line number	New contents of line
akashvibhute	0:bb74812ac6bb	1	/*
akashvibhute	0:bb74812ac6bb	2	Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
akashvibhute	0:bb74812ac6bb	3
akashvibhute	0:bb74812ac6bb	4	This program is free software; you can redistribute it and/or
akashvibhute	0:bb74812ac6bb	5	modify it under the terms of the GNU General Public License
akashvibhute	0:bb74812ac6bb	6	version 2 as published by the Free Software Foundation.
akashvibhute	0:bb74812ac6bb	7	*/
akashvibhute	6:5cc7136648d1	8
akashvibhute	3:e94be00fd19e	9	/*
akashvibhute	3:e94be00fd19e	10	* Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
akashvibhute	3:e94be00fd19e	11	* Porting completed on Nov/05/2015
akashvibhute	3:e94be00fd19e	12	*
akashvibhute	6:5cc7136648d1	13	* Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
akashvibhute	6:5cc7136648d1	14	* Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
akashvibhute	3:e94be00fd19e	15	*
akashvibhute	3:e94be00fd19e	16	*/
akashvibhute	6:5cc7136648d1	17
akashvibhute	2:3bdf0d9bb71f	18	#include "nRF24L01.h"
akashvibhute	2:3bdf0d9bb71f	19	#include "RF24_config.h"
akashvibhute	0:bb74812ac6bb	20	#include "RF24.h"
akashvibhute	0:bb74812ac6bb	21
akashvibhute	0:bb74812ac6bb	22	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	23
akashvibhute	2:3bdf0d9bb71f	24	void RF24::csn(bool mode)
akashvibhute	0:bb74812ac6bb	25	{
akashvibhute	6:5cc7136648d1	26
akashvibhute	6:5cc7136648d1	27	csn_pin = mode;
akashvibhute	6:5cc7136648d1	28
akashvibhute	6:5cc7136648d1	29
akashvibhute	6:5cc7136648d1	30
akashvibhute	6:5cc7136648d1	31
akashvibhute	6:5cc7136648d1	32
akashvibhute	6:5cc7136648d1	33
akashvibhute	6:5cc7136648d1	34
akashvibhute	6:5cc7136648d1	35
akashvibhute	6:5cc7136648d1	36
akashvibhute	6:5cc7136648d1	37
akashvibhute	6:5cc7136648d1	38
akashvibhute	6:5cc7136648d1	39
akashvibhute	6:5cc7136648d1	40
akashvibhute	6:5cc7136648d1	41
akashvibhute	6:5cc7136648d1	42
akashvibhute	6:5cc7136648d1	43
akashvibhute	6:5cc7136648d1	44
akashvibhute	6:5cc7136648d1	45
akashvibhute	6:5cc7136648d1	46
akashvibhute	6:5cc7136648d1	47
akashvibhute	6:5cc7136648d1	48
akashvibhute	6:5cc7136648d1	49
akashvibhute	6:5cc7136648d1	50
akashvibhute	6:5cc7136648d1	51
akashvibhute	6:5cc7136648d1	52
akashvibhute	6:5cc7136648d1	53
akashvibhute	6:5cc7136648d1	54
akashvibhute	6:5cc7136648d1	55
akashvibhute	6:5cc7136648d1	56
akashvibhute	6:5cc7136648d1	57
akashvibhute	6:5cc7136648d1	58
akashvibhute	6:5cc7136648d1	59
akashvibhute	6:5cc7136648d1	60
akashvibhute	6:5cc7136648d1	61
akashvibhute	6:5cc7136648d1	62
akashvibhute	6:5cc7136648d1	63
akashvibhute	6:5cc7136648d1	64
akashvibhute	0:bb74812ac6bb	65	}
akashvibhute	0:bb74812ac6bb	66
akashvibhute	0:bb74812ac6bb	67	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	68
akashvibhute	2:3bdf0d9bb71f	69	void RF24::ce(bool level)
akashvibhute	0:bb74812ac6bb	70	{
akashvibhute	6:5cc7136648d1	71	ce_pin = level;
akashvibhute	6:5cc7136648d1	72
akashvibhute	0:bb74812ac6bb	73	}
akashvibhute	0:bb74812ac6bb	74
akashvibhute	0:bb74812ac6bb	75	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	76
akashvibhute	6:5cc7136648d1	77	inline void RF24::beginTransaction() {
akashvibhute	6:5cc7136648d1	78
akashvibhute	6:5cc7136648d1	79
akashvibhute	6:5cc7136648d1	80	csn(LOW);
akashvibhute	6:5cc7136648d1	81	}
akashvibhute	2:3bdf0d9bb71f	82
akashvibhute	2:3bdf0d9bb71f	83	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	84
akashvibhute	6:5cc7136648d1	85	inline void RF24::endTransaction() {
akashvibhute	6:5cc7136648d1	86	csn(HIGH);
akashvibhute	6:5cc7136648d1	87
akashvibhute	6:5cc7136648d1	88
akashvibhute	6:5cc7136648d1	89
akashvibhute	6:5cc7136648d1	90	}
akashvibhute	2:3bdf0d9bb71f	91
akashvibhute	2:3bdf0d9bb71f	92	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	93
akashvibhute	0:bb74812ac6bb	94	uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
akashvibhute	0:bb74812ac6bb	95	{
akashvibhute	6:5cc7136648d1	96	uint8_t status;
akashvibhute	0:bb74812ac6bb	97
akashvibhute	6:5cc7136648d1	98
akashvibhute	6:5cc7136648d1	99
akashvibhute	6:5cc7136648d1	100
akashvibhute	6:5cc7136648d1	101
akashvibhute	6:5cc7136648d1	102
akashvibhute	6:5cc7136648d1	103
akashvibhute	6:5cc7136648d1	104
akashvibhute	6:5cc7136648d1	105
akashvibhute	6:5cc7136648d1	106
akashvibhute	6:5cc7136648d1	107
akashvibhute	6:5cc7136648d1	108
akashvibhute	6:5cc7136648d1	109
akashvibhute	6:5cc7136648d1	110
akashvibhute	6:5cc7136648d1	111
akashvibhute	6:5cc7136648d1	112
akashvibhute	6:5cc7136648d1	113
akashvibhute	6:5cc7136648d1	114
akashvibhute	6:5cc7136648d1	115
akashvibhute	6:5cc7136648d1	116
akashvibhute	6:5cc7136648d1	117
akashvibhute	3:e94be00fd19e	118
akashvibhute	6:5cc7136648d1	119	beginTransaction();
akashvibhute	6:5cc7136648d1	120	status = spi.write( R_REGISTER \| ( REGISTER_MASK & reg ) );
akashvibhute	6:5cc7136648d1	121	while ( len-- ){
akashvibhute	6:5cc7136648d1	122	*buf++ = spi.write(0xff);
akashvibhute	6:5cc7136648d1	123	}
akashvibhute	6:5cc7136648d1	124	endTransaction();
akashvibhute	6:5cc7136648d1	125
akashvibhute	6:5cc7136648d1	126
akashvibhute	6:5cc7136648d1	127
akashvibhute	6:5cc7136648d1	128	return status;
akashvibhute	0:bb74812ac6bb	129	}
akashvibhute	0:bb74812ac6bb	130
akashvibhute	0:bb74812ac6bb	131	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	132
akashvibhute	0:bb74812ac6bb	133	uint8_t RF24::read_register(uint8_t reg)
akashvibhute	0:bb74812ac6bb	134	{
akashvibhute	6:5cc7136648d1	135	uint8_t result;
akashvibhute	6:5cc7136648d1	136
akashvibhute	6:5cc7136648d1	137
akashvibhute	6:5cc7136648d1	138
akashvibhute	6:5cc7136648d1	139
akashvibhute	6:5cc7136648d1	140
akashvibhute	6:5cc7136648d1	141
akashvibhute	6:5cc7136648d1	142
akashvibhute	6:5cc7136648d1	143
akashvibhute	6:5cc7136648d1	144
akashvibhute	6:5cc7136648d1	145
akashvibhute	6:5cc7136648d1	146
akashvibhute	6:5cc7136648d1	147
akashvibhute	6:5cc7136648d1	148
akashvibhute	6:5cc7136648d1	149
akashvibhute	6:5cc7136648d1	150
akashvibhute	0:bb74812ac6bb	151
akashvibhute	6:5cc7136648d1	152	beginTransaction();
akashvibhute	6:5cc7136648d1	153	spi.write( R_REGISTER \| ( REGISTER_MASK & reg ) );
akashvibhute	6:5cc7136648d1	154	result = spi.write(0xff);
akashvibhute	6:5cc7136648d1	155	endTransaction();
akashvibhute	3:e94be00fd19e	156
akashvibhute	6:5cc7136648d1	157
akashvibhute	6:5cc7136648d1	158
akashvibhute	6:5cc7136648d1	159	return result;
akashvibhute	0:bb74812ac6bb	160	}
akashvibhute	0:bb74812ac6bb	161
akashvibhute	0:bb74812ac6bb	162	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	163
akashvibhute	0:bb74812ac6bb	164	uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
akashvibhute	0:bb74812ac6bb	165	{
akashvibhute	6:5cc7136648d1	166	uint8_t status;
akashvibhute	0:bb74812ac6bb	167
akashvibhute	6:5cc7136648d1	168
akashvibhute	6:5cc7136648d1	169
akashvibhute	6:5cc7136648d1	170
akashvibhute	6:5cc7136648d1	171
akashvibhute	6:5cc7136648d1	172
akashvibhute	6:5cc7136648d1	173
akashvibhute	6:5cc7136648d1	174
akashvibhute	6:5cc7136648d1	175
akashvibhute	6:5cc7136648d1	176
akashvibhute	6:5cc7136648d1	177
akashvibhute	6:5cc7136648d1	178
akashvibhute	6:5cc7136648d1	179
akashvibhute	6:5cc7136648d1	180
akashvibhute	6:5cc7136648d1	181
akashvibhute	3:e94be00fd19e	182
akashvibhute	6:5cc7136648d1	183	beginTransaction();
akashvibhute	6:5cc7136648d1	184	status = spi.write( W_REGISTER \| ( REGISTER_MASK & reg ) );
akashvibhute	6:5cc7136648d1	185	while ( len-- )
akashvibhute	6:5cc7136648d1	186	spi.write(*buf++);
akashvibhute	6:5cc7136648d1	187	endTransaction();
akashvibhute	6:5cc7136648d1	188
akashvibhute	6:5cc7136648d1	189
akashvibhute	6:5cc7136648d1	190
akashvibhute	6:5cc7136648d1	191	return status;
akashvibhute	0:bb74812ac6bb	192	}
akashvibhute	0:bb74812ac6bb	193
akashvibhute	0:bb74812ac6bb	194	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	195
akashvibhute	0:bb74812ac6bb	196	uint8_t RF24::write_register(uint8_t reg, uint8_t value)
akashvibhute	0:bb74812ac6bb	197	{
akashvibhute	6:5cc7136648d1	198	uint8_t status;
akashvibhute	2:3bdf0d9bb71f	199
akashvibhute	6:5cc7136648d1	200	IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
akashvibhute	2:3bdf0d9bb71f	201
akashvibhute	6:5cc7136648d1	202
akashvibhute	6:5cc7136648d1	203
akashvibhute	6:5cc7136648d1	204
akashvibhute	6:5cc7136648d1	205
akashvibhute	6:5cc7136648d1	206
akashvibhute	6:5cc7136648d1	207
akashvibhute	6:5cc7136648d1	208
akashvibhute	6:5cc7136648d1	209
akashvibhute	6:5cc7136648d1	210
akashvibhute	6:5cc7136648d1	211
akashvibhute	6:5cc7136648d1	212
akashvibhute	3:e94be00fd19e	213
akashvibhute	6:5cc7136648d1	214	beginTransaction();
akashvibhute	6:5cc7136648d1	215	status = spi.write( W_REGISTER \| ( REGISTER_MASK & reg ) );
akashvibhute	6:5cc7136648d1	216	spi.write(value);
akashvibhute	6:5cc7136648d1	217	endTransaction();
akashvibhute	6:5cc7136648d1	218
akashvibhute	6:5cc7136648d1	219
akashvibhute	6:5cc7136648d1	220
akashvibhute	6:5cc7136648d1	221	return status;
akashvibhute	2:3bdf0d9bb71f	222	}
akashvibhute	2:3bdf0d9bb71f	223
akashvibhute	2:3bdf0d9bb71f	224	/****************************************************************************/
akashvibhute	6:5cc7136648d1	225
akashvibhute	6:5cc7136648d1	226	uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
akashvibhute	2:3bdf0d9bb71f	227	{
akashvibhute	6:5cc7136648d1	228	uint8_t status;
akashvibhute	6:5cc7136648d1	229	const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
akashvibhute	2:3bdf0d9bb71f	230
akashvibhute	6:5cc7136648d1	231	data_len = rf24_min(data_len, payload_size);
akashvibhute	6:5cc7136648d1	232	uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
akashvibhute	6:5cc7136648d1	233
akashvibhute	6:5cc7136648d1	234	//printf("[Writing %u bytes %u blanks]",data_len,blank_len);
akashvibhute	6:5cc7136648d1	235	IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
akashvibhute	6:5cc7136648d1	236
akashvibhute	6:5cc7136648d1	237
akashvibhute	6:5cc7136648d1	238
akashvibhute	6:5cc7136648d1	239
akashvibhute	6:5cc7136648d1	240
akashvibhute	6:5cc7136648d1	241
akashvibhute	6:5cc7136648d1	242
akashvibhute	6:5cc7136648d1	243
akashvibhute	6:5cc7136648d1	244
akashvibhute	6:5cc7136648d1	245
akashvibhute	6:5cc7136648d1	246
akashvibhute	6:5cc7136648d1	247
akashvibhute	6:5cc7136648d1	248
akashvibhute	6:5cc7136648d1	249
akashvibhute	6:5cc7136648d1	250
akashvibhute	6:5cc7136648d1	251
akashvibhute	6:5cc7136648d1	252
akashvibhute	6:5cc7136648d1	253
akashvibhute	6:5cc7136648d1	254
akashvibhute	3:e94be00fd19e	255
akashvibhute	6:5cc7136648d1	256	beginTransaction();
akashvibhute	6:5cc7136648d1	257	status = spi.write( writeType );
akashvibhute	6:5cc7136648d1	258	while ( data_len-- ) {
akashvibhute	6:5cc7136648d1	259	spi.write(*current++);
akashvibhute	6:5cc7136648d1	260	}
akashvibhute	6:5cc7136648d1	261	while ( blank_len-- ) {
akashvibhute	6:5cc7136648d1	262	spi.write(0);
akashvibhute	6:5cc7136648d1	263	}
akashvibhute	6:5cc7136648d1	264	endTransaction();
akashvibhute	3:e94be00fd19e	265
akashvibhute	6:5cc7136648d1	266
akashvibhute	6:5cc7136648d1	267
akashvibhute	6:5cc7136648d1	268	return status;
akashvibhute	0:bb74812ac6bb	269	}
akashvibhute	0:bb74812ac6bb	270
akashvibhute	0:bb74812ac6bb	271	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	272
akashvibhute	2:3bdf0d9bb71f	273	uint8_t RF24::read_payload(void* buf, uint8_t data_len)
akashvibhute	0:bb74812ac6bb	274	{
akashvibhute	6:5cc7136648d1	275	uint8_t status;
akashvibhute	6:5cc7136648d1	276	uint8_t* current = reinterpret_cast<uint8_t*>(buf);
akashvibhute	2:3bdf0d9bb71f	277
akashvibhute	6:5cc7136648d1	278	if(data_len > payload_size) data_len = payload_size;
akashvibhute	6:5cc7136648d1	279	uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
akashvibhute	6:5cc7136648d1	280
akashvibhute	6:5cc7136648d1	281	//printf("[Reading %u bytes %u blanks]",data_len,blank_len);
akashvibhute	0:bb74812ac6bb	282
akashvibhute	6:5cc7136648d1	283	IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
akashvibhute	6:5cc7136648d1	284
akashvibhute	6:5cc7136648d1	285
akashvibhute	6:5cc7136648d1	286
akashvibhute	6:5cc7136648d1	287
akashvibhute	6:5cc7136648d1	288
akashvibhute	6:5cc7136648d1	289
akashvibhute	6:5cc7136648d1	290
akashvibhute	6:5cc7136648d1	291
akashvibhute	6:5cc7136648d1	292
akashvibhute	6:5cc7136648d1	293
akashvibhute	6:5cc7136648d1	294
akashvibhute	6:5cc7136648d1	295
akashvibhute	6:5cc7136648d1	296
akashvibhute	6:5cc7136648d1	297
akashvibhute	6:5cc7136648d1	298
akashvibhute	6:5cc7136648d1	299
akashvibhute	6:5cc7136648d1	300
akashvibhute	6:5cc7136648d1	301
akashvibhute	6:5cc7136648d1	302
akashvibhute	6:5cc7136648d1	303
akashvibhute	6:5cc7136648d1	304
akashvibhute	6:5cc7136648d1	305
akashvibhute	6:5cc7136648d1	306
akashvibhute	6:5cc7136648d1	307
akashvibhute	6:5cc7136648d1	308
akashvibhute	6:5cc7136648d1	309
akashvibhute	3:e94be00fd19e	310
akashvibhute	6:5cc7136648d1	311	beginTransaction();
akashvibhute	6:5cc7136648d1	312	status = spi.write( R_RX_PAYLOAD );
akashvibhute	6:5cc7136648d1	313	while ( data_len-- ) {
akashvibhute	6:5cc7136648d1	314	*current++ = spi.write(0xFF);
akashvibhute	6:5cc7136648d1	315	}
akashvibhute	6:5cc7136648d1	316	while ( blank_len-- ) {
akashvibhute	6:5cc7136648d1	317	spi.write(0xff);
akashvibhute	6:5cc7136648d1	318	}
akashvibhute	6:5cc7136648d1	319	endTransaction();
akashvibhute	6:5cc7136648d1	320
akashvibhute	6:5cc7136648d1	321
akashvibhute	6:5cc7136648d1	322
akashvibhute	6:5cc7136648d1	323	return status;
akashvibhute	0:bb74812ac6bb	324	}
akashvibhute	0:bb74812ac6bb	325
akashvibhute	0:bb74812ac6bb	326	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	327
akashvibhute	0:bb74812ac6bb	328	uint8_t RF24::flush_rx(void)
akashvibhute	0:bb74812ac6bb	329	{
akashvibhute	6:5cc7136648d1	330	return spiTrans( FLUSH_RX );
akashvibhute	0:bb74812ac6bb	331	}
akashvibhute	0:bb74812ac6bb	332
akashvibhute	0:bb74812ac6bb	333	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	334
akashvibhute	0:bb74812ac6bb	335	uint8_t RF24::flush_tx(void)
akashvibhute	0:bb74812ac6bb	336	{
akashvibhute	6:5cc7136648d1	337	return spiTrans( FLUSH_TX );
akashvibhute	2:3bdf0d9bb71f	338	}
akashvibhute	2:3bdf0d9bb71f	339
akashvibhute	2:3bdf0d9bb71f	340	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	341
akashvibhute	6:5cc7136648d1	342	uint8_t RF24::spiTrans(uint8_t cmd){
akashvibhute	0:bb74812ac6bb	343
akashvibhute	6:5cc7136648d1	344	uint8_t status;
akashvibhute	6:5cc7136648d1	345
akashvibhute	6:5cc7136648d1	346	beginTransaction();
akashvibhute	6:5cc7136648d1	347	status = spi.write( cmd );
akashvibhute	6:5cc7136648d1	348	endTransaction();
akashvibhute	6:5cc7136648d1	349
akashvibhute	6:5cc7136648d1	350	return status;
akashvibhute	0:bb74812ac6bb	351	}
akashvibhute	0:bb74812ac6bb	352
akashvibhute	0:bb74812ac6bb	353	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	354
akashvibhute	0:bb74812ac6bb	355	uint8_t RF24::get_status(void)
akashvibhute	0:bb74812ac6bb	356	{
akashvibhute	6:5cc7136648d1	357	return spiTrans(NOP);
akashvibhute	0:bb74812ac6bb	358	}
akashvibhute	0:bb74812ac6bb	359
akashvibhute	0:bb74812ac6bb	360	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	361	#if !defined (MINIMAL)
akashvibhute	0:bb74812ac6bb	362	void RF24::print_status(uint8_t status)
akashvibhute	0:bb74812ac6bb	363	{
akashvibhute	6:5cc7136648d1	364	printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
akashvibhute	0:bb74812ac6bb	365	status,
akashvibhute	0:bb74812ac6bb	366	(status & _BV(RX_DR))?1:0,
akashvibhute	0:bb74812ac6bb	367	(status & _BV(TX_DS))?1:0,
akashvibhute	0:bb74812ac6bb	368	(status & _BV(MAX_RT))?1:0,
akashvibhute	6:5cc7136648d1	369	((status >> RX_P_NO) & 0b111),
akashvibhute	0:bb74812ac6bb	370	(status & _BV(TX_FULL))?1:0
akashvibhute	0:bb74812ac6bb	371	);
akashvibhute	0:bb74812ac6bb	372	}
akashvibhute	0:bb74812ac6bb	373
akashvibhute	0:bb74812ac6bb	374	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	375
akashvibhute	0:bb74812ac6bb	376	void RF24::print_observe_tx(uint8_t value)
akashvibhute	0:bb74812ac6bb	377	{
akashvibhute	6:5cc7136648d1	378	printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
akashvibhute	0:bb74812ac6bb	379	value,
akashvibhute	6:5cc7136648d1	380	(value >> PLOS_CNT) & 0b1111,
akashvibhute	6:5cc7136648d1	381	(value >> ARC_CNT) & 0b1111
akashvibhute	0:bb74812ac6bb	382	);
akashvibhute	0:bb74812ac6bb	383	}
akashvibhute	0:bb74812ac6bb	384
akashvibhute	0:bb74812ac6bb	385	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	386
akashvibhute	0:bb74812ac6bb	387	void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
akashvibhute	0:bb74812ac6bb	388	{
akashvibhute	6:5cc7136648d1	389	//char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
akashvibhute	6:5cc7136648d1	390	//printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
akashvibhute	6:5cc7136648d1	391
akashvibhute	6:5cc7136648d1	392
akashvibhute	6:5cc7136648d1	393
akashvibhute	6:5cc7136648d1	394	printf_P(PSTR(PRIPSTR"\t ="),name);
akashvibhute	6:5cc7136648d1	395
akashvibhute	6:5cc7136648d1	396	while (qty--)
akashvibhute	6:5cc7136648d1	397	printf_P(PSTR(" 0x%02x"),read_register(reg++));
akashvibhute	6:5cc7136648d1	398	printf_P(PSTR("\r\n"));
akashvibhute	0:bb74812ac6bb	399	}
akashvibhute	0:bb74812ac6bb	400
akashvibhute	0:bb74812ac6bb	401	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	402
akashvibhute	0:bb74812ac6bb	403	void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
akashvibhute	0:bb74812ac6bb	404	{
akashvibhute	0:bb74812ac6bb	405
akashvibhute	6:5cc7136648d1	406
akashvibhute	6:5cc7136648d1	407
akashvibhute	6:5cc7136648d1	408
akashvibhute	6:5cc7136648d1	409	printf_P(PSTR(PRIPSTR"\t ="),name);
akashvibhute	6:5cc7136648d1	410
akashvibhute	6:5cc7136648d1	411	while (qty--)
akashvibhute	6:5cc7136648d1	412	{
akashvibhute	6:5cc7136648d1	413	uint8_t buffer[addr_width];
akashvibhute	6:5cc7136648d1	414	read_register(reg++,buffer,sizeof buffer);
akashvibhute	0:bb74812ac6bb	415
akashvibhute	6:5cc7136648d1	416	printf_P(PSTR(" 0x"));
akashvibhute	6:5cc7136648d1	417	uint8_t* bufptr = buffer + sizeof buffer;
akashvibhute	6:5cc7136648d1	418	while( --bufptr >= buffer )
akashvibhute	6:5cc7136648d1	419	printf_P(PSTR("%02x"),*bufptr);
akashvibhute	6:5cc7136648d1	420	}
akashvibhute	3:e94be00fd19e	421
akashvibhute	6:5cc7136648d1	422	printf_P(PSTR("\r\n"));
akashvibhute	2:3bdf0d9bb71f	423	}
akashvibhute	2:3bdf0d9bb71f	424	#endif
akashvibhute	2:3bdf0d9bb71f	425	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	426	RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin):
akashvibhute	6:5cc7136648d1	427	spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true),
akashvibhute	6:5cc7136648d1	428	payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
akashvibhute	2:3bdf0d9bb71f	429	{
akashvibhute	6:5cc7136648d1	430	pipe0_reading_address[0]=0;
akashvibhute	6:5cc7136648d1	431
akashvibhute	6:5cc7136648d1	432	//spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus
akashvibhute	6:5cc7136648d1	433	spi.frequency(10000000);
akashvibhute	6:5cc7136648d1	434	//spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
akashvibhute	6:5cc7136648d1	435	spi.format(8,0);
akashvibhute	6:5cc7136648d1	436	wait_ms(10);
akashvibhute	0:bb74812ac6bb	437	}
akashvibhute	0:bb74812ac6bb	438
akashvibhute	2:3bdf0d9bb71f	439
akashvibhute	2:3bdf0d9bb71f	440
akashvibhute	0:bb74812ac6bb	441
akashvibhute	2:3bdf0d9bb71f	442
akashvibhute	2:3bdf0d9bb71f	443
akashvibhute	2:3bdf0d9bb71f	444
akashvibhute	0:bb74812ac6bb	445
akashvibhute	0:bb74812ac6bb	446	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	447
akashvibhute	0:bb74812ac6bb	448	void RF24::setChannel(uint8_t channel)
akashvibhute	0:bb74812ac6bb	449	{
akashvibhute	6:5cc7136648d1	450	const uint8_t max_channel = 125;
akashvibhute	6:5cc7136648d1	451	write_register(RF_CH,rf24_min(channel,max_channel));
akashvibhute	0:bb74812ac6bb	452	}
akashvibhute	0:bb74812ac6bb	453
akashvibhute	2:3bdf0d9bb71f	454	uint8_t RF24::getChannel()
akashvibhute	2:3bdf0d9bb71f	455	{
akashvibhute	6:5cc7136648d1	456
akashvibhute	6:5cc7136648d1	457	return read_register(RF_CH);
akashvibhute	2:3bdf0d9bb71f	458	}
akashvibhute	0:bb74812ac6bb	459	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	460
akashvibhute	0:bb74812ac6bb	461	void RF24::setPayloadSize(uint8_t size)
akashvibhute	0:bb74812ac6bb	462	{
akashvibhute	6:5cc7136648d1	463	payload_size = rf24_min(size,32);
akashvibhute	0:bb74812ac6bb	464	}
akashvibhute	0:bb74812ac6bb	465
akashvibhute	0:bb74812ac6bb	466	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	467
akashvibhute	0:bb74812ac6bb	468	uint8_t RF24::getPayloadSize(void)
akashvibhute	0:bb74812ac6bb	469	{
akashvibhute	6:5cc7136648d1	470	return payload_size;
akashvibhute	0:bb74812ac6bb	471	}
akashvibhute	0:bb74812ac6bb	472
akashvibhute	0:bb74812ac6bb	473	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	474
akashvibhute	2:3bdf0d9bb71f	475	#if !defined (MINIMAL)
akashvibhute	2:3bdf0d9bb71f	476
akashvibhute	2:3bdf0d9bb71f	477	static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
akashvibhute	2:3bdf0d9bb71f	478	static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
akashvibhute	2:3bdf0d9bb71f	479	static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
akashvibhute	2:3bdf0d9bb71f	480	static const char * const rf24_datarate_e_str_P[] PROGMEM = {
akashvibhute	6:5cc7136648d1	481	rf24_datarate_e_str_0,
akashvibhute	6:5cc7136648d1	482	rf24_datarate_e_str_1,
akashvibhute	6:5cc7136648d1	483	rf24_datarate_e_str_2,
akashvibhute	0:bb74812ac6bb	484	};
akashvibhute	2:3bdf0d9bb71f	485	static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
akashvibhute	2:3bdf0d9bb71f	486	static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
akashvibhute	2:3bdf0d9bb71f	487	static const char * const rf24_model_e_str_P[] PROGMEM = {
akashvibhute	6:5cc7136648d1	488	rf24_model_e_str_0,
akashvibhute	6:5cc7136648d1	489	rf24_model_e_str_1,
akashvibhute	0:bb74812ac6bb	490	};
akashvibhute	2:3bdf0d9bb71f	491	static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
akashvibhute	2:3bdf0d9bb71f	492	static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
akashvibhute	2:3bdf0d9bb71f	493	static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
akashvibhute	2:3bdf0d9bb71f	494	static const char * const rf24_crclength_e_str_P[] PROGMEM = {
akashvibhute	6:5cc7136648d1	495	rf24_crclength_e_str_0,
akashvibhute	6:5cc7136648d1	496	rf24_crclength_e_str_1,
akashvibhute	6:5cc7136648d1	497	rf24_crclength_e_str_2,
akashvibhute	0:bb74812ac6bb	498	};
akashvibhute	2:3bdf0d9bb71f	499	static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
akashvibhute	2:3bdf0d9bb71f	500	static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
akashvibhute	2:3bdf0d9bb71f	501	static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
akashvibhute	2:3bdf0d9bb71f	502	static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
akashvibhute	2:3bdf0d9bb71f	503	static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
akashvibhute	6:5cc7136648d1	504	rf24_pa_dbm_e_str_0,
akashvibhute	6:5cc7136648d1	505	rf24_pa_dbm_e_str_1,
akashvibhute	6:5cc7136648d1	506	rf24_pa_dbm_e_str_2,
akashvibhute	6:5cc7136648d1	507	rf24_pa_dbm_e_str_3,
akashvibhute	0:bb74812ac6bb	508	};
akashvibhute	0:bb74812ac6bb	509
akashvibhute	6:5cc7136648d1	510
akashvibhute	6:5cc7136648d1	511
akashvibhute	6:5cc7136648d1	512
akashvibhute	6:5cc7136648d1	513
akashvibhute	6:5cc7136648d1	514
akashvibhute	6:5cc7136648d1	515
akashvibhute	6:5cc7136648d1	516
akashvibhute	6:5cc7136648d1	517
akashvibhute	6:5cc7136648d1	518
akashvibhute	6:5cc7136648d1	519
akashvibhute	6:5cc7136648d1	520
akashvibhute	6:5cc7136648d1	521
akashvibhute	6:5cc7136648d1	522
akashvibhute	0:bb74812ac6bb	523	void RF24::printDetails(void)
akashvibhute	0:bb74812ac6bb	524	{
akashvibhute	6:5cc7136648d1	525
akashvibhute	6:5cc7136648d1	526
akashvibhute	6:5cc7136648d1	527
akashvibhute	6:5cc7136648d1	528
akashvibhute	6:5cc7136648d1	529
akashvibhute	6:5cc7136648d1	530
akashvibhute	6:5cc7136648d1	531
akashvibhute	6:5cc7136648d1	532
akashvibhute	6:5cc7136648d1	533
akashvibhute	6:5cc7136648d1	534
akashvibhute	6:5cc7136648d1	535
akashvibhute	6:5cc7136648d1	536
akashvibhute	2:3bdf0d9bb71f	537
akashvibhute	6:5cc7136648d1	538
akashvibhute	6:5cc7136648d1	539
akashvibhute	6:5cc7136648d1	540
akashvibhute	6:5cc7136648d1	541
akashvibhute	6:5cc7136648d1	542
akashvibhute	6:5cc7136648d1	543
akashvibhute	6:5cc7136648d1	544
akashvibhute	6:5cc7136648d1	545
akashvibhute	6:5cc7136648d1	546
akashvibhute	6:5cc7136648d1	547
akashvibhute	6:5cc7136648d1	548
akashvibhute	6:5cc7136648d1	549
akashvibhute	2:3bdf0d9bb71f	550
akashvibhute	6:5cc7136648d1	551
akashvibhute	6:5cc7136648d1	552
akashvibhute	6:5cc7136648d1	553
akashvibhute	6:5cc7136648d1	554
akashvibhute	6:5cc7136648d1	555
akashvibhute	6:5cc7136648d1	556
akashvibhute	6:5cc7136648d1	557
akashvibhute	6:5cc7136648d1	558	print_status(get_status());
akashvibhute	6:5cc7136648d1	559
akashvibhute	6:5cc7136648d1	560	print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
akashvibhute	6:5cc7136648d1	561	print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
akashvibhute	6:5cc7136648d1	562	print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
akashvibhute	0:bb74812ac6bb	563
akashvibhute	6:5cc7136648d1	564	print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
akashvibhute	6:5cc7136648d1	565	print_byte_register(PSTR("EN_AA\t"),EN_AA);
akashvibhute	6:5cc7136648d1	566	print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
akashvibhute	6:5cc7136648d1	567	print_byte_register(PSTR("RF_CH\t"),RF_CH);
akashvibhute	6:5cc7136648d1	568	print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
akashvibhute	6:5cc7136648d1	569	print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
akashvibhute	6:5cc7136648d1	570	print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
akashvibhute	6:5cc7136648d1	571
akashvibhute	6:5cc7136648d1	572	printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
akashvibhute	6:5cc7136648d1	573	printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
akashvibhute	6:5cc7136648d1	574	printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
akashvibhute	6:5cc7136648d1	575	printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
akashvibhute	2:3bdf0d9bb71f	576
akashvibhute	0:bb74812ac6bb	577	}
akashvibhute	0:bb74812ac6bb	578
akashvibhute	2:3bdf0d9bb71f	579	#endif
akashvibhute	0:bb74812ac6bb	580	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	581
akashvibhute	2:3bdf0d9bb71f	582	bool RF24::begin(void)
akashvibhute	0:bb74812ac6bb	583	{
akashvibhute	6:5cc7136648d1	584
akashvibhute	6:5cc7136648d1	585	uint8_t setup=0;
akashvibhute	6:5cc7136648d1	586
akashvibhute	6:5cc7136648d1	587	mainTimer.start();
akashvibhute	6:5cc7136648d1	588
akashvibhute	6:5cc7136648d1	589	ce(LOW);
akashvibhute	6:5cc7136648d1	590	csn(HIGH);
akashvibhute	6:5cc7136648d1	591
akashvibhute	6:5cc7136648d1	592	wait_ms(100);
akashvibhute	6:5cc7136648d1	593
akashvibhute	6:5cc7136648d1	594
akashvibhute	6:5cc7136648d1	595
akashvibhute	6:5cc7136648d1	596
akashvibhute	2:3bdf0d9bb71f	597
akashvibhute	6:5cc7136648d1	598
akashvibhute	6:5cc7136648d1	599
akashvibhute	6:5cc7136648d1	600
akashvibhute	6:5cc7136648d1	601
akashvibhute	6:5cc7136648d1	602
akashvibhute	6:5cc7136648d1	603
akashvibhute	3:e94be00fd19e	604
akashvibhute	6:5cc7136648d1	605
akashvibhute	6:5cc7136648d1	606
akashvibhute	6:5cc7136648d1	607
akashvibhute	6:5cc7136648d1	608
akashvibhute	6:5cc7136648d1	609
akashvibhute	6:5cc7136648d1	610
akashvibhute	0:bb74812ac6bb	611
akashvibhute	6:5cc7136648d1	612
akashvibhute	6:5cc7136648d1	613
akashvibhute	6:5cc7136648d1	614
akashvibhute	6:5cc7136648d1	615
akashvibhute	6:5cc7136648d1	616
akashvibhute	6:5cc7136648d1	617
akashvibhute	6:5cc7136648d1	618
akashvibhute	6:5cc7136648d1	619
akashvibhute	6:5cc7136648d1	620
akashvibhute	6:5cc7136648d1	621
akashvibhute	6:5cc7136648d1	622
akashvibhute	6:5cc7136648d1	623
akashvibhute	6:5cc7136648d1	624
akashvibhute	3:e94be00fd19e	625
akashvibhute	6:5cc7136648d1	626
akashvibhute	6:5cc7136648d1	627
akashvibhute	6:5cc7136648d1	628
akashvibhute	6:5cc7136648d1	629
akashvibhute	6:5cc7136648d1	630
akashvibhute	6:5cc7136648d1	631
akashvibhute	3:e94be00fd19e	632
akashvibhute	6:5cc7136648d1	633	// Must allow the radio time to settle else configuration bits will not necessarily stick.
akashvibhute	6:5cc7136648d1	634	// This is actually only required following power up but some settling time also appears to
akashvibhute	6:5cc7136648d1	635	// be required after resets too. For full coverage, we'll always assume the worst.
akashvibhute	6:5cc7136648d1	636	// Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
akashvibhute	6:5cc7136648d1	637	// Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
akashvibhute	6:5cc7136648d1	638	// WARNING: Delay is based on P-variant whereby non-P may require different timing.
akashvibhute	6:5cc7136648d1	639	wait_ms( 5 ) ;
akashvibhute	0:bb74812ac6bb	640
akashvibhute	6:5cc7136648d1	641	// Reset NRF_CONFIG and enable 16-bit CRC.
akashvibhute	6:5cc7136648d1	642	write_register( NRF_CONFIG, 0b00001100 ) ;
akashvibhute	6:5cc7136648d1	643
akashvibhute	6:5cc7136648d1	644	// Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
akashvibhute	6:5cc7136648d1	645	// WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
akashvibhute	6:5cc7136648d1	646	// sizes must never be used. See documentation for a more complete explanation.
akashvibhute	6:5cc7136648d1	647	setRetries(5,15);
akashvibhute	6:5cc7136648d1	648
akashvibhute	6:5cc7136648d1	649	// Reset value is MAX
akashvibhute	6:5cc7136648d1	650	//setPALevel( RF24_PA_MAX ) ;
akashvibhute	0:bb74812ac6bb	651
akashvibhute	6:5cc7136648d1	652	// check for connected module and if this is a p nRF24l01 variant
akashvibhute	6:5cc7136648d1	653	//
akashvibhute	6:5cc7136648d1	654	if( setDataRate( RF24_250KBPS ) )
akashvibhute	6:5cc7136648d1	655	{
akashvibhute	6:5cc7136648d1	656	p_variant = true ;
akashvibhute	6:5cc7136648d1	657	}
akashvibhute	6:5cc7136648d1	658	setup = read_register(RF_SETUP);
akashvibhute	6:5cc7136648d1	659	/*if( setup == 0b00001110 ) // register default for nRF24L01P
akashvibhute	6:5cc7136648d1	660	{
akashvibhute	6:5cc7136648d1	661	p_variant = true ;
akashvibhute	6:5cc7136648d1	662	}*/
akashvibhute	6:5cc7136648d1	663
akashvibhute	6:5cc7136648d1	664	// Then set the data rate to the slowest (and most reliable) speed supported by all
akashvibhute	6:5cc7136648d1	665	// hardware.
akashvibhute	6:5cc7136648d1	666	//setDataRate( RF24_1MBPS ) ;
akashvibhute	6:5cc7136648d1	667	setDataRate( RF24_2MBPS ) ;
akashvibhute	0:bb74812ac6bb	668
akashvibhute	6:5cc7136648d1	669	// Initialize CRC and request 2-byte (16bit) CRC
akashvibhute	6:5cc7136648d1	670	//setCRCLength( RF24_CRC_16 ) ;
akashvibhute	2:3bdf0d9bb71f	671
akashvibhute	6:5cc7136648d1	672	// Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
akashvibhute	6:5cc7136648d1	673	toggle_features();
akashvibhute	6:5cc7136648d1	674	write_register(FEATURE,0 );
akashvibhute	6:5cc7136648d1	675	write_register(DYNPD,0);
akashvibhute	6:5cc7136648d1	676
akashvibhute	6:5cc7136648d1	677	// Reset current status
akashvibhute	6:5cc7136648d1	678	// Notice reset and flush is the last thing we do
akashvibhute	6:5cc7136648d1	679	write_register(NRF_STATUS,_BV(RX_DR) \| _BV(TX_DS) \| _BV(MAX_RT) );
akashvibhute	0:bb74812ac6bb	680
akashvibhute	6:5cc7136648d1	681	// Set up default configuration. Callers can always change it later.
akashvibhute	6:5cc7136648d1	682	// This channel should be universally safe and not bleed over into adjacent
akashvibhute	6:5cc7136648d1	683	// spectrum.
akashvibhute	6:5cc7136648d1	684	setChannel(76);
akashvibhute	0:bb74812ac6bb	685
akashvibhute	6:5cc7136648d1	686	// Flush buffers
akashvibhute	6:5cc7136648d1	687	flush_rx();
akashvibhute	6:5cc7136648d1	688	flush_tx();
akashvibhute	2:3bdf0d9bb71f	689
akashvibhute	6:5cc7136648d1	690	powerUp(); //Power up by default when begin() is called
akashvibhute	2:3bdf0d9bb71f	691
akashvibhute	6:5cc7136648d1	692	// Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
akashvibhute	6:5cc7136648d1	693	// PTX should use only 22uA of power
akashvibhute	6:5cc7136648d1	694	write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
akashvibhute	6:5cc7136648d1	695	printDetails();
akashvibhute	6:5cc7136648d1	696	// if setup is 0 or ff then there was no response from module
akashvibhute	6:5cc7136648d1	697	return ( setup != 0 && setup != 0xff );
akashvibhute	0:bb74812ac6bb	698	}
akashvibhute	0:bb74812ac6bb	699
akashvibhute	0:bb74812ac6bb	700	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	701
akashvibhute	0:bb74812ac6bb	702	void RF24::startListening(void)
akashvibhute	0:bb74812ac6bb	703	{
akashvibhute	6:5cc7136648d1	704
akashvibhute	6:5cc7136648d1	705
akashvibhute	6:5cc7136648d1	706
akashvibhute	6:5cc7136648d1	707	write_register(NRF_CONFIG, read_register(NRF_CONFIG) \| _BV(PRIM_RX));
akashvibhute	6:5cc7136648d1	708	write_register(NRF_STATUS, _BV(RX_DR) \| _BV(TX_DS) \| _BV(MAX_RT) );
akashvibhute	6:5cc7136648d1	709	ce(HIGH);
akashvibhute	6:5cc7136648d1	710	// Restore the pipe0 adddress, if exists
akashvibhute	6:5cc7136648d1	711	if (pipe0_reading_address[0] > 0){
akashvibhute	6:5cc7136648d1	712	write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
akashvibhute	6:5cc7136648d1	713	}else{
akashvibhute	6:5cc7136648d1	714	closeReadingPipe(0);
akashvibhute	6:5cc7136648d1	715	}
akashvibhute	0:bb74812ac6bb	716
akashvibhute	6:5cc7136648d1	717	// Flush buffers
akashvibhute	6:5cc7136648d1	718	//flush_rx();
akashvibhute	6:5cc7136648d1	719	if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
akashvibhute	6:5cc7136648d1	720	flush_tx();
akashvibhute	6:5cc7136648d1	721	}
akashvibhute	0:bb74812ac6bb	722
akashvibhute	6:5cc7136648d1	723	// Go!
akashvibhute	6:5cc7136648d1	724	//delayMicroseconds(100);
akashvibhute	0:bb74812ac6bb	725	}
akashvibhute	0:bb74812ac6bb	726
akashvibhute	0:bb74812ac6bb	727	/****************************************************************************/
akashvibhute	6:5cc7136648d1	728	static const uint8_t child_pipe_enable[] PROGMEM =
akashvibhute	6:5cc7136648d1	729	{
akashvibhute	6:5cc7136648d1	730	ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
akashvibhute	2:3bdf0d9bb71f	731	};
akashvibhute	0:bb74812ac6bb	732
akashvibhute	0:bb74812ac6bb	733	void RF24::stopListening(void)
akashvibhute	6:5cc7136648d1	734	{
akashvibhute	6:5cc7136648d1	735	ce(LOW);
akashvibhute	2:3bdf0d9bb71f	736
akashvibhute	6:5cc7136648d1	737	wait_us(txRxDelay);
akashvibhute	6:5cc7136648d1	738
akashvibhute	6:5cc7136648d1	739	if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
akashvibhute	6:5cc7136648d1	740	wait_us(txRxDelay); //200
akashvibhute	6:5cc7136648d1	741	flush_tx();
akashvibhute	6:5cc7136648d1	742	}
akashvibhute	6:5cc7136648d1	743	//flush_rx();
akashvibhute	6:5cc7136648d1	744	write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
akashvibhute	6:5cc7136648d1	745
akashvibhute	6:5cc7136648d1	746
akashvibhute	6:5cc7136648d1	747
akashvibhute	6:5cc7136648d1	748
akashvibhute	6:5cc7136648d1	749
akashvibhute	6:5cc7136648d1	750
akashvibhute	6:5cc7136648d1	751
akashvibhute	6:5cc7136648d1	752
akashvibhute	6:5cc7136648d1	753	write_register(EN_RXADDR,read_register(EN_RXADDR) \| _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
akashvibhute	6:5cc7136648d1	754
akashvibhute	6:5cc7136648d1	755	//delayMicroseconds(100);
akashvibhute	2:3bdf0d9bb71f	756
akashvibhute	0:bb74812ac6bb	757	}
akashvibhute	0:bb74812ac6bb	758
akashvibhute	0:bb74812ac6bb	759	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	760
akashvibhute	0:bb74812ac6bb	761	void RF24::powerDown(void)
akashvibhute	0:bb74812ac6bb	762	{
akashvibhute	6:5cc7136648d1	763	ce(LOW); // Guarantee CE is low on powerDown
akashvibhute	6:5cc7136648d1	764	write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
akashvibhute	0:bb74812ac6bb	765	}
akashvibhute	0:bb74812ac6bb	766
akashvibhute	0:bb74812ac6bb	767	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	768
akashvibhute	2:3bdf0d9bb71f	769	//Power up now. Radio will not power down unless instructed by MCU for config changes etc.
akashvibhute	0:bb74812ac6bb	770	void RF24::powerUp(void)
akashvibhute	0:bb74812ac6bb	771	{
akashvibhute	6:5cc7136648d1	772	uint8_t cfg = read_register(NRF_CONFIG);
akashvibhute	2:3bdf0d9bb71f	773
akashvibhute	6:5cc7136648d1	774	// if not powered up then power up and wait for the radio to initialize
akashvibhute	6:5cc7136648d1	775	if (!(cfg & _BV(PWR_UP))){
akashvibhute	6:5cc7136648d1	776	write_register(NRF_CONFIG, cfg \| _BV(PWR_UP));
akashvibhute	2:3bdf0d9bb71f	777
akashvibhute	6:5cc7136648d1	778	// For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
akashvibhute	6:5cc7136648d1	779	// There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
akashvibhute	6:5cc7136648d1	780	// the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
akashvibhute	6:5cc7136648d1	781	wait_ms(5);
akashvibhute	6:5cc7136648d1	782	}
akashvibhute	0:bb74812ac6bb	783	}
akashvibhute	0:bb74812ac6bb	784
akashvibhute	0:bb74812ac6bb	785	/******************************************************************/
akashvibhute	6:5cc7136648d1	786	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	787	void RF24::errNotify(){
akashvibhute	6:5cc7136648d1	788	#if defined (SERIAL_DEBUG) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	789	printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
akashvibhute	6:5cc7136648d1	790	#endif
akashvibhute	6:5cc7136648d1	791	#if defined (FAILURE_HANDLING)
akashvibhute	6:5cc7136648d1	792	failureDetected = 1;
akashvibhute	6:5cc7136648d1	793	#else
akashvibhute	6:5cc7136648d1	794	wait_ms(5000);
akashvibhute	6:5cc7136648d1	795	#endif
akashvibhute	2:3bdf0d9bb71f	796	}
akashvibhute	2:3bdf0d9bb71f	797	#endif
akashvibhute	2:3bdf0d9bb71f	798	/******************************************************************/
akashvibhute	0:bb74812ac6bb	799
akashvibhute	2:3bdf0d9bb71f	800	//Similar to the previous write, clears the interrupt flags
akashvibhute	2:3bdf0d9bb71f	801	bool RF24::write( const void* buf, uint8_t len, const bool multicast )
akashvibhute	2:3bdf0d9bb71f	802	{
akashvibhute	6:5cc7136648d1	803	//Start Writing
akashvibhute	6:5cc7136648d1	804	startFastWrite(buf,len,multicast);
akashvibhute	3:e94be00fd19e	805
akashvibhute	6:5cc7136648d1	806	//Wait until complete or failed
akashvibhute	6:5cc7136648d1	807	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	808	uint32_t timer = mainTimer.read_ms();
akashvibhute	6:5cc7136648d1	809	#endif
akashvibhute	6:5cc7136648d1	810
akashvibhute	6:5cc7136648d1	811	while( ! ( get_status() & ( _BV(TX_DS) \| _BV(MAX_RT) ))) {
akashvibhute	6:5cc7136648d1	812	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	813	if(mainTimer.read_ms() - timer > 95){
akashvibhute	6:5cc7136648d1	814	errNotify();
akashvibhute	6:5cc7136648d1	815	#if defined (FAILURE_HANDLING)
akashvibhute	6:5cc7136648d1	816	return 0;
akashvibhute	6:5cc7136648d1	817	#else
akashvibhute	6:5cc7136648d1	818	wait_ms(100);
akashvibhute	6:5cc7136648d1	819	#endif
akashvibhute	6:5cc7136648d1	820	}
akashvibhute	6:5cc7136648d1	821	#endif
akashvibhute	6:5cc7136648d1	822	}
akashvibhute	6:5cc7136648d1	823
akashvibhute	6:5cc7136648d1	824	ce(LOW);
akashvibhute	3:e94be00fd19e	825
akashvibhute	6:5cc7136648d1	826	uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) \| _BV(TX_DS) \| _BV(MAX_RT) );
akashvibhute	0:bb74812ac6bb	827
akashvibhute	6:5cc7136648d1	828	//Max retries exceeded
akashvibhute	6:5cc7136648d1	829	if( status & _BV(MAX_RT)){
akashvibhute	6:5cc7136648d1	830	flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
akashvibhute	6:5cc7136648d1	831	return 0;
akashvibhute	6:5cc7136648d1	832	}
akashvibhute	6:5cc7136648d1	833	//TX OK 1 or 0
akashvibhute	6:5cc7136648d1	834	return 1;
akashvibhute	2:3bdf0d9bb71f	835	}
akashvibhute	0:bb74812ac6bb	836
akashvibhute	6:5cc7136648d1	837	bool RF24::write( const void* buf, uint8_t len ){
akashvibhute	6:5cc7136648d1	838	return write(buf,len,0);
akashvibhute	0:bb74812ac6bb	839	}
akashvibhute	0:bb74812ac6bb	840	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	841
akashvibhute	2:3bdf0d9bb71f	842	//For general use, the interrupt flags are not important to clear
akashvibhute	2:3bdf0d9bb71f	843	bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
akashvibhute	2:3bdf0d9bb71f	844	{
akashvibhute	6:5cc7136648d1	845	//Block until the FIFO is NOT full.
akashvibhute	6:5cc7136648d1	846	//Keep track of the MAX retries and set auto-retry if seeing failures
akashvibhute	6:5cc7136648d1	847	//This way the FIFO will fill up and allow blocking until packets go through
akashvibhute	6:5cc7136648d1	848	//The radio will auto-clear everything in the FIFO as long as CE remains high
akashvibhute	2:3bdf0d9bb71f	849
akashvibhute	6:5cc7136648d1	850	uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started
akashvibhute	2:3bdf0d9bb71f	851
akashvibhute	6:5cc7136648d1	852	while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
akashvibhute	2:3bdf0d9bb71f	853
akashvibhute	6:5cc7136648d1	854	if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached
akashvibhute	6:5cc7136648d1	855	reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
akashvibhute	6:5cc7136648d1	856	if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0
akashvibhute	6:5cc7136648d1	857	}
akashvibhute	6:5cc7136648d1	858	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	859	if(mainTimer.read_ms() - timer > (timeout+95) ){
akashvibhute	6:5cc7136648d1	860	errNotify();
akashvibhute	6:5cc7136648d1	861	#if defined (FAILURE_HANDLING)
akashvibhute	6:5cc7136648d1	862	return 0;
akashvibhute	6:5cc7136648d1	863	#endif
akashvibhute	6:5cc7136648d1	864	}
akashvibhute	6:5cc7136648d1	865	#endif
akashvibhute	2:3bdf0d9bb71f	866
akashvibhute	6:5cc7136648d1	867	}
akashvibhute	2:3bdf0d9bb71f	868
akashvibhute	6:5cc7136648d1	869	//Start Writing
akashvibhute	6:5cc7136648d1	870	startFastWrite(buf,len,0); //Write the payload if a buffer is clear
akashvibhute	6:5cc7136648d1	871
akashvibhute	6:5cc7136648d1	872	return 1; //Return 1 to indicate successful transmission
akashvibhute	2:3bdf0d9bb71f	873	}
akashvibhute	2:3bdf0d9bb71f	874
akashvibhute	2:3bdf0d9bb71f	875	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	876
akashvibhute	6:5cc7136648d1	877	void RF24::reUseTX(){
akashvibhute	6:5cc7136648d1	878	write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
akashvibhute	6:5cc7136648d1	879	spiTrans( REUSE_TX_PL );
akashvibhute	6:5cc7136648d1	880	ce(LOW); //Re-Transfer packet
akashvibhute	6:5cc7136648d1	881	ce(HIGH);
akashvibhute	2:3bdf0d9bb71f	882	}
akashvibhute	2:3bdf0d9bb71f	883
akashvibhute	2:3bdf0d9bb71f	884	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	885
akashvibhute	2:3bdf0d9bb71f	886	bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
akashvibhute	0:bb74812ac6bb	887	{
akashvibhute	6:5cc7136648d1	888	//Block until the FIFO is NOT full.
akashvibhute	6:5cc7136648d1	889	//Keep track of the MAX retries and set auto-retry if seeing failures
akashvibhute	6:5cc7136648d1	890	//Return 0 so the user can control the retrys and set a timer or failure counter if required
akashvibhute	6:5cc7136648d1	891	//The radio will auto-clear everything in the FIFO as long as CE remains high
akashvibhute	2:3bdf0d9bb71f	892
akashvibhute	6:5cc7136648d1	893	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	894	uint32_t timer = mainTimer.read_ms();
akashvibhute	6:5cc7136648d1	895	#endif
akashvibhute	6:5cc7136648d1	896
akashvibhute	6:5cc7136648d1	897	while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
akashvibhute	2:3bdf0d9bb71f	898
akashvibhute	6:5cc7136648d1	899	if( get_status() & _BV(MAX_RT)){
akashvibhute	6:5cc7136648d1	900	//reUseTX(); //Set re-transmit
akashvibhute	6:5cc7136648d1	901	write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
akashvibhute	6:5cc7136648d1	902	return 0; //Return 0. The previous payload has been retransmitted
akashvibhute	6:5cc7136648d1	903	//From the user perspective, if you get a 0, just keep trying to send the same payload
akashvibhute	6:5cc7136648d1	904	}
akashvibhute	6:5cc7136648d1	905	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	906	if(mainTimer.read_ms() - timer > 95 ){
akashvibhute	6:5cc7136648d1	907	errNotify();
akashvibhute	6:5cc7136648d1	908	#if defined (FAILURE_HANDLING)
akashvibhute	6:5cc7136648d1	909	return 0;
akashvibhute	6:5cc7136648d1	910	#endif
akashvibhute	6:5cc7136648d1	911	}
akashvibhute	6:5cc7136648d1	912	#endif
akashvibhute	6:5cc7136648d1	913	}
akashvibhute	6:5cc7136648d1	914	//Start Writing
akashvibhute	6:5cc7136648d1	915	startFastWrite(buf,len,multicast);
akashvibhute	2:3bdf0d9bb71f	916
akashvibhute	6:5cc7136648d1	917	return 1;
akashvibhute	2:3bdf0d9bb71f	918	}
akashvibhute	2:3bdf0d9bb71f	919
akashvibhute	6:5cc7136648d1	920	bool RF24::writeFast( const void* buf, uint8_t len ){
akashvibhute	6:5cc7136648d1	921	return writeFast(buf,len,0);
akashvibhute	2:3bdf0d9bb71f	922	}
akashvibhute	2:3bdf0d9bb71f	923
akashvibhute	2:3bdf0d9bb71f	924	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	925
akashvibhute	2:3bdf0d9bb71f	926	//Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
akashvibhute	2:3bdf0d9bb71f	927	//In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
akashvibhute	2:3bdf0d9bb71f	928	//Otherwise we enter Standby-II mode, which is still faster than standby mode
akashvibhute	2:3bdf0d9bb71f	929	//Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
akashvibhute	2:3bdf0d9bb71f	930
akashvibhute	6:5cc7136648d1	931	void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
akashvibhute	2:3bdf0d9bb71f	932
akashvibhute	6:5cc7136648d1	933	//write_payload( buf,len);
akashvibhute	6:5cc7136648d1	934	write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
akashvibhute	6:5cc7136648d1	935	if(startTx){
akashvibhute	6:5cc7136648d1	936	ce(HIGH);
akashvibhute	6:5cc7136648d1	937	}
akashvibhute	6:5cc7136648d1	938
akashvibhute	2:3bdf0d9bb71f	939	}
akashvibhute	2:3bdf0d9bb71f	940
akashvibhute	2:3bdf0d9bb71f	941	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	942
akashvibhute	2:3bdf0d9bb71f	943	//Added the original startWrite back in so users can still use interrupts, ack payloads, etc
akashvibhute	2:3bdf0d9bb71f	944	//Allows the library to pass all tests
akashvibhute	6:5cc7136648d1	945	void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
akashvibhute	2:3bdf0d9bb71f	946
akashvibhute	6:5cc7136648d1	947	// Send the payload
akashvibhute	2:3bdf0d9bb71f	948
akashvibhute	6:5cc7136648d1	949	//write_payload( buf, len );
akashvibhute	6:5cc7136648d1	950	write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
akashvibhute	6:5cc7136648d1	951	ce(HIGH);
akashvibhute	6:5cc7136648d1	952
akashvibhute	6:5cc7136648d1	953	wait_us(10);
akashvibhute	6:5cc7136648d1	954
akashvibhute	6:5cc7136648d1	955	ce(LOW);
akashvibhute	2:3bdf0d9bb71f	956
akashvibhute	2:3bdf0d9bb71f	957
akashvibhute	2:3bdf0d9bb71f	958	}
akashvibhute	2:3bdf0d9bb71f	959
akashvibhute	2:3bdf0d9bb71f	960	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	961
akashvibhute	6:5cc7136648d1	962	bool RF24::rxFifoFull(){
akashvibhute	6:5cc7136648d1	963	return read_register(FIFO_STATUS) & _BV(RX_FULL);
akashvibhute	6:5cc7136648d1	964	}
akashvibhute	6:5cc7136648d1	965	/****************************************************************************/
akashvibhute	6:5cc7136648d1	966
akashvibhute	6:5cc7136648d1	967	bool RF24::txStandBy(){
akashvibhute	6:5cc7136648d1	968
akashvibhute	6:5cc7136648d1	969	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	970	uint32_t timeout = mainTimer.read_ms();
akashvibhute	6:5cc7136648d1	971	#endif
akashvibhute	6:5cc7136648d1	972	while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
akashvibhute	6:5cc7136648d1	973	if( get_status() & _BV(MAX_RT)){
akashvibhute	6:5cc7136648d1	974	write_register(NRF_STATUS,_BV(MAX_RT) );
akashvibhute	6:5cc7136648d1	975	ce(LOW);
akashvibhute	6:5cc7136648d1	976	flush_tx(); //Non blocking, flush the data
akashvibhute	6:5cc7136648d1	977	return 0;
akashvibhute	6:5cc7136648d1	978	}
akashvibhute	6:5cc7136648d1	979	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	980	if( mainTimer.read_ms() - timeout > 95){
akashvibhute	6:5cc7136648d1	981	errNotify();
akashvibhute	6:5cc7136648d1	982	#if defined (FAILURE_HANDLING)
akashvibhute	6:5cc7136648d1	983	return 0;
akashvibhute	6:5cc7136648d1	984	#endif
akashvibhute	6:5cc7136648d1	985	}
akashvibhute	6:5cc7136648d1	986	#endif
akashvibhute	6:5cc7136648d1	987	}
akashvibhute	6:5cc7136648d1	988
akashvibhute	6:5cc7136648d1	989	ce(LOW); //Set STANDBY-I mode
akashvibhute	6:5cc7136648d1	990	return 1;
akashvibhute	6:5cc7136648d1	991	}
akashvibhute	6:5cc7136648d1	992
akashvibhute	6:5cc7136648d1	993	/****************************************************************************/
akashvibhute	6:5cc7136648d1	994
akashvibhute	6:5cc7136648d1	995	bool RF24::txStandBy(uint32_t timeout, bool startTx){
akashvibhute	2:3bdf0d9bb71f	996
akashvibhute	6:5cc7136648d1	997	if(startTx){
akashvibhute	6:5cc7136648d1	998	stopListening();
akashvibhute	6:5cc7136648d1	999	ce(HIGH);
akashvibhute	6:5cc7136648d1	1000	}
akashvibhute	6:5cc7136648d1	1001	uint32_t start = mainTimer.read_ms();
akashvibhute	6:5cc7136648d1	1002
akashvibhute	6:5cc7136648d1	1003	while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
akashvibhute	6:5cc7136648d1	1004	if( get_status() & _BV(MAX_RT)){
akashvibhute	6:5cc7136648d1	1005	write_register(NRF_STATUS,_BV(MAX_RT) );
akashvibhute	6:5cc7136648d1	1006	ce(LOW); //Set re-transmit
akashvibhute	6:5cc7136648d1	1007	ce(HIGH);
akashvibhute	6:5cc7136648d1	1008	if(mainTimer.read_ms() - start >= timeout){
akashvibhute	6:5cc7136648d1	1009	ce(LOW); flush_tx(); return 0;
akashvibhute	6:5cc7136648d1	1010	}
akashvibhute	6:5cc7136648d1	1011	}
akashvibhute	6:5cc7136648d1	1012	#if defined (FAILURE_HANDLING) \|\| defined (RF24_LINUX)
akashvibhute	6:5cc7136648d1	1013	if( mainTimer.read_ms() - start > (timeout+95)){
akashvibhute	6:5cc7136648d1	1014	errNotify();
akashvibhute	6:5cc7136648d1	1015	#if defined (FAILURE_HANDLING)
akashvibhute	6:5cc7136648d1	1016	return 0;
akashvibhute	6:5cc7136648d1	1017	#endif
akashvibhute	6:5cc7136648d1	1018	}
akashvibhute	6:5cc7136648d1	1019	#endif
akashvibhute	6:5cc7136648d1	1020	}
akashvibhute	6:5cc7136648d1	1021
akashvibhute	6:5cc7136648d1	1022
akashvibhute	6:5cc7136648d1	1023	ce(LOW); //Set STANDBY-I mode
akashvibhute	6:5cc7136648d1	1024	return 1;
akashvibhute	6:5cc7136648d1	1025
akashvibhute	6:5cc7136648d1	1026	}
akashvibhute	6:5cc7136648d1	1027
akashvibhute	6:5cc7136648d1	1028	/****************************************************************************/
akashvibhute	6:5cc7136648d1	1029
akashvibhute	6:5cc7136648d1	1030	void RF24::maskIRQ(bool tx, bool fail, bool rx){
akashvibhute	6:5cc7136648d1	1031
akashvibhute	6:5cc7136648d1	1032	uint8_t config = read_register(NRF_CONFIG);
akashvibhute	6:5cc7136648d1	1033	/* clear the interrupt flags */
akashvibhute	6:5cc7136648d1	1034	config &= ~(1 << MASK_MAX_RT \| 1 << MASK_TX_DS \| 1 << MASK_RX_DR);
akashvibhute	6:5cc7136648d1	1035	/* set the specified interrupt flags */
akashvibhute	6:5cc7136648d1	1036	config \|= fail << MASK_MAX_RT \| tx << MASK_TX_DS \| rx << MASK_RX_DR;
akashvibhute	6:5cc7136648d1	1037	write_register(NRF_CONFIG, config);
akashvibhute	0:bb74812ac6bb	1038	}
akashvibhute	0:bb74812ac6bb	1039
akashvibhute	0:bb74812ac6bb	1040	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1041
akashvibhute	0:bb74812ac6bb	1042	uint8_t RF24::getDynamicPayloadSize(void)
akashvibhute	0:bb74812ac6bb	1043	{
akashvibhute	6:5cc7136648d1	1044	uint8_t result = 0;
akashvibhute	0:bb74812ac6bb	1045
akashvibhute	6:5cc7136648d1	1046
akashvibhute	6:5cc7136648d1	1047
akashvibhute	6:5cc7136648d1	1048
akashvibhute	6:5cc7136648d1	1049
akashvibhute	6:5cc7136648d1	1050
akashvibhute	6:5cc7136648d1	1051
akashvibhute	6:5cc7136648d1	1052
akashvibhute	6:5cc7136648d1	1053
akashvibhute	6:5cc7136648d1	1054	beginTransaction();
akashvibhute	6:5cc7136648d1	1055	spi.write( R_RX_PL_WID );
akashvibhute	6:5cc7136648d1	1056	result = spi.write(0xff);
akashvibhute	6:5cc7136648d1	1057	endTransaction();
akashvibhute	6:5cc7136648d1	1058
akashvibhute	0:bb74812ac6bb	1059
akashvibhute	6:5cc7136648d1	1060	if(result > 32) { flush_rx(); wait_ms(2); return 0; }
akashvibhute	6:5cc7136648d1	1061	return result;
akashvibhute	0:bb74812ac6bb	1062	}
akashvibhute	0:bb74812ac6bb	1063
akashvibhute	0:bb74812ac6bb	1064	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1065
akashvibhute	0:bb74812ac6bb	1066	bool RF24::available(void)
akashvibhute	0:bb74812ac6bb	1067	{
akashvibhute	6:5cc7136648d1	1068	return available(NULL);
akashvibhute	0:bb74812ac6bb	1069	}
akashvibhute	0:bb74812ac6bb	1070
akashvibhute	0:bb74812ac6bb	1071	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1072
akashvibhute	0:bb74812ac6bb	1073	bool RF24::available(uint8_t* pipe_num)
akashvibhute	0:bb74812ac6bb	1074	{
akashvibhute	6:5cc7136648d1	1075	if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
akashvibhute	0:bb74812ac6bb	1076
akashvibhute	6:5cc7136648d1	1077	// If the caller wants the pipe number, include that
akashvibhute	6:5cc7136648d1	1078	if ( pipe_num ){
akashvibhute	6:5cc7136648d1	1079	uint8_t status = get_status();
akashvibhute	6:5cc7136648d1	1080	*pipe_num = ( status >> RX_P_NO ) & 0b111;
akashvibhute	6:5cc7136648d1	1081	}
akashvibhute	6:5cc7136648d1	1082	return 1;
akashvibhute	6:5cc7136648d1	1083	}
akashvibhute	3:e94be00fd19e	1084
akashvibhute	6:5cc7136648d1	1085
akashvibhute	6:5cc7136648d1	1086	return 0;
akashvibhute	6:5cc7136648d1	1087
akashvibhute	6:5cc7136648d1	1088
akashvibhute	0:bb74812ac6bb	1089	}
akashvibhute	0:bb74812ac6bb	1090
akashvibhute	0:bb74812ac6bb	1091	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1092
akashvibhute	6:5cc7136648d1	1093	void RF24::read( void* buf, uint8_t len ){
akashvibhute	2:3bdf0d9bb71f	1094
akashvibhute	6:5cc7136648d1	1095	// Fetch the payload
akashvibhute	6:5cc7136648d1	1096	read_payload( buf, len );
akashvibhute	0:bb74812ac6bb	1097
akashvibhute	6:5cc7136648d1	1098	//Clear the two possible interrupt flags with one command
akashvibhute	6:5cc7136648d1	1099	write_register(NRF_STATUS,_BV(RX_DR) \| _BV(MAX_RT) \| _BV(TX_DS) );
akashvibhute	6:5cc7136648d1	1100
akashvibhute	0:bb74812ac6bb	1101	}
akashvibhute	0:bb74812ac6bb	1102
akashvibhute	0:bb74812ac6bb	1103	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1104
akashvibhute	0:bb74812ac6bb	1105	void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
akashvibhute	0:bb74812ac6bb	1106	{
akashvibhute	6:5cc7136648d1	1107	// Read the status & reset the status in one easy call
akashvibhute	6:5cc7136648d1	1108	// Or is that such a good idea?
akashvibhute	6:5cc7136648d1	1109	uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) \| _BV(TX_DS) \| _BV(MAX_RT) );
akashvibhute	0:bb74812ac6bb	1110
akashvibhute	6:5cc7136648d1	1111	// Report to the user what happened
akashvibhute	6:5cc7136648d1	1112	tx_ok = status & _BV(TX_DS);
akashvibhute	6:5cc7136648d1	1113	tx_fail = status & _BV(MAX_RT);
akashvibhute	6:5cc7136648d1	1114	rx_ready = status & _BV(RX_DR);
akashvibhute	0:bb74812ac6bb	1115	}
akashvibhute	0:bb74812ac6bb	1116
akashvibhute	0:bb74812ac6bb	1117	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1118
akashvibhute	0:bb74812ac6bb	1119	void RF24::openWritingPipe(uint64_t value)
akashvibhute	0:bb74812ac6bb	1120	{
akashvibhute	6:5cc7136648d1	1121	// Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
akashvibhute	6:5cc7136648d1	1122	// expects it LSB first too, so we're good.
akashvibhute	0:bb74812ac6bb	1123
akashvibhute	6:5cc7136648d1	1124	write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
akashvibhute	6:5cc7136648d1	1125	write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
akashvibhute	6:5cc7136648d1	1126
akashvibhute	6:5cc7136648d1	1127
akashvibhute	6:5cc7136648d1	1128	//const uint8_t max_payload_size = 32;
akashvibhute	6:5cc7136648d1	1129	//write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
akashvibhute	6:5cc7136648d1	1130	write_register(RX_PW_P0,payload_size);
akashvibhute	0:bb74812ac6bb	1131	}
akashvibhute	0:bb74812ac6bb	1132
akashvibhute	0:bb74812ac6bb	1133	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	1134	void RF24::openWritingPipe(const uint8_t *address)
akashvibhute	2:3bdf0d9bb71f	1135	{
akashvibhute	6:5cc7136648d1	1136	// Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
akashvibhute	6:5cc7136648d1	1137	// expects it LSB first too, so we're good.
akashvibhute	0:bb74812ac6bb	1138
akashvibhute	6:5cc7136648d1	1139	write_register(RX_ADDR_P0,address, addr_width);
akashvibhute	6:5cc7136648d1	1140	write_register(TX_ADDR, address, addr_width);
akashvibhute	2:3bdf0d9bb71f	1141
akashvibhute	6:5cc7136648d1	1142	//const uint8_t max_payload_size = 32;
akashvibhute	6:5cc7136648d1	1143	//write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
akashvibhute	6:5cc7136648d1	1144	write_register(RX_PW_P0,payload_size);
akashvibhute	2:3bdf0d9bb71f	1145	}
akashvibhute	2:3bdf0d9bb71f	1146
akashvibhute	2:3bdf0d9bb71f	1147	/****************************************************************************/
akashvibhute	6:5cc7136648d1	1148	static const uint8_t child_pipe[] PROGMEM =
akashvibhute	6:5cc7136648d1	1149	{
akashvibhute	6:5cc7136648d1	1150	RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
akashvibhute	0:bb74812ac6bb	1151	};
akashvibhute	6:5cc7136648d1	1152	static const uint8_t child_payload_size[] PROGMEM =
akashvibhute	6:5cc7136648d1	1153	{
akashvibhute	6:5cc7136648d1	1154	RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
akashvibhute	0:bb74812ac6bb	1155	};
akashvibhute	2:3bdf0d9bb71f	1156
akashvibhute	0:bb74812ac6bb	1157
akashvibhute	0:bb74812ac6bb	1158	void RF24::openReadingPipe(uint8_t child, uint64_t address)
akashvibhute	0:bb74812ac6bb	1159	{
akashvibhute	6:5cc7136648d1	1160	// If this is pipe 0, cache the address. This is needed because
akashvibhute	6:5cc7136648d1	1161	// openWritingPipe() will overwrite the pipe 0 address, so
akashvibhute	6:5cc7136648d1	1162	// startListening() will have to restore it.
akashvibhute	6:5cc7136648d1	1163	if (child == 0){
akashvibhute	6:5cc7136648d1	1164	memcpy(pipe0_reading_address,&address,addr_width);
akashvibhute	6:5cc7136648d1	1165	}
akashvibhute	0:bb74812ac6bb	1166
akashvibhute	6:5cc7136648d1	1167	if (child <= 6)
akashvibhute	6:5cc7136648d1	1168	{
akashvibhute	6:5cc7136648d1	1169	// For pipes 2-5, only write the LSB
akashvibhute	6:5cc7136648d1	1170	if ( child < 2 )
akashvibhute	6:5cc7136648d1	1171	write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
akashvibhute	6:5cc7136648d1	1172	else
akashvibhute	6:5cc7136648d1	1173	write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
akashvibhute	0:bb74812ac6bb	1174
akashvibhute	6:5cc7136648d1	1175	write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
akashvibhute	0:bb74812ac6bb	1176
akashvibhute	6:5cc7136648d1	1177	// Note it would be more efficient to set all of the bits for all open
akashvibhute	6:5cc7136648d1	1178	// pipes at once. However, I thought it would make the calling code
akashvibhute	6:5cc7136648d1	1179	// more simple to do it this way.
akashvibhute	6:5cc7136648d1	1180	write_register(EN_RXADDR,read_register(EN_RXADDR) \| _BV(pgm_read_byte(&child_pipe_enable[child])));
akashvibhute	6:5cc7136648d1	1181	}
akashvibhute	2:3bdf0d9bb71f	1182	}
akashvibhute	2:3bdf0d9bb71f	1183
akashvibhute	2:3bdf0d9bb71f	1184	/****************************************************************************/
akashvibhute	6:5cc7136648d1	1185	void RF24::setAddressWidth(uint8_t a_width){
akashvibhute	2:3bdf0d9bb71f	1186
akashvibhute	6:5cc7136648d1	1187	if(a_width -= 2){
akashvibhute	6:5cc7136648d1	1188	write_register(SETUP_AW,a_width%4);
akashvibhute	6:5cc7136648d1	1189	addr_width = (a_width%4) + 2;
akashvibhute	6:5cc7136648d1	1190	}
akashvibhute	6:5cc7136648d1	1191
akashvibhute	2:3bdf0d9bb71f	1192	}
akashvibhute	2:3bdf0d9bb71f	1193
akashvibhute	2:3bdf0d9bb71f	1194	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	1195
akashvibhute	2:3bdf0d9bb71f	1196	void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
akashvibhute	2:3bdf0d9bb71f	1197	{
akashvibhute	6:5cc7136648d1	1198	// If this is pipe 0, cache the address. This is needed because
akashvibhute	6:5cc7136648d1	1199	// openWritingPipe() will overwrite the pipe 0 address, so
akashvibhute	6:5cc7136648d1	1200	// startListening() will have to restore it.
akashvibhute	6:5cc7136648d1	1201	if (child == 0){
akashvibhute	6:5cc7136648d1	1202	memcpy(pipe0_reading_address,address,addr_width);
akashvibhute	6:5cc7136648d1	1203	}
akashvibhute	6:5cc7136648d1	1204	if (child <= 6)
akashvibhute	6:5cc7136648d1	1205	{
akashvibhute	6:5cc7136648d1	1206	// For pipes 2-5, only write the LSB
akashvibhute	6:5cc7136648d1	1207	if ( child < 2 ){
akashvibhute	6:5cc7136648d1	1208	write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
akashvibhute	6:5cc7136648d1	1209	}else{
akashvibhute	6:5cc7136648d1	1210	write_register(pgm_read_byte(&child_pipe[child]), address, 1);
akashvibhute	6:5cc7136648d1	1211	}
akashvibhute	6:5cc7136648d1	1212	write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
akashvibhute	2:3bdf0d9bb71f	1213
akashvibhute	6:5cc7136648d1	1214	// Note it would be more efficient to set all of the bits for all open
akashvibhute	6:5cc7136648d1	1215	// pipes at once. However, I thought it would make the calling code
akashvibhute	6:5cc7136648d1	1216	// more simple to do it this way.
akashvibhute	6:5cc7136648d1	1217	write_register(EN_RXADDR,read_register(EN_RXADDR) \| _BV(pgm_read_byte(&child_pipe_enable[child])));
akashvibhute	6:5cc7136648d1	1218
akashvibhute	6:5cc7136648d1	1219	}
akashvibhute	2:3bdf0d9bb71f	1220	}
akashvibhute	2:3bdf0d9bb71f	1221
akashvibhute	2:3bdf0d9bb71f	1222	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	1223
akashvibhute	2:3bdf0d9bb71f	1224	void RF24::closeReadingPipe( uint8_t pipe )
akashvibhute	2:3bdf0d9bb71f	1225	{
akashvibhute	6:5cc7136648d1	1226	write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
akashvibhute	0:bb74812ac6bb	1227	}
akashvibhute	0:bb74812ac6bb	1228
akashvibhute	0:bb74812ac6bb	1229	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1230
akashvibhute	0:bb74812ac6bb	1231	void RF24::toggle_features(void)
akashvibhute	0:bb74812ac6bb	1232	{
akashvibhute	2:3bdf0d9bb71f	1233	beginTransaction();
akashvibhute	6:5cc7136648d1	1234	spi.write( ACTIVATE );
akashvibhute	2:3bdf0d9bb71f	1235	spi.write( 0x73 );
akashvibhute	6:5cc7136648d1	1236	endTransaction();
akashvibhute	0:bb74812ac6bb	1237	}
akashvibhute	0:bb74812ac6bb	1238
akashvibhute	0:bb74812ac6bb	1239	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1240
akashvibhute	0:bb74812ac6bb	1241	void RF24::enableDynamicPayloads(void)
akashvibhute	0:bb74812ac6bb	1242	{
akashvibhute	6:5cc7136648d1	1243	// Enable dynamic payload throughout the system
akashvibhute	0:bb74812ac6bb	1244
akashvibhute	2:3bdf0d9bb71f	1245	//toggle_features();
akashvibhute	0:bb74812ac6bb	1246	write_register(FEATURE,read_register(FEATURE) \| _BV(EN_DPL) );
akashvibhute	2:3bdf0d9bb71f	1247
akashvibhute	6:5cc7136648d1	1248
akashvibhute	6:5cc7136648d1	1249	IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
akashvibhute	0:bb74812ac6bb	1250
akashvibhute	6:5cc7136648d1	1251	// Enable dynamic payload on all pipes
akashvibhute	6:5cc7136648d1	1252	//
akashvibhute	6:5cc7136648d1	1253	// Not sure the use case of only having dynamic payload on certain
akashvibhute	6:5cc7136648d1	1254	// pipes, so the library does not support it.
akashvibhute	6:5cc7136648d1	1255	write_register(DYNPD,read_register(DYNPD) \| _BV(DPL_P5) \| _BV(DPL_P4) \| _BV(DPL_P3) \| _BV(DPL_P2) \| _BV(DPL_P1) \| _BV(DPL_P0));
akashvibhute	0:bb74812ac6bb	1256
akashvibhute	6:5cc7136648d1	1257	dynamic_payloads_enabled = true;
akashvibhute	0:bb74812ac6bb	1258	}
akashvibhute	0:bb74812ac6bb	1259
akashvibhute	0:bb74812ac6bb	1260	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1261
akashvibhute	0:bb74812ac6bb	1262	void RF24::enableAckPayload(void)
akashvibhute	0:bb74812ac6bb	1263	{
akashvibhute	6:5cc7136648d1	1264	//
akashvibhute	6:5cc7136648d1	1265	// enable ack payload and dynamic payload features
akashvibhute	6:5cc7136648d1	1266	//
akashvibhute	0:bb74812ac6bb	1267
akashvibhute	2:3bdf0d9bb71f	1268	//toggle_features();
akashvibhute	2:3bdf0d9bb71f	1269	write_register(FEATURE,read_register(FEATURE) \| _BV(EN_ACK_PAY) \| _BV(EN_DPL) );
akashvibhute	0:bb74812ac6bb	1270
akashvibhute	6:5cc7136648d1	1271	IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
akashvibhute	0:bb74812ac6bb	1272
akashvibhute	6:5cc7136648d1	1273	//
akashvibhute	6:5cc7136648d1	1274	// Enable dynamic payload on pipes 0 & 1
akashvibhute	6:5cc7136648d1	1275	//
akashvibhute	0:bb74812ac6bb	1276
akashvibhute	6:5cc7136648d1	1277	write_register(DYNPD,read_register(DYNPD) \| _BV(DPL_P1) \| _BV(DPL_P0));
akashvibhute	6:5cc7136648d1	1278	dynamic_payloads_enabled = true;
akashvibhute	2:3bdf0d9bb71f	1279	}
akashvibhute	2:3bdf0d9bb71f	1280
akashvibhute	2:3bdf0d9bb71f	1281	/****************************************************************************/
akashvibhute	2:3bdf0d9bb71f	1282
akashvibhute	6:5cc7136648d1	1283	void RF24::enableDynamicAck(void){
akashvibhute	6:5cc7136648d1	1284	//
akashvibhute	6:5cc7136648d1	1285	// enable dynamic ack features
akashvibhute	6:5cc7136648d1	1286	//
akashvibhute	2:3bdf0d9bb71f	1287	//toggle_features();
akashvibhute	2:3bdf0d9bb71f	1288	write_register(FEATURE,read_register(FEATURE) \| _BV(EN_DYN_ACK) );
akashvibhute	2:3bdf0d9bb71f	1289
akashvibhute	6:5cc7136648d1	1290	IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
akashvibhute	2:3bdf0d9bb71f	1291
akashvibhute	2:3bdf0d9bb71f	1292
akashvibhute	0:bb74812ac6bb	1293	}
akashvibhute	0:bb74812ac6bb	1294
akashvibhute	0:bb74812ac6bb	1295	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1296
akashvibhute	0:bb74812ac6bb	1297	void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
akashvibhute	0:bb74812ac6bb	1298	{
akashvibhute	6:5cc7136648d1	1299	const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
akashvibhute	0:bb74812ac6bb	1300
akashvibhute	6:5cc7136648d1	1301	uint8_t data_len = rf24_min(len,32);
akashvibhute	2:3bdf0d9bb71f	1302
akashvibhute	6:5cc7136648d1	1303
akashvibhute	6:5cc7136648d1	1304
akashvibhute	6:5cc7136648d1	1305
akashvibhute	6:5cc7136648d1	1306
akashvibhute	6:5cc7136648d1	1307
akashvibhute	6:5cc7136648d1	1308
akashvibhute	6:5cc7136648d1	1309
akashvibhute	6:5cc7136648d1	1310
akashvibhute	6:5cc7136648d1	1311
akashvibhute	6:5cc7136648d1	1312
akashvibhute	6:5cc7136648d1	1313
akashvibhute	6:5cc7136648d1	1314
akashvibhute	6:5cc7136648d1	1315	beginTransaction();
akashvibhute	6:5cc7136648d1	1316	spi.write(W_ACK_PAYLOAD \| ( pipe & 0b111 ) );
akashvibhute	2:3bdf0d9bb71f	1317
akashvibhute	6:5cc7136648d1	1318	while ( data_len-- )
akashvibhute	6:5cc7136648d1	1319	spi.write(*current++);
akashvibhute	6:5cc7136648d1	1320	endTransaction();
akashvibhute	6:5cc7136648d1	1321
akashvibhute	6:5cc7136648d1	1322
akashvibhute	0:bb74812ac6bb	1323
akashvibhute	0:bb74812ac6bb	1324	}
akashvibhute	0:bb74812ac6bb	1325
akashvibhute	0:bb74812ac6bb	1326	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1327
akashvibhute	0:bb74812ac6bb	1328	bool RF24::isAckPayloadAvailable(void)
akashvibhute	0:bb74812ac6bb	1329	{
akashvibhute	6:5cc7136648d1	1330	return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
akashvibhute	0:bb74812ac6bb	1331	}
akashvibhute	0:bb74812ac6bb	1332
akashvibhute	0:bb74812ac6bb	1333	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1334
akashvibhute	0:bb74812ac6bb	1335	bool RF24::isPVariant(void)
akashvibhute	0:bb74812ac6bb	1336	{
akashvibhute	6:5cc7136648d1	1337	return p_variant ;
akashvibhute	0:bb74812ac6bb	1338	}
akashvibhute	0:bb74812ac6bb	1339
akashvibhute	0:bb74812ac6bb	1340	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1341
akashvibhute	0:bb74812ac6bb	1342	void RF24::setAutoAck(bool enable)
akashvibhute	0:bb74812ac6bb	1343	{
akashvibhute	6:5cc7136648d1	1344	if ( enable )
akashvibhute	6:5cc7136648d1	1345	write_register(EN_AA, 0b111111);
akashvibhute	6:5cc7136648d1	1346	else
akashvibhute	6:5cc7136648d1	1347	write_register(EN_AA, 0);
akashvibhute	0:bb74812ac6bb	1348	}
akashvibhute	0:bb74812ac6bb	1349
akashvibhute	0:bb74812ac6bb	1350	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1351
akashvibhute	0:bb74812ac6bb	1352	void RF24::setAutoAck( uint8_t pipe, bool enable )
akashvibhute	0:bb74812ac6bb	1353	{
akashvibhute	6:5cc7136648d1	1354	if ( pipe <= 6 )
akashvibhute	6:5cc7136648d1	1355	{
akashvibhute	6:5cc7136648d1	1356	uint8_t en_aa = read_register( EN_AA ) ;
akashvibhute	6:5cc7136648d1	1357	if( enable )
akashvibhute	6:5cc7136648d1	1358	{
akashvibhute	6:5cc7136648d1	1359	en_aa \|= _BV(pipe) ;
akashvibhute	0:bb74812ac6bb	1360	}
akashvibhute	6:5cc7136648d1	1361	else
akashvibhute	6:5cc7136648d1	1362	{
akashvibhute	6:5cc7136648d1	1363	en_aa &= ~_BV(pipe) ;
akashvibhute	6:5cc7136648d1	1364	}
akashvibhute	6:5cc7136648d1	1365	write_register( EN_AA, en_aa ) ;
akashvibhute	6:5cc7136648d1	1366	}
akashvibhute	0:bb74812ac6bb	1367	}
akashvibhute	0:bb74812ac6bb	1368
akashvibhute	0:bb74812ac6bb	1369	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1370
akashvibhute	0:bb74812ac6bb	1371	bool RF24::testCarrier(void)
akashvibhute	0:bb74812ac6bb	1372	{
akashvibhute	6:5cc7136648d1	1373	return ( read_register(CD) & 1 );
akashvibhute	0:bb74812ac6bb	1374	}
akashvibhute	0:bb74812ac6bb	1375
akashvibhute	0:bb74812ac6bb	1376	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1377
akashvibhute	0:bb74812ac6bb	1378	bool RF24::testRPD(void)
akashvibhute	0:bb74812ac6bb	1379	{
akashvibhute	6:5cc7136648d1	1380	return ( read_register(RPD) & 1 ) ;
akashvibhute	0:bb74812ac6bb	1381	}
akashvibhute	0:bb74812ac6bb	1382
akashvibhute	0:bb74812ac6bb	1383	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1384
akashvibhute	2:3bdf0d9bb71f	1385	void RF24::setPALevel(uint8_t level)
akashvibhute	0:bb74812ac6bb	1386	{
akashvibhute	2:3bdf0d9bb71f	1387
akashvibhute	6:5cc7136648d1	1388	uint8_t setup = read_register(RF_SETUP) & 0b11111000;
akashvibhute	0:bb74812ac6bb	1389
akashvibhute	6:5cc7136648d1	1390	if(level > 3){ // If invalid level, go to max PA
akashvibhute	6:5cc7136648d1	1391	level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
akashvibhute	6:5cc7136648d1	1392	}else{
akashvibhute	6:5cc7136648d1	1393	level = (level << 1) + 1; // Else set level as requested
akashvibhute	6:5cc7136648d1	1394	}
akashvibhute	0:bb74812ac6bb	1395
akashvibhute	2:3bdf0d9bb71f	1396
akashvibhute	6:5cc7136648d1	1397	write_register( RF_SETUP, setup \|= level ) ; // Write it to the chip
akashvibhute	0:bb74812ac6bb	1398	}
akashvibhute	0:bb74812ac6bb	1399
akashvibhute	0:bb74812ac6bb	1400	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1401
akashvibhute	2:3bdf0d9bb71f	1402	uint8_t RF24::getPALevel(void)
akashvibhute	0:bb74812ac6bb	1403	{
akashvibhute	0:bb74812ac6bb	1404
akashvibhute	6:5cc7136648d1	1405	return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) \| _BV(RF_PWR_HIGH))) >> 1 ;
akashvibhute	0:bb74812ac6bb	1406	}
akashvibhute	0:bb74812ac6bb	1407
akashvibhute	0:bb74812ac6bb	1408	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1409
akashvibhute	0:bb74812ac6bb	1410	bool RF24::setDataRate(rf24_datarate_e speed)
akashvibhute	0:bb74812ac6bb	1411	{
akashvibhute	6:5cc7136648d1	1412	bool result = false;
akashvibhute	6:5cc7136648d1	1413	uint8_t setup = read_register(RF_SETUP) ;
akashvibhute	0:bb74812ac6bb	1414
akashvibhute	6:5cc7136648d1	1415	// HIGH and LOW '00' is 1Mbs - our default
akashvibhute	6:5cc7136648d1	1416	setup &= ~(_BV(RF_DR_LOW) \| _BV(RF_DR_HIGH)) ;
akashvibhute	6:5cc7136648d1	1417
akashvibhute	6:5cc7136648d1	1418
akashvibhute	6:5cc7136648d1	1419
akashvibhute	6:5cc7136648d1	1420
akashvibhute	2:3bdf0d9bb71f	1421	txRxDelay=85;
akashvibhute	2:3bdf0d9bb71f	1422
akashvibhute	6:5cc7136648d1	1423	if( speed == RF24_250KBPS )
akashvibhute	6:5cc7136648d1	1424	{
akashvibhute	6:5cc7136648d1	1425	// Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
akashvibhute	6:5cc7136648d1	1426	// Making it '10'.
akashvibhute	6:5cc7136648d1	1427	setup \|= _BV( RF_DR_LOW ) ;
akashvibhute	6:5cc7136648d1	1428
akashvibhute	6:5cc7136648d1	1429
akashvibhute	6:5cc7136648d1	1430
akashvibhute	6:5cc7136648d1	1431	txRxDelay=155;
akashvibhute	6:5cc7136648d1	1432
akashvibhute	6:5cc7136648d1	1433	}
akashvibhute	6:5cc7136648d1	1434	else
akashvibhute	6:5cc7136648d1	1435	{
akashvibhute	6:5cc7136648d1	1436	// Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
akashvibhute	6:5cc7136648d1	1437	// Making it '01'
akashvibhute	6:5cc7136648d1	1438	if ( speed == RF24_2MBPS )
akashvibhute	6:5cc7136648d1	1439	{
akashvibhute	6:5cc7136648d1	1440	setup \|= _BV(RF_DR_HIGH);
akashvibhute	6:5cc7136648d1	1441
akashvibhute	6:5cc7136648d1	1442
akashvibhute	6:5cc7136648d1	1443	//txRxDelay=65;
akashvibhute	6:5cc7136648d1	1444	txRxDelay=15; //mbed works fine with this latency
akashvibhute	6:5cc7136648d1	1445
akashvibhute	0:bb74812ac6bb	1446	}
akashvibhute	6:5cc7136648d1	1447	}
akashvibhute	6:5cc7136648d1	1448	write_register(RF_SETUP,setup);
akashvibhute	0:bb74812ac6bb	1449
akashvibhute	6:5cc7136648d1	1450	// Verify our result
akashvibhute	6:5cc7136648d1	1451	if ( read_register(RF_SETUP) == setup )
akashvibhute	6:5cc7136648d1	1452	{
akashvibhute	6:5cc7136648d1	1453	result = true;
akashvibhute	6:5cc7136648d1	1454	}
akashvibhute	6:5cc7136648d1	1455	return result;
akashvibhute	0:bb74812ac6bb	1456	}
akashvibhute	0:bb74812ac6bb	1457
akashvibhute	0:bb74812ac6bb	1458	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1459
akashvibhute	0:bb74812ac6bb	1460	rf24_datarate_e RF24::getDataRate( void )
akashvibhute	0:bb74812ac6bb	1461	{
akashvibhute	6:5cc7136648d1	1462	rf24_datarate_e result ;
akashvibhute	6:5cc7136648d1	1463	uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) \| _BV(RF_DR_HIGH));
akashvibhute	2:3bdf0d9bb71f	1464
akashvibhute	6:5cc7136648d1	1465	// switch uses RAM (evil!)
akashvibhute	6:5cc7136648d1	1466	// Order matters in our case below
akashvibhute	6:5cc7136648d1	1467	if ( dr == _BV(RF_DR_LOW) )
akashvibhute	6:5cc7136648d1	1468	{
akashvibhute	6:5cc7136648d1	1469	// '10' = 250KBPS
akashvibhute	6:5cc7136648d1	1470	result = RF24_250KBPS ;
akashvibhute	6:5cc7136648d1	1471	}
akashvibhute	6:5cc7136648d1	1472	else if ( dr == _BV(RF_DR_HIGH) )
akashvibhute	6:5cc7136648d1	1473	{
akashvibhute	6:5cc7136648d1	1474	// '01' = 2MBPS
akashvibhute	6:5cc7136648d1	1475	result = RF24_2MBPS ;
akashvibhute	6:5cc7136648d1	1476	}
akashvibhute	6:5cc7136648d1	1477	else
akashvibhute	6:5cc7136648d1	1478	{
akashvibhute	6:5cc7136648d1	1479	// '00' = 1MBPS
akashvibhute	6:5cc7136648d1	1480	result = RF24_1MBPS ;
akashvibhute	6:5cc7136648d1	1481	}
akashvibhute	6:5cc7136648d1	1482	return result ;
akashvibhute	0:bb74812ac6bb	1483	}
akashvibhute	0:bb74812ac6bb	1484
akashvibhute	0:bb74812ac6bb	1485	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1486
akashvibhute	0:bb74812ac6bb	1487	void RF24::setCRCLength(rf24_crclength_e length)
akashvibhute	0:bb74812ac6bb	1488	{
akashvibhute	6:5cc7136648d1	1489	uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) \| _BV(EN_CRC)) ;
akashvibhute	2:3bdf0d9bb71f	1490
akashvibhute	6:5cc7136648d1	1491	// switch uses RAM (evil!)
akashvibhute	6:5cc7136648d1	1492	if ( length == RF24_CRC_DISABLED )
akashvibhute	6:5cc7136648d1	1493	{
akashvibhute	6:5cc7136648d1	1494	// Do nothing, we turned it off above.
akashvibhute	6:5cc7136648d1	1495	}
akashvibhute	6:5cc7136648d1	1496	else if ( length == RF24_CRC_8 )
akashvibhute	6:5cc7136648d1	1497	{
akashvibhute	6:5cc7136648d1	1498	config \|= _BV(EN_CRC);
akashvibhute	6:5cc7136648d1	1499	}
akashvibhute	6:5cc7136648d1	1500	else
akashvibhute	6:5cc7136648d1	1501	{
akashvibhute	6:5cc7136648d1	1502	config \|= _BV(EN_CRC);
akashvibhute	6:5cc7136648d1	1503	config \|= _BV( CRCO );
akashvibhute	6:5cc7136648d1	1504	}
akashvibhute	6:5cc7136648d1	1505	write_register( NRF_CONFIG, config ) ;
akashvibhute	0:bb74812ac6bb	1506	}
akashvibhute	0:bb74812ac6bb	1507
akashvibhute	0:bb74812ac6bb	1508	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1509
akashvibhute	0:bb74812ac6bb	1510	rf24_crclength_e RF24::getCRCLength(void)
akashvibhute	0:bb74812ac6bb	1511	{
akashvibhute	6:5cc7136648d1	1512	rf24_crclength_e result = RF24_CRC_DISABLED;
akashvibhute	6:5cc7136648d1	1513
akashvibhute	6:5cc7136648d1	1514	uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) \| _BV(EN_CRC)) ;
akashvibhute	6:5cc7136648d1	1515	uint8_t AA = read_register(EN_AA);
akashvibhute	6:5cc7136648d1	1516
akashvibhute	6:5cc7136648d1	1517	if ( config & _BV(EN_CRC ) \|\| AA)
akashvibhute	6:5cc7136648d1	1518	{
akashvibhute	6:5cc7136648d1	1519	if ( config & _BV(CRCO) )
akashvibhute	6:5cc7136648d1	1520	result = RF24_CRC_16;
akashvibhute	6:5cc7136648d1	1521	else
akashvibhute	6:5cc7136648d1	1522	result = RF24_CRC_8;
akashvibhute	6:5cc7136648d1	1523	}
akashvibhute	0:bb74812ac6bb	1524
akashvibhute	6:5cc7136648d1	1525	return result;
akashvibhute	0:bb74812ac6bb	1526	}
akashvibhute	0:bb74812ac6bb	1527
akashvibhute	0:bb74812ac6bb	1528	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1529
akashvibhute	0:bb74812ac6bb	1530	void RF24::disableCRC( void )
akashvibhute	0:bb74812ac6bb	1531	{
akashvibhute	6:5cc7136648d1	1532	uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
akashvibhute	6:5cc7136648d1	1533	write_register( NRF_CONFIG, disable ) ;
akashvibhute	0:bb74812ac6bb	1534	}
akashvibhute	0:bb74812ac6bb	1535
akashvibhute	0:bb74812ac6bb	1536	/****************************************************************************/
akashvibhute	0:bb74812ac6bb	1537	void RF24::setRetries(uint8_t delay, uint8_t count)
akashvibhute	0:bb74812ac6bb	1538	{
akashvibhute	6:5cc7136648d1	1539	write_register(SETUP_RETR,(delay&0xf)<<ARD \| (count&0xf)<<ARC);
akashvibhute	0:bb74812ac6bb	1540	}
akashvibhute	6:5cc7136648d1	1541

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Type:	Library
Created:	20 May 2021
Imports:	5
Forks:	0
Commits:	11
Dependents:	2
Dependencies:	0
Followers:	22

RF24.cpp@6:5cc7136648d1, 2016-04-21 (annotated)

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