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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c@168:1dc8c8bdd03d, 2017-06-29 (annotated)

Committer:
krebyy
Date:
Thu Jun 29 20:34:04 2017 +0000
Revision:
168:1dc8c8bdd03d
Parent:
167:e84263d55307 
First commit - mbed for TON Board V1.2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_hal_can.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Controller Area Network (CAN) peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable the CAN controller interface clock using
AnnaBridge 167:e84263d55307 20 __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
AnnaBridge 167:e84263d55307 21 and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
<> 144:ef7eb2e8f9f7 22 -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) CAN pins configuration
<> 144:ef7eb2e8f9f7 25 (++) Enable the clock for the CAN GPIOs using the following function:
<> 144:ef7eb2e8f9f7 26 __GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 27 (++) Connect and configure the involved CAN pins to AF9 using the
<> 144:ef7eb2e8f9f7 28 following function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (#) Initialize and configure the CAN using CAN_Init() function.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
AnnaBridge 167:e84263d55307 33
AnnaBridge 167:e84263d55307 34 (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (#) Receive a CAN frame using HAL_CAN_Receive() function.
<> 144:ef7eb2e8f9f7 37
AnnaBridge 167:e84263d55307 38 (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
AnnaBridge 167:e84263d55307 39
<> 144:ef7eb2e8f9f7 40 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 41 =================================
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 (+) Start the CAN peripheral transmission and wait the end of this operation
<> 144:ef7eb2e8f9f7 44 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 45 according to his end application
<> 144:ef7eb2e8f9f7 46 (+) Start the CAN peripheral reception and wait the end of this operation
<> 144:ef7eb2e8f9f7 47 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 48 according to his end application
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 51 ===================================
<> 144:ef7eb2e8f9f7 52 [..]
<> 144:ef7eb2e8f9f7 53 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
<> 144:ef7eb2e8f9f7 54 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
<> 144:ef7eb2e8f9f7 55 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
<> 144:ef7eb2e8f9f7 56 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 57 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
<> 144:ef7eb2e8f9f7 58 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 59 add his own code by customization of function pointer HAL_CAN_ErrorCallback
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 *** CAN HAL driver macros list ***
<> 144:ef7eb2e8f9f7 62 =============================================
<> 144:ef7eb2e8f9f7 63 [..]
<> 144:ef7eb2e8f9f7 64 Below the list of most used macros in CAN HAL driver.
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 67 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 68 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
<> 144:ef7eb2e8f9f7 69 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
<> 144:ef7eb2e8f9f7 70 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 [..]
<> 144:ef7eb2e8f9f7 73 (@) You can refer to the CAN HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 @endverbatim
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 ******************************************************************************
<> 144:ef7eb2e8f9f7 78 * @attention
<> 144:ef7eb2e8f9f7 79 *
AnnaBridge 167:e84263d55307 80 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 83 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 84 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 85 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 86 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 87 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 88 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 89 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 90 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 91 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 92 *
<> 144:ef7eb2e8f9f7 93 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 94 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 95 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 96 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 97 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 98 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 99 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 100 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 101 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 102 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 ******************************************************************************
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 108 #include "stm32f4xx_hal.h"
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @defgroup CAN CAN
<> 144:ef7eb2e8f9f7 115 * @brief CAN driver modules
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 #ifdef HAL_CAN_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
<> 144:ef7eb2e8f9f7 122 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
<> 144:ef7eb2e8f9f7 123 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
AnnaBridge 167:e84263d55307 124 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
AnnaBridge 167:e84263d55307 125 defined(STM32F423xx)
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /** @addtogroup CAN_Private_Constants
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 #define CAN_TIMEOUT_VALUE 10U
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @addtogroup CAN_Private_Functions
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 143 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /** @defgroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 154 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 155 *
<> 144:ef7eb2e8f9f7 156 @verbatim
<> 144:ef7eb2e8f9f7 157 ==============================================================================
<> 144:ef7eb2e8f9f7 158 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 159 ==============================================================================
<> 144:ef7eb2e8f9f7 160 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 161 (+) Initialize and configure the CAN.
<> 144:ef7eb2e8f9f7 162 (+) De-initialize the CAN.
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 @endverbatim
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Initializes the CAN peripheral according to the specified
<> 144:ef7eb2e8f9f7 170 * parameters in the CAN_InitStruct.
<> 144:ef7eb2e8f9f7 171 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 172 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 173 * @retval HAL status
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 176 {
AnnaBridge 167:e84263d55307 177 uint32_t InitStatus = CAN_INITSTATUS_FAILED;
<> 144:ef7eb2e8f9f7 178 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 181 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Check the parameters */
<> 144:ef7eb2e8f9f7 187 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
<> 144:ef7eb2e8f9f7 191 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
<> 144:ef7eb2e8f9f7 192 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
<> 144:ef7eb2e8f9f7 193 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_CAN_MODE(hcan->Init.Mode));
<> 144:ef7eb2e8f9f7 195 assert_param(IS_CAN_SJW(hcan->Init.SJW));
<> 144:ef7eb2e8f9f7 196 assert_param(IS_CAN_BS1(hcan->Init.BS1));
<> 144:ef7eb2e8f9f7 197 assert_param(IS_CAN_BS2(hcan->Init.BS2));
<> 144:ef7eb2e8f9f7 198 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 if(hcan->State == HAL_CAN_STATE_RESET)
AnnaBridge 167:e84263d55307 202 {
<> 144:ef7eb2e8f9f7 203 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 204 hcan->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 205 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 206 HAL_CAN_MspInit(hcan);
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Initialize the CAN state*/
<> 144:ef7eb2e8f9f7 210 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Exit from sleep mode */
<> 144:ef7eb2e8f9f7 213 hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Request initialisation */
<> 144:ef7eb2e8f9f7 216 hcan->Instance->MCR |= CAN_MCR_INRQ ;
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Get tick */
<> 144:ef7eb2e8f9f7 219 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 222 while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 227 /* Process unlocked */
<> 144:ef7eb2e8f9f7 228 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 229 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Check acknowledge */
AnnaBridge 167:e84263d55307 234 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Set the time triggered communication mode */
<> 144:ef7eb2e8f9f7 237 if (hcan->Init.TTCM == ENABLE)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 hcan->Instance->MCR |= CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 else
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Set the automatic bus-off management */
<> 144:ef7eb2e8f9f7 247 if (hcan->Init.ABOM == ENABLE)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 hcan->Instance->MCR |= CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 else
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Set the automatic wake-up mode */
<> 144:ef7eb2e8f9f7 257 if (hcan->Init.AWUM == ENABLE)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 hcan->Instance->MCR |= CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 else
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Set the no automatic retransmission */
<> 144:ef7eb2e8f9f7 267 if (hcan->Init.NART == ENABLE)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 hcan->Instance->MCR |= CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271 else
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Set the receive FIFO locked mode */
<> 144:ef7eb2e8f9f7 277 if (hcan->Init.RFLM == ENABLE)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 hcan->Instance->MCR |= CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 else
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Set the transmit FIFO priority */
<> 144:ef7eb2e8f9f7 287 if (hcan->Init.TXFP == ENABLE)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 hcan->Instance->MCR |= CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 else
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Set the bit timing register */
<> 144:ef7eb2e8f9f7 297 hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
<> 144:ef7eb2e8f9f7 298 ((uint32_t)hcan->Init.SJW) | \
<> 144:ef7eb2e8f9f7 299 ((uint32_t)hcan->Init.BS1) | \
<> 144:ef7eb2e8f9f7 300 ((uint32_t)hcan->Init.BS2) | \
<> 144:ef7eb2e8f9f7 301 ((uint32_t)hcan->Init.Prescaler - 1U);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Request leave initialisation */
<> 144:ef7eb2e8f9f7 304 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Get tick */
<> 144:ef7eb2e8f9f7 307 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 310 while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 315 /* Process unlocked */
<> 144:ef7eb2e8f9f7 316 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 317 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Check acknowledged */
AnnaBridge 167:e84263d55307 322 if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 InitStatus = CAN_INITSTATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 if(InitStatus == CAN_INITSTATUS_SUCCESS)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 331 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 334 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Return function status */
<> 144:ef7eb2e8f9f7 337 return HAL_OK;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 else
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 342 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Return function status */
<> 144:ef7eb2e8f9f7 345 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @brief Configures the CAN reception filter according to the specified
<> 144:ef7eb2e8f9f7 351 * parameters in the CAN_FilterInitStruct.
<> 144:ef7eb2e8f9f7 352 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 353 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 354 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
<> 144:ef7eb2e8f9f7 355 * contains the filter configuration information.
<> 144:ef7eb2e8f9f7 356 * @retval None
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 uint32_t filternbrbitpos = 0U;
AnnaBridge 167:e84263d55307 361 CAN_TypeDef *can_ip;
<> 144:ef7eb2e8f9f7 362
AnnaBridge 167:e84263d55307 363 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 364 UNUSED(hcan);
AnnaBridge 167:e84263d55307 365
<> 144:ef7eb2e8f9f7 366 /* Check the parameters */
<> 144:ef7eb2e8f9f7 367 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
<> 144:ef7eb2e8f9f7 368 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
<> 144:ef7eb2e8f9f7 369 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
<> 144:ef7eb2e8f9f7 370 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
<> 144:ef7eb2e8f9f7 371 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
<> 144:ef7eb2e8f9f7 372 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
<> 144:ef7eb2e8f9f7 373
AnnaBridge 167:e84263d55307 374 filternbrbitpos = 1U << sFilterConfig->FilterNumber;
AnnaBridge 167:e84263d55307 375 #if defined (CAN3)
AnnaBridge 167:e84263d55307 376 /* Check the CAN instance */
AnnaBridge 167:e84263d55307 377 if(hcan->Instance == CAN3)
AnnaBridge 167:e84263d55307 378 {
AnnaBridge 167:e84263d55307 379 can_ip = CAN3;
AnnaBridge 167:e84263d55307 380 }
AnnaBridge 167:e84263d55307 381 else
AnnaBridge 167:e84263d55307 382 {
AnnaBridge 167:e84263d55307 383 can_ip = CAN1;
AnnaBridge 167:e84263d55307 384 }
AnnaBridge 167:e84263d55307 385 #else
AnnaBridge 167:e84263d55307 386 can_ip = CAN1;
AnnaBridge 167:e84263d55307 387 #endif
AnnaBridge 167:e84263d55307 388
<> 144:ef7eb2e8f9f7 389 /* Initialisation mode for the filter */
AnnaBridge 167:e84263d55307 390 can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
AnnaBridge 167:e84263d55307 391
AnnaBridge 167:e84263d55307 392 #if defined (CAN2)
<> 144:ef7eb2e8f9f7 393 /* Select the start slave bank */
AnnaBridge 167:e84263d55307 394 can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
AnnaBridge 167:e84263d55307 395 can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
AnnaBridge 167:e84263d55307 396 #endif
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Filter Deactivation */
AnnaBridge 167:e84263d55307 399 can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* Filter Scale */
<> 144:ef7eb2e8f9f7 402 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 /* 16-bit scale for the filter */
AnnaBridge 167:e84263d55307 405 can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* First 16-bit identifier and First 16-bit mask */
<> 144:ef7eb2e8f9f7 408 /* Or First 16-bit identifier and Second 16-bit identifier */
AnnaBridge 167:e84263d55307 409 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 410 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
<> 144:ef7eb2e8f9f7 411 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Second 16-bit identifier and Second 16-bit mask */
<> 144:ef7eb2e8f9f7 414 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
AnnaBridge 167:e84263d55307 415 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 416 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 417 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* 32-bit scale for the filter */
AnnaBridge 167:e84263d55307 423 can_ip->FS1R |= filternbrbitpos;
AnnaBridge 167:e84263d55307 424
<> 144:ef7eb2e8f9f7 425 /* 32-bit identifier or First 32-bit identifier */
AnnaBridge 167:e84263d55307 426 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 427 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 428 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 429 /* 32-bit mask or Second 32-bit identifier */
AnnaBridge 167:e84263d55307 430 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 431 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 432 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Filter Mode */
<> 144:ef7eb2e8f9f7 436 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /*Id/Mask mode for the filter*/
AnnaBridge 167:e84263d55307 439 can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 /*Identifier list mode for the filter*/
AnnaBridge 167:e84263d55307 444 can_ip->FM1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Filter FIFO assignment */
<> 144:ef7eb2e8f9f7 448 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* FIFO 0 assignation for the filter */
AnnaBridge 167:e84263d55307 451 can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 /* FIFO 1 assignation for the filter */
AnnaBridge 167:e84263d55307 457 can_ip->FFA1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Filter activation */
<> 144:ef7eb2e8f9f7 461 if (sFilterConfig->FilterActivation == ENABLE)
<> 144:ef7eb2e8f9f7 462 {
AnnaBridge 167:e84263d55307 463 can_ip->FA1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Leave the initialisation mode for the filter */
AnnaBridge 167:e84263d55307 467 can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Return function status */
<> 144:ef7eb2e8f9f7 470 return HAL_OK;
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /**
<> 144:ef7eb2e8f9f7 474 * @brief Deinitializes the CANx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 475 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 476 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 477 * @retval HAL status
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 482 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Check the parameters */
<> 144:ef7eb2e8f9f7 488 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* Change CAN state */
<> 144:ef7eb2e8f9f7 491 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 494 HAL_CAN_MspDeInit(hcan);
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Change CAN state */
<> 144:ef7eb2e8f9f7 497 hcan->State = HAL_CAN_STATE_RESET;
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* Release Lock */
<> 144:ef7eb2e8f9f7 500 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Return function status */
<> 144:ef7eb2e8f9f7 503 return HAL_OK;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /**
<> 144:ef7eb2e8f9f7 507 * @brief Initializes the CAN MSP.
<> 144:ef7eb2e8f9f7 508 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 509 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 510 * @retval None
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 515 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 516 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 517 the HAL_CAN_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /**
<> 144:ef7eb2e8f9f7 522 * @brief DeInitializes the CAN MSP.
<> 144:ef7eb2e8f9f7 523 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 524 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 525 * @retval None
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 530 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 531 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 532 the HAL_CAN_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @}
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /** @defgroup CAN_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 541 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 542 *
<> 144:ef7eb2e8f9f7 543 @verbatim
<> 144:ef7eb2e8f9f7 544 ==============================================================================
<> 144:ef7eb2e8f9f7 545 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 546 ==============================================================================
<> 144:ef7eb2e8f9f7 547 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 548 (+) Transmit a CAN frame message.
<> 144:ef7eb2e8f9f7 549 (+) Receive a CAN frame message.
<> 144:ef7eb2e8f9f7 550 (+) Enter CAN peripheral in sleep mode.
<> 144:ef7eb2e8f9f7 551 (+) Wake up the CAN peripheral from sleep mode.
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 @endverbatim
<> 144:ef7eb2e8f9f7 554 * @{
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 559 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 560 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 561 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 562 * @retval HAL status
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 565 {
AnnaBridge 167:e84263d55307 566 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 567 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Check the parameters */
<> 144:ef7eb2e8f9f7 570 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 571 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 572 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 575 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 576 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* Process locked */
<> 144:ef7eb2e8f9f7 579 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 580
AnnaBridge 167:e84263d55307 581 /* Change CAN state */
AnnaBridge 167:e84263d55307 582 switch(hcan->State)
<> 144:ef7eb2e8f9f7 583 {
AnnaBridge 167:e84263d55307 584 case(HAL_CAN_STATE_BUSY_RX0):
AnnaBridge 167:e84263d55307 585 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
AnnaBridge 167:e84263d55307 586 break;
AnnaBridge 167:e84263d55307 587 case(HAL_CAN_STATE_BUSY_RX1):
AnnaBridge 167:e84263d55307 588 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
AnnaBridge 167:e84263d55307 589 break;
AnnaBridge 167:e84263d55307 590 case(HAL_CAN_STATE_BUSY_RX0_RX1):
AnnaBridge 167:e84263d55307 591 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
AnnaBridge 167:e84263d55307 592 break;
AnnaBridge 167:e84263d55307 593 default: /* HAL_CAN_STATE_READY */
AnnaBridge 167:e84263d55307 594 hcan->State = HAL_CAN_STATE_BUSY_TX;
AnnaBridge 167:e84263d55307 595 break;
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 599 if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 600 {
AnnaBridge 167:e84263d55307 601 transmitmailbox = CAN_TXMAILBOX_0;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603 else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 604 {
AnnaBridge 167:e84263d55307 605 transmitmailbox = CAN_TXMAILBOX_1;
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607 else
<> 144:ef7eb2e8f9f7 608 {
AnnaBridge 167:e84263d55307 609 transmitmailbox = CAN_TXMAILBOX_2;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Set up the Id */
<> 144:ef7eb2e8f9f7 613 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 614 if (hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 617 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
<> 144:ef7eb2e8f9f7 618 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620 else
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 623 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
<> 144:ef7eb2e8f9f7 624 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 625 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Set up the DLC */
AnnaBridge 167:e84263d55307 629 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
<> 144:ef7eb2e8f9f7 630 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 631 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Set up the data field */
<> 144:ef7eb2e8f9f7 634 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
<> 144:ef7eb2e8f9f7 635 ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
<> 144:ef7eb2e8f9f7 636 ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
<> 144:ef7eb2e8f9f7 637 ((uint32_t)hcan->pTxMsg->Data[0U]));
<> 144:ef7eb2e8f9f7 638 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
<> 144:ef7eb2e8f9f7 639 ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
<> 144:ef7eb2e8f9f7 640 ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
<> 144:ef7eb2e8f9f7 641 ((uint32_t)hcan->pTxMsg->Data[4U]));
<> 144:ef7eb2e8f9f7 642 /* Request transmission */
<> 144:ef7eb2e8f9f7 643 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 644
AnnaBridge 167:e84263d55307 645 /* Get tick */
<> 144:ef7eb2e8f9f7 646 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 649 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 652 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 hcan->State = HAL_CAN_STATE_TIMEOUT;
AnnaBridge 167:e84263d55307 657
AnnaBridge 167:e84263d55307 658 __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
AnnaBridge 167:e84263d55307 659
<> 144:ef7eb2e8f9f7 660 /* Process unlocked */
<> 144:ef7eb2e8f9f7 661 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 662 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665 }
AnnaBridge 167:e84263d55307 666
AnnaBridge 167:e84263d55307 667 /* Change CAN state */
AnnaBridge 167:e84263d55307 668 switch(hcan->State)
<> 144:ef7eb2e8f9f7 669 {
AnnaBridge 167:e84263d55307 670 case(HAL_CAN_STATE_BUSY_TX_RX0):
AnnaBridge 167:e84263d55307 671 hcan->State = HAL_CAN_STATE_BUSY_RX0;
AnnaBridge 167:e84263d55307 672 break;
AnnaBridge 167:e84263d55307 673 case(HAL_CAN_STATE_BUSY_TX_RX1):
AnnaBridge 167:e84263d55307 674 hcan->State = HAL_CAN_STATE_BUSY_RX1;
AnnaBridge 167:e84263d55307 675 break;
AnnaBridge 167:e84263d55307 676 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
AnnaBridge 167:e84263d55307 677 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
AnnaBridge 167:e84263d55307 678 break;
AnnaBridge 167:e84263d55307 679 default: /* HAL_CAN_STATE_BUSY_TX */
AnnaBridge 167:e84263d55307 680 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 681 break;
<> 144:ef7eb2e8f9f7 682 }
AnnaBridge 167:e84263d55307 683
<> 144:ef7eb2e8f9f7 684 /* Process unlocked */
<> 144:ef7eb2e8f9f7 685 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Return function status */
<> 144:ef7eb2e8f9f7 688 return HAL_OK;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 else
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 /* Change CAN state */
<> 144:ef7eb2e8f9f7 693 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Return function status */
<> 144:ef7eb2e8f9f7 696 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 702 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 703 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 704 * @retval HAL status
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 707 {
AnnaBridge 167:e84263d55307 708 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* Check the parameters */
<> 144:ef7eb2e8f9f7 711 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 712 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 713 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 716 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 717 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 /* Process Locked */
<> 144:ef7eb2e8f9f7 720 __HAL_LOCK(hcan);
AnnaBridge 167:e84263d55307 721
<> 144:ef7eb2e8f9f7 722 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 723 if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 724 {
AnnaBridge 167:e84263d55307 725 transmitmailbox = CAN_TXMAILBOX_0;
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727 else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 728 {
AnnaBridge 167:e84263d55307 729 transmitmailbox = CAN_TXMAILBOX_1;
<> 144:ef7eb2e8f9f7 730 }
<> 144:ef7eb2e8f9f7 731 else
<> 144:ef7eb2e8f9f7 732 {
AnnaBridge 167:e84263d55307 733 transmitmailbox = CAN_TXMAILBOX_2;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Set up the Id */
<> 144:ef7eb2e8f9f7 737 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 738 if(hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 741 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
<> 144:ef7eb2e8f9f7 742 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744 else
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 747 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
<> 144:ef7eb2e8f9f7 748 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 749 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 750 }
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Set up the DLC */
AnnaBridge 167:e84263d55307 753 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
<> 144:ef7eb2e8f9f7 754 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 755 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Set up the data field */
AnnaBridge 167:e84263d55307 758 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
<> 144:ef7eb2e8f9f7 759 ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
<> 144:ef7eb2e8f9f7 760 ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
<> 144:ef7eb2e8f9f7 761 ((uint32_t)hcan->pTxMsg->Data[0U]));
AnnaBridge 167:e84263d55307 762 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
<> 144:ef7eb2e8f9f7 763 ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
<> 144:ef7eb2e8f9f7 764 ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
<> 144:ef7eb2e8f9f7 765 ((uint32_t)hcan->pTxMsg->Data[4U]));
AnnaBridge 167:e84263d55307 766
AnnaBridge 167:e84263d55307 767 /* Change CAN state */
AnnaBridge 167:e84263d55307 768 switch(hcan->State)
<> 144:ef7eb2e8f9f7 769 {
AnnaBridge 167:e84263d55307 770 case(HAL_CAN_STATE_BUSY_RX0):
AnnaBridge 167:e84263d55307 771 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
AnnaBridge 167:e84263d55307 772 break;
AnnaBridge 167:e84263d55307 773 case(HAL_CAN_STATE_BUSY_RX1):
AnnaBridge 167:e84263d55307 774 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
AnnaBridge 167:e84263d55307 775 break;
AnnaBridge 167:e84263d55307 776 case(HAL_CAN_STATE_BUSY_RX0_RX1):
AnnaBridge 167:e84263d55307 777 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
AnnaBridge 167:e84263d55307 778 break;
AnnaBridge 167:e84263d55307 779 default: /* HAL_CAN_STATE_READY */
AnnaBridge 167:e84263d55307 780 hcan->State = HAL_CAN_STATE_BUSY_TX;
AnnaBridge 167:e84263d55307 781 break;
<> 144:ef7eb2e8f9f7 782 }
AnnaBridge 167:e84263d55307 783
<> 144:ef7eb2e8f9f7 784 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 785 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
AnnaBridge 167:e84263d55307 786
<> 144:ef7eb2e8f9f7 787 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 788 __HAL_UNLOCK(hcan);
AnnaBridge 167:e84263d55307 789
<> 144:ef7eb2e8f9f7 790 /* Request transmission */
<> 144:ef7eb2e8f9f7 791 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
AnnaBridge 167:e84263d55307 792
AnnaBridge 167:e84263d55307 793 /* Enable Error warning, Error passive, Bus-off,
AnnaBridge 167:e84263d55307 794 Last error and Error Interrupts */
AnnaBridge 167:e84263d55307 795 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
AnnaBridge 167:e84263d55307 796 CAN_IT_EPV |
AnnaBridge 167:e84263d55307 797 CAN_IT_BOF |
AnnaBridge 167:e84263d55307 798 CAN_IT_LEC |
AnnaBridge 167:e84263d55307 799 CAN_IT_ERR |
AnnaBridge 167:e84263d55307 800 CAN_IT_TME);
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802 else
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 /* Change CAN state */
<> 144:ef7eb2e8f9f7 805 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Return function status */
<> 144:ef7eb2e8f9f7 808 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 return HAL_OK;
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /**
<> 144:ef7eb2e8f9f7 815 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 816 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 817 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 818 * @param FIFONumber: FIFO Number value
<> 144:ef7eb2e8f9f7 819 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 820 * @retval HAL status
<> 144:ef7eb2e8f9f7 821 */
<> 144:ef7eb2e8f9f7 822 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 825 CanRxMsgTypeDef* pRxMsg = NULL;
AnnaBridge 167:e84263d55307 826
<> 144:ef7eb2e8f9f7 827 /* Check the parameters */
<> 144:ef7eb2e8f9f7 828 assert_param(IS_CAN_FIFO(FIFONumber));
AnnaBridge 167:e84263d55307 829
AnnaBridge 167:e84263d55307 830 /* Check if CAN state is not busy for RX FIFO0 */
AnnaBridge 167:e84263d55307 831 if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
AnnaBridge 167:e84263d55307 832 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
AnnaBridge 167:e84263d55307 833 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
AnnaBridge 167:e84263d55307 834 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
AnnaBridge 167:e84263d55307 835 {
AnnaBridge 167:e84263d55307 836 return HAL_BUSY;
AnnaBridge 167:e84263d55307 837 }
AnnaBridge 167:e84263d55307 838
AnnaBridge 167:e84263d55307 839 /* Check if CAN state is not busy for RX FIFO1 */
AnnaBridge 167:e84263d55307 840 if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
AnnaBridge 167:e84263d55307 841 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
AnnaBridge 167:e84263d55307 842 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
AnnaBridge 167:e84263d55307 843 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
AnnaBridge 167:e84263d55307 844 {
AnnaBridge 167:e84263d55307 845 return HAL_BUSY;
AnnaBridge 167:e84263d55307 846 }
AnnaBridge 167:e84263d55307 847
<> 144:ef7eb2e8f9f7 848 /* Process locked */
<> 144:ef7eb2e8f9f7 849 __HAL_LOCK(hcan);
AnnaBridge 167:e84263d55307 850
AnnaBridge 167:e84263d55307 851 /* Change CAN state */
AnnaBridge 167:e84263d55307 852 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 853 {
AnnaBridge 167:e84263d55307 854 switch(hcan->State)
AnnaBridge 167:e84263d55307 855 {
AnnaBridge 167:e84263d55307 856 case(HAL_CAN_STATE_BUSY_TX):
AnnaBridge 167:e84263d55307 857 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
AnnaBridge 167:e84263d55307 858 break;
AnnaBridge 167:e84263d55307 859 case(HAL_CAN_STATE_BUSY_RX1):
AnnaBridge 167:e84263d55307 860 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
AnnaBridge 167:e84263d55307 861 break;
AnnaBridge 167:e84263d55307 862 case(HAL_CAN_STATE_BUSY_TX_RX1):
AnnaBridge 167:e84263d55307 863 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
AnnaBridge 167:e84263d55307 864 break;
AnnaBridge 167:e84263d55307 865 default: /* HAL_CAN_STATE_READY */
AnnaBridge 167:e84263d55307 866 hcan->State = HAL_CAN_STATE_BUSY_RX0;
AnnaBridge 167:e84263d55307 867 break;
AnnaBridge 167:e84263d55307 868 }
<> 144:ef7eb2e8f9f7 869 }
AnnaBridge 167:e84263d55307 870 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 871 {
AnnaBridge 167:e84263d55307 872 switch(hcan->State)
AnnaBridge 167:e84263d55307 873 {
AnnaBridge 167:e84263d55307 874 case(HAL_CAN_STATE_BUSY_TX):
AnnaBridge 167:e84263d55307 875 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
AnnaBridge 167:e84263d55307 876 break;
AnnaBridge 167:e84263d55307 877 case(HAL_CAN_STATE_BUSY_RX0):
AnnaBridge 167:e84263d55307 878 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
AnnaBridge 167:e84263d55307 879 break;
AnnaBridge 167:e84263d55307 880 case(HAL_CAN_STATE_BUSY_TX_RX0):
AnnaBridge 167:e84263d55307 881 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
AnnaBridge 167:e84263d55307 882 break;
AnnaBridge 167:e84263d55307 883 default: /* HAL_CAN_STATE_READY */
AnnaBridge 167:e84263d55307 884 hcan->State = HAL_CAN_STATE_BUSY_RX1;
AnnaBridge 167:e84263d55307 885 break;
AnnaBridge 167:e84263d55307 886 }
<> 144:ef7eb2e8f9f7 887 }
AnnaBridge 167:e84263d55307 888
<> 144:ef7eb2e8f9f7 889 /* Get tick */
<> 144:ef7eb2e8f9f7 890 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Check pending message */
<> 144:ef7eb2e8f9f7 893 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 896 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 899 {
<> 144:ef7eb2e8f9f7 900 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 901 /* Process unlocked */
<> 144:ef7eb2e8f9f7 902 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 903 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906 }
AnnaBridge 167:e84263d55307 907
AnnaBridge 167:e84263d55307 908 /* Set RxMsg pointer */
AnnaBridge 167:e84263d55307 909 if(FIFONumber == CAN_FIFO0)
AnnaBridge 167:e84263d55307 910 {
AnnaBridge 167:e84263d55307 911 pRxMsg = hcan->pRxMsg;
AnnaBridge 167:e84263d55307 912 }
AnnaBridge 167:e84263d55307 913 else /* FIFONumber == CAN_FIFO1 */
AnnaBridge 167:e84263d55307 914 {
AnnaBridge 167:e84263d55307 915 pRxMsg = hcan->pRx1Msg;
AnnaBridge 167:e84263d55307 916 }
AnnaBridge 167:e84263d55307 917
<> 144:ef7eb2e8f9f7 918 /* Get the Id */
AnnaBridge 167:e84263d55307 919 pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
AnnaBridge 167:e84263d55307 920 if (pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 921 {
AnnaBridge 167:e84263d55307 922 pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924 else
<> 144:ef7eb2e8f9f7 925 {
AnnaBridge 167:e84263d55307 926 pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
AnnaBridge 167:e84263d55307 929 pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 930 /* Get the DLC */
AnnaBridge 167:e84263d55307 931 pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 932 /* Get the FMI */
AnnaBridge 167:e84263d55307 933 pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
AnnaBridge 167:e84263d55307 934 /* Get the FIFONumber */
AnnaBridge 167:e84263d55307 935 pRxMsg->FIFONumber = FIFONumber;
<> 144:ef7eb2e8f9f7 936 /* Get the data field */
AnnaBridge 167:e84263d55307 937 pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
AnnaBridge 167:e84263d55307 938 pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
AnnaBridge 167:e84263d55307 939 pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
AnnaBridge 167:e84263d55307 940 pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
AnnaBridge 167:e84263d55307 941 pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
AnnaBridge 167:e84263d55307 942 pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
AnnaBridge 167:e84263d55307 943 pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
AnnaBridge 167:e84263d55307 944 pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
AnnaBridge 167:e84263d55307 945
<> 144:ef7eb2e8f9f7 946 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 947 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 950 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 953 {
<> 144:ef7eb2e8f9f7 954 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 955 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 956 }
AnnaBridge 167:e84263d55307 957
AnnaBridge 167:e84263d55307 958 /* Change CAN state */
AnnaBridge 167:e84263d55307 959 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 960 {
AnnaBridge 167:e84263d55307 961 switch(hcan->State)
AnnaBridge 167:e84263d55307 962 {
AnnaBridge 167:e84263d55307 963 case(HAL_CAN_STATE_BUSY_TX_RX0):
AnnaBridge 167:e84263d55307 964 hcan->State = HAL_CAN_STATE_BUSY_TX;
AnnaBridge 167:e84263d55307 965 break;
AnnaBridge 167:e84263d55307 966 case(HAL_CAN_STATE_BUSY_RX0_RX1):
AnnaBridge 167:e84263d55307 967 hcan->State = HAL_CAN_STATE_BUSY_RX1;
AnnaBridge 167:e84263d55307 968 break;
AnnaBridge 167:e84263d55307 969 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
AnnaBridge 167:e84263d55307 970 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
AnnaBridge 167:e84263d55307 971 break;
AnnaBridge 167:e84263d55307 972 default: /* HAL_CAN_STATE_BUSY_RX0 */
AnnaBridge 167:e84263d55307 973 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 974 break;
AnnaBridge 167:e84263d55307 975 }
<> 144:ef7eb2e8f9f7 976 }
AnnaBridge 167:e84263d55307 977 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 978 {
AnnaBridge 167:e84263d55307 979 switch(hcan->State)
AnnaBridge 167:e84263d55307 980 {
AnnaBridge 167:e84263d55307 981 case(HAL_CAN_STATE_BUSY_TX_RX1):
AnnaBridge 167:e84263d55307 982 hcan->State = HAL_CAN_STATE_BUSY_TX;
AnnaBridge 167:e84263d55307 983 break;
AnnaBridge 167:e84263d55307 984 case(HAL_CAN_STATE_BUSY_RX0_RX1):
AnnaBridge 167:e84263d55307 985 hcan->State = HAL_CAN_STATE_BUSY_RX0;
AnnaBridge 167:e84263d55307 986 break;
AnnaBridge 167:e84263d55307 987 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
AnnaBridge 167:e84263d55307 988 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
AnnaBridge 167:e84263d55307 989 break;
AnnaBridge 167:e84263d55307 990 default: /* HAL_CAN_STATE_BUSY_RX1 */
AnnaBridge 167:e84263d55307 991 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 992 break;
AnnaBridge 167:e84263d55307 993 }
<> 144:ef7eb2e8f9f7 994 }
AnnaBridge 167:e84263d55307 995
AnnaBridge 167:e84263d55307 996 /* Process unlocked */
AnnaBridge 167:e84263d55307 997 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /* Return function status */
<> 144:ef7eb2e8f9f7 1000 return HAL_OK;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 1005 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1006 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1007 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 1008 * @retval HAL status
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1013 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 1014
AnnaBridge 167:e84263d55307 1015 /* Check if CAN state is not busy for RX FIFO0 */
AnnaBridge 167:e84263d55307 1016 if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
AnnaBridge 167:e84263d55307 1017 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
AnnaBridge 167:e84263d55307 1018 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
AnnaBridge 167:e84263d55307 1019 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
<> 144:ef7eb2e8f9f7 1020 {
AnnaBridge 167:e84263d55307 1021 return HAL_BUSY;
AnnaBridge 167:e84263d55307 1022 }
AnnaBridge 167:e84263d55307 1023
AnnaBridge 167:e84263d55307 1024 /* Check if CAN state is not busy for RX FIFO1 */
AnnaBridge 167:e84263d55307 1025 if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
AnnaBridge 167:e84263d55307 1026 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
AnnaBridge 167:e84263d55307 1027 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
AnnaBridge 167:e84263d55307 1028 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
AnnaBridge 167:e84263d55307 1029 {
AnnaBridge 167:e84263d55307 1030 return HAL_BUSY;
AnnaBridge 167:e84263d55307 1031 }
AnnaBridge 167:e84263d55307 1032
AnnaBridge 167:e84263d55307 1033 /* Process locked */
AnnaBridge 167:e84263d55307 1034 __HAL_LOCK(hcan);
AnnaBridge 167:e84263d55307 1035
AnnaBridge 167:e84263d55307 1036 /* Change CAN state */
AnnaBridge 167:e84263d55307 1037 if(FIFONumber == CAN_FIFO0)
AnnaBridge 167:e84263d55307 1038 {
AnnaBridge 167:e84263d55307 1039 switch(hcan->State)
<> 144:ef7eb2e8f9f7 1040 {
AnnaBridge 167:e84263d55307 1041 case(HAL_CAN_STATE_BUSY_TX):
AnnaBridge 167:e84263d55307 1042 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
AnnaBridge 167:e84263d55307 1043 break;
AnnaBridge 167:e84263d55307 1044 case(HAL_CAN_STATE_BUSY_RX1):
AnnaBridge 167:e84263d55307 1045 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
AnnaBridge 167:e84263d55307 1046 break;
AnnaBridge 167:e84263d55307 1047 case(HAL_CAN_STATE_BUSY_TX_RX1):
AnnaBridge 167:e84263d55307 1048 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
AnnaBridge 167:e84263d55307 1049 break;
AnnaBridge 167:e84263d55307 1050 default: /* HAL_CAN_STATE_READY */
AnnaBridge 167:e84263d55307 1051 hcan->State = HAL_CAN_STATE_BUSY_RX0;
AnnaBridge 167:e84263d55307 1052 break;
<> 144:ef7eb2e8f9f7 1053 }
AnnaBridge 167:e84263d55307 1054 }
AnnaBridge 167:e84263d55307 1055 else /* FIFONumber == CAN_FIFO1 */
AnnaBridge 167:e84263d55307 1056 {
AnnaBridge 167:e84263d55307 1057 switch(hcan->State)
AnnaBridge 167:e84263d55307 1058 {
AnnaBridge 167:e84263d55307 1059 case(HAL_CAN_STATE_BUSY_TX):
AnnaBridge 167:e84263d55307 1060 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
AnnaBridge 167:e84263d55307 1061 break;
AnnaBridge 167:e84263d55307 1062 case(HAL_CAN_STATE_BUSY_RX0):
AnnaBridge 167:e84263d55307 1063 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
AnnaBridge 167:e84263d55307 1064 break;
AnnaBridge 167:e84263d55307 1065 case(HAL_CAN_STATE_BUSY_TX_RX0):
AnnaBridge 167:e84263d55307 1066 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
AnnaBridge 167:e84263d55307 1067 break;
AnnaBridge 167:e84263d55307 1068 default: /* HAL_CAN_STATE_READY */
AnnaBridge 167:e84263d55307 1069 hcan->State = HAL_CAN_STATE_BUSY_RX1;
AnnaBridge 167:e84263d55307 1070 break;
AnnaBridge 167:e84263d55307 1071 }
AnnaBridge 167:e84263d55307 1072 }
AnnaBridge 167:e84263d55307 1073 /* Set CAN error code to none */
AnnaBridge 167:e84263d55307 1074 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1075
AnnaBridge 167:e84263d55307 1076 /* Enable interrupts: */
AnnaBridge 167:e84263d55307 1077 /* - Enable Error warning Interrupt */
AnnaBridge 167:e84263d55307 1078 /* - Enable Error passive Interrupt */
AnnaBridge 167:e84263d55307 1079 /* - Enable Bus-off Interrupt */
AnnaBridge 167:e84263d55307 1080 /* - Enable Last error code Interrupt */
AnnaBridge 167:e84263d55307 1081 /* - Enable Error Interrupt */
AnnaBridge 167:e84263d55307 1082 /* - Enable Transmit mailbox empty Interrupt */
AnnaBridge 167:e84263d55307 1083 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
AnnaBridge 167:e84263d55307 1084 CAN_IT_EPV |
AnnaBridge 167:e84263d55307 1085 CAN_IT_BOF |
AnnaBridge 167:e84263d55307 1086 CAN_IT_LEC |
AnnaBridge 167:e84263d55307 1087 CAN_IT_ERR |
AnnaBridge 167:e84263d55307 1088 CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1089
AnnaBridge 167:e84263d55307 1090 /* Process unlocked */
AnnaBridge 167:e84263d55307 1091 __HAL_UNLOCK(hcan);
AnnaBridge 167:e84263d55307 1092
AnnaBridge 167:e84263d55307 1093 if(FIFONumber == CAN_FIFO0)
AnnaBridge 167:e84263d55307 1094 {
AnnaBridge 167:e84263d55307 1095 /* Enable FIFO 0 overrun and message pending Interrupt */
AnnaBridge 167:e84263d55307 1096 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1097 }
<> 144:ef7eb2e8f9f7 1098 else
<> 144:ef7eb2e8f9f7 1099 {
AnnaBridge 167:e84263d55307 1100 /* Enable FIFO 1 overrun and message pending Interrupt */
AnnaBridge 167:e84263d55307 1101 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1102 }
AnnaBridge 167:e84263d55307 1103
<> 144:ef7eb2e8f9f7 1104 /* Return function status */
<> 144:ef7eb2e8f9f7 1105 return HAL_OK;
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /**
<> 144:ef7eb2e8f9f7 1109 * @brief Enters the Sleep (low power) mode.
<> 144:ef7eb2e8f9f7 1110 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1111 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1112 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1113 */
<> 144:ef7eb2e8f9f7 1114 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Process locked */
<> 144:ef7eb2e8f9f7 1119 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1122 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /* Request Sleep mode */
<> 144:ef7eb2e8f9f7 1125 hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
AnnaBridge 167:e84263d55307 1126
<> 144:ef7eb2e8f9f7 1127 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 1128 if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1131 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /* Return function status */
<> 144:ef7eb2e8f9f7 1134 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1135 }
AnnaBridge 167:e84263d55307 1136
AnnaBridge 167:e84263d55307 1137 /* Get tick */
<> 144:ef7eb2e8f9f7 1138 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 1141 while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1142 {
<> 144:ef7eb2e8f9f7 1143 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1146 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1147 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1148 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1149 }
<> 144:ef7eb2e8f9f7 1150 }
AnnaBridge 167:e84263d55307 1151
<> 144:ef7eb2e8f9f7 1152 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1153 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 1154
<> 144:ef7eb2e8f9f7 1155 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1156 __HAL_UNLOCK(hcan);
AnnaBridge 167:e84263d55307 1157
<> 144:ef7eb2e8f9f7 1158 /* Return function status */
<> 144:ef7eb2e8f9f7 1159 return HAL_OK;
<> 144:ef7eb2e8f9f7 1160 }
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /**
<> 144:ef7eb2e8f9f7 1163 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
<> 144:ef7eb2e8f9f7 1164 * is in the normal mode.
<> 144:ef7eb2e8f9f7 1165 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1166 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1167 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Process locked */
<> 144:ef7eb2e8f9f7 1174 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1177 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /* Wake up request */
<> 144:ef7eb2e8f9f7 1180 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Get tick */
<> 144:ef7eb2e8f9f7 1183 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 1186 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1187 {
<> 144:ef7eb2e8f9f7 1188 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1191 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1192 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1193 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196 if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1197 {
<> 144:ef7eb2e8f9f7 1198 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1199 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /* Return function status */
<> 144:ef7eb2e8f9f7 1202 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1203 }
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1206 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1209 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Return function status */
<> 144:ef7eb2e8f9f7 1212 return HAL_OK;
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /**
<> 144:ef7eb2e8f9f7 1216 * @brief Handles CAN interrupt request
<> 144:ef7eb2e8f9f7 1217 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1218 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1219 * @retval None
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1222 {
<> 144:ef7eb2e8f9f7 1223 uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
AnnaBridge 167:e84263d55307 1224 uint32_t errorcode = HAL_CAN_ERROR_NONE;
AnnaBridge 167:e84263d55307 1225
AnnaBridge 167:e84263d55307 1226 /* Check Overrun flag for FIFO0 */
AnnaBridge 167:e84263d55307 1227 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
AnnaBridge 167:e84263d55307 1228 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
AnnaBridge 167:e84263d55307 1229 if(tmp1 && tmp2)
AnnaBridge 167:e84263d55307 1230 {
AnnaBridge 167:e84263d55307 1231 /* Set CAN error code to FOV0 error */
AnnaBridge 167:e84263d55307 1232 errorcode |= HAL_CAN_ERROR_FOV0;
AnnaBridge 167:e84263d55307 1233
AnnaBridge 167:e84263d55307 1234 /* Clear FIFO0 Overrun Flag */
AnnaBridge 167:e84263d55307 1235 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
AnnaBridge 167:e84263d55307 1236 }
AnnaBridge 167:e84263d55307 1237 /* Check Overrun flag for FIFO1 */
AnnaBridge 167:e84263d55307 1238 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
AnnaBridge 167:e84263d55307 1239 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
AnnaBridge 167:e84263d55307 1240
AnnaBridge 167:e84263d55307 1241 if(tmp1 && tmp2)
AnnaBridge 167:e84263d55307 1242 {
AnnaBridge 167:e84263d55307 1243 /* Set CAN error code to FOV1 error */
AnnaBridge 167:e84263d55307 1244 errorcode |= HAL_CAN_ERROR_FOV1;
AnnaBridge 167:e84263d55307 1245
AnnaBridge 167:e84263d55307 1246 /* Clear FIFO1 Overrun Flag */
AnnaBridge 167:e84263d55307 1247 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
AnnaBridge 167:e84263d55307 1248 }
AnnaBridge 167:e84263d55307 1249
<> 144:ef7eb2e8f9f7 1250 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 1251 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
<> 144:ef7eb2e8f9f7 1252 {
<> 144:ef7eb2e8f9f7 1253 tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
<> 144:ef7eb2e8f9f7 1254 tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
<> 144:ef7eb2e8f9f7 1255 tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
<> 144:ef7eb2e8f9f7 1256 if(tmp1 || tmp2 || tmp3)
<> 144:ef7eb2e8f9f7 1257 {
AnnaBridge 167:e84263d55307 1258 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
AnnaBridge 167:e84263d55307 1259 tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
AnnaBridge 167:e84263d55307 1260 tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
AnnaBridge 167:e84263d55307 1261 /* Check Transmit success */
AnnaBridge 167:e84263d55307 1262 if(tmp1 || tmp2 || tmp3)
AnnaBridge 167:e84263d55307 1263 {
AnnaBridge 167:e84263d55307 1264 /* Call transmit function */
AnnaBridge 167:e84263d55307 1265 CAN_Transmit_IT(hcan);
AnnaBridge 167:e84263d55307 1266 }
AnnaBridge 167:e84263d55307 1267 else /* Transmit failure */
AnnaBridge 167:e84263d55307 1268 {
AnnaBridge 167:e84263d55307 1269 /* Set CAN error code to TXFAIL error */
AnnaBridge 167:e84263d55307 1270 errorcode |= HAL_CAN_ERROR_TXFAIL;
AnnaBridge 167:e84263d55307 1271 }
AnnaBridge 167:e84263d55307 1272
AnnaBridge 167:e84263d55307 1273 /* Clear transmission status flags (RQCPx and TXOKx) */
AnnaBridge 167:e84263d55307 1274 SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
AnnaBridge 167:e84263d55307 1275 CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
<> 144:ef7eb2e8f9f7 1276 }
<> 144:ef7eb2e8f9f7 1277 }
AnnaBridge 167:e84263d55307 1278
<> 144:ef7eb2e8f9f7 1279 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1280 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1281 /* Check End of reception flag for FIFO0 */
<> 144:ef7eb2e8f9f7 1282 if((tmp1 != 0U) && tmp2)
<> 144:ef7eb2e8f9f7 1283 {
<> 144:ef7eb2e8f9f7 1284 /* Call receive function */
<> 144:ef7eb2e8f9f7 1285 CAN_Receive_IT(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1286 }
AnnaBridge 167:e84263d55307 1287
<> 144:ef7eb2e8f9f7 1288 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1289 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1290 /* Check End of reception flag for FIFO1 */
<> 144:ef7eb2e8f9f7 1291 if((tmp1 != 0U) && tmp2)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 /* Call receive function */
<> 144:ef7eb2e8f9f7 1294 CAN_Receive_IT(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1295 }
AnnaBridge 167:e84263d55307 1296
AnnaBridge 167:e84263d55307 1297 /* Set error code in handle */
AnnaBridge 167:e84263d55307 1298 hcan->ErrorCode |= errorcode;
AnnaBridge 167:e84263d55307 1299
<> 144:ef7eb2e8f9f7 1300 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
<> 144:ef7eb2e8f9f7 1301 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1302 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1303 /* Check Error Warning Flag */
<> 144:ef7eb2e8f9f7 1304 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 /* Set CAN error code to EWG error */
<> 144:ef7eb2e8f9f7 1307 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
<> 144:ef7eb2e8f9f7 1308 }
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
<> 144:ef7eb2e8f9f7 1311 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1312 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1313 /* Check Error Passive Flag */
<> 144:ef7eb2e8f9f7 1314 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* Set CAN error code to EPV error */
<> 144:ef7eb2e8f9f7 1317 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
<> 144:ef7eb2e8f9f7 1321 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1322 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1323 /* Check Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1324 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1325 {
<> 144:ef7eb2e8f9f7 1326 /* Set CAN error code to BOF error */
<> 144:ef7eb2e8f9f7 1327 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1331 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1332 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1333 /* Check Last error code Flag */
<> 144:ef7eb2e8f9f7 1334 if((!tmp1) && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336 tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
<> 144:ef7eb2e8f9f7 1337 switch(tmp1)
<> 144:ef7eb2e8f9f7 1338 {
<> 144:ef7eb2e8f9f7 1339 case(CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1340 /* Set CAN error code to STF error */
<> 144:ef7eb2e8f9f7 1341 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
<> 144:ef7eb2e8f9f7 1342 break;
<> 144:ef7eb2e8f9f7 1343 case(CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1344 /* Set CAN error code to FOR error */
<> 144:ef7eb2e8f9f7 1345 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
<> 144:ef7eb2e8f9f7 1346 break;
<> 144:ef7eb2e8f9f7 1347 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1348 /* Set CAN error code to ACK error */
<> 144:ef7eb2e8f9f7 1349 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
<> 144:ef7eb2e8f9f7 1350 break;
<> 144:ef7eb2e8f9f7 1351 case(CAN_ESR_LEC_2):
<> 144:ef7eb2e8f9f7 1352 /* Set CAN error code to BR error */
<> 144:ef7eb2e8f9f7 1353 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
<> 144:ef7eb2e8f9f7 1354 break;
<> 144:ef7eb2e8f9f7 1355 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1356 /* Set CAN error code to BD error */
<> 144:ef7eb2e8f9f7 1357 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
<> 144:ef7eb2e8f9f7 1358 break;
<> 144:ef7eb2e8f9f7 1359 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1360 /* Set CAN error code to CRC error */
<> 144:ef7eb2e8f9f7 1361 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1362 break;
<> 144:ef7eb2e8f9f7 1363 default:
<> 144:ef7eb2e8f9f7 1364 break;
<> 144:ef7eb2e8f9f7 1365 }
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Clear Last error code Flag */
<> 144:ef7eb2e8f9f7 1368 hcan->Instance->ESR &= ~(CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1369 }
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1372 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1373 {
<> 144:ef7eb2e8f9f7 1374 /* Clear ERRI Flag */
<> 144:ef7eb2e8f9f7 1375 hcan->Instance->MSR = CAN_MSR_ERRI;
<> 144:ef7eb2e8f9f7 1376 /* Set the CAN state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1377 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 1378
AnnaBridge 167:e84263d55307 1379 /* Disable interrupts: */
AnnaBridge 167:e84263d55307 1380 /* - Disable Error warning Interrupt */
AnnaBridge 167:e84263d55307 1381 /* - Disable Error passive Interrupt */
AnnaBridge 167:e84263d55307 1382 /* - Disable Bus-off Interrupt */
AnnaBridge 167:e84263d55307 1383 /* - Disable Last error code Interrupt */
AnnaBridge 167:e84263d55307 1384 /* - Disable Error Interrupt */
AnnaBridge 167:e84263d55307 1385 /* - Disable FIFO 0 message pending Interrupt */
AnnaBridge 167:e84263d55307 1386 /* - Disable FIFO 0 Overrun Interrupt */
AnnaBridge 167:e84263d55307 1387 /* - Disable FIFO 1 message pending Interrupt */
AnnaBridge 167:e84263d55307 1388 /* - Disable FIFO 1 Overrun Interrupt */
AnnaBridge 167:e84263d55307 1389 /* - Disable Transmit mailbox empty Interrupt */
AnnaBridge 167:e84263d55307 1390 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
AnnaBridge 167:e84263d55307 1391 CAN_IT_EPV |
AnnaBridge 167:e84263d55307 1392 CAN_IT_BOF |
AnnaBridge 167:e84263d55307 1393 CAN_IT_LEC |
AnnaBridge 167:e84263d55307 1394 CAN_IT_ERR |
AnnaBridge 167:e84263d55307 1395 CAN_IT_FMP0|
AnnaBridge 167:e84263d55307 1396 CAN_IT_FOV0|
AnnaBridge 167:e84263d55307 1397 CAN_IT_FMP1|
AnnaBridge 167:e84263d55307 1398 CAN_IT_FOV1|
AnnaBridge 167:e84263d55307 1399 CAN_IT_TME);
AnnaBridge 167:e84263d55307 1400
<> 144:ef7eb2e8f9f7 1401 /* Call Error callback function */
<> 144:ef7eb2e8f9f7 1402 HAL_CAN_ErrorCallback(hcan);
<> 144:ef7eb2e8f9f7 1403 }
<> 144:ef7eb2e8f9f7 1404 }
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /**
<> 144:ef7eb2e8f9f7 1407 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1408 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1409 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1410 * @retval None
<> 144:ef7eb2e8f9f7 1411 */
<> 144:ef7eb2e8f9f7 1412 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1413 {
<> 144:ef7eb2e8f9f7 1414 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1415 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1416 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1417 the HAL_CAN_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1418 */
<> 144:ef7eb2e8f9f7 1419 }
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /**
<> 144:ef7eb2e8f9f7 1422 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1423 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1424 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1425 * @retval None
<> 144:ef7eb2e8f9f7 1426 */
<> 144:ef7eb2e8f9f7 1427 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1430 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1431 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1432 the HAL_CAN_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1433 */
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /**
<> 144:ef7eb2e8f9f7 1437 * @brief Error CAN callback.
<> 144:ef7eb2e8f9f7 1438 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1439 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1440 * @retval None
<> 144:ef7eb2e8f9f7 1441 */
<> 144:ef7eb2e8f9f7 1442 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1443 {
<> 144:ef7eb2e8f9f7 1444 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1445 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1446 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1447 the HAL_CAN_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1448 */
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /**
<> 144:ef7eb2e8f9f7 1452 * @}
<> 144:ef7eb2e8f9f7 1453 */
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
AnnaBridge 167:e84263d55307 1456 * @brief CAN Peripheral State functions
AnnaBridge 167:e84263d55307 1457 *
<> 144:ef7eb2e8f9f7 1458 @verbatim
<> 144:ef7eb2e8f9f7 1459 ==============================================================================
<> 144:ef7eb2e8f9f7 1460 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1461 ==============================================================================
<> 144:ef7eb2e8f9f7 1462 [..]
<> 144:ef7eb2e8f9f7 1463 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1464 (+) Check the CAN state.
<> 144:ef7eb2e8f9f7 1465 (+) Check CAN Errors detected during interrupt process
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 @endverbatim
<> 144:ef7eb2e8f9f7 1468 * @{
<> 144:ef7eb2e8f9f7 1469 */
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 /**
<> 144:ef7eb2e8f9f7 1472 * @brief return the CAN state
<> 144:ef7eb2e8f9f7 1473 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1474 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1475 * @retval HAL state
<> 144:ef7eb2e8f9f7 1476 */
<> 144:ef7eb2e8f9f7 1477 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1478 {
<> 144:ef7eb2e8f9f7 1479 /* Return CAN state */
<> 144:ef7eb2e8f9f7 1480 return hcan->State;
<> 144:ef7eb2e8f9f7 1481 }
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 /**
<> 144:ef7eb2e8f9f7 1484 * @brief Return the CAN error code
<> 144:ef7eb2e8f9f7 1485 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1486 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1487 * @retval CAN Error Code
<> 144:ef7eb2e8f9f7 1488 */
<> 144:ef7eb2e8f9f7 1489 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1490 {
<> 144:ef7eb2e8f9f7 1491 return hcan->ErrorCode;
<> 144:ef7eb2e8f9f7 1492 }
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 /**
<> 144:ef7eb2e8f9f7 1495 * @}
<> 144:ef7eb2e8f9f7 1496 */
<> 144:ef7eb2e8f9f7 1497 /**
<> 144:ef7eb2e8f9f7 1498 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 1499 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1500 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1501 * @retval HAL status
<> 144:ef7eb2e8f9f7 1502 */
<> 144:ef7eb2e8f9f7 1503 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1504 {
<> 144:ef7eb2e8f9f7 1505 /* Disable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 1506 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1509 {
AnnaBridge 167:e84263d55307 1510 /* Disable Error warning, Error passive, Bus-off, Last error code
AnnaBridge 167:e84263d55307 1511 and Error Interrupts */
AnnaBridge 167:e84263d55307 1512 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
AnnaBridge 167:e84263d55307 1513 CAN_IT_EPV |
AnnaBridge 167:e84263d55307 1514 CAN_IT_BOF |
AnnaBridge 167:e84263d55307 1515 CAN_IT_LEC |
AnnaBridge 167:e84263d55307 1516 CAN_IT_ERR );
<> 144:ef7eb2e8f9f7 1517 }
AnnaBridge 167:e84263d55307 1518
AnnaBridge 167:e84263d55307 1519 /* Change CAN state */
AnnaBridge 167:e84263d55307 1520 switch(hcan->State)
<> 144:ef7eb2e8f9f7 1521 {
AnnaBridge 167:e84263d55307 1522 case(HAL_CAN_STATE_BUSY_TX_RX0):
AnnaBridge 167:e84263d55307 1523 hcan->State = HAL_CAN_STATE_BUSY_RX0;
AnnaBridge 167:e84263d55307 1524 break;
AnnaBridge 167:e84263d55307 1525 case(HAL_CAN_STATE_BUSY_TX_RX1):
AnnaBridge 167:e84263d55307 1526 hcan->State = HAL_CAN_STATE_BUSY_RX1;
AnnaBridge 167:e84263d55307 1527 break;
AnnaBridge 167:e84263d55307 1528 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
AnnaBridge 167:e84263d55307 1529 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
AnnaBridge 167:e84263d55307 1530 break;
AnnaBridge 167:e84263d55307 1531 default: /* HAL_CAN_STATE_BUSY_TX */
AnnaBridge 167:e84263d55307 1532 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 1533 break;
<> 144:ef7eb2e8f9f7 1534 }
AnnaBridge 167:e84263d55307 1535
<> 144:ef7eb2e8f9f7 1536 /* Transmission complete callback */
<> 144:ef7eb2e8f9f7 1537 HAL_CAN_TxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 return HAL_OK;
<> 144:ef7eb2e8f9f7 1540 }
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 /**
<> 144:ef7eb2e8f9f7 1543 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 1544 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1545 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1546 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 1547 * @retval HAL status
<> 144:ef7eb2e8f9f7 1548 * @retval None
<> 144:ef7eb2e8f9f7 1549 */
<> 144:ef7eb2e8f9f7 1550 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1551 {
AnnaBridge 167:e84263d55307 1552 uint32_t tmp1 = 0U;
AnnaBridge 167:e84263d55307 1553 CanRxMsgTypeDef* pRxMsg = NULL;
AnnaBridge 167:e84263d55307 1554
AnnaBridge 167:e84263d55307 1555 /* Set RxMsg pointer */
AnnaBridge 167:e84263d55307 1556 if(FIFONumber == CAN_FIFO0)
AnnaBridge 167:e84263d55307 1557 {
AnnaBridge 167:e84263d55307 1558 pRxMsg = hcan->pRxMsg;
AnnaBridge 167:e84263d55307 1559 }
AnnaBridge 167:e84263d55307 1560 else /* FIFONumber == CAN_FIFO1 */
AnnaBridge 167:e84263d55307 1561 {
AnnaBridge 167:e84263d55307 1562 pRxMsg = hcan->pRx1Msg;
AnnaBridge 167:e84263d55307 1563 }
AnnaBridge 167:e84263d55307 1564
<> 144:ef7eb2e8f9f7 1565 /* Get the Id */
AnnaBridge 167:e84263d55307 1566 pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
AnnaBridge 167:e84263d55307 1567 if (pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 1568 {
AnnaBridge 167:e84263d55307 1569 pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
<> 144:ef7eb2e8f9f7 1570 }
<> 144:ef7eb2e8f9f7 1571 else
<> 144:ef7eb2e8f9f7 1572 {
AnnaBridge 167:e84263d55307 1573 pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
<> 144:ef7eb2e8f9f7 1574 }
<> 144:ef7eb2e8f9f7 1575
AnnaBridge 167:e84263d55307 1576 pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1577 /* Get the DLC */
AnnaBridge 167:e84263d55307 1578 pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
AnnaBridge 167:e84263d55307 1579 /* Get the FIFONumber */
AnnaBridge 167:e84263d55307 1580 pRxMsg->FIFONumber = FIFONumber;
<> 144:ef7eb2e8f9f7 1581 /* Get the FMI */
AnnaBridge 167:e84263d55307 1582 pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
<> 144:ef7eb2e8f9f7 1583 /* Get the data field */
AnnaBridge 167:e84263d55307 1584 pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
AnnaBridge 167:e84263d55307 1585 pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
AnnaBridge 167:e84263d55307 1586 pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
AnnaBridge 167:e84263d55307 1587 pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
AnnaBridge 167:e84263d55307 1588 pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
AnnaBridge 167:e84263d55307 1589 pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
AnnaBridge 167:e84263d55307 1590 pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
AnnaBridge 167:e84263d55307 1591 pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
<> 144:ef7eb2e8f9f7 1592 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 1593 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 1594 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1595 {
<> 144:ef7eb2e8f9f7 1596 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
AnnaBridge 167:e84263d55307 1597
AnnaBridge 167:e84263d55307 1598 /* Disable FIFO 0 overrun and message pending Interrupt */
AnnaBridge 167:e84263d55307 1599 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1600 }
<> 144:ef7eb2e8f9f7 1601 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 1602 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
AnnaBridge 167:e84263d55307 1605
AnnaBridge 167:e84263d55307 1606 /* Disable FIFO 1 overrun and message pending Interrupt */
AnnaBridge 167:e84263d55307 1607 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1608 }
AnnaBridge 167:e84263d55307 1609
AnnaBridge 167:e84263d55307 1610 tmp1 = hcan->State;
AnnaBridge 167:e84263d55307 1611 if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
<> 144:ef7eb2e8f9f7 1612 {
AnnaBridge 167:e84263d55307 1613 /* Disable Error warning, Error passive, Bus-off, Last error code
AnnaBridge 167:e84263d55307 1614 and Error Interrupts */
AnnaBridge 167:e84263d55307 1615 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
AnnaBridge 167:e84263d55307 1616 CAN_IT_EPV |
AnnaBridge 167:e84263d55307 1617 CAN_IT_BOF |
AnnaBridge 167:e84263d55307 1618 CAN_IT_LEC |
AnnaBridge 167:e84263d55307 1619 CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1620 }
AnnaBridge 167:e84263d55307 1621
AnnaBridge 167:e84263d55307 1622 /* Change CAN state */
AnnaBridge 167:e84263d55307 1623 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1624 {
AnnaBridge 167:e84263d55307 1625 switch(hcan->State)
AnnaBridge 167:e84263d55307 1626 {
AnnaBridge 167:e84263d55307 1627 case(HAL_CAN_STATE_BUSY_TX_RX0):
AnnaBridge 167:e84263d55307 1628 hcan->State = HAL_CAN_STATE_BUSY_TX;
AnnaBridge 167:e84263d55307 1629 break;
AnnaBridge 167:e84263d55307 1630 case(HAL_CAN_STATE_BUSY_RX0_RX1):
AnnaBridge 167:e84263d55307 1631 hcan->State = HAL_CAN_STATE_BUSY_RX1;
AnnaBridge 167:e84263d55307 1632 break;
AnnaBridge 167:e84263d55307 1633 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
AnnaBridge 167:e84263d55307 1634 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
AnnaBridge 167:e84263d55307 1635 break;
AnnaBridge 167:e84263d55307 1636 default: /* HAL_CAN_STATE_BUSY_RX0 */
AnnaBridge 167:e84263d55307 1637 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 1638 break;
AnnaBridge 167:e84263d55307 1639 }
<> 144:ef7eb2e8f9f7 1640 }
AnnaBridge 167:e84263d55307 1641 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1642 {
AnnaBridge 167:e84263d55307 1643 switch(hcan->State)
AnnaBridge 167:e84263d55307 1644 {
AnnaBridge 167:e84263d55307 1645 case(HAL_CAN_STATE_BUSY_TX_RX1):
AnnaBridge 167:e84263d55307 1646 hcan->State = HAL_CAN_STATE_BUSY_TX;
AnnaBridge 167:e84263d55307 1647 break;
AnnaBridge 167:e84263d55307 1648 case(HAL_CAN_STATE_BUSY_RX0_RX1):
AnnaBridge 167:e84263d55307 1649 hcan->State = HAL_CAN_STATE_BUSY_RX0;
AnnaBridge 167:e84263d55307 1650 break;
AnnaBridge 167:e84263d55307 1651 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
AnnaBridge 167:e84263d55307 1652 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
AnnaBridge 167:e84263d55307 1653 break;
AnnaBridge 167:e84263d55307 1654 default: /* HAL_CAN_STATE_BUSY_RX1 */
AnnaBridge 167:e84263d55307 1655 hcan->State = HAL_CAN_STATE_READY;
AnnaBridge 167:e84263d55307 1656 break;
AnnaBridge 167:e84263d55307 1657 }
<> 144:ef7eb2e8f9f7 1658 }
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 1661 HAL_CAN_RxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /* Return function status */
<> 144:ef7eb2e8f9f7 1664 return HAL_OK;
<> 144:ef7eb2e8f9f7 1665 }
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 /**
<> 144:ef7eb2e8f9f7 1668 * @}
<> 144:ef7eb2e8f9f7 1669 */
<> 144:ef7eb2e8f9f7 1670 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
AnnaBridge 167:e84263d55307 1671 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
AnnaBridge 167:e84263d55307 1672 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 #endif /* HAL_CAN_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1675 /**
<> 144:ef7eb2e8f9f7 1676 * @}
<> 144:ef7eb2e8f9f7 1677 */
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 /**
<> 144:ef7eb2e8f9f7 1680 * @}
<> 144:ef7eb2e8f9f7 1681 */
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/