I-O DATA DEV2 / Private_lora_SX1276

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Dependents:   Nucleo_Private_LoRa

sx1276/sx1276.cpp@29:cc4c7c1defca, 2020-12-18 (annotated)

Committer:
hakusan270
Date:
Fri Dec 18 00:26:38 2020 +0000
Revision:
29:cc4c7c1defca
Parent:
25:3778e6204cc1 
Private Lora SX1276  1st

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
mluis 16:d447f8d2d2d6 40 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
mluis 21:2e496deb7858 44 SX1276::SX1276( RadioEvents_t *events,
mluis 13:618826a997e2 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 21:2e496deb7858 47 : Radio( events ),
mluis 13:618826a997e2 48 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 49 nss( nss ),
mluis 13:618826a997e2 50 reset( reset ),
mluis 13:618826a997e2 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
mluis 13:618826a997e2 54 wait_ms( 10 );
mluis 13:618826a997e2 55 this->rxTx = 0;
GregCr 23:1e143575df0f 56 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 25:3778e6204cc1 57 currentOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 58
mluis 21:2e496deb7858 59 this->RadioEvents = events;
mluis 21:2e496deb7858 60
mluis 13:618826a997e2 61 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 62
mluis 13:618826a997e2 63 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 64 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 65 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 66 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 67 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 68 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 69
mluis 21:2e496deb7858 70 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 71 }
GregCr 0:e6ceb13d2d05 72
GregCr 0:e6ceb13d2d05 73 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 74 {
GregCr 23:1e143575df0f 75 delete this->rxtxBuffer;
mluis 13:618826a997e2 76 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 77 }
GregCr 0:e6ceb13d2d05 78
mluis 21:2e496deb7858 79 void SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 80 {
mluis 21:2e496deb7858 81 this->RadioEvents = events;
mluis 21:2e496deb7858 82 }
mluis 21:2e496deb7858 83
GregCr 19:71a47bb03fbb 84 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 85 {
GregCr 0:e6ceb13d2d05 86 return this->settings.State;
GregCr 0:e6ceb13d2d05 87 }
GregCr 0:e6ceb13d2d05 88
GregCr 0:e6ceb13d2d05 89 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 90 {
GregCr 0:e6ceb13d2d05 91 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 92 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 93 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 94 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 95 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 96 }
GregCr 0:e6ceb13d2d05 97
mluis 22:7f3aab69cca9 98 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 99 {
GregCr 7:2b555111463f 100 int16_t rssi = 0;
mluis 25:3778e6204cc1 101
GregCr 0:e6ceb13d2d05 102 SetModem( modem );
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 SetChannel( freq );
mluis 25:3778e6204cc1 105
GregCr 0:e6ceb13d2d05 106 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 107
GregCr 4:f0ce52e94d3f 108 wait_ms( 1 );
mluis 25:3778e6204cc1 109
GregCr 0:e6ceb13d2d05 110 rssi = GetRssi( modem );
mluis 25:3778e6204cc1 111
GregCr 0:e6ceb13d2d05 112 Sleep( );
mluis 25:3778e6204cc1 113
mluis 22:7f3aab69cca9 114 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 115 {
GregCr 0:e6ceb13d2d05 116 return false;
GregCr 0:e6ceb13d2d05 117 }
GregCr 0:e6ceb13d2d05 118 return true;
GregCr 0:e6ceb13d2d05 119 }
GregCr 0:e6ceb13d2d05 120
GregCr 0:e6ceb13d2d05 121 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 122 {
GregCr 0:e6ceb13d2d05 123 uint8_t i;
GregCr 0:e6ceb13d2d05 124 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 125
GregCr 0:e6ceb13d2d05 126 /*
mluis 25:3778e6204cc1 127 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 128 */
GregCr 0:e6ceb13d2d05 129 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 130 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 131
GregCr 0:e6ceb13d2d05 132 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 133 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 134 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 135 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 136 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 137 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 138 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 139 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 140 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 141
GregCr 0:e6ceb13d2d05 142 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 143 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 146 {
GregCr 4:f0ce52e94d3f 147 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 148 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 149 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 150 }
GregCr 0:e6ceb13d2d05 151
GregCr 0:e6ceb13d2d05 152 Sleep( );
GregCr 0:e6ceb13d2d05 153
GregCr 0:e6ceb13d2d05 154 return rnd;
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 /*!
mluis 22:7f3aab69cca9 158 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 159 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 160 * default values
mluis 22:7f3aab69cca9 161 */
mluis 22:7f3aab69cca9 162 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 163 {
mluis 22:7f3aab69cca9 164 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 165 uint32_t initialFreq;
mluis 22:7f3aab69cca9 166
mluis 22:7f3aab69cca9 167 // Save context
mluis 22:7f3aab69cca9 168 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 169 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 170 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 171 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 172
mluis 22:7f3aab69cca9 173 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 174 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 175
mluis 22:7f3aab69cca9 176 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 177 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 178 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 179 {
mluis 22:7f3aab69cca9 180 }
mluis 22:7f3aab69cca9 181
mluis 22:7f3aab69cca9 182 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 183 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 184
mluis 25:3778e6204cc1 185 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 186 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 187 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 188 {
mluis 22:7f3aab69cca9 189 }
mluis 22:7f3aab69cca9 190
mluis 22:7f3aab69cca9 191 // Restore context
mluis 22:7f3aab69cca9 192 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 193 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 194 }
mluis 22:7f3aab69cca9 195
mluis 22:7f3aab69cca9 196 /*!
GregCr 0:e6ceb13d2d05 197 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 198 *
GregCr 0:e6ceb13d2d05 199 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 200 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 201 */
GregCr 0:e6ceb13d2d05 202 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 203 {
GregCr 0:e6ceb13d2d05 204 uint8_t i;
GregCr 0:e6ceb13d2d05 205
GregCr 0:e6ceb13d2d05 206 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 207 {
GregCr 0:e6ceb13d2d05 208 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 209 {
GregCr 0:e6ceb13d2d05 210 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 211 }
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 214 while( 1 );
GregCr 0:e6ceb13d2d05 215 }
GregCr 0:e6ceb13d2d05 216
mluis 22:7f3aab69cca9 217 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 218 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 219 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 220 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 221 uint8_t payloadLen,
mluis 13:618826a997e2 222 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 223 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 SetModem( modem );
GregCr 0:e6ceb13d2d05 226
GregCr 0:e6ceb13d2d05 227 switch( modem )
GregCr 0:e6ceb13d2d05 228 {
GregCr 0:e6ceb13d2d05 229 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 230 {
GregCr 0:e6ceb13d2d05 231 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 234 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 235 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 236 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 239 this->settings.Fsk.PreambleLen = preambleLen;
mluis 25:3778e6204cc1 240
GregCr 0:e6ceb13d2d05 241 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 242 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 243 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 246 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 247
mluis 14:8552d0b840be 248 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 249 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 25:3778e6204cc1 250
mluis 22:7f3aab69cca9 251 if( fixLen == 1 )
mluis 22:7f3aab69cca9 252 {
mluis 22:7f3aab69cca9 253 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 254 }
GregCr 23:1e143575df0f 255 else
GregCr 23:1e143575df0f 256 {
mluis 25:3778e6204cc1 257 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
GregCr 23:1e143575df0f 258 }
GregCr 23:1e143575df0f 259
GregCr 0:e6ceb13d2d05 260 Write( REG_PACKETCONFIG1,
mluis 25:3778e6204cc1 261 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 262 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 263 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 264 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 265 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 266 }
GregCr 0:e6ceb13d2d05 267 break;
GregCr 0:e6ceb13d2d05 268 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 269 {
GregCr 0:e6ceb13d2d05 270 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 271 {
GregCr 0:e6ceb13d2d05 272 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 273 while( 1 );
GregCr 0:e6ceb13d2d05 274 }
GregCr 0:e6ceb13d2d05 275 bandwidth += 7;
GregCr 0:e6ceb13d2d05 276 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 277 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 278 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 279 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 280 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 281 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 283 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 284 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 285 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 286 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 287
GregCr 0:e6ceb13d2d05 288 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 datarate = 12;
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 293 {
GregCr 0:e6ceb13d2d05 294 datarate = 6;
GregCr 0:e6ceb13d2d05 295 }
mluis 25:3778e6204cc1 296
GregCr 0:e6ceb13d2d05 297 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 298 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 299 {
GregCr 0:e6ceb13d2d05 300 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 301 }
GregCr 0:e6ceb13d2d05 302 else
GregCr 0:e6ceb13d2d05 303 {
GregCr 0:e6ceb13d2d05 304 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 305 }
GregCr 0:e6ceb13d2d05 306
mluis 25:3778e6204cc1 307 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 308 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 309 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 310 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 311 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
mluis 25:3778e6204cc1 312 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 313 fixLen );
mluis 25:3778e6204cc1 314
GregCr 0:e6ceb13d2d05 315 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 316 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 317 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 318 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 319 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 320 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 321 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 322
mluis 25:3778e6204cc1 323 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 324 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 325 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 326 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 327
GregCr 0:e6ceb13d2d05 328 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 25:3778e6204cc1 329
GregCr 0:e6ceb13d2d05 330 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 331 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 332
mluis 13:618826a997e2 333 if( fixLen == 1 )
mluis 13:618826a997e2 334 {
mluis 13:618826a997e2 335 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 336 }
mluis 13:618826a997e2 337
GregCr 6:e7f02929cd3d 338 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 339 {
GregCr 6:e7f02929cd3d 340 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 341 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 342 }
GregCr 6:e7f02929cd3d 343
mluis 24:79c5b50b2b9c 344 if( ( bandwidth == 9 ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 345 {
mluis 25:3778e6204cc1 346 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 347 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 348 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 349 }
mluis 22:7f3aab69cca9 350 else if( bandwidth == 9 )
mluis 22:7f3aab69cca9 351 {
mluis 22:7f3aab69cca9 352 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 353 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 354 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 355 }
mluis 22:7f3aab69cca9 356 else
mluis 22:7f3aab69cca9 357 {
mluis 22:7f3aab69cca9 358 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 359 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 360 }
mluis 25:3778e6204cc1 361
GregCr 0:e6ceb13d2d05 362 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 363 {
mluis 25:3778e6204cc1 364 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 365 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 366 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 367 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 25:3778e6204cc1 368 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 369 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 370 }
GregCr 0:e6ceb13d2d05 371 else
GregCr 0:e6ceb13d2d05 372 {
GregCr 0:e6ceb13d2d05 373 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 374 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 375 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 376 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 25:3778e6204cc1 377 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 378 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 379 }
GregCr 0:e6ceb13d2d05 380 }
GregCr 0:e6ceb13d2d05 381 break;
GregCr 0:e6ceb13d2d05 382 }
GregCr 0:e6ceb13d2d05 383 }
GregCr 0:e6ceb13d2d05 384
mluis 25:3778e6204cc1 385 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 386 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 387 uint8_t coderate, uint16_t preambleLen,
mluis 25:3778e6204cc1 388 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 389 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 390 {
GregCr 0:e6ceb13d2d05 391 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 392 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 393
GregCr 0:e6ceb13d2d05 394 SetModem( modem );
mluis 25:3778e6204cc1 395
GregCr 0:e6ceb13d2d05 396 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 397 paDac = Read( REG_PADAC );
hakusan270 29:cc4c7c1defca 398 printf("1 pa config %02x dac %02x\r\n",paConfig ,paDac);
GregCr 0:e6ceb13d2d05 399
GregCr 0:e6ceb13d2d05 400 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 401 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
hakusan270 29:cc4c7c1defca 402 printf("2 pa config %02x dac %02x\r\n",paConfig ,paDac);
GregCr 0:e6ceb13d2d05 403
GregCr 0:e6ceb13d2d05 404 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 405 {
GregCr 0:e6ceb13d2d05 406 if( power > 17 )
GregCr 0:e6ceb13d2d05 407 {
GregCr 0:e6ceb13d2d05 408 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
hakusan270 29:cc4c7c1defca 409 printf("20dBm on\r\n");
GregCr 0:e6ceb13d2d05 410 }
GregCr 0:e6ceb13d2d05 411 else
GregCr 0:e6ceb13d2d05 412 {
GregCr 0:e6ceb13d2d05 413 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
hakusan270 29:cc4c7c1defca 414 printf("20dBm off\r\n");
GregCr 0:e6ceb13d2d05 415 }
GregCr 0:e6ceb13d2d05 416 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 417 {
GregCr 0:e6ceb13d2d05 418 if( power < 5 )
GregCr 0:e6ceb13d2d05 419 {
GregCr 0:e6ceb13d2d05 420 power = 5;
GregCr 0:e6ceb13d2d05 421 }
GregCr 0:e6ceb13d2d05 422 if( power > 20 )
GregCr 0:e6ceb13d2d05 423 {
GregCr 0:e6ceb13d2d05 424 power = 20;
GregCr 0:e6ceb13d2d05 425 }
hakusan270 29:cc4c7c1defca 426 printf("power = %d\r\n",power);
hakusan270 29:cc4c7c1defca 427
GregCr 0:e6ceb13d2d05 428 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 429 }
GregCr 0:e6ceb13d2d05 430 else
GregCr 0:e6ceb13d2d05 431 {
GregCr 0:e6ceb13d2d05 432 if( power < 2 )
GregCr 0:e6ceb13d2d05 433 {
GregCr 0:e6ceb13d2d05 434 power = 2;
GregCr 0:e6ceb13d2d05 435 }
GregCr 0:e6ceb13d2d05 436 if( power > 17 )
GregCr 0:e6ceb13d2d05 437 {
GregCr 0:e6ceb13d2d05 438 power = 17;
GregCr 0:e6ceb13d2d05 439 }
hakusan270 29:cc4c7c1defca 440 printf("power 2 = %d\r\n",power);
GregCr 0:e6ceb13d2d05 441 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 442 }
GregCr 0:e6ceb13d2d05 443 }
GregCr 0:e6ceb13d2d05 444 else
GregCr 0:e6ceb13d2d05 445 {
GregCr 0:e6ceb13d2d05 446 if( power < -1 )
GregCr 0:e6ceb13d2d05 447 {
GregCr 0:e6ceb13d2d05 448 power = -1;
GregCr 0:e6ceb13d2d05 449 }
GregCr 0:e6ceb13d2d05 450 if( power > 14 )
GregCr 0:e6ceb13d2d05 451 {
GregCr 0:e6ceb13d2d05 452 power = 14;
GregCr 0:e6ceb13d2d05 453 }
hakusan270 29:cc4c7c1defca 454 printf("power 3 = %d\r\n",power);
GregCr 0:e6ceb13d2d05 455 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 456 }
GregCr 0:e6ceb13d2d05 457 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 458 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 459
GregCr 0:e6ceb13d2d05 460 switch( modem )
GregCr 0:e6ceb13d2d05 461 {
GregCr 0:e6ceb13d2d05 462 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 463 {
GregCr 0:e6ceb13d2d05 464 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 465 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 466 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 467 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 468 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 469 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 470 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 471 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 472 this->settings.Fsk.TxTimeout = timeout;
mluis 25:3778e6204cc1 473
GregCr 0:e6ceb13d2d05 474 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 475 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 476 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 477
GregCr 0:e6ceb13d2d05 478 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 479 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 480 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 481
GregCr 0:e6ceb13d2d05 482 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 483 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 484
GregCr 0:e6ceb13d2d05 485 Write( REG_PACKETCONFIG1,
mluis 25:3778e6204cc1 486 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 487 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 488 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 489 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 490 ( crcOn << 4 ) );
mluis 25:3778e6204cc1 491
GregCr 0:e6ceb13d2d05 492 }
GregCr 0:e6ceb13d2d05 493 break;
GregCr 0:e6ceb13d2d05 494 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 495 {
GregCr 0:e6ceb13d2d05 496 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 497 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 498 {
GregCr 0:e6ceb13d2d05 499 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 500 while( 1 );
GregCr 0:e6ceb13d2d05 501 }
GregCr 0:e6ceb13d2d05 502 bandwidth += 7;
GregCr 0:e6ceb13d2d05 503 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 504 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 505 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 506 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 507 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 508 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 509 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 510 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 511 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 512 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 513
GregCr 0:e6ceb13d2d05 514 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 515 {
GregCr 0:e6ceb13d2d05 516 datarate = 12;
GregCr 0:e6ceb13d2d05 517 }
GregCr 0:e6ceb13d2d05 518 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 519 {
GregCr 0:e6ceb13d2d05 520 datarate = 6;
GregCr 0:e6ceb13d2d05 521 }
GregCr 0:e6ceb13d2d05 522 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 523 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 524 {
GregCr 0:e6ceb13d2d05 525 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 526 }
GregCr 0:e6ceb13d2d05 527 else
GregCr 0:e6ceb13d2d05 528 {
GregCr 0:e6ceb13d2d05 529 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 530 }
mluis 22:7f3aab69cca9 531
GregCr 6:e7f02929cd3d 532 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 533 {
GregCr 6:e7f02929cd3d 534 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 535 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 536 }
mluis 22:7f3aab69cca9 537
mluis 25:3778e6204cc1 538 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 539 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 540 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 541 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 542 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
mluis 25:3778e6204cc1 543 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 544 fixLen );
GregCr 0:e6ceb13d2d05 545
GregCr 0:e6ceb13d2d05 546 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 547 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 548 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 549 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 550 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 551
mluis 25:3778e6204cc1 552 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 553 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 554 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 555 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
mluis 25:3778e6204cc1 556
GregCr 0:e6ceb13d2d05 557 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 558 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 25:3778e6204cc1 559
GregCr 0:e6ceb13d2d05 560 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 561 {
mluis 25:3778e6204cc1 562 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 563 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 564 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 565 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 25:3778e6204cc1 566 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 567 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 568 }
GregCr 0:e6ceb13d2d05 569 else
GregCr 0:e6ceb13d2d05 570 {
GregCr 0:e6ceb13d2d05 571 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 572 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 573 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 574 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 25:3778e6204cc1 575 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 576 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 577 }
GregCr 0:e6ceb13d2d05 578 }
GregCr 0:e6ceb13d2d05 579 break;
GregCr 0:e6ceb13d2d05 580 }
GregCr 0:e6ceb13d2d05 581 }
GregCr 0:e6ceb13d2d05 582
mluis 22:7f3aab69cca9 583 double SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 584 {
mluis 22:7f3aab69cca9 585 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 586
GregCr 0:e6ceb13d2d05 587 switch( modem )
GregCr 0:e6ceb13d2d05 588 {
GregCr 0:e6ceb13d2d05 589 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 590 {
mluis 22:7f3aab69cca9 591 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 592 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 593 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 594 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 595 pktLen +
GregCr 0:e6ceb13d2d05 596 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 597 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 598 }
GregCr 0:e6ceb13d2d05 599 break;
GregCr 0:e6ceb13d2d05 600 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 601 {
GregCr 0:e6ceb13d2d05 602 double bw = 0.0;
GregCr 0:e6ceb13d2d05 603 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 604 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 605 {
GregCr 0:e6ceb13d2d05 606 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 607 // bw = 78e2;
GregCr 0:e6ceb13d2d05 608 // break;
GregCr 0:e6ceb13d2d05 609 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 610 // bw = 104e2;
GregCr 0:e6ceb13d2d05 611 // break;
GregCr 0:e6ceb13d2d05 612 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 613 // bw = 156e2;
GregCr 0:e6ceb13d2d05 614 // break;
GregCr 0:e6ceb13d2d05 615 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 616 // bw = 208e2;
GregCr 0:e6ceb13d2d05 617 // break;
GregCr 0:e6ceb13d2d05 618 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 619 // bw = 312e2;
GregCr 0:e6ceb13d2d05 620 // break;
GregCr 0:e6ceb13d2d05 621 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 622 // bw = 414e2;
GregCr 0:e6ceb13d2d05 623 // break;
GregCr 0:e6ceb13d2d05 624 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 625 // bw = 625e2;
GregCr 0:e6ceb13d2d05 626 // break;
GregCr 0:e6ceb13d2d05 627 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 628 bw = 125e3;
GregCr 0:e6ceb13d2d05 629 break;
GregCr 0:e6ceb13d2d05 630 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 631 bw = 250e3;
GregCr 0:e6ceb13d2d05 632 break;
GregCr 0:e6ceb13d2d05 633 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 634 bw = 500e3;
GregCr 0:e6ceb13d2d05 635 break;
GregCr 0:e6ceb13d2d05 636 }
GregCr 0:e6ceb13d2d05 637
GregCr 0:e6ceb13d2d05 638 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 639 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 640 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 641 // time of preamble
GregCr 0:e6ceb13d2d05 642 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 643 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 644 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 645 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 646 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 647 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 22:7f3aab69cca9 648 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 649 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 650 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 651 double tPayload = nPayload * ts;
mluis 25:3778e6204cc1 652 // Time on air
GregCr 0:e6ceb13d2d05 653 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 654 // return us secs
GregCr 0:e6ceb13d2d05 655 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 656 }
GregCr 0:e6ceb13d2d05 657 break;
GregCr 0:e6ceb13d2d05 658 }
GregCr 0:e6ceb13d2d05 659 return airTime;
GregCr 0:e6ceb13d2d05 660 }
GregCr 0:e6ceb13d2d05 661
GregCr 0:e6ceb13d2d05 662 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 663 {
GregCr 0:e6ceb13d2d05 664 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 665
GregCr 0:e6ceb13d2d05 666 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 667 {
GregCr 0:e6ceb13d2d05 668 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 669 {
GregCr 0:e6ceb13d2d05 670 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 671 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 672
GregCr 0:e6ceb13d2d05 673 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 674 {
GregCr 0:e6ceb13d2d05 675 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 676 }
GregCr 0:e6ceb13d2d05 677 else
GregCr 0:e6ceb13d2d05 678 {
GregCr 0:e6ceb13d2d05 679 Write( REG_PAYLOADLENGTH, size );
mluis 25:3778e6204cc1 680 }
mluis 25:3778e6204cc1 681
GregCr 0:e6ceb13d2d05 682 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 683 {
GregCr 0:e6ceb13d2d05 684 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 685 }
GregCr 0:e6ceb13d2d05 686 else
GregCr 0:e6ceb13d2d05 687 {
GregCr 23:1e143575df0f 688 memcpy( rxtxBuffer, buffer, size );
GregCr 0:e6ceb13d2d05 689 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 690 }
GregCr 0:e6ceb13d2d05 691
GregCr 0:e6ceb13d2d05 692 // Write payload buffer
GregCr 0:e6ceb13d2d05 693 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 694 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 695 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 696 }
GregCr 0:e6ceb13d2d05 697 break;
GregCr 0:e6ceb13d2d05 698 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 699 {
GregCr 0:e6ceb13d2d05 700 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 701 {
GregCr 0:e6ceb13d2d05 702 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 703 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 704 }
GregCr 0:e6ceb13d2d05 705 else
GregCr 0:e6ceb13d2d05 706 {
GregCr 0:e6ceb13d2d05 707 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 708 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 25:3778e6204cc1 709 }
mluis 25:3778e6204cc1 710
GregCr 0:e6ceb13d2d05 711 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 712
GregCr 0:e6ceb13d2d05 713 // Initializes the payload size
GregCr 0:e6ceb13d2d05 714 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 715
mluis 25:3778e6204cc1 716 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 717 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 718 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 719
GregCr 0:e6ceb13d2d05 720 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 721 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 722 {
GregCr 0:e6ceb13d2d05 723 Standby( );
GregCr 4:f0ce52e94d3f 724 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 725 }
GregCr 0:e6ceb13d2d05 726 // Write payload buffer
GregCr 0:e6ceb13d2d05 727 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 728 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 729 }
GregCr 0:e6ceb13d2d05 730 break;
GregCr 0:e6ceb13d2d05 731 }
GregCr 0:e6ceb13d2d05 732
GregCr 0:e6ceb13d2d05 733 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 734 }
GregCr 0:e6ceb13d2d05 735
GregCr 0:e6ceb13d2d05 736 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 737 {
mluis 13:618826a997e2 738 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 739 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 740
GregCr 0:e6ceb13d2d05 741 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 742 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 743 }
GregCr 0:e6ceb13d2d05 744
GregCr 0:e6ceb13d2d05 745 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 746 {
GregCr 0:e6ceb13d2d05 747 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 748 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 749
GregCr 0:e6ceb13d2d05 750 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 751 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 752 }
GregCr 0:e6ceb13d2d05 753
GregCr 0:e6ceb13d2d05 754 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 755 {
GregCr 0:e6ceb13d2d05 756 bool rxContinuous = false;
mluis 22:7f3aab69cca9 757
GregCr 0:e6ceb13d2d05 758 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 759 {
GregCr 0:e6ceb13d2d05 760 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 761 {
GregCr 0:e6ceb13d2d05 762 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 25:3778e6204cc1 763
GregCr 0:e6ceb13d2d05 764 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 765 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 766 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 767 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 768 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 769 // DIO5=ModeReady
mluis 22:7f3aab69cca9 770 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 23:1e143575df0f 771 RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 772 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 773 RF_DIOMAPPING1_DIO0_00 |
mluis 25:3778e6204cc1 774 RF_DIOMAPPING1_DIO1_00 |
GregCr 0:e6ceb13d2d05 775 RF_DIOMAPPING1_DIO2_11 );
mluis 25:3778e6204cc1 776
GregCr 0:e6ceb13d2d05 777 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 25:3778e6204cc1 778 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 779 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 780 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 25:3778e6204cc1 781
GregCr 0:e6ceb13d2d05 782 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 25:3778e6204cc1 783
mluis 25:3778e6204cc1 784 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
mluis 25:3778e6204cc1 785
GregCr 0:e6ceb13d2d05 786 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 787 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 788 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 789 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 790 }
GregCr 0:e6ceb13d2d05 791 break;
GregCr 0:e6ceb13d2d05 792 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 793 {
GregCr 0:e6ceb13d2d05 794 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 795 {
GregCr 0:e6ceb13d2d05 796 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 797 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 798 }
GregCr 0:e6ceb13d2d05 799 else
GregCr 0:e6ceb13d2d05 800 {
GregCr 0:e6ceb13d2d05 801 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 802 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 25:3778e6204cc1 803 }
mluis 22:7f3aab69cca9 804
mluis 22:7f3aab69cca9 805 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
mluis 22:7f3aab69cca9 806 if( this->settings.LoRa.Bandwidth < 9 )
mluis 22:7f3aab69cca9 807 {
mluis 22:7f3aab69cca9 808 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 809 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 810 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 811 {
mluis 22:7f3aab69cca9 812 case 0: // 7.8 kHz
mluis 22:7f3aab69cca9 813 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 814 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 815 break;
mluis 22:7f3aab69cca9 816 case 1: // 10.4 kHz
mluis 22:7f3aab69cca9 817 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 818 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 819 break;
mluis 22:7f3aab69cca9 820 case 2: // 15.6 kHz
mluis 22:7f3aab69cca9 821 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 822 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 823 break;
mluis 22:7f3aab69cca9 824 case 3: // 20.8 kHz
mluis 22:7f3aab69cca9 825 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 826 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 827 break;
mluis 22:7f3aab69cca9 828 case 4: // 31.2 kHz
mluis 22:7f3aab69cca9 829 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 830 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 831 break;
mluis 22:7f3aab69cca9 832 case 5: // 41.4 kHz
mluis 22:7f3aab69cca9 833 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 834 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 835 break;
mluis 22:7f3aab69cca9 836 case 6: // 62.5 kHz
mluis 22:7f3aab69cca9 837 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 838 break;
mluis 22:7f3aab69cca9 839 case 7: // 125 kHz
mluis 22:7f3aab69cca9 840 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 841 break;
mluis 22:7f3aab69cca9 842 case 8: // 250 kHz
mluis 22:7f3aab69cca9 843 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 844 break;
mluis 22:7f3aab69cca9 845 }
mluis 22:7f3aab69cca9 846 }
mluis 22:7f3aab69cca9 847 else
mluis 22:7f3aab69cca9 848 {
mluis 22:7f3aab69cca9 849 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 850 }
mluis 22:7f3aab69cca9 851
GregCr 0:e6ceb13d2d05 852 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 25:3778e6204cc1 853
GregCr 6:e7f02929cd3d 854 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 855 {
GregCr 6:e7f02929cd3d 856 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 857 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 858 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 859 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 860 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 861 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 862 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 863 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 864
mluis 13:618826a997e2 865 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 866 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 867 }
GregCr 6:e7f02929cd3d 868 else
GregCr 6:e7f02929cd3d 869 {
GregCr 6:e7f02929cd3d 870 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 871 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 872 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 873 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 874 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 875 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 876 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 877 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 878
GregCr 6:e7f02929cd3d 879 // DIO0=RxDone
GregCr 6:e7f02929cd3d 880 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 881 }
GregCr 0:e6ceb13d2d05 882 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 883 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 884 }
GregCr 0:e6ceb13d2d05 885 break;
GregCr 0:e6ceb13d2d05 886 }
GregCr 0:e6ceb13d2d05 887
GregCr 23:1e143575df0f 888 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 889
mluis 21:2e496deb7858 890 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 891 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 892 {
GregCr 0:e6ceb13d2d05 893 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 894 }
GregCr 0:e6ceb13d2d05 895
GregCr 0:e6ceb13d2d05 896 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 897 {
GregCr 0:e6ceb13d2d05 898 SetOpMode( RF_OPMODE_RECEIVER );
mluis 25:3778e6204cc1 899
GregCr 0:e6ceb13d2d05 900 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 901 {
mluis 25:3778e6204cc1 902 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 25:3778e6204cc1 903 ( ( Read( REG_SYNCCONFIG ) &
mluis 25:3778e6204cc1 904 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 25:3778e6204cc1 905 1.0 ) + 10.0 ) /
mluis 25:3778e6204cc1 906 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 0:e6ceb13d2d05 907 }
GregCr 0:e6ceb13d2d05 908 }
GregCr 0:e6ceb13d2d05 909 else
GregCr 0:e6ceb13d2d05 910 {
GregCr 0:e6ceb13d2d05 911 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 912 {
GregCr 0:e6ceb13d2d05 913 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 914 }
GregCr 0:e6ceb13d2d05 915 else
GregCr 0:e6ceb13d2d05 916 {
GregCr 0:e6ceb13d2d05 917 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 918 }
GregCr 0:e6ceb13d2d05 919 }
GregCr 0:e6ceb13d2d05 920 }
GregCr 0:e6ceb13d2d05 921
GregCr 0:e6ceb13d2d05 922 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 923 {
mluis 22:7f3aab69cca9 924
GregCr 0:e6ceb13d2d05 925 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 926 {
GregCr 0:e6ceb13d2d05 927 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 928 {
GregCr 0:e6ceb13d2d05 929 // DIO0=PacketSent
GregCr 23:1e143575df0f 930 // DIO1=FifoEmpty
GregCr 0:e6ceb13d2d05 931 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 932 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 933 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 934 // DIO5=ModeReady
mluis 22:7f3aab69cca9 935 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 25:3778e6204cc1 936 RF_DIOMAPPING1_DIO1_MASK &
mluis 25:3778e6204cc1 937 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 25:3778e6204cc1 938 RF_DIOMAPPING1_DIO1_01 );
GregCr 0:e6ceb13d2d05 939
GregCr 0:e6ceb13d2d05 940 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 941 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 942 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 943 }
GregCr 0:e6ceb13d2d05 944 break;
GregCr 0:e6ceb13d2d05 945 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 946 {
GregCr 6:e7f02929cd3d 947 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 948 {
GregCr 6:e7f02929cd3d 949 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 950 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 951 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 952 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 953 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 954 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 955 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 956 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 957
mluis 22:7f3aab69cca9 958 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 959 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 960 }
GregCr 6:e7f02929cd3d 961 else
GregCr 6:e7f02929cd3d 962 {
GregCr 6:e7f02929cd3d 963 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 964 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 965 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 966 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 967 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 968 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 969 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 970 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 971
GregCr 6:e7f02929cd3d 972 // DIO0=TxDone
mluis 22:7f3aab69cca9 973 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 974 }
GregCr 0:e6ceb13d2d05 975 }
GregCr 0:e6ceb13d2d05 976 break;
GregCr 0:e6ceb13d2d05 977 }
GregCr 0:e6ceb13d2d05 978
mluis 21:2e496deb7858 979 this->settings.State = RF_TX_RUNNING;
mluis 13:618826a997e2 980 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 981 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 982 }
GregCr 0:e6ceb13d2d05 983
GregCr 7:2b555111463f 984 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 985 {
GregCr 7:2b555111463f 986 switch( this->settings.Modem )
GregCr 7:2b555111463f 987 {
GregCr 7:2b555111463f 988 case MODEM_FSK:
GregCr 7:2b555111463f 989 {
mluis 25:3778e6204cc1 990
GregCr 7:2b555111463f 991 }
GregCr 7:2b555111463f 992 break;
GregCr 7:2b555111463f 993 case MODEM_LORA:
GregCr 7:2b555111463f 994 {
GregCr 7:2b555111463f 995 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 996 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 997 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 998 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 999 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 1000 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 1001 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
mluis 25:3778e6204cc1 1002 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 1003 );
mluis 25:3778e6204cc1 1004
GregCr 7:2b555111463f 1005 // DIO3=CADDone
GregCr 7:2b555111463f 1006 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 25:3778e6204cc1 1007
mluis 21:2e496deb7858 1008 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 1009 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 1010 }
GregCr 7:2b555111463f 1011 break;
GregCr 7:2b555111463f 1012 default:
GregCr 7:2b555111463f 1013 break;
GregCr 7:2b555111463f 1014 }
GregCr 7:2b555111463f 1015 }
GregCr 7:2b555111463f 1016
mluis 22:7f3aab69cca9 1017 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1018 {
GregCr 7:2b555111463f 1019 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1020
GregCr 0:e6ceb13d2d05 1021 switch( modem )
GregCr 0:e6ceb13d2d05 1022 {
GregCr 0:e6ceb13d2d05 1023 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1024 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1025 break;
GregCr 0:e6ceb13d2d05 1026 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1027 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1028 {
GregCr 0:e6ceb13d2d05 1029 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1030 }
GregCr 0:e6ceb13d2d05 1031 else
GregCr 0:e6ceb13d2d05 1032 {
GregCr 0:e6ceb13d2d05 1033 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1034 }
GregCr 0:e6ceb13d2d05 1035 break;
GregCr 0:e6ceb13d2d05 1036 default:
GregCr 0:e6ceb13d2d05 1037 rssi = -1;
GregCr 0:e6ceb13d2d05 1038 break;
GregCr 0:e6ceb13d2d05 1039 }
GregCr 0:e6ceb13d2d05 1040 return rssi;
GregCr 0:e6ceb13d2d05 1041 }
GregCr 0:e6ceb13d2d05 1042
GregCr 0:e6ceb13d2d05 1043 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1044 {
mluis 25:3778e6204cc1 1045 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1046 {
mluis 25:3778e6204cc1 1047 SetAntSwLowPower( true );
mluis 25:3778e6204cc1 1048 }
mluis 25:3778e6204cc1 1049 else
mluis 25:3778e6204cc1 1050 {
mluis 25:3778e6204cc1 1051 SetAntSwLowPower( false );
mluis 25:3778e6204cc1 1052 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 1053 {
mluis 25:3778e6204cc1 1054 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 1055 }
GregCr 0:e6ceb13d2d05 1056 else
GregCr 0:e6ceb13d2d05 1057 {
mluis 25:3778e6204cc1 1058 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1059 }
GregCr 0:e6ceb13d2d05 1060 }
mluis 25:3778e6204cc1 1061 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1062 }
GregCr 0:e6ceb13d2d05 1063
mluis 22:7f3aab69cca9 1064 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1065 {
mluis 22:7f3aab69cca9 1066 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1067 {
mluis 22:7f3aab69cca9 1068 return;
mluis 22:7f3aab69cca9 1069 }
mluis 22:7f3aab69cca9 1070
mluis 22:7f3aab69cca9 1071 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1072 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1073 {
mluis 22:7f3aab69cca9 1074 default:
mluis 22:7f3aab69cca9 1075 case MODEM_FSK:
mluis 22:7f3aab69cca9 1076 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1077 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1078
mluis 22:7f3aab69cca9 1079 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1080 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1081 break;
mluis 22:7f3aab69cca9 1082 case MODEM_LORA:
mluis 22:7f3aab69cca9 1083 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1084 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1085
mluis 22:7f3aab69cca9 1086 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1087 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1088 break;
GregCr 0:e6ceb13d2d05 1089 }
GregCr 0:e6ceb13d2d05 1090 }
GregCr 0:e6ceb13d2d05 1091
mluis 22:7f3aab69cca9 1092 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1093 {
mluis 20:e05596ba4166 1094 this->SetModem( modem );
mluis 20:e05596ba4166 1095
mluis 20:e05596ba4166 1096 switch( modem )
mluis 20:e05596ba4166 1097 {
mluis 20:e05596ba4166 1098 case MODEM_FSK:
mluis 20:e05596ba4166 1099 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1100 {
mluis 20:e05596ba4166 1101 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1102 }
mluis 20:e05596ba4166 1103 break;
mluis 20:e05596ba4166 1104 case MODEM_LORA:
mluis 20:e05596ba4166 1105 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1106 break;
mluis 20:e05596ba4166 1107 }
mluis 20:e05596ba4166 1108 }
mluis 20:e05596ba4166 1109
GregCr 0:e6ceb13d2d05 1110 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1111 {
GregCr 0:e6ceb13d2d05 1112 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1113 {
mluis 21:2e496deb7858 1114 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1115 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1116 {
GregCr 0:e6ceb13d2d05 1117 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1118 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1119 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1120 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1121
GregCr 0:e6ceb13d2d05 1122 // Clear Irqs
mluis 25:3778e6204cc1 1123 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1124 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1125 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1126 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1127
GregCr 0:e6ceb13d2d05 1128 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1129 {
GregCr 0:e6ceb13d2d05 1130 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1131 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 25:3778e6204cc1 1132 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 25:3778e6204cc1 1133 ( ( Read( REG_SYNCCONFIG ) &
mluis 25:3778e6204cc1 1134 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 25:3778e6204cc1 1135 1.0 ) + 10.0 ) /
mluis 25:3778e6204cc1 1136 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 0:e6ceb13d2d05 1137 }
GregCr 0:e6ceb13d2d05 1138 else
GregCr 0:e6ceb13d2d05 1139 {
mluis 21:2e496deb7858 1140 this->settings.State = RF_IDLE;
GregCr 5:11ec8a6ba4f0 1141 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1142 }
GregCr 0:e6ceb13d2d05 1143 }
mluis 22:7f3aab69cca9 1144 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1145 {
mluis 21:2e496deb7858 1146 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1147 }
GregCr 0:e6ceb13d2d05 1148 break;
mluis 21:2e496deb7858 1149 case RF_TX_RUNNING:
mluis 21:2e496deb7858 1150 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1151 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1152 {
mluis 21:2e496deb7858 1153 this->RadioEvents->TxTimeout( );
GregCr 0:e6ceb13d2d05 1154 }
GregCr 0:e6ceb13d2d05 1155 break;
GregCr 0:e6ceb13d2d05 1156 default:
GregCr 0:e6ceb13d2d05 1157 break;
GregCr 0:e6ceb13d2d05 1158 }
GregCr 0:e6ceb13d2d05 1159 }
GregCr 0:e6ceb13d2d05 1160
GregCr 0:e6ceb13d2d05 1161 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1162 {
mluis 20:e05596ba4166 1163 volatile uint8_t irqFlags = 0;
mluis 22:7f3aab69cca9 1164
GregCr 0:e6ceb13d2d05 1165 switch( this->settings.State )
mluis 25:3778e6204cc1 1166 {
mluis 21:2e496deb7858 1167 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1168 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1169 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1170 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1171 {
GregCr 0:e6ceb13d2d05 1172 case MODEM_FSK:
GregCr 18:99c6e44c1672 1173 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1174 {
GregCr 18:99c6e44c1672 1175 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1176 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1177 {
GregCr 18:99c6e44c1672 1178 // Clear Irqs
mluis 25:3778e6204cc1 1179 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1180 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1181 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1182 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 25:3778e6204cc1 1183
mluis 25:3778e6204cc1 1184 rxTimeoutTimer.detach( );
mluis 25:3778e6204cc1 1185
GregCr 18:99c6e44c1672 1186 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1187 {
mluis 25:3778e6204cc1 1188 rxTimeoutSyncWord.detach( );
mluis 21:2e496deb7858 1189 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1190 }
GregCr 18:99c6e44c1672 1191 else
GregCr 18:99c6e44c1672 1192 {
GregCr 18:99c6e44c1672 1193 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1194 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 25:3778e6204cc1 1195 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 25:3778e6204cc1 1196 ( ( Read( REG_SYNCCONFIG ) &
mluis 25:3778e6204cc1 1197 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 25:3778e6204cc1 1198 1.0 ) + 10.0 ) /
mluis 25:3778e6204cc1 1199 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 18:99c6e44c1672 1200 }
mluis 25:3778e6204cc1 1201
mluis 25:3778e6204cc1 1202
mluis 22:7f3aab69cca9 1203 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 18:99c6e44c1672 1204 {
mluis 22:7f3aab69cca9 1205 this->RadioEvents->RxError( );
GregCr 18:99c6e44c1672 1206 }
GregCr 18:99c6e44c1672 1207 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1208 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1209 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1210 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1211 break;
GregCr 0:e6ceb13d2d05 1212 }
GregCr 0:e6ceb13d2d05 1213 }
mluis 25:3778e6204cc1 1214
GregCr 0:e6ceb13d2d05 1215 // Read received packet size
GregCr 0:e6ceb13d2d05 1216 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1217 {
GregCr 0:e6ceb13d2d05 1218 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1219 {
GregCr 0:e6ceb13d2d05 1220 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1221 }
GregCr 0:e6ceb13d2d05 1222 else
GregCr 0:e6ceb13d2d05 1223 {
GregCr 0:e6ceb13d2d05 1224 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1225 }
GregCr 23:1e143575df0f 1226 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1227 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1228 }
GregCr 0:e6ceb13d2d05 1229 else
GregCr 0:e6ceb13d2d05 1230 {
GregCr 23:1e143575df0f 1231 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1232 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1233 }
GregCr 0:e6ceb13d2d05 1234
mluis 25:3778e6204cc1 1235 rxTimeoutTimer.detach( );
mluis 25:3778e6204cc1 1236
GregCr 0:e6ceb13d2d05 1237 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1238 {
mluis 21:2e496deb7858 1239 this->settings.State = RF_IDLE;
mluis 25:3778e6204cc1 1240 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1241 }
GregCr 0:e6ceb13d2d05 1242 else
GregCr 0:e6ceb13d2d05 1243 {
GregCr 0:e6ceb13d2d05 1244 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1245 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 25:3778e6204cc1 1246 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 25:3778e6204cc1 1247 ( ( Read( REG_SYNCCONFIG ) &
mluis 25:3778e6204cc1 1248 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 25:3778e6204cc1 1249 1.0 ) + 10.0 ) /
mluis 25:3778e6204cc1 1250 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 0:e6ceb13d2d05 1251 }
GregCr 0:e6ceb13d2d05 1252
mluis 22:7f3aab69cca9 1253 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1254 {
mluis 25:3778e6204cc1 1255 this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 25:3778e6204cc1 1256 }
GregCr 0:e6ceb13d2d05 1257 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1258 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1259 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1260 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1261 break;
GregCr 0:e6ceb13d2d05 1262 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1263 {
mluis 22:7f3aab69cca9 1264 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1265
GregCr 0:e6ceb13d2d05 1266 // Clear Irq
GregCr 0:e6ceb13d2d05 1267 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1268
GregCr 0:e6ceb13d2d05 1269 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1270 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1271 {
GregCr 0:e6ceb13d2d05 1272 // Clear Irq
GregCr 0:e6ceb13d2d05 1273 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1274
GregCr 0:e6ceb13d2d05 1275 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1276 {
mluis 21:2e496deb7858 1277 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1278 }
GregCr 0:e6ceb13d2d05 1279 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1280
mluis 22:7f3aab69cca9 1281 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 0:e6ceb13d2d05 1282 {
mluis 22:7f3aab69cca9 1283 this->RadioEvents->RxError( );
GregCr 0:e6ceb13d2d05 1284 }
GregCr 0:e6ceb13d2d05 1285 break;
GregCr 0:e6ceb13d2d05 1286 }
GregCr 0:e6ceb13d2d05 1287
GregCr 0:e6ceb13d2d05 1288 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1289 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1290 {
GregCr 0:e6ceb13d2d05 1291 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1292 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1293 snr = -snr;
GregCr 0:e6ceb13d2d05 1294 }
GregCr 0:e6ceb13d2d05 1295 else
GregCr 0:e6ceb13d2d05 1296 {
GregCr 0:e6ceb13d2d05 1297 // Divide by 4
GregCr 0:e6ceb13d2d05 1298 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1299 }
GregCr 0:e6ceb13d2d05 1300
GregCr 7:2b555111463f 1301 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1302 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1303 {
GregCr 0:e6ceb13d2d05 1304 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1305 {
GregCr 0:e6ceb13d2d05 1306 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1307 snr;
GregCr 0:e6ceb13d2d05 1308 }
GregCr 0:e6ceb13d2d05 1309 else
GregCr 0:e6ceb13d2d05 1310 {
GregCr 0:e6ceb13d2d05 1311 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1312 snr;
GregCr 0:e6ceb13d2d05 1313 }
GregCr 0:e6ceb13d2d05 1314 }
GregCr 0:e6ceb13d2d05 1315 else
mluis 25:3778e6204cc1 1316 {
GregCr 0:e6ceb13d2d05 1317 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1318 {
GregCr 0:e6ceb13d2d05 1319 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1320 }
GregCr 0:e6ceb13d2d05 1321 else
GregCr 0:e6ceb13d2d05 1322 {
GregCr 0:e6ceb13d2d05 1323 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1324 }
GregCr 0:e6ceb13d2d05 1325 }
GregCr 0:e6ceb13d2d05 1326
GregCr 0:e6ceb13d2d05 1327 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 23:1e143575df0f 1328 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 25:3778e6204cc1 1329
GregCr 0:e6ceb13d2d05 1330 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1331 {
mluis 21:2e496deb7858 1332 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1333 }
GregCr 0:e6ceb13d2d05 1334 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1335
mluis 22:7f3aab69cca9 1336 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1337 {
GregCr 23:1e143575df0f 1338 this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1339 }
GregCr 0:e6ceb13d2d05 1340 }
GregCr 0:e6ceb13d2d05 1341 break;
GregCr 0:e6ceb13d2d05 1342 default:
GregCr 0:e6ceb13d2d05 1343 break;
GregCr 0:e6ceb13d2d05 1344 }
GregCr 0:e6ceb13d2d05 1345 break;
mluis 21:2e496deb7858 1346 case RF_TX_RUNNING:
mluis 25:3778e6204cc1 1347 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1348 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1349 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1350 {
GregCr 0:e6ceb13d2d05 1351 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1352 // Clear Irq
GregCr 0:e6ceb13d2d05 1353 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1354 // Intentional fall through
GregCr 0:e6ceb13d2d05 1355 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1356 default:
mluis 21:2e496deb7858 1357 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1358 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1359 {
mluis 22:7f3aab69cca9 1360 this->RadioEvents->TxDone( );
mluis 25:3778e6204cc1 1361 }
GregCr 0:e6ceb13d2d05 1362 break;
GregCr 0:e6ceb13d2d05 1363 }
GregCr 0:e6ceb13d2d05 1364 break;
GregCr 0:e6ceb13d2d05 1365 default:
GregCr 0:e6ceb13d2d05 1366 break;
GregCr 0:e6ceb13d2d05 1367 }
GregCr 0:e6ceb13d2d05 1368 }
GregCr 0:e6ceb13d2d05 1369
GregCr 0:e6ceb13d2d05 1370 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1371 {
GregCr 0:e6ceb13d2d05 1372 switch( this->settings.State )
mluis 25:3778e6204cc1 1373 {
mluis 21:2e496deb7858 1374 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1375 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1376 {
GregCr 0:e6ceb13d2d05 1377 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1378 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1379 // Read received packet size
GregCr 0:e6ceb13d2d05 1380 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1381 {
GregCr 0:e6ceb13d2d05 1382 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1383 {
GregCr 0:e6ceb13d2d05 1384 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1385 }
GregCr 0:e6ceb13d2d05 1386 else
GregCr 0:e6ceb13d2d05 1387 {
GregCr 0:e6ceb13d2d05 1388 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1389 }
GregCr 0:e6ceb13d2d05 1390 }
GregCr 0:e6ceb13d2d05 1391
GregCr 0:e6ceb13d2d05 1392 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1393 {
GregCr 23:1e143575df0f 1394 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1395 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1396 }
GregCr 0:e6ceb13d2d05 1397 else
GregCr 0:e6ceb13d2d05 1398 {
GregCr 23:1e143575df0f 1399 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1400 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1401 }
GregCr 0:e6ceb13d2d05 1402 break;
GregCr 0:e6ceb13d2d05 1403 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1404 // Sync time out
GregCr 0:e6ceb13d2d05 1405 rxTimeoutTimer.detach( );
mluis 21:2e496deb7858 1406 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1407 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1408 {
mluis 21:2e496deb7858 1409 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1410 }
GregCr 0:e6ceb13d2d05 1411 break;
GregCr 0:e6ceb13d2d05 1412 default:
GregCr 0:e6ceb13d2d05 1413 break;
GregCr 0:e6ceb13d2d05 1414 }
GregCr 0:e6ceb13d2d05 1415 break;
mluis 21:2e496deb7858 1416 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1417 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1418 {
GregCr 0:e6ceb13d2d05 1419 case MODEM_FSK:
mluis 25:3778e6204cc1 1420 // FifoEmpty interrupt
GregCr 0:e6ceb13d2d05 1421 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1422 {
GregCr 23:1e143575df0f 1423 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1424 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1425 }
mluis 25:3778e6204cc1 1426 else
GregCr 0:e6ceb13d2d05 1427 {
GregCr 0:e6ceb13d2d05 1428 // Write the last chunk of data
GregCr 23:1e143575df0f 1429 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1430 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1431 }
GregCr 0:e6ceb13d2d05 1432 break;
GregCr 0:e6ceb13d2d05 1433 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1434 break;
GregCr 0:e6ceb13d2d05 1435 default:
GregCr 0:e6ceb13d2d05 1436 break;
GregCr 0:e6ceb13d2d05 1437 }
mluis 22:7f3aab69cca9 1438 break;
GregCr 0:e6ceb13d2d05 1439 default:
GregCr 0:e6ceb13d2d05 1440 break;
GregCr 0:e6ceb13d2d05 1441 }
GregCr 0:e6ceb13d2d05 1442 }
GregCr 0:e6ceb13d2d05 1443
GregCr 0:e6ceb13d2d05 1444 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1445 {
GregCr 0:e6ceb13d2d05 1446 switch( this->settings.State )
mluis 25:3778e6204cc1 1447 {
mluis 21:2e496deb7858 1448 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1449 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1450 {
GregCr 0:e6ceb13d2d05 1451 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1452 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1453 {
GregCr 0:e6ceb13d2d05 1454 rxTimeoutSyncWord.detach( );
mluis 25:3778e6204cc1 1455
GregCr 0:e6ceb13d2d05 1456 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 25:3778e6204cc1 1457
GregCr 0:e6ceb13d2d05 1458 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1459
GregCr 0:e6ceb13d2d05 1460 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1461 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1462 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1463 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1464 }
GregCr 0:e6ceb13d2d05 1465 break;
GregCr 0:e6ceb13d2d05 1466 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1467 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1468 {
GregCr 6:e7f02929cd3d 1469 // Clear Irq
GregCr 6:e7f02929cd3d 1470 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 25:3778e6204cc1 1471
mluis 22:7f3aab69cca9 1472 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1473 {
mluis 21:2e496deb7858 1474 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1475 }
mluis 22:7f3aab69cca9 1476 }
GregCr 0:e6ceb13d2d05 1477 break;
GregCr 0:e6ceb13d2d05 1478 default:
GregCr 0:e6ceb13d2d05 1479 break;
GregCr 0:e6ceb13d2d05 1480 }
GregCr 0:e6ceb13d2d05 1481 break;
mluis 21:2e496deb7858 1482 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1483 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1484 {
GregCr 0:e6ceb13d2d05 1485 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1486 break;
GregCr 0:e6ceb13d2d05 1487 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1488 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1489 {
GregCr 6:e7f02929cd3d 1490 // Clear Irq
GregCr 6:e7f02929cd3d 1491 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 25:3778e6204cc1 1492
mluis 22:7f3aab69cca9 1493 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1494 {
mluis 21:2e496deb7858 1495 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1496 }
mluis 22:7f3aab69cca9 1497 }
GregCr 0:e6ceb13d2d05 1498 break;
GregCr 0:e6ceb13d2d05 1499 default:
GregCr 0:e6ceb13d2d05 1500 break;
GregCr 0:e6ceb13d2d05 1501 }
mluis 22:7f3aab69cca9 1502 break;
GregCr 0:e6ceb13d2d05 1503 default:
GregCr 0:e6ceb13d2d05 1504 break;
GregCr 0:e6ceb13d2d05 1505 }
GregCr 0:e6ceb13d2d05 1506 }
GregCr 0:e6ceb13d2d05 1507
GregCr 0:e6ceb13d2d05 1508 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1509 {
GregCr 0:e6ceb13d2d05 1510 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1511 {
GregCr 0:e6ceb13d2d05 1512 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1513 break;
GregCr 0:e6ceb13d2d05 1514 case MODEM_LORA:
mluis 22:7f3aab69cca9 1515 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1516 {
mluis 13:618826a997e2 1517 // Clear Irq
mluis 22:7f3aab69cca9 1518 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1519 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1520 {
mluis 21:2e496deb7858 1521 this->RadioEvents->CadDone( true );
mluis 13:618826a997e2 1522 }
GregCr 12:aa5b3bf7fdf4 1523 }
GregCr 12:aa5b3bf7fdf4 1524 else
mluis 25:3778e6204cc1 1525 {
mluis 13:618826a997e2 1526 // Clear Irq
mluis 13:618826a997e2 1527 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1528 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1529 {
mluis 21:2e496deb7858 1530 this->RadioEvents->CadDone( false );
mluis 13:618826a997e2 1531 }
GregCr 7:2b555111463f 1532 }
GregCr 0:e6ceb13d2d05 1533 break;
GregCr 0:e6ceb13d2d05 1534 default:
GregCr 0:e6ceb13d2d05 1535 break;
GregCr 0:e6ceb13d2d05 1536 }
GregCr 0:e6ceb13d2d05 1537 }
GregCr 0:e6ceb13d2d05 1538
GregCr 0:e6ceb13d2d05 1539 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1540 {
GregCr 0:e6ceb13d2d05 1541 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1542 {
GregCr 0:e6ceb13d2d05 1543 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1544 {
GregCr 0:e6ceb13d2d05 1545 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1546 {
GregCr 0:e6ceb13d2d05 1547 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 25:3778e6204cc1 1548 }
GregCr 0:e6ceb13d2d05 1549 }
GregCr 0:e6ceb13d2d05 1550 break;
GregCr 0:e6ceb13d2d05 1551 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1552 break;
GregCr 0:e6ceb13d2d05 1553 default:
GregCr 0:e6ceb13d2d05 1554 break;
GregCr 0:e6ceb13d2d05 1555 }
GregCr 0:e6ceb13d2d05 1556 }
GregCr 0:e6ceb13d2d05 1557
GregCr 0:e6ceb13d2d05 1558 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1559 {
GregCr 0:e6ceb13d2d05 1560 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1561 {
GregCr 0:e6ceb13d2d05 1562 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1563 break;
GregCr 0:e6ceb13d2d05 1564 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1565 break;
GregCr 0:e6ceb13d2d05 1566 default:
GregCr 0:e6ceb13d2d05 1567 break;
GregCr 0:e6ceb13d2d05 1568 }
mluis 13:618826a997e2 1569 }