I-O DATA DEV2 / Private_lora_SX1276

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Dependents:   Nucleo_Private_LoRa

sx1276/sx1276-hal.cpp@29:cc4c7c1defca, 2020-12-18 (annotated)

Committer:
hakusan270
Date:
Fri Dec 18 00:26:38 2020 +0000
Revision:
29:cc4c7c1defca
Parent:
28:9ee41259a3eb 
Private Lora SX1276  1st

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 22 PinName antSwitch )
mluis 21:2e496deb7858 23 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
GregCr 0:e6ceb13d2d05 24 antSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 25 #if( defined ( TARGET_NUCLEO_L152RE ) )
mluis 25:3778e6204cc1 26 fake( D8 )
GregCr 12:aa5b3bf7fdf4 27 #else
GregCr 0:e6ceb13d2d05 28 fake( A3 )
GregCr 0:e6ceb13d2d05 29 #endif
GregCr 0:e6ceb13d2d05 30 {
mluis 21:2e496deb7858 31 this->RadioEvents = events;
mluis 21:2e496deb7858 32
GregCr 0:e6ceb13d2d05 33 Reset( );
mluis 25:3778e6204cc1 34
GregCr 0:e6ceb13d2d05 35 RxChainCalibration( );
mluis 25:3778e6204cc1 36
GregCr 0:e6ceb13d2d05 37 IoInit( );
mluis 25:3778e6204cc1 38
GregCr 0:e6ceb13d2d05 39 SetOpMode( RF_OPMODE_SLEEP );
mluis 25:3778e6204cc1 40
GregCr 0:e6ceb13d2d05 41 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 42
GregCr 0:e6ceb13d2d05 43 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 46
mluis 21:2e496deb7858 47 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 48 }
GregCr 0:e6ceb13d2d05 49
mluis 25:3778e6204cc1 50 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
hakusan270 28:9ee41259a3eb 51 #if ( defined ( TARGET_NUCLEO_L152RE )|| defined ( TARGET_NUCLEO_L073RZ ) || defined ( TARGET_NUCLEO_L053R8 ) )
hakusan270 28:9ee41259a3eb 52 : SX1276( events, D11, D12, D13, D10, D9, D8, D3, D4, D5, A3, A1 ), // For NUCLEO L152RE dio4 is on port A3
GregCr 0:e6ceb13d2d05 53 antSwitch( A4 ),
GregCr 0:e6ceb13d2d05 54 fake( D8 )
mluis 20:e05596ba4166 55 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 56 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 20:e05596ba4166 57 antSwitch( P0_23 ),
mluis 20:e05596ba4166 58 fake( A3 )
GregCr 0:e6ceb13d2d05 59 #else
hakusan270 29:cc4c7c1defca 60 : SX1276( events, D11, D12, D13, D10, D9, D8, D7, D6, D4, D3, D2 ), // For NUCLEO
hakusan270 29:cc4c7c1defca 61 antSwitch( A4 ),
hakusan270 29:cc4c7c1defca 62 fake( D8 )
hakusan270 29:cc4c7c1defca 63 // : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
hakusan270 29:cc4c7c1defca 64 // antSwitch( A4 ),
hakusan270 29:cc4c7c1defca 65 // fake( A3 )
GregCr 0:e6ceb13d2d05 66 #endif
GregCr 0:e6ceb13d2d05 67 {
mluis 21:2e496deb7858 68 this->RadioEvents = events;
mluis 21:2e496deb7858 69
GregCr 0:e6ceb13d2d05 70 Reset( );
mluis 25:3778e6204cc1 71
GregCr 5:11ec8a6ba4f0 72 boardConnected = UNKNOWN;
mluis 25:3778e6204cc1 73
GregCr 1:f979673946c0 74 DetectBoardType( );
mluis 25:3778e6204cc1 75
GregCr 0:e6ceb13d2d05 76 RxChainCalibration( );
mluis 25:3778e6204cc1 77
GregCr 0:e6ceb13d2d05 78 IoInit( );
mluis 25:3778e6204cc1 79
GregCr 0:e6ceb13d2d05 80 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 81 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 82
GregCr 0:e6ceb13d2d05 83 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 84
GregCr 0:e6ceb13d2d05 85 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 86
mluis 21:2e496deb7858 87 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 88 }
GregCr 0:e6ceb13d2d05 89
GregCr 0:e6ceb13d2d05 90 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 91 // Board relative functions
GregCr 0:e6ceb13d2d05 92 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 93 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 94 {
GregCr 5:11ec8a6ba4f0 95 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 96 {
GregCr 5:11ec8a6ba4f0 97 antSwitch.input( );
hakusan270 29:cc4c7c1defca 98 // printf("antSwitch %d\r\n",ant);
GregCr 5:11ec8a6ba4f0 99 wait_ms( 1 );
hakusan270 29:cc4c7c1defca 100 int ant=1;
hakusan270 29:cc4c7c1defca 101 if(ant == 1)
hakusan270 29:cc4c7c1defca 102 {
hakusan270 29:cc4c7c1defca 103 printf("SX1276MB1LAS \r\n");
GregCr 5:11ec8a6ba4f0 104 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 105 }
GregCr 5:11ec8a6ba4f0 106 else
GregCr 5:11ec8a6ba4f0 107 {
GregCr 5:11ec8a6ba4f0 108 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 109 }
GregCr 5:11ec8a6ba4f0 110 antSwitch.output( );
GregCr 5:11ec8a6ba4f0 111 wait_ms( 1 );
GregCr 1:f979673946c0 112 }
GregCr 2:5eb3066446dd 113 return ( boardConnected );
GregCr 1:f979673946c0 114 }
GregCr 0:e6ceb13d2d05 115
GregCr 0:e6ceb13d2d05 116 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 117 {
GregCr 0:e6ceb13d2d05 118 AntSwInit( );
GregCr 0:e6ceb13d2d05 119 SpiInit( );
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
mluis 22:7f3aab69cca9 122 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 123 {
GregCr 0:e6ceb13d2d05 124 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 125 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 126 {
GregCr 0:e6ceb13d2d05 127 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 128 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 129 }
GregCr 0:e6ceb13d2d05 130 }
GregCr 0:e6ceb13d2d05 131
GregCr 0:e6ceb13d2d05 132 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 133 {
GregCr 0:e6ceb13d2d05 134 nss = 1;
GregCr 0:e6ceb13d2d05 135 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 136 uint32_t frequencyToSet = 8000000;
hakusan270 28:9ee41259a3eb 137 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_NUCLEO_L073RZ ) || defined ( TARGET_NUCLEO_L053R8 ))
GregCr 0:e6ceb13d2d05 138 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 139 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 140 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 141 #else
hakusan270 29:cc4c7c1defca 142 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 143 #endif
GregCr 0:e6ceb13d2d05 144 wait(0.1);
GregCr 0:e6ceb13d2d05 145 }
GregCr 0:e6ceb13d2d05 146
GregCr 0:e6ceb13d2d05 147 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 148 {
hakusan270 29:cc4c7c1defca 149 //#if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_NUCLEO_L073RZ ) || defined ( TARGET_NUCLEO_L053R8 ) )
mluis 25:3778e6204cc1 150 dio0.mode( PullDown );
hakusan270 29:cc4c7c1defca 151 // dio1.mode( PullDown );
hakusan270 29:cc4c7c1defca 152 // dio2.mode( PullDown );
hakusan270 29:cc4c7c1defca 153 // dio3.mode( PullDown );
hakusan270 29:cc4c7c1defca 154 // dio4.mode( PullDown );
hakusan270 29:cc4c7c1defca 155 //#endif
GregCr 0:e6ceb13d2d05 156 dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) );
hakusan270 29:cc4c7c1defca 157 // dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) );
hakusan270 29:cc4c7c1defca 158 // dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) );
hakusan270 29:cc4c7c1defca 159 // dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) );
hakusan270 29:cc4c7c1defca 160 // dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) );
GregCr 0:e6ceb13d2d05 161 }
GregCr 0:e6ceb13d2d05 162
GregCr 0:e6ceb13d2d05 163 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 164 {
GregCr 0:e6ceb13d2d05 165 //nothing
GregCr 0:e6ceb13d2d05 166 }
GregCr 0:e6ceb13d2d05 167
GregCr 0:e6ceb13d2d05 168 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 169 {
hakusan270 29:cc4c7c1defca 170 if( 1 /*channel > RF_MID_BAND_THRESH*/ )
GregCr 0:e6ceb13d2d05 171 {
GregCr 3:ca84be1f3fac 172 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 173 {
GregCr 1:f979673946c0 174 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 175 }
GregCr 1:f979673946c0 176 else
GregCr 1:f979673946c0 177 {
GregCr 1:f979673946c0 178 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 179 }
GregCr 0:e6ceb13d2d05 180 }
GregCr 0:e6ceb13d2d05 181 else
GregCr 0:e6ceb13d2d05 182 {
GregCr 0:e6ceb13d2d05 183 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 184 }
GregCr 0:e6ceb13d2d05 185 }
GregCr 0:e6ceb13d2d05 186
GregCr 0:e6ceb13d2d05 187 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 188 {
GregCr 0:e6ceb13d2d05 189 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 190 {
GregCr 0:e6ceb13d2d05 191 isRadioActive = status;
GregCr 0:e6ceb13d2d05 192
GregCr 0:e6ceb13d2d05 193 if( status == false )
GregCr 0:e6ceb13d2d05 194 {
GregCr 0:e6ceb13d2d05 195 AntSwInit( );
GregCr 0:e6ceb13d2d05 196 }
GregCr 0:e6ceb13d2d05 197 else
GregCr 0:e6ceb13d2d05 198 {
GregCr 0:e6ceb13d2d05 199 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 200 }
GregCr 0:e6ceb13d2d05 201 }
GregCr 0:e6ceb13d2d05 202 }
GregCr 0:e6ceb13d2d05 203
GregCr 0:e6ceb13d2d05 204 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 205 {
GregCr 0:e6ceb13d2d05 206 antSwitch = 0;
GregCr 0:e6ceb13d2d05 207 }
GregCr 0:e6ceb13d2d05 208
GregCr 0:e6ceb13d2d05 209 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 210 {
GregCr 0:e6ceb13d2d05 211 antSwitch = 0;
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213
GregCr 0:e6ceb13d2d05 214 void SX1276MB1xAS::SetAntSw( uint8_t rxTx )
GregCr 0:e6ceb13d2d05 215 {
GregCr 0:e6ceb13d2d05 216
GregCr 0:e6ceb13d2d05 217 this->rxTx = rxTx;
GregCr 0:e6ceb13d2d05 218
mluis 25:3778e6204cc1 219 // 1: Tx, 0: Rx
GregCr 0:e6ceb13d2d05 220 if( rxTx != 0 )
GregCr 0:e6ceb13d2d05 221 {
GregCr 0:e6ceb13d2d05 222 antSwitch = 1;
GregCr 0:e6ceb13d2d05 223 }
GregCr 0:e6ceb13d2d05 224 else
GregCr 0:e6ceb13d2d05 225 {
GregCr 0:e6ceb13d2d05 226 antSwitch = 0;
GregCr 0:e6ceb13d2d05 227 }
GregCr 0:e6ceb13d2d05 228 }
GregCr 0:e6ceb13d2d05 229
GregCr 0:e6ceb13d2d05 230 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 231 {
GregCr 0:e6ceb13d2d05 232 //TODO: Implement check, currently all frequencies are supported
GregCr 0:e6ceb13d2d05 233 return true;
GregCr 0:e6ceb13d2d05 234 }
GregCr 0:e6ceb13d2d05 235
GregCr 0:e6ceb13d2d05 236
GregCr 0:e6ceb13d2d05 237 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 238 {
GregCr 4:f0ce52e94d3f 239 reset.output();
GregCr 0:e6ceb13d2d05 240 reset = 0;
GregCr 0:e6ceb13d2d05 241 wait_ms( 1 );
GregCr 4:f0ce52e94d3f 242 reset.input();
GregCr 0:e6ceb13d2d05 243 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 244 }
GregCr 0:e6ceb13d2d05 245
GregCr 0:e6ceb13d2d05 246 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 247 {
GregCr 0:e6ceb13d2d05 248 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 249 }
GregCr 0:e6ceb13d2d05 250
GregCr 0:e6ceb13d2d05 251 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 252 {
GregCr 0:e6ceb13d2d05 253 uint8_t data;
GregCr 0:e6ceb13d2d05 254 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 255 return data;
GregCr 0:e6ceb13d2d05 256 }
GregCr 0:e6ceb13d2d05 257
GregCr 0:e6ceb13d2d05 258 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 259 {
GregCr 0:e6ceb13d2d05 260 uint8_t i;
GregCr 0:e6ceb13d2d05 261
GregCr 0:e6ceb13d2d05 262 nss = 0;
GregCr 0:e6ceb13d2d05 263 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 264 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 265 {
GregCr 0:e6ceb13d2d05 266 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 267 }
GregCr 0:e6ceb13d2d05 268 nss = 1;
GregCr 0:e6ceb13d2d05 269 }
GregCr 0:e6ceb13d2d05 270
GregCr 0:e6ceb13d2d05 271 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 272 {
GregCr 0:e6ceb13d2d05 273 uint8_t i;
GregCr 0:e6ceb13d2d05 274
GregCr 0:e6ceb13d2d05 275 nss = 0;
GregCr 0:e6ceb13d2d05 276 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 277 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 278 {
GregCr 0:e6ceb13d2d05 279 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 280 }
GregCr 0:e6ceb13d2d05 281 nss = 1;
GregCr 0:e6ceb13d2d05 282 }
GregCr 0:e6ceb13d2d05 283
GregCr 0:e6ceb13d2d05 284 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 285 {
GregCr 0:e6ceb13d2d05 286 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 287 }
GregCr 0:e6ceb13d2d05 288
GregCr 0:e6ceb13d2d05 289 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 290 {
GregCr 0:e6ceb13d2d05 291 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 292 }