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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_adc.h@525:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 525:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 525:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 2 | * @file efm32hg_adc.h |
| mbed_official | 525:c320967f86b9 | 3 | * @brief EFM32HG_ADC register and bit field definitions |
| mbed_official | 525:c320967f86b9 | 4 | * @version 3.20.12 |
| mbed_official | 525:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 6 | * @section License |
| mbed_official | 525:c320967f86b9 | 7 | * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 525:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 9 | * |
| mbed_official | 525:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 525:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 525:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 525:c320967f86b9 | 13 | * |
| mbed_official | 525:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 525:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 525:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 525:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 525:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 525:c320967f86b9 | 19 | * |
| mbed_official | 525:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 525:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 525:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 525:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 525:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 525:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 525:c320967f86b9 | 26 | * |
| mbed_official | 525:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 525:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 525:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 525:c320967f86b9 | 30 | * |
| mbed_official | 525:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 33 | * @defgroup EFM32HG_ADC |
| mbed_official | 525:c320967f86b9 | 34 | * @{ |
| mbed_official | 525:c320967f86b9 | 35 | * @brief EFM32HG_ADC Register Declaration |
| mbed_official | 525:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 37 | typedef struct |
| mbed_official | 525:c320967f86b9 | 38 | { |
| mbed_official | 525:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 525:c320967f86b9 | 40 | __IO uint32_t CMD; /**< Command Register */ |
| mbed_official | 525:c320967f86b9 | 41 | __I uint32_t STATUS; /**< Status Register */ |
| mbed_official | 525:c320967f86b9 | 42 | __IO uint32_t SINGLECTRL; /**< Single Sample Control Register */ |
| mbed_official | 525:c320967f86b9 | 43 | __IO uint32_t SCANCTRL; /**< Scan Control Register */ |
| mbed_official | 525:c320967f86b9 | 44 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 525:c320967f86b9 | 45 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 525:c320967f86b9 | 46 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 525:c320967f86b9 | 47 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 525:c320967f86b9 | 48 | __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */ |
| mbed_official | 525:c320967f86b9 | 49 | __I uint32_t SCANDATA; /**< Scan Conversion Result Data */ |
| mbed_official | 525:c320967f86b9 | 50 | __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ |
| mbed_official | 525:c320967f86b9 | 51 | __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ |
| mbed_official | 525:c320967f86b9 | 52 | __IO uint32_t CAL; /**< Calibration Register */ |
| mbed_official | 525:c320967f86b9 | 53 | |
| mbed_official | 525:c320967f86b9 | 54 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 55 | __IO uint32_t BIASPROG; /**< Bias Programming Register */ |
| mbed_official | 525:c320967f86b9 | 56 | } ADC_TypeDef; /** @} */ |
| mbed_official | 525:c320967f86b9 | 57 | |
| mbed_official | 525:c320967f86b9 | 58 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 59 | * @defgroup EFM32HG_ADC_BitFields |
| mbed_official | 525:c320967f86b9 | 60 | * @{ |
| mbed_official | 525:c320967f86b9 | 61 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 62 | |
| mbed_official | 525:c320967f86b9 | 63 | /* Bit fields for ADC CTRL */ |
| mbed_official | 525:c320967f86b9 | 64 | #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 65 | #define _ADC_CTRL_MASK 0x1F7F7F3BUL /**< Mask for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 66 | #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ |
| mbed_official | 525:c320967f86b9 | 67 | #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ |
| mbed_official | 525:c320967f86b9 | 68 | #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 69 | #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 70 | #define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 71 | #define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 72 | #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 73 | #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 74 | #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 75 | #define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 76 | #define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 77 | #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 78 | #define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */ |
| mbed_official | 525:c320967f86b9 | 79 | #define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */ |
| mbed_official | 525:c320967f86b9 | 80 | #define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */ |
| mbed_official | 525:c320967f86b9 | 81 | #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 82 | #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 83 | #define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */ |
| mbed_official | 525:c320967f86b9 | 84 | #define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */ |
| mbed_official | 525:c320967f86b9 | 85 | #define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 86 | #define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 87 | #define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 88 | #define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 89 | #define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 90 | #define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 91 | #define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 92 | #define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 93 | #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ |
| mbed_official | 525:c320967f86b9 | 94 | #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ |
| mbed_official | 525:c320967f86b9 | 95 | #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 96 | #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 97 | #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 98 | #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 99 | #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 100 | #define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 101 | #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 102 | #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 103 | #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ |
| mbed_official | 525:c320967f86b9 | 104 | #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ |
| mbed_official | 525:c320967f86b9 | 105 | #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 106 | #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 107 | #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 108 | #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 109 | #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 110 | #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 111 | #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 112 | #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 113 | #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 114 | #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 115 | #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 116 | #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 117 | #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 118 | #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 119 | #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 120 | #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 121 | #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 122 | #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 123 | #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 124 | #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 125 | #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 126 | #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 127 | #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 128 | #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 129 | #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 130 | #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 131 | #define ADC_CTRL_CHCONIDLE (0x1UL << 28) /**< Input channel connected when ADC is IDLE */ |
| mbed_official | 525:c320967f86b9 | 132 | #define _ADC_CTRL_CHCONIDLE_SHIFT 28 /**< Shift value for ADC_CHCONIDLE */ |
| mbed_official | 525:c320967f86b9 | 133 | #define _ADC_CTRL_CHCONIDLE_MASK 0x10000000UL /**< Bit mask for ADC_CHCONIDLE */ |
| mbed_official | 525:c320967f86b9 | 134 | #define _ADC_CTRL_CHCONIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 135 | #define _ADC_CTRL_CHCONIDLE_DISCONNECT 0x00000000UL /**< Mode DISCONNECT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 136 | #define _ADC_CTRL_CHCONIDLE_KEEPCON 0x00000001UL /**< Mode KEEPCON for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 137 | #define ADC_CTRL_CHCONIDLE_DEFAULT (_ADC_CTRL_CHCONIDLE_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 138 | #define ADC_CTRL_CHCONIDLE_DISCONNECT (_ADC_CTRL_CHCONIDLE_DISCONNECT << 28) /**< Shifted mode DISCONNECT for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 139 | #define ADC_CTRL_CHCONIDLE_KEEPCON (_ADC_CTRL_CHCONIDLE_KEEPCON << 28) /**< Shifted mode KEEPCON for ADC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 140 | |
| mbed_official | 525:c320967f86b9 | 141 | /* Bit fields for ADC CMD */ |
| mbed_official | 525:c320967f86b9 | 142 | #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 143 | #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 144 | #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */ |
| mbed_official | 525:c320967f86b9 | 145 | #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ |
| mbed_official | 525:c320967f86b9 | 146 | #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ |
| mbed_official | 525:c320967f86b9 | 147 | #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 148 | #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 149 | #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */ |
| mbed_official | 525:c320967f86b9 | 150 | #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ |
| mbed_official | 525:c320967f86b9 | 151 | #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ |
| mbed_official | 525:c320967f86b9 | 152 | #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 153 | #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 154 | #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ |
| mbed_official | 525:c320967f86b9 | 155 | #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ |
| mbed_official | 525:c320967f86b9 | 156 | #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ |
| mbed_official | 525:c320967f86b9 | 157 | #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 158 | #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 159 | #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ |
| mbed_official | 525:c320967f86b9 | 160 | #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ |
| mbed_official | 525:c320967f86b9 | 161 | #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ |
| mbed_official | 525:c320967f86b9 | 162 | #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 163 | #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ |
| mbed_official | 525:c320967f86b9 | 164 | |
| mbed_official | 525:c320967f86b9 | 165 | /* Bit fields for ADC STATUS */ |
| mbed_official | 525:c320967f86b9 | 166 | #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 167 | #define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 168 | #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */ |
| mbed_official | 525:c320967f86b9 | 169 | #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ |
| mbed_official | 525:c320967f86b9 | 170 | #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ |
| mbed_official | 525:c320967f86b9 | 171 | #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 172 | #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 173 | #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ |
| mbed_official | 525:c320967f86b9 | 174 | #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ |
| mbed_official | 525:c320967f86b9 | 175 | #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ |
| mbed_official | 525:c320967f86b9 | 176 | #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 177 | #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 178 | #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */ |
| mbed_official | 525:c320967f86b9 | 179 | #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ |
| mbed_official | 525:c320967f86b9 | 180 | #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ |
| mbed_official | 525:c320967f86b9 | 181 | #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 182 | #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 183 | #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ |
| mbed_official | 525:c320967f86b9 | 184 | #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ |
| mbed_official | 525:c320967f86b9 | 185 | #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ |
| mbed_official | 525:c320967f86b9 | 186 | #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 187 | #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 188 | #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ |
| mbed_official | 525:c320967f86b9 | 189 | #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ |
| mbed_official | 525:c320967f86b9 | 190 | #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ |
| mbed_official | 525:c320967f86b9 | 191 | #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 192 | #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 193 | #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */ |
| mbed_official | 525:c320967f86b9 | 194 | #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ |
| mbed_official | 525:c320967f86b9 | 195 | #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ |
| mbed_official | 525:c320967f86b9 | 196 | #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 197 | #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 198 | #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ |
| mbed_official | 525:c320967f86b9 | 199 | #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ |
| mbed_official | 525:c320967f86b9 | 200 | #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ |
| mbed_official | 525:c320967f86b9 | 201 | #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 202 | #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 203 | #define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */ |
| mbed_official | 525:c320967f86b9 | 204 | #define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */ |
| mbed_official | 525:c320967f86b9 | 205 | #define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 206 | #define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 207 | #define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 208 | #define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 209 | #define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 210 | #define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 211 | #define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 212 | #define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 213 | #define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 214 | #define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 215 | #define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 216 | #define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 217 | #define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 218 | #define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 219 | #define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 220 | #define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 221 | #define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 222 | #define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 223 | |
| mbed_official | 525:c320967f86b9 | 224 | /* Bit fields for ADC SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 225 | #define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 226 | #define _ADC_SINGLECTRL_MASK 0x71F70F37UL /**< Mask for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 227 | #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */ |
| mbed_official | 525:c320967f86b9 | 228 | #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ |
| mbed_official | 525:c320967f86b9 | 229 | #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ |
| mbed_official | 525:c320967f86b9 | 230 | #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 231 | #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 232 | #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */ |
| mbed_official | 525:c320967f86b9 | 233 | #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ |
| mbed_official | 525:c320967f86b9 | 234 | #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ |
| mbed_official | 525:c320967f86b9 | 235 | #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 236 | #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 237 | #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */ |
| mbed_official | 525:c320967f86b9 | 238 | #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ |
| mbed_official | 525:c320967f86b9 | 239 | #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ |
| mbed_official | 525:c320967f86b9 | 240 | #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 241 | #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 242 | #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 243 | #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 244 | #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 245 | #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 246 | #define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */ |
| mbed_official | 525:c320967f86b9 | 247 | #define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */ |
| mbed_official | 525:c320967f86b9 | 248 | #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 249 | #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 250 | #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 251 | #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 252 | #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 253 | #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 254 | #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 255 | #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 256 | #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 257 | #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 258 | #define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 259 | #define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 260 | #define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 261 | #define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 262 | #define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 263 | #define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 264 | #define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 265 | #define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 266 | #define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 267 | #define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 268 | #define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 269 | #define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 270 | #define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 271 | #define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 272 | #define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 273 | #define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 274 | #define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 275 | #define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 276 | #define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 277 | #define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 278 | #define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 279 | #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 280 | #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 281 | #define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 282 | #define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 283 | #define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 284 | #define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 285 | #define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 286 | #define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 287 | #define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 288 | #define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 289 | #define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 290 | #define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 291 | #define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 292 | #define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 293 | #define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 294 | #define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 295 | #define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 296 | #define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 297 | #define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 298 | #define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 299 | #define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 300 | #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 301 | #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 302 | #define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */ |
| mbed_official | 525:c320967f86b9 | 303 | #define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */ |
| mbed_official | 525:c320967f86b9 | 304 | #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 305 | #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 306 | #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 307 | #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 308 | #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 309 | #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 310 | #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 311 | #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 312 | #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 313 | #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 314 | #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 315 | #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 316 | #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 317 | #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 318 | #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 319 | #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 320 | #define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */ |
| mbed_official | 525:c320967f86b9 | 321 | #define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */ |
| mbed_official | 525:c320967f86b9 | 322 | #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 323 | #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 324 | #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 325 | #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 326 | #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 327 | #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 328 | #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 329 | #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 330 | #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 331 | #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 332 | #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 333 | #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 334 | #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 335 | #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 336 | #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 337 | #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 338 | #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 339 | #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 340 | #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 341 | #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 342 | #define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */ |
| mbed_official | 525:c320967f86b9 | 343 | #define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */ |
| mbed_official | 525:c320967f86b9 | 344 | #define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */ |
| mbed_official | 525:c320967f86b9 | 345 | #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 346 | #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 347 | #define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */ |
| mbed_official | 525:c320967f86b9 | 348 | #define _ADC_SINGLECTRL_PRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_PRSSEL */ |
| mbed_official | 525:c320967f86b9 | 349 | #define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 350 | #define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 351 | #define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 352 | #define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 353 | #define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 354 | #define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 355 | #define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 356 | #define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 357 | #define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 358 | #define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 359 | #define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 360 | #define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 361 | #define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 362 | #define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */ |
| mbed_official | 525:c320967f86b9 | 363 | |
| mbed_official | 525:c320967f86b9 | 364 | /* Bit fields for ADC SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 365 | #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 366 | #define _ADC_SCANCTRL_MASK 0x71F7FF37UL /**< Mask for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 367 | #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ |
| mbed_official | 525:c320967f86b9 | 368 | #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ |
| mbed_official | 525:c320967f86b9 | 369 | #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ |
| mbed_official | 525:c320967f86b9 | 370 | #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 371 | #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 372 | #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ |
| mbed_official | 525:c320967f86b9 | 373 | #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ |
| mbed_official | 525:c320967f86b9 | 374 | #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ |
| mbed_official | 525:c320967f86b9 | 375 | #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 376 | #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 377 | #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ |
| mbed_official | 525:c320967f86b9 | 378 | #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ |
| mbed_official | 525:c320967f86b9 | 379 | #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ |
| mbed_official | 525:c320967f86b9 | 380 | #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 381 | #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 382 | #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 383 | #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 384 | #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 385 | #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 386 | #define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */ |
| mbed_official | 525:c320967f86b9 | 387 | #define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */ |
| mbed_official | 525:c320967f86b9 | 388 | #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 389 | #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 390 | #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 391 | #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 392 | #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 393 | #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 394 | #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 395 | #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 396 | #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 397 | #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 398 | #define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */ |
| mbed_official | 525:c320967f86b9 | 399 | #define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */ |
| mbed_official | 525:c320967f86b9 | 400 | #define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 401 | #define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 402 | #define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 403 | #define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 404 | #define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 405 | #define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 406 | #define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 407 | #define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 408 | #define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 409 | #define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 410 | #define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 411 | #define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 412 | #define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 413 | #define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 414 | #define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 415 | #define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 416 | #define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 417 | #define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 418 | #define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 419 | #define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 420 | #define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 421 | #define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 422 | #define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 423 | #define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 424 | #define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 425 | #define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 426 | #define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */ |
| mbed_official | 525:c320967f86b9 | 427 | #define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */ |
| mbed_official | 525:c320967f86b9 | 428 | #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 429 | #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 430 | #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 431 | #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 432 | #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 433 | #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 434 | #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 435 | #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 436 | #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 437 | #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 438 | #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 439 | #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 440 | #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 441 | #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 442 | #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 443 | #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 444 | #define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */ |
| mbed_official | 525:c320967f86b9 | 445 | #define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */ |
| mbed_official | 525:c320967f86b9 | 446 | #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 447 | #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 448 | #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 449 | #define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 450 | #define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 451 | #define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 452 | #define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 453 | #define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 454 | #define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 455 | #define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 456 | #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 457 | #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 458 | #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 459 | #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 460 | #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 461 | #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 462 | #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 463 | #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 464 | #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 465 | #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 466 | #define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */ |
| mbed_official | 525:c320967f86b9 | 467 | #define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */ |
| mbed_official | 525:c320967f86b9 | 468 | #define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */ |
| mbed_official | 525:c320967f86b9 | 469 | #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 470 | #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 471 | #define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */ |
| mbed_official | 525:c320967f86b9 | 472 | #define _ADC_SCANCTRL_PRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_PRSSEL */ |
| mbed_official | 525:c320967f86b9 | 473 | #define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 474 | #define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 475 | #define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 476 | #define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 477 | #define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 478 | #define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 479 | #define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 480 | #define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 481 | #define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 482 | #define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 483 | #define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 484 | #define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 485 | #define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 486 | #define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */ |
| mbed_official | 525:c320967f86b9 | 487 | |
| mbed_official | 525:c320967f86b9 | 488 | /* Bit fields for ADC IEN */ |
| mbed_official | 525:c320967f86b9 | 489 | #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 490 | #define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 491 | #define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 492 | #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 493 | #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 494 | #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 495 | #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 496 | #define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 497 | #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 498 | #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 499 | #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 500 | #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 501 | #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 502 | #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 503 | #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 504 | #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 505 | #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 506 | #define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 507 | #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 508 | #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 509 | #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 510 | #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ |
| mbed_official | 525:c320967f86b9 | 511 | |
| mbed_official | 525:c320967f86b9 | 512 | /* Bit fields for ADC IF */ |
| mbed_official | 525:c320967f86b9 | 513 | #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 514 | #define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 515 | #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 516 | #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 517 | #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 518 | #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 519 | #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 520 | #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 521 | #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 522 | #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 523 | #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 524 | #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 525 | #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 526 | #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 527 | #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 528 | #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 529 | #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 530 | #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 531 | #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 532 | #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 533 | #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 534 | #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ |
| mbed_official | 525:c320967f86b9 | 535 | |
| mbed_official | 525:c320967f86b9 | 536 | /* Bit fields for ADC IFS */ |
| mbed_official | 525:c320967f86b9 | 537 | #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 538 | #define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 539 | #define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 540 | #define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 541 | #define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 542 | #define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 543 | #define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 544 | #define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 545 | #define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 546 | #define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 547 | #define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 548 | #define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 549 | #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 550 | #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 551 | #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 552 | #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 553 | #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 554 | #define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 555 | #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 556 | #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 557 | #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 558 | #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ |
| mbed_official | 525:c320967f86b9 | 559 | |
| mbed_official | 525:c320967f86b9 | 560 | /* Bit fields for ADC IFC */ |
| mbed_official | 525:c320967f86b9 | 561 | #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 562 | #define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 563 | #define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 564 | #define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 565 | #define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ |
| mbed_official | 525:c320967f86b9 | 566 | #define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 567 | #define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 568 | #define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 569 | #define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 570 | #define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ |
| mbed_official | 525:c320967f86b9 | 571 | #define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 572 | #define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 573 | #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 574 | #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 575 | #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ |
| mbed_official | 525:c320967f86b9 | 576 | #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 577 | #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 578 | #define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 579 | #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 580 | #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ |
| mbed_official | 525:c320967f86b9 | 581 | #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 582 | #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ |
| mbed_official | 525:c320967f86b9 | 583 | |
| mbed_official | 525:c320967f86b9 | 584 | /* Bit fields for ADC SINGLEDATA */ |
| mbed_official | 525:c320967f86b9 | 585 | #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ |
| mbed_official | 525:c320967f86b9 | 586 | #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ |
| mbed_official | 525:c320967f86b9 | 587 | #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ |
| mbed_official | 525:c320967f86b9 | 588 | #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ |
| mbed_official | 525:c320967f86b9 | 589 | #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ |
| mbed_official | 525:c320967f86b9 | 590 | #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ |
| mbed_official | 525:c320967f86b9 | 591 | |
| mbed_official | 525:c320967f86b9 | 592 | /* Bit fields for ADC SCANDATA */ |
| mbed_official | 525:c320967f86b9 | 593 | #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ |
| mbed_official | 525:c320967f86b9 | 594 | #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ |
| mbed_official | 525:c320967f86b9 | 595 | #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ |
| mbed_official | 525:c320967f86b9 | 596 | #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ |
| mbed_official | 525:c320967f86b9 | 597 | #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ |
| mbed_official | 525:c320967f86b9 | 598 | #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ |
| mbed_official | 525:c320967f86b9 | 599 | |
| mbed_official | 525:c320967f86b9 | 600 | /* Bit fields for ADC SINGLEDATAP */ |
| mbed_official | 525:c320967f86b9 | 601 | #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ |
| mbed_official | 525:c320967f86b9 | 602 | #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ |
| mbed_official | 525:c320967f86b9 | 603 | #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ |
| mbed_official | 525:c320967f86b9 | 604 | #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ |
| mbed_official | 525:c320967f86b9 | 605 | #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ |
| mbed_official | 525:c320967f86b9 | 606 | #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ |
| mbed_official | 525:c320967f86b9 | 607 | |
| mbed_official | 525:c320967f86b9 | 608 | /* Bit fields for ADC SCANDATAP */ |
| mbed_official | 525:c320967f86b9 | 609 | #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ |
| mbed_official | 525:c320967f86b9 | 610 | #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ |
| mbed_official | 525:c320967f86b9 | 611 | #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ |
| mbed_official | 525:c320967f86b9 | 612 | #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ |
| mbed_official | 525:c320967f86b9 | 613 | #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ |
| mbed_official | 525:c320967f86b9 | 614 | #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ |
| mbed_official | 525:c320967f86b9 | 615 | |
| mbed_official | 525:c320967f86b9 | 616 | /* Bit fields for ADC CAL */ |
| mbed_official | 525:c320967f86b9 | 617 | #define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 618 | #define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 619 | #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ |
| mbed_official | 525:c320967f86b9 | 620 | #define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */ |
| mbed_official | 525:c320967f86b9 | 621 | #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 622 | #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 623 | #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ |
| mbed_official | 525:c320967f86b9 | 624 | #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ |
| mbed_official | 525:c320967f86b9 | 625 | #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 626 | #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 627 | #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ |
| mbed_official | 525:c320967f86b9 | 628 | #define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */ |
| mbed_official | 525:c320967f86b9 | 629 | #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 630 | #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 631 | #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ |
| mbed_official | 525:c320967f86b9 | 632 | #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ |
| mbed_official | 525:c320967f86b9 | 633 | #define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 634 | #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ |
| mbed_official | 525:c320967f86b9 | 635 | |
| mbed_official | 525:c320967f86b9 | 636 | /* Bit fields for ADC BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 637 | #define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 638 | #define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 639 | #define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 640 | #define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 641 | #define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 642 | #define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 643 | #define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */ |
| mbed_official | 525:c320967f86b9 | 644 | #define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */ |
| mbed_official | 525:c320967f86b9 | 645 | #define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */ |
| mbed_official | 525:c320967f86b9 | 646 | #define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 647 | #define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 648 | #define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */ |
| mbed_official | 525:c320967f86b9 | 649 | #define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */ |
| mbed_official | 525:c320967f86b9 | 650 | #define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 651 | #define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 652 | |
| mbed_official | 525:c320967f86b9 | 653 | /** @} End of group EFM32HG_ADC */ |
| mbed_official | 525:c320967f86b9 | 654 | |
| mbed_official | 525:c320967f86b9 | 655 |