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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@226:b062af740e40, 2014-06-11 (annotated)

Committer:: mbed_official
Date:: Wed Jun 11 09:45:09 2014 +0100
Revision:: 226:b062af740e40
Parent:: 106:ced8cbb51063
Child:: 369:2e96f1b71984

Synchronized with git revision 42deb9ac55f9bdf9835e9c41dc757117d344ffda



Full URL: https://github.com/mbedmicro/mbed/commit/42deb9ac55f9bdf9835e9c41dc757117d344ffda/



[NUCLEO_F401RE] Remove call to Systick + bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_spi.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	226:b062af740e40	5	* @version V1.1.0RC2
mbed_official	226:b062af740e40	6	* @date 14-May-2014
mbed_official	87:085cde657901	7	* @brief SPI HAL module driver.
mbed_official	87:085cde657901	8	*
mbed_official	87:085cde657901	9	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	87:085cde657901	11	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	12	* + IO operation functions
mbed_official	87:085cde657901	13	* + Peripheral Control functions
mbed_official	87:085cde657901	14	* + Peripheral State functions
mbed_official	87:085cde657901	15	@verbatim
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	##### How to use this driver #####
mbed_official	87:085cde657901	18	==============================================================================
mbed_official	87:085cde657901	19	[..]
mbed_official	87:085cde657901	20	The SPI HAL driver can be used as follows:
mbed_official	87:085cde657901	21
mbed_official	87:085cde657901	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	87:085cde657901	23	SPI_HandleTypeDef hspi;
mbed_official	87:085cde657901	24
mbed_official	226:b062af740e40	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official	87:085cde657901	26	(##) Enable the SPIx interface clock
mbed_official	87:085cde657901	27	(##) SPI pins configuration
mbed_official	87:085cde657901	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	87:085cde657901	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	87:085cde657901	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	87:085cde657901	31	(+++) Configure the SPIx interrupt priority
mbed_official	87:085cde657901	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	87:085cde657901	33	(##) DMA Configuration if you need to use DMA process
mbed_official	87:085cde657901	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official	87:085cde657901	35	(+++) Enable the DMAx interface clock using
mbed_official	87:085cde657901	36	(+++) Configure the DMA handle parameters
mbed_official	87:085cde657901	37	(+++) Configure the DMA Tx or Rx Stream
mbed_official	87:085cde657901	38	(+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	87:085cde657901	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official	87:085cde657901	40
mbed_official	87:085cde657901	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	87:085cde657901	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	87:085cde657901	43
mbed_official	87:085cde657901	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	87:085cde657901	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	226:b062af740e40	46	by calling the customed HAL_SPI_MspInit() API.
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	@endverbatim
mbed_official	87:085cde657901	49	******************************************************************************
mbed_official	87:085cde657901	50	* @attention
mbed_official	87:085cde657901	51	*
mbed_official	87:085cde657901	52	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	53	*
mbed_official	87:085cde657901	54	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	55	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	56	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	57	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	58	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	59	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	60	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	61	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	62	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	63	* without specific prior written permission.
mbed_official	87:085cde657901	64	*
mbed_official	87:085cde657901	65	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	66	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	67	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	68	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	69	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	70	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	71	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	72	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	73	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	74	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	75	*
mbed_official	87:085cde657901	76	******************************************************************************
mbed_official	87:085cde657901	77	*/
mbed_official	87:085cde657901	78
mbed_official	87:085cde657901	79	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	80	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	81
mbed_official	87:085cde657901	82	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	83	* @{
mbed_official	87:085cde657901	84	*/
mbed_official	87:085cde657901	85
mbed_official	87:085cde657901	86	/** @defgroup SPI
mbed_official	87:085cde657901	87	* @brief SPI HAL module driver
mbed_official	87:085cde657901	88	* @{
mbed_official	87:085cde657901	89	*/
mbed_official	87:085cde657901	90
mbed_official	87:085cde657901	91	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	87:085cde657901	92
mbed_official	87:085cde657901	93	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	94	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	95	#define SPI_TIMEOUT_VALUE 10
mbed_official	87:085cde657901	96	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	97	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	98	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	99	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	100	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	106:ced8cbb51063	101	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	102	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	103	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	104	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	105	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	106	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	107	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	108	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	87:085cde657901	109
mbed_official	87:085cde657901	110	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	111
mbed_official	87:085cde657901	112	/** @defgroup SPI_Private_Functions
mbed_official	87:085cde657901	113	* @{
mbed_official	87:085cde657901	114	*/
mbed_official	87:085cde657901	115
mbed_official	87:085cde657901	116	/** @defgroup SPI_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	117	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	118	*
mbed_official	87:085cde657901	119	@verbatim
mbed_official	87:085cde657901	120	===============================================================================
mbed_official	87:085cde657901	121	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	122	===============================================================================
mbed_official	87:085cde657901	123	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	87:085cde657901	124	de-initialiaze the SPIx peripheral:
mbed_official	87:085cde657901	125
mbed_official	226:b062af740e40	126	(+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official	87:085cde657901	127	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	87:085cde657901	128
mbed_official	87:085cde657901	129	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	87:085cde657901	130	the selected configuration:
mbed_official	87:085cde657901	131	(++) Mode
mbed_official	87:085cde657901	132	(++) Direction
mbed_official	87:085cde657901	133	(++) Data Size
mbed_official	87:085cde657901	134	(++) Clock Polarity and Phase
mbed_official	87:085cde657901	135	(++) NSS Management
mbed_official	87:085cde657901	136	(++) BaudRate Prescaler
mbed_official	87:085cde657901	137	(++) FirstBit
mbed_official	87:085cde657901	138	(++) TIMode
mbed_official	87:085cde657901	139	(++) CRC Calculation
mbed_official	87:085cde657901	140	(++) CRC Polynomial if CRC enabled
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	87:085cde657901	143	of the selected SPIx periperal.
mbed_official	87:085cde657901	144
mbed_official	87:085cde657901	145	@endverbatim
mbed_official	87:085cde657901	146	* @{
mbed_official	87:085cde657901	147	*/
mbed_official	87:085cde657901	148
mbed_official	87:085cde657901	149	/**
mbed_official	87:085cde657901	150	* @brief Initializes the SPI according to the specified parameters
mbed_official	87:085cde657901	151	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	226:b062af740e40	152	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	153	* the configuration information for SPI module.
mbed_official	87:085cde657901	154	* @retval HAL status
mbed_official	87:085cde657901	155	*/
mbed_official	87:085cde657901	156	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	157	{
mbed_official	87:085cde657901	158	/* Check the SPI handle allocation */
mbed_official	87:085cde657901	159	if(hspi == NULL)
mbed_official	87:085cde657901	160	{
mbed_official	87:085cde657901	161	return HAL_ERROR;
mbed_official	87:085cde657901	162	}
mbed_official	87:085cde657901	163
mbed_official	87:085cde657901	164	/* Check the parameters */
mbed_official	87:085cde657901	165	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	87:085cde657901	166	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	87:085cde657901	167	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	87:085cde657901	168	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	87:085cde657901	169	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	87:085cde657901	170	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	87:085cde657901	171	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	87:085cde657901	172	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	87:085cde657901	173	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	87:085cde657901	174	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	87:085cde657901	175	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	87:085cde657901	176
mbed_official	87:085cde657901	177	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	87:085cde657901	178	{
mbed_official	87:085cde657901	179	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	180	HAL_SPI_MspInit(hspi);
mbed_official	87:085cde657901	181	}
mbed_official	87:085cde657901	182
mbed_official	87:085cde657901	183	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	87:085cde657901	184
mbed_official	87:085cde657901	185	/* Disble the selected SPI peripheral */
mbed_official	87:085cde657901	186	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	187
mbed_official	87:085cde657901	188	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	87:085cde657901	189	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	87:085cde657901	190	Communication speed, First bit and CRC calculation state */
mbed_official	87:085cde657901	191	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	87:085cde657901	192	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	87:085cde657901	193	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	87:085cde657901	194
mbed_official	87:085cde657901	195	/* Configure : NSS management */
mbed_official	87:085cde657901	196	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode);
mbed_official	87:085cde657901	197
mbed_official	87:085cde657901	198	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	87:085cde657901	199	/* Configure : CRC Polynomial */
mbed_official	87:085cde657901	200	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	87:085cde657901	201
mbed_official	87:085cde657901	202	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	87:085cde657901	203	hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official	87:085cde657901	204
mbed_official	87:085cde657901	205	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	206	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	207
mbed_official	87:085cde657901	208	return HAL_OK;
mbed_official	87:085cde657901	209	}
mbed_official	87:085cde657901	210
mbed_official	87:085cde657901	211	/**
mbed_official	87:085cde657901	212	* @brief DeInitializes the SPI peripheral
mbed_official	226:b062af740e40	213	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	214	* the configuration information for SPI module.
mbed_official	87:085cde657901	215	* @retval HAL status
mbed_official	87:085cde657901	216	*/
mbed_official	87:085cde657901	217	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	218	{
mbed_official	87:085cde657901	219	/* Check the SPI handle allocation */
mbed_official	87:085cde657901	220	if(hspi == NULL)
mbed_official	87:085cde657901	221	{
mbed_official	87:085cde657901	222	return HAL_ERROR;
mbed_official	87:085cde657901	223	}
mbed_official	87:085cde657901	224
mbed_official	87:085cde657901	225	/* Disable the SPI Peripheral Clock */
mbed_official	87:085cde657901	226	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	227
mbed_official	87:085cde657901	228	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	229	HAL_SPI_MspDeInit(hspi);
mbed_official	87:085cde657901	230
mbed_official	87:085cde657901	231	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	232	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	87:085cde657901	233
mbed_official	106:ced8cbb51063	234	/* Release Lock */
mbed_official	106:ced8cbb51063	235	__HAL_UNLOCK(hspi);
mbed_official	106:ced8cbb51063	236
mbed_official	87:085cde657901	237	return HAL_OK;
mbed_official	87:085cde657901	238	}
mbed_official	87:085cde657901	239
mbed_official	87:085cde657901	240	/**
mbed_official	87:085cde657901	241	* @brief SPI MSP Init
mbed_official	226:b062af740e40	242	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	243	* the configuration information for SPI module.
mbed_official	87:085cde657901	244	* @retval None
mbed_official	87:085cde657901	245	*/
mbed_official	87:085cde657901	246	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	247	{
mbed_official	87:085cde657901	248	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	249	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	87:085cde657901	250	*/
mbed_official	87:085cde657901	251	}
mbed_official	87:085cde657901	252
mbed_official	87:085cde657901	253	/**
mbed_official	87:085cde657901	254	* @brief SPI MSP DeInit
mbed_official	226:b062af740e40	255	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	256	* the configuration information for SPI module.
mbed_official	87:085cde657901	257	* @retval None
mbed_official	87:085cde657901	258	*/
mbed_official	87:085cde657901	259	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	260	{
mbed_official	87:085cde657901	261	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	262	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	87:085cde657901	263	*/
mbed_official	87:085cde657901	264	}
mbed_official	87:085cde657901	265
mbed_official	87:085cde657901	266	/**
mbed_official	87:085cde657901	267	* @}
mbed_official	87:085cde657901	268	*/
mbed_official	87:085cde657901	269
mbed_official	87:085cde657901	270	/** @defgroup SPI_Group2 IO operation functions
mbed_official	87:085cde657901	271	* @brief Data transfers functions
mbed_official	87:085cde657901	272	*
mbed_official	87:085cde657901	273	@verbatim
mbed_official	87:085cde657901	274	==============================================================================
mbed_official	87:085cde657901	275	##### IO operation functions #####
mbed_official	87:085cde657901	276	===============================================================================
mbed_official	87:085cde657901	277	This subsection provides a set of functions allowing to manage the SPI
mbed_official	87:085cde657901	278	data transfers.
mbed_official	87:085cde657901	279
mbed_official	87:085cde657901	280	[..] The SPI supports master and slave mode :
mbed_official	87:085cde657901	281
mbed_official	226:b062af740e40	282	(#) There are two modes of transfer:
mbed_official	87:085cde657901	283	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	87:085cde657901	284	The HAL status of all data processing is returned by the same function
mbed_official	87:085cde657901	285	after finishing transfer.
mbed_official	87:085cde657901	286	(++) No-Blocking mode: The communication is performed using Interrupts
mbed_official	226:b062af740e40	287	or DMA, These APIs return the HAL status.
mbed_official	87:085cde657901	288	The end of the data processing will be indicated through the
mbed_official	87:085cde657901	289	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	87:085cde657901	290	using DMA mode.
mbed_official	87:085cde657901	291	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	87:085cde657901	292	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	87:085cde657901	293	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	87:085cde657901	294
mbed_official	226:b062af740e40	295	(#) Blocking mode APIs are :
mbed_official	87:085cde657901	296	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	297	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	298	(++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	87:085cde657901	299
mbed_official	226:b062af740e40	300	(#) Non Blocking mode API's with Interrupt are :
mbed_official	87:085cde657901	301	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	302	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	303	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	87:085cde657901	304	(++) HAL_SPI_IRQHandler()
mbed_official	87:085cde657901	305
mbed_official	226:b062af740e40	306	(#) Non Blocking mode functions with DMA are :
mbed_official	87:085cde657901	307	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	308	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	309	(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	87:085cde657901	310
mbed_official	226:b062af740e40	311	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
mbed_official	87:085cde657901	312	(++) HAL_SPI_TxCpltCallback()
mbed_official	87:085cde657901	313	(++) HAL_SPI_RxCpltCallback()
mbed_official	87:085cde657901	314	(++) HAL_SPI_ErrorCallback()
mbed_official	87:085cde657901	315	(++) HAL_SPI_TxRxCpltCallback()
mbed_official	87:085cde657901	316
mbed_official	87:085cde657901	317	@endverbatim
mbed_official	87:085cde657901	318	* @{
mbed_official	87:085cde657901	319	*/
mbed_official	87:085cde657901	320
mbed_official	87:085cde657901	321	/**
mbed_official	87:085cde657901	322	* @brief Transmit an amount of data in blocking mode
mbed_official	226:b062af740e40	323	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	324	* the configuration information for SPI module.
mbed_official	87:085cde657901	325	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	326	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	327	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	328	* @retval HAL status
mbed_official	87:085cde657901	329	*/
mbed_official	87:085cde657901	330	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	331	{
mbed_official	87:085cde657901	332
mbed_official	87:085cde657901	333	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	334	{
mbed_official	87:085cde657901	335	if((pData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	336	{
mbed_official	87:085cde657901	337	return HAL_ERROR;
mbed_official	87:085cde657901	338	}
mbed_official	87:085cde657901	339
mbed_official	87:085cde657901	340	/* Check the parameters */
mbed_official	87:085cde657901	341	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	342
mbed_official	87:085cde657901	343	/* Process Locked */
mbed_official	87:085cde657901	344	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	345
mbed_official	87:085cde657901	346	/* Configure communication */
mbed_official	87:085cde657901	347	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	348	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	349
mbed_official	87:085cde657901	350	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	351	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	352	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	353
mbed_official	87:085cde657901	354	/Init field not used in handle to zero /
mbed_official	87:085cde657901	355	hspi->TxISR = 0;
mbed_official	87:085cde657901	356	hspi->RxISR = 0;
mbed_official	87:085cde657901	357	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	358	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	359
mbed_official	87:085cde657901	360	/* Reset CRC Calculation */
mbed_official	87:085cde657901	361	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	362	{
mbed_official	87:085cde657901	363	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	364	}
mbed_official	87:085cde657901	365
mbed_official	87:085cde657901	366	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	367	{
mbed_official	87:085cde657901	368	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	369	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	370	}
mbed_official	87:085cde657901	371
mbed_official	87:085cde657901	372	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	373	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	374	{
mbed_official	87:085cde657901	375	/* Enable SPI peripheral */
mbed_official	87:085cde657901	376	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	377	}
mbed_official	87:085cde657901	378
mbed_official	87:085cde657901	379	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	380	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	381	{
mbed_official	87:085cde657901	382
mbed_official	87:085cde657901	383	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	384	hspi->TxXferCount--;
mbed_official	87:085cde657901	385
mbed_official	87:085cde657901	386	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	387	{
mbed_official	87:085cde657901	388	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	389	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	390	{
mbed_official	87:085cde657901	391	return HAL_TIMEOUT;
mbed_official	87:085cde657901	392	}
mbed_official	87:085cde657901	393	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	394	hspi->TxXferCount--;
mbed_official	87:085cde657901	395	}
mbed_official	87:085cde657901	396	/* Enable CRC Transmission */
mbed_official	87:085cde657901	397	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	398	{
mbed_official	87:085cde657901	399	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	400	}
mbed_official	87:085cde657901	401	}
mbed_official	87:085cde657901	402	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	403	else
mbed_official	87:085cde657901	404	{
mbed_official	87:085cde657901	405	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	406	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	407	hspi->TxXferCount--;
mbed_official	87:085cde657901	408
mbed_official	87:085cde657901	409	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	410	{
mbed_official	87:085cde657901	411	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	412	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	413	{
mbed_official	87:085cde657901	414	return HAL_TIMEOUT;
mbed_official	87:085cde657901	415	}
mbed_official	87:085cde657901	416	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	417	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	418	hspi->TxXferCount--;
mbed_official	87:085cde657901	419	}
mbed_official	87:085cde657901	420	/* Enable CRC Transmission */
mbed_official	87:085cde657901	421	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	422	{
mbed_official	87:085cde657901	423	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	424	}
mbed_official	87:085cde657901	425	}
mbed_official	87:085cde657901	426
mbed_official	87:085cde657901	427	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	428	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	429	{
mbed_official	87:085cde657901	430	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	431	return HAL_TIMEOUT;
mbed_official	87:085cde657901	432	}
mbed_official	87:085cde657901	433
mbed_official	87:085cde657901	434	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	435	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	436	{
mbed_official	87:085cde657901	437	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	438	return HAL_TIMEOUT;
mbed_official	87:085cde657901	439	}
mbed_official	87:085cde657901	440
mbed_official	87:085cde657901	441	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	442	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	443	{
mbed_official	87:085cde657901	444	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	445	}
mbed_official	87:085cde657901	446
mbed_official	87:085cde657901	447	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	448
mbed_official	87:085cde657901	449	/* Process Unlocked */
mbed_official	87:085cde657901	450	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	451
mbed_official	87:085cde657901	452	return HAL_OK;
mbed_official	87:085cde657901	453	}
mbed_official	87:085cde657901	454	else
mbed_official	87:085cde657901	455	{
mbed_official	87:085cde657901	456	return HAL_BUSY;
mbed_official	87:085cde657901	457	}
mbed_official	87:085cde657901	458	}
mbed_official	87:085cde657901	459
mbed_official	87:085cde657901	460	/**
mbed_official	87:085cde657901	461	* @brief Receive an amount of data in blocking mode
mbed_official	226:b062af740e40	462	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	463	* the configuration information for SPI module.
mbed_official	87:085cde657901	464	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	465	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	466	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	467	* @retval HAL status
mbed_official	87:085cde657901	468	*/
mbed_official	87:085cde657901	469	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	470	{
mbed_official	87:085cde657901	471	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	472	uint32_t tmp = 0;
mbed_official	87:085cde657901	473
mbed_official	87:085cde657901	474	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	475	{
mbed_official	87:085cde657901	476	if((pData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	477	{
mbed_official	87:085cde657901	478	return HAL_ERROR;
mbed_official	87:085cde657901	479	}
mbed_official	87:085cde657901	480
mbed_official	87:085cde657901	481	/* Process Locked */
mbed_official	87:085cde657901	482	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	483
mbed_official	87:085cde657901	484	/* Configure communication */
mbed_official	87:085cde657901	485	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	486	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	487
mbed_official	87:085cde657901	488	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	489	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	490	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	491
mbed_official	87:085cde657901	492	/Init field not used in handle to zero /
mbed_official	87:085cde657901	493	hspi->RxISR = 0;
mbed_official	87:085cde657901	494	hspi->TxISR = 0;
mbed_official	87:085cde657901	495	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	496	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	497
mbed_official	87:085cde657901	498	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	499	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	500	{
mbed_official	87:085cde657901	501	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	502	}
mbed_official	87:085cde657901	503
mbed_official	87:085cde657901	504	/* Reset CRC Calculation */
mbed_official	87:085cde657901	505	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	506	{
mbed_official	87:085cde657901	507	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	508	}
mbed_official	87:085cde657901	509
mbed_official	87:085cde657901	510	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	87:085cde657901	511	{
mbed_official	87:085cde657901	512	/* Process Unlocked */
mbed_official	87:085cde657901	513	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	514
mbed_official	87:085cde657901	515	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	516	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	87:085cde657901	517	}
mbed_official	87:085cde657901	518
mbed_official	87:085cde657901	519	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	520	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	521	{
mbed_official	87:085cde657901	522	/* Enable SPI peripheral */
mbed_official	87:085cde657901	523	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	524	}
mbed_official	87:085cde657901	525
mbed_official	87:085cde657901	526	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	527	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	528	{
mbed_official	87:085cde657901	529	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	530	{
mbed_official	87:085cde657901	531	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	532	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	533	{
mbed_official	87:085cde657901	534	return HAL_TIMEOUT;
mbed_official	87:085cde657901	535	}
mbed_official	87:085cde657901	536
mbed_official	87:085cde657901	537	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	538	hspi->RxXferCount--;
mbed_official	87:085cde657901	539	}
mbed_official	87:085cde657901	540	/* Enable CRC Transmission */
mbed_official	87:085cde657901	541	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	542	{
mbed_official	87:085cde657901	543	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	544	}
mbed_official	87:085cde657901	545	}
mbed_official	87:085cde657901	546	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	547	else
mbed_official	87:085cde657901	548	{
mbed_official	87:085cde657901	549	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	550	{
mbed_official	87:085cde657901	551	/* Wait until RXNE flag is set to read data */
mbed_official	87:085cde657901	552	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	553	{
mbed_official	87:085cde657901	554	return HAL_TIMEOUT;
mbed_official	87:085cde657901	555	}
mbed_official	87:085cde657901	556
mbed_official	87:085cde657901	557	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	558	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	559	hspi->RxXferCount--;
mbed_official	87:085cde657901	560	}
mbed_official	87:085cde657901	561	/* Enable CRC Transmission */
mbed_official	87:085cde657901	562	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	563	{
mbed_official	87:085cde657901	564	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	565	}
mbed_official	87:085cde657901	566	}
mbed_official	87:085cde657901	567
mbed_official	87:085cde657901	568	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	569	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	570	{
mbed_official	87:085cde657901	571	return HAL_TIMEOUT;
mbed_official	87:085cde657901	572	}
mbed_official	87:085cde657901	573
mbed_official	87:085cde657901	574	/* Receive last data in 8 Bit mode */
mbed_official	87:085cde657901	575	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	576	{
mbed_official	87:085cde657901	577	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	578	}
mbed_official	87:085cde657901	579	/* Receive last data in 16 Bit mode */
mbed_official	87:085cde657901	580	else
mbed_official	87:085cde657901	581	{
mbed_official	87:085cde657901	582	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	583	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	584	}
mbed_official	87:085cde657901	585	hspi->RxXferCount--;
mbed_official	87:085cde657901	586
mbed_official	87:085cde657901	587	/* Wait until RXNE flag is set: CRC Received */
mbed_official	87:085cde657901	588	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	589	{
mbed_official	87:085cde657901	590	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	591	{
mbed_official	87:085cde657901	592	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	593	return HAL_TIMEOUT;
mbed_official	87:085cde657901	594	}
mbed_official	87:085cde657901	595
mbed_official	87:085cde657901	596	/* Read CRC to Flush RXNE flag */
mbed_official	87:085cde657901	597	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	598	}
mbed_official	87:085cde657901	599
mbed_official	87:085cde657901	600	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	601	{
mbed_official	87:085cde657901	602	/* Disable SPI peripheral */
mbed_official	87:085cde657901	603	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	604	}
mbed_official	87:085cde657901	605
mbed_official	87:085cde657901	606	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	607
mbed_official	87:085cde657901	608	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	609	/* Check if CRC error occurred */
mbed_official	87:085cde657901	610	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	611	{
mbed_official	87:085cde657901	612	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	613
mbed_official	87:085cde657901	614	/* Reset CRC Calculation */
mbed_official	87:085cde657901	615	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	616
mbed_official	87:085cde657901	617	/* Process Unlocked */
mbed_official	87:085cde657901	618	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	619
mbed_official	87:085cde657901	620	return HAL_ERROR;
mbed_official	87:085cde657901	621	}
mbed_official	87:085cde657901	622
mbed_official	87:085cde657901	623	/* Process Unlocked */
mbed_official	87:085cde657901	624	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	625
mbed_official	87:085cde657901	626	return HAL_OK;
mbed_official	87:085cde657901	627	}
mbed_official	87:085cde657901	628	else
mbed_official	87:085cde657901	629	{
mbed_official	87:085cde657901	630	return HAL_BUSY;
mbed_official	87:085cde657901	631	}
mbed_official	87:085cde657901	632	}
mbed_official	87:085cde657901	633
mbed_official	87:085cde657901	634	/**
mbed_official	87:085cde657901	635	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	226:b062af740e40	636	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	637	* the configuration information for SPI module.
mbed_official	87:085cde657901	638	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	639	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	640	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	641	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	642	* @retval HAL status
mbed_official	87:085cde657901	643	*/
mbed_official	87:085cde657901	644	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	645	{
mbed_official	87:085cde657901	646	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	647	uint32_t tmp = 0;
mbed_official	87:085cde657901	648
mbed_official	87:085cde657901	649	tmp = hspi->State;
mbed_official	87:085cde657901	650	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	651	{
mbed_official	87:085cde657901	652	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	653	{
mbed_official	87:085cde657901	654	return HAL_ERROR;
mbed_official	87:085cde657901	655	}
mbed_official	87:085cde657901	656
mbed_official	87:085cde657901	657	/* Check the parameters */
mbed_official	87:085cde657901	658	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	659
mbed_official	87:085cde657901	660	/* Process Locked */
mbed_official	87:085cde657901	661	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	662
mbed_official	87:085cde657901	663	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	664	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	665	{
mbed_official	106:ced8cbb51063	666	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	667	}
mbed_official	87:085cde657901	668
mbed_official	87:085cde657901	669	/* Configure communication */
mbed_official	87:085cde657901	670	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	671
mbed_official	87:085cde657901	672	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	673	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	674	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	675
mbed_official	87:085cde657901	676	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	677	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	678	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	679
mbed_official	87:085cde657901	680	/Init field not used in handle to zero /
mbed_official	87:085cde657901	681	hspi->RxISR = 0;
mbed_official	87:085cde657901	682	hspi->TxISR = 0;
mbed_official	87:085cde657901	683
mbed_official	87:085cde657901	684	/* Reset CRC Calculation */
mbed_official	87:085cde657901	685	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	686	{
mbed_official	87:085cde657901	687	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	688	}
mbed_official	87:085cde657901	689
mbed_official	87:085cde657901	690	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	691	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	692	{
mbed_official	87:085cde657901	693	/* Enable SPI peripheral */
mbed_official	87:085cde657901	694	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	695	}
mbed_official	87:085cde657901	696
mbed_official	87:085cde657901	697	/* Transmit and Receive data in 16 Bit mode */
mbed_official	87:085cde657901	698	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	87:085cde657901	699	{
mbed_official	87:085cde657901	700	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	701	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	702	hspi->TxXferCount--;
mbed_official	87:085cde657901	703
mbed_official	87:085cde657901	704	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	705	{
mbed_official	87:085cde657901	706	/* Enable CRC Transmission */
mbed_official	87:085cde657901	707	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	708	{
mbed_official	87:085cde657901	709	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	710	}
mbed_official	87:085cde657901	711
mbed_official	87:085cde657901	712	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	713	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	714	{
mbed_official	87:085cde657901	715	return HAL_TIMEOUT;
mbed_official	87:085cde657901	716	}
mbed_official	87:085cde657901	717
mbed_official	87:085cde657901	718	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	719	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	720	hspi->RxXferCount--;
mbed_official	87:085cde657901	721	}
mbed_official	87:085cde657901	722	else
mbed_official	87:085cde657901	723	{
mbed_official	87:085cde657901	724	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	725	{
mbed_official	87:085cde657901	726	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	727	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	728	{
mbed_official	87:085cde657901	729	return HAL_TIMEOUT;
mbed_official	87:085cde657901	730	}
mbed_official	87:085cde657901	731
mbed_official	87:085cde657901	732	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	733	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	734	hspi->TxXferCount--;
mbed_official	87:085cde657901	735
mbed_official	87:085cde657901	736	/* Enable CRC Transmission */
mbed_official	87:085cde657901	737	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	738	{
mbed_official	87:085cde657901	739	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	740	}
mbed_official	87:085cde657901	741
mbed_official	87:085cde657901	742	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	743	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	744	{
mbed_official	87:085cde657901	745	return HAL_TIMEOUT;
mbed_official	87:085cde657901	746	}
mbed_official	87:085cde657901	747
mbed_official	87:085cde657901	748	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	749	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	750	hspi->RxXferCount--;
mbed_official	87:085cde657901	751	}
mbed_official	87:085cde657901	752
mbed_official	87:085cde657901	753	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	754	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	755	{
mbed_official	87:085cde657901	756	return HAL_TIMEOUT;
mbed_official	87:085cde657901	757	}
mbed_official	87:085cde657901	758
mbed_official	87:085cde657901	759	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	760	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	761	hspi->RxXferCount--;
mbed_official	87:085cde657901	762	}
mbed_official	87:085cde657901	763	}
mbed_official	87:085cde657901	764	/* Transmit and Receive data in 8 Bit mode */
mbed_official	87:085cde657901	765	else
mbed_official	87:085cde657901	766	{
mbed_official	87:085cde657901	767
mbed_official	87:085cde657901	768	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	769	hspi->TxXferCount--;
mbed_official	87:085cde657901	770
mbed_official	87:085cde657901	771	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	772	{
mbed_official	87:085cde657901	773	/* Enable CRC Transmission */
mbed_official	87:085cde657901	774	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	775	{
mbed_official	87:085cde657901	776	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	777	}
mbed_official	87:085cde657901	778
mbed_official	87:085cde657901	779	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	780	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	781	{
mbed_official	87:085cde657901	782	return HAL_TIMEOUT;
mbed_official	87:085cde657901	783	}
mbed_official	87:085cde657901	784
mbed_official	87:085cde657901	785	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	786	hspi->RxXferCount--;
mbed_official	87:085cde657901	787	}
mbed_official	87:085cde657901	788	else
mbed_official	87:085cde657901	789	{
mbed_official	87:085cde657901	790	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	791	{
mbed_official	87:085cde657901	792	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	793	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	794	{
mbed_official	87:085cde657901	795	return HAL_TIMEOUT;
mbed_official	87:085cde657901	796	}
mbed_official	87:085cde657901	797
mbed_official	87:085cde657901	798	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	799	hspi->TxXferCount--;
mbed_official	87:085cde657901	800
mbed_official	87:085cde657901	801	/* Enable CRC Transmission */
mbed_official	87:085cde657901	802	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	803	{
mbed_official	87:085cde657901	804	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	805	}
mbed_official	87:085cde657901	806
mbed_official	87:085cde657901	807	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	808	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	809	{
mbed_official	87:085cde657901	810	return HAL_TIMEOUT;
mbed_official	87:085cde657901	811	}
mbed_official	87:085cde657901	812
mbed_official	87:085cde657901	813	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	814	hspi->RxXferCount--;
mbed_official	87:085cde657901	815	}
mbed_official	87:085cde657901	816
mbed_official	87:085cde657901	817	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	818	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	819	{
mbed_official	87:085cde657901	820	return HAL_TIMEOUT;
mbed_official	87:085cde657901	821	}
mbed_official	87:085cde657901	822
mbed_official	87:085cde657901	823	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	824	hspi->RxXferCount--;
mbed_official	87:085cde657901	825	}
mbed_official	87:085cde657901	826	}
mbed_official	87:085cde657901	827
mbed_official	87:085cde657901	828	/* Read CRC from DR to close CRC calculation process */
mbed_official	87:085cde657901	829	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	830	{
mbed_official	87:085cde657901	831	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	832	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	833	{
mbed_official	87:085cde657901	834	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	835	return HAL_TIMEOUT;
mbed_official	87:085cde657901	836	}
mbed_official	87:085cde657901	837	/* Read CRC */
mbed_official	87:085cde657901	838	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	839	}
mbed_official	87:085cde657901	840
mbed_official	87:085cde657901	841	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	842	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	843	{
mbed_official	87:085cde657901	844	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	845	return HAL_TIMEOUT;
mbed_official	87:085cde657901	846	}
mbed_official	87:085cde657901	847
mbed_official	87:085cde657901	848	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	849
mbed_official	87:085cde657901	850	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	851	/* Check if CRC error occurred */
mbed_official	87:085cde657901	852	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	853	{
mbed_official	87:085cde657901	854	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	855
mbed_official	87:085cde657901	856	/* Reset CRC Calculation */
mbed_official	87:085cde657901	857	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	858	{
mbed_official	87:085cde657901	859	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	860	}
mbed_official	87:085cde657901	861
mbed_official	87:085cde657901	862	/* Process Unlocked */
mbed_official	87:085cde657901	863	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	864
mbed_official	87:085cde657901	865	return HAL_ERROR;
mbed_official	87:085cde657901	866	}
mbed_official	87:085cde657901	867
mbed_official	87:085cde657901	868	/* Process Unlocked */
mbed_official	87:085cde657901	869	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	870
mbed_official	87:085cde657901	871	return HAL_OK;
mbed_official	87:085cde657901	872	}
mbed_official	87:085cde657901	873	else
mbed_official	87:085cde657901	874	{
mbed_official	87:085cde657901	875	return HAL_BUSY;
mbed_official	87:085cde657901	876	}
mbed_official	87:085cde657901	877	}
mbed_official	87:085cde657901	878
mbed_official	87:085cde657901	879	/**
mbed_official	87:085cde657901	880	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	226:b062af740e40	881	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	882	* the configuration information for SPI module.
mbed_official	87:085cde657901	883	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	884	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	885	* @retval HAL status
mbed_official	87:085cde657901	886	*/
mbed_official	87:085cde657901	887	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	888	{
mbed_official	87:085cde657901	889	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	890	{
mbed_official	87:085cde657901	891	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	892	{
mbed_official	87:085cde657901	893	return HAL_ERROR;
mbed_official	87:085cde657901	894	}
mbed_official	87:085cde657901	895
mbed_official	87:085cde657901	896	/* Check the parameters */
mbed_official	87:085cde657901	897	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	898
mbed_official	87:085cde657901	899	/* Process Locked */
mbed_official	87:085cde657901	900	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	901
mbed_official	87:085cde657901	902	/* Configure communication */
mbed_official	87:085cde657901	903	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	904	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	905
mbed_official	87:085cde657901	906	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	907	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	908	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	909	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	910
mbed_official	87:085cde657901	911	/Init field not used in handle to zero /
mbed_official	87:085cde657901	912	hspi->RxISR = 0;
mbed_official	87:085cde657901	913	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	914	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	915
mbed_official	87:085cde657901	916	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	917	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	918	{
mbed_official	87:085cde657901	919	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	920	}
mbed_official	87:085cde657901	921
mbed_official	87:085cde657901	922	/* Reset CRC Calculation */
mbed_official	87:085cde657901	923	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	924	{
mbed_official	87:085cde657901	925	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	926	}
mbed_official	87:085cde657901	927
mbed_official	87:085cde657901	928	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	929	{
mbed_official	87:085cde657901	930	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	87:085cde657901	931	}else
mbed_official	87:085cde657901	932	{
mbed_official	87:085cde657901	933	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	934	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	87:085cde657901	935	}
mbed_official	87:085cde657901	936	/* Process Unlocked */
mbed_official	87:085cde657901	937	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	938
mbed_official	87:085cde657901	939	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	940	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	941	{
mbed_official	87:085cde657901	942	/* Enable SPI peripheral */
mbed_official	87:085cde657901	943	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	944	}
mbed_official	87:085cde657901	945
mbed_official	87:085cde657901	946	return HAL_OK;
mbed_official	87:085cde657901	947	}
mbed_official	87:085cde657901	948	else
mbed_official	87:085cde657901	949	{
mbed_official	87:085cde657901	950	return HAL_BUSY;
mbed_official	87:085cde657901	951	}
mbed_official	87:085cde657901	952	}
mbed_official	87:085cde657901	953
mbed_official	87:085cde657901	954	/**
mbed_official	87:085cde657901	955	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	226:b062af740e40	956	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	957	* the configuration information for SPI module.
mbed_official	87:085cde657901	958	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	959	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	960	* @retval HAL status
mbed_official	87:085cde657901	961	*/
mbed_official	87:085cde657901	962	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	963	{
mbed_official	87:085cde657901	964	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	965	{
mbed_official	87:085cde657901	966	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	967	{
mbed_official	87:085cde657901	968	return HAL_ERROR;
mbed_official	87:085cde657901	969	}
mbed_official	87:085cde657901	970
mbed_official	87:085cde657901	971	/* Process Locked */
mbed_official	87:085cde657901	972	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	973
mbed_official	87:085cde657901	974	/* Configure communication */
mbed_official	87:085cde657901	975	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	976	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	977
mbed_official	87:085cde657901	978	hspi->RxISR = &SPI_RxISR;
mbed_official	87:085cde657901	979	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	980	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	981	hspi->RxXferCount = Size ;
mbed_official	87:085cde657901	982
mbed_official	87:085cde657901	983	/Init field not used in handle to zero /
mbed_official	87:085cde657901	984	hspi->TxISR = 0;
mbed_official	87:085cde657901	985	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	986	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	987
mbed_official	87:085cde657901	988	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	989	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	990	{
mbed_official	87:085cde657901	991	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	992	}
mbed_official	87:085cde657901	993	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	994	{
mbed_official	87:085cde657901	995	/* Process Unlocked */
mbed_official	87:085cde657901	996	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	997
mbed_official	87:085cde657901	998	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	999	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	87:085cde657901	1000	}
mbed_official	87:085cde657901	1001
mbed_official	87:085cde657901	1002	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1003	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1004	{
mbed_official	87:085cde657901	1005	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1006	}
mbed_official	87:085cde657901	1007
mbed_official	87:085cde657901	1008	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	1009	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1010
mbed_official	87:085cde657901	1011	/* Process Unlocked */
mbed_official	87:085cde657901	1012	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1013
mbed_official	87:085cde657901	1014	/* Note : The SPI must be enabled after unlocking current process
mbed_official	87:085cde657901	1015	to avoid the risk of SPI interrupt handle execution before current
mbed_official	87:085cde657901	1016	process unlock */
mbed_official	87:085cde657901	1017
mbed_official	87:085cde657901	1018	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1019	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1020	{
mbed_official	87:085cde657901	1021	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1022	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1023	}
mbed_official	87:085cde657901	1024
mbed_official	87:085cde657901	1025	return HAL_OK;
mbed_official	87:085cde657901	1026	}
mbed_official	87:085cde657901	1027	else
mbed_official	87:085cde657901	1028	{
mbed_official	87:085cde657901	1029	return HAL_BUSY;
mbed_official	87:085cde657901	1030	}
mbed_official	87:085cde657901	1031	}
mbed_official	87:085cde657901	1032
mbed_official	87:085cde657901	1033	/**
mbed_official	87:085cde657901	1034	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	226:b062af740e40	1035	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1036	* the configuration information for SPI module.
mbed_official	87:085cde657901	1037	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1038	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	1039	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1040	* @retval HAL status
mbed_official	87:085cde657901	1041	*/
mbed_official	87:085cde657901	1042	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1043	{
mbed_official	87:085cde657901	1044	uint32_t tmp = 0;
mbed_official	87:085cde657901	1045
mbed_official	87:085cde657901	1046	tmp = hspi->State;
mbed_official	87:085cde657901	1047	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	1048	{
mbed_official	87:085cde657901	1049	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1050	{
mbed_official	87:085cde657901	1051	return HAL_ERROR;
mbed_official	87:085cde657901	1052	}
mbed_official	87:085cde657901	1053
mbed_official	87:085cde657901	1054	/* Check the parameters */
mbed_official	87:085cde657901	1055	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1056
mbed_official	87:085cde657901	1057	/* Process locked */
mbed_official	87:085cde657901	1058	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1059
mbed_official	87:085cde657901	1060	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	1061	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1062	{
mbed_official	106:ced8cbb51063	1063	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1064	}
mbed_official	87:085cde657901	1065
mbed_official	87:085cde657901	1066	/* Configure communication */
mbed_official	87:085cde657901	1067	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1068
mbed_official	87:085cde657901	1069	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	1070	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	1071	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1072	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1073
mbed_official	87:085cde657901	1074	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	87:085cde657901	1075	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	1076	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1077	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1078
mbed_official	87:085cde657901	1079	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1080	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1081	{
mbed_official	87:085cde657901	1082	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1083	}
mbed_official	87:085cde657901	1084
mbed_official	87:085cde657901	1085	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	87:085cde657901	1086	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1087
mbed_official	87:085cde657901	1088	/* Process Unlocked */
mbed_official	87:085cde657901	1089	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1090
mbed_official	87:085cde657901	1091	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1092	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1093	{
mbed_official	87:085cde657901	1094	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1095	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1096	}
mbed_official	87:085cde657901	1097
mbed_official	87:085cde657901	1098	return HAL_OK;
mbed_official	87:085cde657901	1099	}
mbed_official	87:085cde657901	1100	else
mbed_official	87:085cde657901	1101	{
mbed_official	87:085cde657901	1102	return HAL_BUSY;
mbed_official	87:085cde657901	1103	}
mbed_official	87:085cde657901	1104	}
mbed_official	87:085cde657901	1105
mbed_official	87:085cde657901	1106	/**
mbed_official	87:085cde657901	1107	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	226:b062af740e40	1108	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1109	* the configuration information for SPI module.
mbed_official	87:085cde657901	1110	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1111	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1112	* @retval HAL status
mbed_official	87:085cde657901	1113	*/
mbed_official	87:085cde657901	1114	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1115	{
mbed_official	87:085cde657901	1116	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1117	{
mbed_official	87:085cde657901	1118	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1119	{
mbed_official	87:085cde657901	1120	return HAL_ERROR;
mbed_official	87:085cde657901	1121	}
mbed_official	87:085cde657901	1122
mbed_official	87:085cde657901	1123	/* Check the parameters */
mbed_official	87:085cde657901	1124	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	1125
mbed_official	87:085cde657901	1126	/* Process Locked */
mbed_official	87:085cde657901	1127	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1128
mbed_official	87:085cde657901	1129	/* Configure communication */
mbed_official	87:085cde657901	1130	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	1131	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1132
mbed_official	87:085cde657901	1133	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	1134	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1135	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1136
mbed_official	87:085cde657901	1137	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1138	hspi->TxISR = 0;
mbed_official	87:085cde657901	1139	hspi->RxISR = 0;
mbed_official	87:085cde657901	1140	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	1141	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1142
mbed_official	87:085cde657901	1143	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1144	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1145	{
mbed_official	87:085cde657901	1146	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	1147	}
mbed_official	87:085cde657901	1148
mbed_official	87:085cde657901	1149	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1150	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1151	{
mbed_official	87:085cde657901	1152	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1153	}
mbed_official	87:085cde657901	1154
mbed_official	87:085cde657901	1155	/* Set the SPI TxDMA transfer complete callback */
mbed_official	87:085cde657901	1156	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	87:085cde657901	1157
mbed_official	87:085cde657901	1158	/* Set the DMA error callback */
mbed_official	87:085cde657901	1159	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1160
mbed_official	87:085cde657901	1161	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1162	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1163
mbed_official	87:085cde657901	1164	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1165	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1166
mbed_official	87:085cde657901	1167	/* Process Unlocked */
mbed_official	87:085cde657901	1168	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1169
mbed_official	87:085cde657901	1170	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1171	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1172	{
mbed_official	87:085cde657901	1173	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1174	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1175	}
mbed_official	87:085cde657901	1176
mbed_official	87:085cde657901	1177	return HAL_OK;
mbed_official	87:085cde657901	1178	}
mbed_official	87:085cde657901	1179	else
mbed_official	87:085cde657901	1180	{
mbed_official	87:085cde657901	1181	return HAL_BUSY;
mbed_official	87:085cde657901	1182	}
mbed_official	87:085cde657901	1183	}
mbed_official	87:085cde657901	1184
mbed_official	87:085cde657901	1185	/**
mbed_official	87:085cde657901	1186	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	226:b062af740e40	1187	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1188	* the configuration information for SPI module.
mbed_official	87:085cde657901	1189	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1190	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	87:085cde657901	1191	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1192	* @retval HAL status
mbed_official	87:085cde657901	1193	*/
mbed_official	87:085cde657901	1194	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1195	{
mbed_official	87:085cde657901	1196	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1197	{
mbed_official	87:085cde657901	1198	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1199	{
mbed_official	87:085cde657901	1200	return HAL_ERROR;
mbed_official	87:085cde657901	1201	}
mbed_official	87:085cde657901	1202
mbed_official	87:085cde657901	1203	/* Process Locked */
mbed_official	87:085cde657901	1204	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1205
mbed_official	87:085cde657901	1206	/* Configure communication */
mbed_official	87:085cde657901	1207	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	1208	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1209
mbed_official	87:085cde657901	1210	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	1211	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1212	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1213
mbed_official	87:085cde657901	1214	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1215	hspi->RxISR = 0;
mbed_official	87:085cde657901	1216	hspi->TxISR = 0;
mbed_official	87:085cde657901	1217	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	1218	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1219
mbed_official	87:085cde657901	1220	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1221	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1222	{
mbed_official	87:085cde657901	1223	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	1224	}
mbed_official	87:085cde657901	1225	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	1226	{
mbed_official	87:085cde657901	1227	/* Process Unlocked */
mbed_official	87:085cde657901	1228	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1229
mbed_official	87:085cde657901	1230	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	1231	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	87:085cde657901	1232	}
mbed_official	87:085cde657901	1233
mbed_official	87:085cde657901	1234	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1235	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1236	{
mbed_official	87:085cde657901	1237	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1238	}
mbed_official	87:085cde657901	1239
mbed_official	87:085cde657901	1240	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	87:085cde657901	1241	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	87:085cde657901	1242
mbed_official	87:085cde657901	1243	/* Set the DMA error callback */
mbed_official	87:085cde657901	1244	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1245
mbed_official	87:085cde657901	1246	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1247	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1248
mbed_official	87:085cde657901	1249	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1250	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1251
mbed_official	87:085cde657901	1252	/* Process Unlocked */
mbed_official	87:085cde657901	1253	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1254
mbed_official	87:085cde657901	1255	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1256	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1257	{
mbed_official	87:085cde657901	1258	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1259	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1260	}
mbed_official	87:085cde657901	1261
mbed_official	87:085cde657901	1262	return HAL_OK;
mbed_official	87:085cde657901	1263	}
mbed_official	87:085cde657901	1264	else
mbed_official	87:085cde657901	1265	{
mbed_official	87:085cde657901	1266	return HAL_BUSY;
mbed_official	87:085cde657901	1267	}
mbed_official	87:085cde657901	1268	}
mbed_official	87:085cde657901	1269
mbed_official	87:085cde657901	1270	/**
mbed_official	87:085cde657901	1271	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	226:b062af740e40	1272	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1273	* the configuration information for SPI module.
mbed_official	87:085cde657901	1274	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1275	* @param pRxData: pointer to reception data buffer
mbed_official	87:085cde657901	1276	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	87:085cde657901	1277	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1278	* @retval HAL status
mbed_official	87:085cde657901	1279	*/
mbed_official	87:085cde657901	1280	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1281	{
mbed_official	87:085cde657901	1282	uint32_t tmpstate = 0;
mbed_official	87:085cde657901	1283	tmpstate = hspi->State;
mbed_official	87:085cde657901	1284	if((tmpstate == HAL_SPI_STATE_READY) \|\| (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	1285	{
mbed_official	87:085cde657901	1286	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1287	{
mbed_official	87:085cde657901	1288	return HAL_ERROR;
mbed_official	87:085cde657901	1289	}
mbed_official	87:085cde657901	1290
mbed_official	87:085cde657901	1291	/* Check the parameters */
mbed_official	87:085cde657901	1292	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1293
mbed_official	87:085cde657901	1294	/* Process locked */
mbed_official	87:085cde657901	1295	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1296
mbed_official	87:085cde657901	1297	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	1298	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1299	{
mbed_official	106:ced8cbb51063	1300	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1301	}
mbed_official	87:085cde657901	1302
mbed_official	87:085cde657901	1303	/* Configure communication */
mbed_official	87:085cde657901	1304	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1305
mbed_official	87:085cde657901	1306	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	87:085cde657901	1307	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1308	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1309
mbed_official	87:085cde657901	1310	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	87:085cde657901	1311	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1312	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1313
mbed_official	87:085cde657901	1314	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1315	hspi->RxISR = 0;
mbed_official	87:085cde657901	1316	hspi->TxISR = 0;
mbed_official	87:085cde657901	1317
mbed_official	87:085cde657901	1318	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1319	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1320	{
mbed_official	87:085cde657901	1321	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1322	}
mbed_official	87:085cde657901	1323
mbed_official	106:ced8cbb51063	1324	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official	106:ced8cbb51063	1325	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	106:ced8cbb51063	1326	{
mbed_official	106:ced8cbb51063	1327	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	106:ced8cbb51063	1328	}
mbed_official	106:ced8cbb51063	1329	else
mbed_official	106:ced8cbb51063	1330	{
mbed_official	106:ced8cbb51063	1331	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	106:ced8cbb51063	1332	}
mbed_official	87:085cde657901	1333
mbed_official	87:085cde657901	1334	/* Set the DMA error callback */
mbed_official	87:085cde657901	1335	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1336
mbed_official	87:085cde657901	1337	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1338	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1339
mbed_official	87:085cde657901	1340	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1341	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1342
mbed_official	87:085cde657901	1343	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	87:085cde657901	1344	is performed in DMA reception complete callback */
mbed_official	87:085cde657901	1345	hspi->hdmatx->XferCpltCallback = NULL;
mbed_official	87:085cde657901	1346
mbed_official	87:085cde657901	1347	/* Set the DMA error callback */
mbed_official	87:085cde657901	1348	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1349
mbed_official	87:085cde657901	1350	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1351	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1352
mbed_official	87:085cde657901	1353	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1354	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1355
mbed_official	87:085cde657901	1356	/* Process Unlocked */
mbed_official	87:085cde657901	1357	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1358
mbed_official	87:085cde657901	1359	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1360	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1361	{
mbed_official	87:085cde657901	1362	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1363	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1364	}
mbed_official	87:085cde657901	1365
mbed_official	87:085cde657901	1366	return HAL_OK;
mbed_official	87:085cde657901	1367	}
mbed_official	87:085cde657901	1368	else
mbed_official	87:085cde657901	1369	{
mbed_official	87:085cde657901	1370	return HAL_BUSY;
mbed_official	87:085cde657901	1371	}
mbed_official	87:085cde657901	1372	}
mbed_official	87:085cde657901	1373
mbed_official	87:085cde657901	1374	/**
mbed_official	87:085cde657901	1375	* @brief This function handles SPI interrupt request.
mbed_official	226:b062af740e40	1376	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1377	* the configuration information for SPI module.
mbed_official	87:085cde657901	1378	* @retval HAL status
mbed_official	87:085cde657901	1379	*/
mbed_official	87:085cde657901	1380	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1381	{
mbed_official	87:085cde657901	1382	uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official	87:085cde657901	1383
mbed_official	87:085cde657901	1384	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official	87:085cde657901	1385	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official	87:085cde657901	1386	tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official	87:085cde657901	1387	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	87:085cde657901	1388	if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official	87:085cde657901	1389	{
mbed_official	87:085cde657901	1390	hspi->RxISR(hspi);
mbed_official	87:085cde657901	1391	return;
mbed_official	87:085cde657901	1392	}
mbed_official	87:085cde657901	1393
mbed_official	87:085cde657901	1394	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official	87:085cde657901	1395	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official	87:085cde657901	1396	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	87:085cde657901	1397	if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official	87:085cde657901	1398	{
mbed_official	87:085cde657901	1399	hspi->TxISR(hspi);
mbed_official	87:085cde657901	1400	return;
mbed_official	87:085cde657901	1401	}
mbed_official	87:085cde657901	1402
mbed_official	87:085cde657901	1403	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	87:085cde657901	1404	{
mbed_official	226:b062af740e40	1405	/* SPI CRC error interrupt occurred ---------------------------------------*/
mbed_official	87:085cde657901	1406	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1407	{
mbed_official	87:085cde657901	1408	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1409	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1410	}
mbed_official	226:b062af740e40	1411	/* SPI Mode Fault error interrupt occurred --------------------------------*/
mbed_official	87:085cde657901	1412	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	87:085cde657901	1413	{
mbed_official	87:085cde657901	1414	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	87:085cde657901	1415	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	87:085cde657901	1416	}
mbed_official	87:085cde657901	1417
mbed_official	226:b062af740e40	1418	/* SPI Overrun error interrupt occurred -----------------------------------*/
mbed_official	87:085cde657901	1419	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	87:085cde657901	1420	{
mbed_official	87:085cde657901	1421	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	87:085cde657901	1422	{
mbed_official	87:085cde657901	1423	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	87:085cde657901	1424	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1425	}
mbed_official	87:085cde657901	1426	}
mbed_official	87:085cde657901	1427
mbed_official	226:b062af740e40	1428	/* SPI Frame error interrupt occurred -------------------------------------*/
mbed_official	87:085cde657901	1429	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	87:085cde657901	1430	{
mbed_official	87:085cde657901	1431	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	87:085cde657901	1432	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	87:085cde657901	1433	}
mbed_official	87:085cde657901	1434
mbed_official	87:085cde657901	1435	/* Call the Error call Back in case of Errors */
mbed_official	87:085cde657901	1436	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1437	{
mbed_official	87:085cde657901	1438	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1439	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1440	}
mbed_official	87:085cde657901	1441	}
mbed_official	87:085cde657901	1442	}
mbed_official	87:085cde657901	1443
mbed_official	87:085cde657901	1444	/**
mbed_official	87:085cde657901	1445	* @brief Tx Transfer completed callbacks
mbed_official	226:b062af740e40	1446	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1447	* the configuration information for SPI module.
mbed_official	87:085cde657901	1448	* @retval None
mbed_official	87:085cde657901	1449	*/
mbed_official	87:085cde657901	1450	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1451	{
mbed_official	87:085cde657901	1452	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1453	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	87:085cde657901	1454	*/
mbed_official	87:085cde657901	1455	}
mbed_official	87:085cde657901	1456
mbed_official	87:085cde657901	1457	/**
mbed_official	87:085cde657901	1458	* @brief Rx Transfer completed callbacks
mbed_official	226:b062af740e40	1459	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1460	* the configuration information for SPI module.
mbed_official	87:085cde657901	1461	* @retval None
mbed_official	87:085cde657901	1462	*/
mbed_official	87:085cde657901	1463	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1464	{
mbed_official	87:085cde657901	1465	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1466	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1467	*/
mbed_official	87:085cde657901	1468	}
mbed_official	87:085cde657901	1469
mbed_official	87:085cde657901	1470	/**
mbed_official	87:085cde657901	1471	* @brief Tx and Rx Transfer completed callbacks
mbed_official	226:b062af740e40	1472	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1473	* the configuration information for SPI module.
mbed_official	87:085cde657901	1474	* @retval None
mbed_official	87:085cde657901	1475	*/
mbed_official	87:085cde657901	1476	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1477	{
mbed_official	87:085cde657901	1478	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1479	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1480	*/
mbed_official	87:085cde657901	1481	}
mbed_official	87:085cde657901	1482
mbed_official	87:085cde657901	1483	/**
mbed_official	87:085cde657901	1484	* @brief SPI error callbacks
mbed_official	226:b062af740e40	1485	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1486	* the configuration information for SPI module.
mbed_official	87:085cde657901	1487	* @retval None
mbed_official	87:085cde657901	1488	*/
mbed_official	87:085cde657901	1489	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1490	{
mbed_official	87:085cde657901	1491	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1492	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	87:085cde657901	1493	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	226:b062af740e40	1494	and user can use HAL_SPI_GetError() API to check the latest error occurred.
mbed_official	87:085cde657901	1495	*/
mbed_official	87:085cde657901	1496	}
mbed_official	87:085cde657901	1497
mbed_official	87:085cde657901	1498	/**
mbed_official	87:085cde657901	1499	* @}
mbed_official	87:085cde657901	1500	*/
mbed_official	87:085cde657901	1501
mbed_official	87:085cde657901	1502	/** @defgroup SPI_Group3 Peripheral State and Errors functions
mbed_official	87:085cde657901	1503	* @brief SPI control functions
mbed_official	87:085cde657901	1504	*
mbed_official	87:085cde657901	1505	@verbatim
mbed_official	87:085cde657901	1506	===============================================================================
mbed_official	87:085cde657901	1507	##### Peripheral State and Errors functions #####
mbed_official	87:085cde657901	1508	===============================================================================
mbed_official	87:085cde657901	1509	[..]
mbed_official	87:085cde657901	1510	This subsection provides a set of functions allowing to control the SPI.
mbed_official	87:085cde657901	1511	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	87:085cde657901	1512	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	87:085cde657901	1513	@endverbatim
mbed_official	87:085cde657901	1514	* @{
mbed_official	87:085cde657901	1515	*/
mbed_official	87:085cde657901	1516
mbed_official	87:085cde657901	1517	/**
mbed_official	87:085cde657901	1518	* @brief Return the SPI state
mbed_official	226:b062af740e40	1519	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1520	* the configuration information for SPI module.
mbed_official	226:b062af740e40	1521	* @retval HAL state
mbed_official	87:085cde657901	1522	*/
mbed_official	87:085cde657901	1523	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1524	{
mbed_official	87:085cde657901	1525	return hspi->State;
mbed_official	87:085cde657901	1526	}
mbed_official	87:085cde657901	1527
mbed_official	87:085cde657901	1528	/**
mbed_official	87:085cde657901	1529	* @brief Return the SPI error code
mbed_official	226:b062af740e40	1530	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1531	* the configuration information for SPI module.
mbed_official	87:085cde657901	1532	* @retval SPI Error Code
mbed_official	87:085cde657901	1533	*/
mbed_official	87:085cde657901	1534	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1535	{
mbed_official	87:085cde657901	1536	return hspi->ErrorCode;
mbed_official	87:085cde657901	1537	}
mbed_official	87:085cde657901	1538
mbed_official	87:085cde657901	1539	/**
mbed_official	87:085cde657901	1540	* @}
mbed_official	87:085cde657901	1541	*/
mbed_official	87:085cde657901	1542
mbed_official	87:085cde657901	1543	/**
mbed_official	87:085cde657901	1544	* @brief Interrupt Handler to close Tx transfer
mbed_official	226:b062af740e40	1545	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1546	* the configuration information for SPI module.
mbed_official	87:085cde657901	1547	* @retval void
mbed_official	87:085cde657901	1548	*/
mbed_official	87:085cde657901	1549	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1550	{
mbed_official	106:ced8cbb51063	1551	/* Wait until TXE flag is set to send data */
mbed_official	106:ced8cbb51063	1552	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1553	{
mbed_official	106:ced8cbb51063	1554	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1555	}
mbed_official	87:085cde657901	1556
mbed_official	87:085cde657901	1557	/* Disable TXE interrupt */
mbed_official	87:085cde657901	1558	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
mbed_official	87:085cde657901	1559
mbed_official	87:085cde657901	1560	/* Disable ERR interrupt if Receive process is finished */
mbed_official	87:085cde657901	1561	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	87:085cde657901	1562	{
mbed_official	87:085cde657901	1563	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1564
mbed_official	87:085cde657901	1565	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1566	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1567	{
mbed_official	87:085cde657901	1568	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1569	}
mbed_official	87:085cde657901	1570
mbed_official	87:085cde657901	1571	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1572	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1573	{
mbed_official	87:085cde657901	1574	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1575	}
mbed_official	87:085cde657901	1576
mbed_official	87:085cde657901	1577	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1578	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1579	{
mbed_official	87:085cde657901	1580	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1581	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1582	{
mbed_official	106:ced8cbb51063	1583	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1584	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1585	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1586	}
mbed_official	87:085cde657901	1587	else
mbed_official	87:085cde657901	1588	{
mbed_official	106:ced8cbb51063	1589	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1590	hspi->State = HAL_SPI_STATE_READY;
mbed_official	106:ced8cbb51063	1591	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1592	}
mbed_official	87:085cde657901	1593	}
mbed_official	87:085cde657901	1594	else
mbed_official	87:085cde657901	1595	{
mbed_official	106:ced8cbb51063	1596	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1597	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1598	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1599	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1600	}
mbed_official	87:085cde657901	1601	}
mbed_official	87:085cde657901	1602	}
mbed_official	87:085cde657901	1603
mbed_official	87:085cde657901	1604	/**
mbed_official	87:085cde657901	1605	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	226:b062af740e40	1606	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1607	* the configuration information for SPI module.
mbed_official	87:085cde657901	1608	* @retval void
mbed_official	87:085cde657901	1609	*/
mbed_official	87:085cde657901	1610	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1611	{
mbed_official	87:085cde657901	1612	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	1613	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1614	{
mbed_official	87:085cde657901	1615	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	1616	}
mbed_official	87:085cde657901	1617	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	1618	else
mbed_official	87:085cde657901	1619	{
mbed_official	87:085cde657901	1620	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	1621	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	1622	}
mbed_official	87:085cde657901	1623	hspi->TxXferCount--;
mbed_official	87:085cde657901	1624
mbed_official	87:085cde657901	1625	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	1626	{
mbed_official	87:085cde657901	1627	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1628	{
mbed_official	87:085cde657901	1629	/* calculate and transfer CRC on Tx line */
mbed_official	87:085cde657901	1630	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1631	}
mbed_official	87:085cde657901	1632	SPI_TxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1633	}
mbed_official	87:085cde657901	1634	}
mbed_official	87:085cde657901	1635
mbed_official	87:085cde657901	1636	/**
mbed_official	87:085cde657901	1637	* @brief Interrupt Handler to close Rx transfer
mbed_official	226:b062af740e40	1638	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1639	* the configuration information for SPI module.
mbed_official	87:085cde657901	1640	* @retval void
mbed_official	87:085cde657901	1641	*/
mbed_official	106:ced8cbb51063	1642	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1643	{
mbed_official	87:085cde657901	1644	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1645
mbed_official	87:085cde657901	1646	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1647	{
mbed_official	87:085cde657901	1648	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1649	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1650	{
mbed_official	87:085cde657901	1651	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1652	}
mbed_official	87:085cde657901	1653
mbed_official	87:085cde657901	1654	/* Read CRC to reset RXNE flag */
mbed_official	87:085cde657901	1655	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1656
mbed_official	87:085cde657901	1657	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1658	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1659	{
mbed_official	87:085cde657901	1660	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1661	}
mbed_official	87:085cde657901	1662
mbed_official	87:085cde657901	1663	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1664	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1665	{
mbed_official	87:085cde657901	1666	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1667
mbed_official	87:085cde657901	1668	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1669	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1670	}
mbed_official	87:085cde657901	1671	}
mbed_official	87:085cde657901	1672
mbed_official	87:085cde657901	1673	/* Disable RXNE and ERR interrupt */
mbed_official	87:085cde657901	1674	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official	87:085cde657901	1675
mbed_official	87:085cde657901	1676	/* if Transmit process is finished */
mbed_official	87:085cde657901	1677	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	87:085cde657901	1678	{
mbed_official	87:085cde657901	1679	/* Disable ERR interrupt */
mbed_official	87:085cde657901	1680	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1681
mbed_official	87:085cde657901	1682	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1683	{
mbed_official	87:085cde657901	1684	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1685	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1686	}
mbed_official	87:085cde657901	1687
mbed_official	87:085cde657901	1688	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1689	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1690	{
mbed_official	87:085cde657901	1691	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1692	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1693	{
mbed_official	106:ced8cbb51063	1694	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1695	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1696	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1697	}else
mbed_official	87:085cde657901	1698	{
mbed_official	106:ced8cbb51063	1699	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1700	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1701	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1702	}
mbed_official	87:085cde657901	1703	}
mbed_official	87:085cde657901	1704	else
mbed_official	87:085cde657901	1705	{
mbed_official	106:ced8cbb51063	1706	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1707	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1708	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1709	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1710	}
mbed_official	87:085cde657901	1711	}
mbed_official	87:085cde657901	1712	}
mbed_official	87:085cde657901	1713
mbed_official	87:085cde657901	1714	/**
mbed_official	87:085cde657901	1715	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	226:b062af740e40	1716	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1717	* the configuration information for SPI module.
mbed_official	87:085cde657901	1718	* @retval void
mbed_official	87:085cde657901	1719	*/
mbed_official	87:085cde657901	1720	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1721	{
mbed_official	87:085cde657901	1722	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1723	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1724	{
mbed_official	87:085cde657901	1725	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1726	}
mbed_official	87:085cde657901	1727	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1728	else
mbed_official	87:085cde657901	1729	{
mbed_official	87:085cde657901	1730	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1731	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1732	}
mbed_official	87:085cde657901	1733	hspi->RxXferCount--;
mbed_official	87:085cde657901	1734
mbed_official	87:085cde657901	1735	if(hspi->RxXferCount==0)
mbed_official	87:085cde657901	1736	{
mbed_official	106:ced8cbb51063	1737	SPI_RxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1738	}
mbed_official	87:085cde657901	1739	}
mbed_official	87:085cde657901	1740
mbed_official	87:085cde657901	1741	/**
mbed_official	87:085cde657901	1742	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	226:b062af740e40	1743	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1744	* the configuration information for SPI module.
mbed_official	87:085cde657901	1745	* @retval void
mbed_official	87:085cde657901	1746	*/
mbed_official	87:085cde657901	1747	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1748	{
mbed_official	87:085cde657901	1749	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1750	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1751	{
mbed_official	87:085cde657901	1752	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1753	}
mbed_official	87:085cde657901	1754	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1755	else
mbed_official	87:085cde657901	1756	{
mbed_official	87:085cde657901	1757	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1758	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1759	}
mbed_official	87:085cde657901	1760	hspi->RxXferCount--;
mbed_official	87:085cde657901	1761
mbed_official	87:085cde657901	1762	/* Enable CRC Transmission */
mbed_official	87:085cde657901	1763	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	1764	{
mbed_official	87:085cde657901	1765	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	87:085cde657901	1766	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1767	}
mbed_official	87:085cde657901	1768
mbed_official	87:085cde657901	1769	if(hspi->RxXferCount == 0)
mbed_official	87:085cde657901	1770	{
mbed_official	106:ced8cbb51063	1771	SPI_RxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1772	}
mbed_official	87:085cde657901	1773	}
mbed_official	87:085cde657901	1774
mbed_official	87:085cde657901	1775	/**
mbed_official	87:085cde657901	1776	* @brief DMA SPI transmit process complete callback
mbed_official	226:b062af740e40	1777	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1778	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	1779	* @retval None
mbed_official	87:085cde657901	1780	*/
mbed_official	87:085cde657901	1781	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1782	{
mbed_official	87:085cde657901	1783	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1784
mbed_official	87:085cde657901	1785	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1786	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1787	{
mbed_official	87:085cde657901	1788	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1789	}
mbed_official	87:085cde657901	1790
mbed_official	87:085cde657901	1791	/* Disable Tx DMA Request */
mbed_official	87:085cde657901	1792	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1793
mbed_official	87:085cde657901	1794	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1795	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1796	{
mbed_official	87:085cde657901	1797	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1798	}
mbed_official	87:085cde657901	1799
mbed_official	87:085cde657901	1800	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1801
mbed_official	87:085cde657901	1802	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1803
mbed_official	87:085cde657901	1804	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1805	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1806	{
mbed_official	87:085cde657901	1807	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1808	}
mbed_official	87:085cde657901	1809
mbed_official	87:085cde657901	1810	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1811	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1812	{
mbed_official	87:085cde657901	1813	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1814	}
mbed_official	87:085cde657901	1815	else
mbed_official	87:085cde657901	1816	{
mbed_official	87:085cde657901	1817	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1818	}
mbed_official	87:085cde657901	1819	}
mbed_official	87:085cde657901	1820
mbed_official	87:085cde657901	1821	/**
mbed_official	87:085cde657901	1822	* @brief DMA SPI receive process complete callback
mbed_official	226:b062af740e40	1823	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1824	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	1825	* @retval None
mbed_official	87:085cde657901	1826	*/
mbed_official	87:085cde657901	1827	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1828	{
mbed_official	87:085cde657901	1829	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1830
mbed_official	87:085cde657901	1831	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1832
mbed_official	87:085cde657901	1833	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1834	{
mbed_official	87:085cde657901	1835	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1836	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1837	}
mbed_official	87:085cde657901	1838
mbed_official	87:085cde657901	1839	/* Disable Rx DMA Request */
mbed_official	87:085cde657901	1840	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	87:085cde657901	1841
mbed_official	87:085cde657901	1842	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1843	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1844	{
mbed_official	87:085cde657901	1845	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1846	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1847	{
mbed_official	87:085cde657901	1848	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1849	}
mbed_official	87:085cde657901	1850
mbed_official	87:085cde657901	1851	/* Read CRC */
mbed_official	87:085cde657901	1852	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1853
mbed_official	87:085cde657901	1854	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1855	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1856	{
mbed_official	87:085cde657901	1857	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1858	}
mbed_official	87:085cde657901	1859	}
mbed_official	87:085cde657901	1860
mbed_official	87:085cde657901	1861	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1862	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1863
mbed_official	87:085cde657901	1864	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1865	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1866	{
mbed_official	87:085cde657901	1867	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1868	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1869	}
mbed_official	87:085cde657901	1870
mbed_official	87:085cde657901	1871	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1872	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1873	{
mbed_official	87:085cde657901	1874	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1875	}
mbed_official	87:085cde657901	1876	else
mbed_official	87:085cde657901	1877	{
mbed_official	87:085cde657901	1878	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1879	}
mbed_official	87:085cde657901	1880	}
mbed_official	87:085cde657901	1881
mbed_official	87:085cde657901	1882	/**
mbed_official	87:085cde657901	1883	* @brief DMA SPI transmit receive process complete callback
mbed_official	226:b062af740e40	1884	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1885	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	1886	* @retval None
mbed_official	87:085cde657901	1887	*/
mbed_official	87:085cde657901	1888	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1889	{
mbed_official	87:085cde657901	1890	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1891
mbed_official	87:085cde657901	1892	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1893
mbed_official	87:085cde657901	1894	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1895	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1896	{
mbed_official	87:085cde657901	1897	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	87:085cde657901	1898	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	87:085cde657901	1899	{
mbed_official	87:085cde657901	1900	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1901	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1902	{
mbed_official	87:085cde657901	1903	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1904	}
mbed_official	87:085cde657901	1905	}
mbed_official	87:085cde657901	1906	/* Read CRC */
mbed_official	87:085cde657901	1907	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1908	}
mbed_official	87:085cde657901	1909
mbed_official	87:085cde657901	1910	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1911	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1912	{
mbed_official	87:085cde657901	1913	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1914	}
mbed_official	87:085cde657901	1915	/* Disable Tx DMA Request */
mbed_official	87:085cde657901	1916	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1917
mbed_official	87:085cde657901	1918	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1919	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1920	{
mbed_official	87:085cde657901	1921	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1922	}
mbed_official	87:085cde657901	1923
mbed_official	87:085cde657901	1924	/* Disable Rx DMA Request */
mbed_official	87:085cde657901	1925	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	87:085cde657901	1926
mbed_official	87:085cde657901	1927	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1928	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1929
mbed_official	87:085cde657901	1930	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1931
mbed_official	87:085cde657901	1932	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1933	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1934	{
mbed_official	87:085cde657901	1935	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1936	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1937	}
mbed_official	87:085cde657901	1938
mbed_official	87:085cde657901	1939	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1940	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1941	{
mbed_official	87:085cde657901	1942	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1943	}
mbed_official	87:085cde657901	1944	else
mbed_official	87:085cde657901	1945	{
mbed_official	87:085cde657901	1946	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1947	}
mbed_official	87:085cde657901	1948	}
mbed_official	87:085cde657901	1949
mbed_official	87:085cde657901	1950	/**
mbed_official	87:085cde657901	1951	* @brief DMA SPI communication error callback
mbed_official	226:b062af740e40	1952	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1953	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	1954	* @retval None
mbed_official	87:085cde657901	1955	*/
mbed_official	87:085cde657901	1956	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1957	{
mbed_official	87:085cde657901	1958	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1959	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1960	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1961	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1962	hspi->ErrorCode \|= HAL_SPI_ERROR_DMA;
mbed_official	87:085cde657901	1963	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1964	}
mbed_official	87:085cde657901	1965
mbed_official	87:085cde657901	1966	/**
mbed_official	87:085cde657901	1967	* @brief This function handles SPI Communication Timeout.
mbed_official	226:b062af740e40	1968	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1969	* the configuration information for SPI module.
mbed_official	87:085cde657901	1970	* @retval HAL status
mbed_official	87:085cde657901	1971	*/
mbed_official	87:085cde657901	1972	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	87:085cde657901	1973	{
mbed_official	87:085cde657901	1974	uint32_t timeout = 0;
mbed_official	87:085cde657901	1975
mbed_official	87:085cde657901	1976	timeout = HAL_GetTick() + Timeout;
mbed_official	87:085cde657901	1977
mbed_official	87:085cde657901	1978	/* Wait until flag is set */
mbed_official	87:085cde657901	1979	if(Status == RESET)
mbed_official	87:085cde657901	1980	{
mbed_official	87:085cde657901	1981	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	87:085cde657901	1982	{
mbed_official	87:085cde657901	1983	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	1984	{
mbed_official	87:085cde657901	1985	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	1986	{
mbed_official	87:085cde657901	1987	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	1988	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	1989	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	1990
mbed_official	87:085cde657901	1991	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	1992	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1993
mbed_official	87:085cde657901	1994	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1995	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1996
mbed_official	87:085cde657901	1997	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1998	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1999	{
mbed_official	87:085cde657901	2000	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	2001	}
mbed_official	87:085cde657901	2002
mbed_official	87:085cde657901	2003	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	2004
mbed_official	87:085cde657901	2005	/* Process Unlocked */
mbed_official	87:085cde657901	2006	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	2007
mbed_official	87:085cde657901	2008	return HAL_TIMEOUT;
mbed_official	87:085cde657901	2009	}
mbed_official	87:085cde657901	2010	}
mbed_official	87:085cde657901	2011	}
mbed_official	87:085cde657901	2012	}
mbed_official	87:085cde657901	2013	else
mbed_official	87:085cde657901	2014	{
mbed_official	87:085cde657901	2015	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	87:085cde657901	2016	{
mbed_official	87:085cde657901	2017	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	2018	{
mbed_official	87:085cde657901	2019	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	2020	{
mbed_official	87:085cde657901	2021	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	2022	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	2023	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	2024
mbed_official	87:085cde657901	2025	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	2026	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	2027
mbed_official	87:085cde657901	2028	/* Disable SPI peripheral */
mbed_official	87:085cde657901	2029	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	2030
mbed_official	87:085cde657901	2031	/* Reset CRC Calculation */
mbed_official	87:085cde657901	2032	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	2033	{
mbed_official	87:085cde657901	2034	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	2035	}
mbed_official	87:085cde657901	2036
mbed_official	87:085cde657901	2037	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	2038
mbed_official	87:085cde657901	2039	/* Process Unlocked */
mbed_official	87:085cde657901	2040	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	2041
mbed_official	87:085cde657901	2042	return HAL_TIMEOUT;
mbed_official	87:085cde657901	2043	}
mbed_official	87:085cde657901	2044	}
mbed_official	87:085cde657901	2045	}
mbed_official	87:085cde657901	2046	}
mbed_official	87:085cde657901	2047	return HAL_OK;
mbed_official	87:085cde657901	2048	}
mbed_official	87:085cde657901	2049
mbed_official	87:085cde657901	2050
mbed_official	87:085cde657901	2051	/**
mbed_official	87:085cde657901	2052	* @}
mbed_official	87:085cde657901	2053	*/
mbed_official	87:085cde657901	2054
mbed_official	87:085cde657901	2055	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	87:085cde657901	2056	/**
mbed_official	87:085cde657901	2057	* @}
mbed_official	87:085cde657901	2058	*/
mbed_official	87:085cde657901	2059
mbed_official	87:085cde657901	2060	/**
mbed_official	87:085cde657901	2061	* @}
mbed_official	87:085cde657901	2062	*/
mbed_official	87:085cde657901	2063
mbed_official	87:085cde657901	2064	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	09 Aug 2015
Imports:	2
Forks:	0
Commits:	604
Dependents:	0
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@226:b062af740e40, 2014-06-11 (annotated)

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