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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@87:085cde657901, 2014-02-08 (annotated)

Committer:: mbed_official
Date:: Sat Feb 08 19:45:06 2014 +0000
Revision:: 87:085cde657901
Child:: 106:ced8cbb51063

Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2

Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/

Add NUCLEO_F401RE, improvements

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_spi.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	87:085cde657901	5	* @version V1.0.0RC2
mbed_official	87:085cde657901	6	* @date 04-February-2014
mbed_official	87:085cde657901	7	* @brief SPI HAL module driver.
mbed_official	87:085cde657901	8	*
mbed_official	87:085cde657901	9	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	87:085cde657901	11	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	12	* + IO operation functions
mbed_official	87:085cde657901	13	* + Peripheral Control functions
mbed_official	87:085cde657901	14	* + Peripheral State functions
mbed_official	87:085cde657901	15	@verbatim
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	##### How to use this driver #####
mbed_official	87:085cde657901	18	==============================================================================
mbed_official	87:085cde657901	19	[..]
mbed_official	87:085cde657901	20	The SPI HAL driver can be used as follows:
mbed_official	87:085cde657901	21
mbed_official	87:085cde657901	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	87:085cde657901	23	SPI_HandleTypeDef hspi;
mbed_official	87:085cde657901	24
mbed_official	87:085cde657901	25	(#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official	87:085cde657901	26	(##) Enable the SPIx interface clock
mbed_official	87:085cde657901	27	(##) SPI pins configuration
mbed_official	87:085cde657901	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	87:085cde657901	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	87:085cde657901	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	87:085cde657901	31	(+++) Configure the SPIx interrupt priority
mbed_official	87:085cde657901	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	87:085cde657901	33	(##) DMA Configuration if you need to use DMA process
mbed_official	87:085cde657901	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official	87:085cde657901	35	(+++) Enable the DMAx interface clock using
mbed_official	87:085cde657901	36	(+++) Configure the DMA handle parameters
mbed_official	87:085cde657901	37	(+++) Configure the DMA Tx or Rx Stream
mbed_official	87:085cde657901	38	(+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	87:085cde657901	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official	87:085cde657901	40
mbed_official	87:085cde657901	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	87:085cde657901	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	87:085cde657901	43
mbed_official	87:085cde657901	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	87:085cde657901	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	87:085cde657901	46	by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	@endverbatim
mbed_official	87:085cde657901	49	******************************************************************************
mbed_official	87:085cde657901	50	* @attention
mbed_official	87:085cde657901	51	*
mbed_official	87:085cde657901	52	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	53	*
mbed_official	87:085cde657901	54	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	55	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	56	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	57	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	58	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	59	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	60	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	61	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	62	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	63	* without specific prior written permission.
mbed_official	87:085cde657901	64	*
mbed_official	87:085cde657901	65	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	66	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	67	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	68	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	69	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	70	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	71	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	72	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	73	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	74	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	75	*
mbed_official	87:085cde657901	76	******************************************************************************
mbed_official	87:085cde657901	77	*/
mbed_official	87:085cde657901	78
mbed_official	87:085cde657901	79	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	80	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	81
mbed_official	87:085cde657901	82	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	83	* @{
mbed_official	87:085cde657901	84	*/
mbed_official	87:085cde657901	85
mbed_official	87:085cde657901	86	/** @defgroup SPI
mbed_official	87:085cde657901	87	* @brief SPI HAL module driver
mbed_official	87:085cde657901	88	* @{
mbed_official	87:085cde657901	89	*/
mbed_official	87:085cde657901	90
mbed_official	87:085cde657901	91	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	87:085cde657901	92
mbed_official	87:085cde657901	93	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	94	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	95	#define SPI_TIMEOUT_VALUE 10
mbed_official	87:085cde657901	96	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	97	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	98	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	99	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	100	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	101	static void SPI_RxClose_IRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	102	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	103	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	104	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	105	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	106	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	107	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	108	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	87:085cde657901	109
mbed_official	87:085cde657901	110	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	111
mbed_official	87:085cde657901	112	/** @defgroup SPI_Private_Functions
mbed_official	87:085cde657901	113	* @{
mbed_official	87:085cde657901	114	*/
mbed_official	87:085cde657901	115
mbed_official	87:085cde657901	116	/** @defgroup SPI_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	117	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	118	*
mbed_official	87:085cde657901	119	@verbatim
mbed_official	87:085cde657901	120	===============================================================================
mbed_official	87:085cde657901	121	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	122	===============================================================================
mbed_official	87:085cde657901	123	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	87:085cde657901	124	de-initialiaze the SPIx peripheral:
mbed_official	87:085cde657901	125
mbed_official	87:085cde657901	126	(+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official	87:085cde657901	127	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	87:085cde657901	128
mbed_official	87:085cde657901	129	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	87:085cde657901	130	the selected configuration:
mbed_official	87:085cde657901	131	(++) Mode
mbed_official	87:085cde657901	132	(++) Direction
mbed_official	87:085cde657901	133	(++) Data Size
mbed_official	87:085cde657901	134	(++) Clock Polarity and Phase
mbed_official	87:085cde657901	135	(++) NSS Management
mbed_official	87:085cde657901	136	(++) BaudRate Prescaler
mbed_official	87:085cde657901	137	(++) FirstBit
mbed_official	87:085cde657901	138	(++) TIMode
mbed_official	87:085cde657901	139	(++) CRC Calculation
mbed_official	87:085cde657901	140	(++) CRC Polynomial if CRC enabled
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	87:085cde657901	143	of the selected SPIx periperal.
mbed_official	87:085cde657901	144
mbed_official	87:085cde657901	145	@endverbatim
mbed_official	87:085cde657901	146	* @{
mbed_official	87:085cde657901	147	*/
mbed_official	87:085cde657901	148
mbed_official	87:085cde657901	149	/**
mbed_official	87:085cde657901	150	* @brief Initializes the SPI according to the specified parameters
mbed_official	87:085cde657901	151	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	87:085cde657901	152	* @param hspi: SPI handle
mbed_official	87:085cde657901	153	* @retval HAL status
mbed_official	87:085cde657901	154	*/
mbed_official	87:085cde657901	155	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	156	{
mbed_official	87:085cde657901	157	/* Check the SPI handle allocation */
mbed_official	87:085cde657901	158	if(hspi == NULL)
mbed_official	87:085cde657901	159	{
mbed_official	87:085cde657901	160	return HAL_ERROR;
mbed_official	87:085cde657901	161	}
mbed_official	87:085cde657901	162
mbed_official	87:085cde657901	163	/* Check the parameters */
mbed_official	87:085cde657901	164	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	87:085cde657901	165	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	87:085cde657901	166	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	87:085cde657901	167	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	87:085cde657901	168	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	87:085cde657901	169	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	87:085cde657901	170	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	87:085cde657901	171	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	87:085cde657901	172	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	87:085cde657901	173	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	87:085cde657901	174	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	87:085cde657901	175
mbed_official	87:085cde657901	176	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	87:085cde657901	177	{
mbed_official	87:085cde657901	178	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	179	HAL_SPI_MspInit(hspi);
mbed_official	87:085cde657901	180	}
mbed_official	87:085cde657901	181
mbed_official	87:085cde657901	182	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	87:085cde657901	183
mbed_official	87:085cde657901	184	/* Disble the selected SPI peripheral */
mbed_official	87:085cde657901	185	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	186
mbed_official	87:085cde657901	187	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	87:085cde657901	188	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	87:085cde657901	189	Communication speed, First bit and CRC calculation state */
mbed_official	87:085cde657901	190	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	87:085cde657901	191	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	87:085cde657901	192	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	87:085cde657901	193
mbed_official	87:085cde657901	194	/* Configure : NSS management */
mbed_official	87:085cde657901	195	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode);
mbed_official	87:085cde657901	196
mbed_official	87:085cde657901	197	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	87:085cde657901	198	/* Configure : CRC Polynomial */
mbed_official	87:085cde657901	199	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	87:085cde657901	200
mbed_official	87:085cde657901	201	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	87:085cde657901	202	hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official	87:085cde657901	203
mbed_official	87:085cde657901	204	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	205	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	206
mbed_official	87:085cde657901	207	return HAL_OK;
mbed_official	87:085cde657901	208	}
mbed_official	87:085cde657901	209
mbed_official	87:085cde657901	210	/**
mbed_official	87:085cde657901	211	* @brief DeInitializes the SPI peripheral
mbed_official	87:085cde657901	212	* @param hspi: SPI handle
mbed_official	87:085cde657901	213	* @retval HAL status
mbed_official	87:085cde657901	214	*/
mbed_official	87:085cde657901	215	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	216	{
mbed_official	87:085cde657901	217	/* Check the SPI handle allocation */
mbed_official	87:085cde657901	218	if(hspi == NULL)
mbed_official	87:085cde657901	219	{
mbed_official	87:085cde657901	220	return HAL_ERROR;
mbed_official	87:085cde657901	221	}
mbed_official	87:085cde657901	222
mbed_official	87:085cde657901	223	/* Disable the SPI Peripheral Clock */
mbed_official	87:085cde657901	224	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	225
mbed_official	87:085cde657901	226	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	227	HAL_SPI_MspDeInit(hspi);
mbed_official	87:085cde657901	228
mbed_official	87:085cde657901	229	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	230	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	87:085cde657901	231
mbed_official	87:085cde657901	232	return HAL_OK;
mbed_official	87:085cde657901	233	}
mbed_official	87:085cde657901	234
mbed_official	87:085cde657901	235	/**
mbed_official	87:085cde657901	236	* @brief SPI MSP Init
mbed_official	87:085cde657901	237	* @param hspi: SPI handle
mbed_official	87:085cde657901	238	* @retval None
mbed_official	87:085cde657901	239	*/
mbed_official	87:085cde657901	240	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	241	{
mbed_official	87:085cde657901	242	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	243	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	87:085cde657901	244	*/
mbed_official	87:085cde657901	245	}
mbed_official	87:085cde657901	246
mbed_official	87:085cde657901	247	/**
mbed_official	87:085cde657901	248	* @brief SPI MSP DeInit
mbed_official	87:085cde657901	249	* @param hspi: SPI handle
mbed_official	87:085cde657901	250	* @retval None
mbed_official	87:085cde657901	251	*/
mbed_official	87:085cde657901	252	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	253	{
mbed_official	87:085cde657901	254	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	255	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	87:085cde657901	256	*/
mbed_official	87:085cde657901	257	}
mbed_official	87:085cde657901	258
mbed_official	87:085cde657901	259	/**
mbed_official	87:085cde657901	260	* @}
mbed_official	87:085cde657901	261	*/
mbed_official	87:085cde657901	262
mbed_official	87:085cde657901	263	/** @defgroup SPI_Group2 IO operation functions
mbed_official	87:085cde657901	264	* @brief Data transfers functions
mbed_official	87:085cde657901	265	*
mbed_official	87:085cde657901	266	@verbatim
mbed_official	87:085cde657901	267	==============================================================================
mbed_official	87:085cde657901	268	##### IO operation functions #####
mbed_official	87:085cde657901	269	===============================================================================
mbed_official	87:085cde657901	270	This subsection provides a set of functions allowing to manage the SPI
mbed_official	87:085cde657901	271	data transfers.
mbed_official	87:085cde657901	272
mbed_official	87:085cde657901	273	[..] The SPI supports master and slave mode :
mbed_official	87:085cde657901	274
mbed_official	87:085cde657901	275	(#) There are two mode of transfer:
mbed_official	87:085cde657901	276	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	87:085cde657901	277	The HAL status of all data processing is returned by the same function
mbed_official	87:085cde657901	278	after finishing transfer.
mbed_official	87:085cde657901	279	(++) No-Blocking mode: The communication is performed using Interrupts
mbed_official	87:085cde657901	280	or DMA, These API's return the HAL status.
mbed_official	87:085cde657901	281	The end of the data processing will be indicated through the
mbed_official	87:085cde657901	282	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	87:085cde657901	283	using DMA mode.
mbed_official	87:085cde657901	284	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	87:085cde657901	285	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	87:085cde657901	286	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	87:085cde657901	287
mbed_official	87:085cde657901	288	(#) Blocking mode API's are :
mbed_official	87:085cde657901	289	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	290	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	291	(++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	87:085cde657901	292
mbed_official	87:085cde657901	293	(#) Non-Blocking mode API's with Interrupt are :
mbed_official	87:085cde657901	294	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	295	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	296	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	87:085cde657901	297	(++) HAL_SPI_IRQHandler()
mbed_official	87:085cde657901	298
mbed_official	87:085cde657901	299	(#) No-Blocking mode functions with DMA are :
mbed_official	87:085cde657901	300	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	301	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	302	(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	87:085cde657901	303
mbed_official	87:085cde657901	304	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official	87:085cde657901	305	(++) HAL_SPI_TxCpltCallback()
mbed_official	87:085cde657901	306	(++) HAL_SPI_RxCpltCallback()
mbed_official	87:085cde657901	307	(++) HAL_SPI_ErrorCallback()
mbed_official	87:085cde657901	308	(++) HAL_SPI_TxRxCpltCallback()
mbed_official	87:085cde657901	309
mbed_official	87:085cde657901	310	@endverbatim
mbed_official	87:085cde657901	311	* @{
mbed_official	87:085cde657901	312	*/
mbed_official	87:085cde657901	313
mbed_official	87:085cde657901	314	/**
mbed_official	87:085cde657901	315	* @brief Transmit an amount of data in blocking mode
mbed_official	87:085cde657901	316	* @param hspi: SPI handle
mbed_official	87:085cde657901	317	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	318	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	319	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	320	* @retval HAL status
mbed_official	87:085cde657901	321	*/
mbed_official	87:085cde657901	322	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	323	{
mbed_official	87:085cde657901	324
mbed_official	87:085cde657901	325	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	326	{
mbed_official	87:085cde657901	327	if((pData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	328	{
mbed_official	87:085cde657901	329	return HAL_ERROR;
mbed_official	87:085cde657901	330	}
mbed_official	87:085cde657901	331
mbed_official	87:085cde657901	332	/* Check the parameters */
mbed_official	87:085cde657901	333	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	334
mbed_official	87:085cde657901	335	/* Process Locked */
mbed_official	87:085cde657901	336	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	337
mbed_official	87:085cde657901	338	/* Configure communication */
mbed_official	87:085cde657901	339	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	340	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	341
mbed_official	87:085cde657901	342	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	343	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	344	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	345
mbed_official	87:085cde657901	346	/Init field not used in handle to zero /
mbed_official	87:085cde657901	347	hspi->TxISR = 0;
mbed_official	87:085cde657901	348	hspi->RxISR = 0;
mbed_official	87:085cde657901	349	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	350	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	351
mbed_official	87:085cde657901	352	/* Reset CRC Calculation */
mbed_official	87:085cde657901	353	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	354	{
mbed_official	87:085cde657901	355	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	356	}
mbed_official	87:085cde657901	357
mbed_official	87:085cde657901	358	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	359	{
mbed_official	87:085cde657901	360	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	361	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	362	}
mbed_official	87:085cde657901	363
mbed_official	87:085cde657901	364	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	365	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	366	{
mbed_official	87:085cde657901	367	/* Enable SPI peripheral */
mbed_official	87:085cde657901	368	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	369	}
mbed_official	87:085cde657901	370
mbed_official	87:085cde657901	371	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	372	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	373	{
mbed_official	87:085cde657901	374
mbed_official	87:085cde657901	375	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	376	hspi->TxXferCount--;
mbed_official	87:085cde657901	377
mbed_official	87:085cde657901	378	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	379	{
mbed_official	87:085cde657901	380	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	381	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	382	{
mbed_official	87:085cde657901	383	return HAL_TIMEOUT;
mbed_official	87:085cde657901	384	}
mbed_official	87:085cde657901	385	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	386	hspi->TxXferCount--;
mbed_official	87:085cde657901	387	}
mbed_official	87:085cde657901	388	/* Enable CRC Transmission */
mbed_official	87:085cde657901	389	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	390	{
mbed_official	87:085cde657901	391	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	392	}
mbed_official	87:085cde657901	393	}
mbed_official	87:085cde657901	394	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	395	else
mbed_official	87:085cde657901	396	{
mbed_official	87:085cde657901	397	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	398	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	399	hspi->TxXferCount--;
mbed_official	87:085cde657901	400
mbed_official	87:085cde657901	401	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	402	{
mbed_official	87:085cde657901	403	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	404	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	405	{
mbed_official	87:085cde657901	406	return HAL_TIMEOUT;
mbed_official	87:085cde657901	407	}
mbed_official	87:085cde657901	408	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	409	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	410	hspi->TxXferCount--;
mbed_official	87:085cde657901	411	}
mbed_official	87:085cde657901	412	/* Enable CRC Transmission */
mbed_official	87:085cde657901	413	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	414	{
mbed_official	87:085cde657901	415	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	416	}
mbed_official	87:085cde657901	417	}
mbed_official	87:085cde657901	418
mbed_official	87:085cde657901	419	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	420	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	421	{
mbed_official	87:085cde657901	422	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	423	return HAL_TIMEOUT;
mbed_official	87:085cde657901	424	}
mbed_official	87:085cde657901	425
mbed_official	87:085cde657901	426	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	427	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	428	{
mbed_official	87:085cde657901	429	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	430	return HAL_TIMEOUT;
mbed_official	87:085cde657901	431	}
mbed_official	87:085cde657901	432
mbed_official	87:085cde657901	433	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	434	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	435	{
mbed_official	87:085cde657901	436	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	437	}
mbed_official	87:085cde657901	438
mbed_official	87:085cde657901	439	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	440
mbed_official	87:085cde657901	441	/* Process Unlocked */
mbed_official	87:085cde657901	442	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	443
mbed_official	87:085cde657901	444	return HAL_OK;
mbed_official	87:085cde657901	445	}
mbed_official	87:085cde657901	446	else
mbed_official	87:085cde657901	447	{
mbed_official	87:085cde657901	448	return HAL_BUSY;
mbed_official	87:085cde657901	449	}
mbed_official	87:085cde657901	450	}
mbed_official	87:085cde657901	451
mbed_official	87:085cde657901	452	/**
mbed_official	87:085cde657901	453	* @brief Receive an amount of data in blocking mode
mbed_official	87:085cde657901	454	* @param hspi: SPI handle
mbed_official	87:085cde657901	455	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	456	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	457	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	458	* @retval HAL status
mbed_official	87:085cde657901	459	*/
mbed_official	87:085cde657901	460	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	461	{
mbed_official	87:085cde657901	462	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	463	uint32_t tmp = 0;
mbed_official	87:085cde657901	464
mbed_official	87:085cde657901	465	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	466	{
mbed_official	87:085cde657901	467	if((pData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	468	{
mbed_official	87:085cde657901	469	return HAL_ERROR;
mbed_official	87:085cde657901	470	}
mbed_official	87:085cde657901	471
mbed_official	87:085cde657901	472	/* Process Locked */
mbed_official	87:085cde657901	473	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	474
mbed_official	87:085cde657901	475	/* Configure communication */
mbed_official	87:085cde657901	476	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	477	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	478
mbed_official	87:085cde657901	479	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	480	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	481	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	482
mbed_official	87:085cde657901	483	/Init field not used in handle to zero /
mbed_official	87:085cde657901	484	hspi->RxISR = 0;
mbed_official	87:085cde657901	485	hspi->TxISR = 0;
mbed_official	87:085cde657901	486	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	487	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	488
mbed_official	87:085cde657901	489	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	490	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	491	{
mbed_official	87:085cde657901	492	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	493	}
mbed_official	87:085cde657901	494
mbed_official	87:085cde657901	495	/* Reset CRC Calculation */
mbed_official	87:085cde657901	496	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	497	{
mbed_official	87:085cde657901	498	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	499	}
mbed_official	87:085cde657901	500
mbed_official	87:085cde657901	501	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	87:085cde657901	502	{
mbed_official	87:085cde657901	503	/* Process Unlocked */
mbed_official	87:085cde657901	504	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	505
mbed_official	87:085cde657901	506	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	507	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	87:085cde657901	508	}
mbed_official	87:085cde657901	509
mbed_official	87:085cde657901	510	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	511	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	512	{
mbed_official	87:085cde657901	513	/* Enable SPI peripheral */
mbed_official	87:085cde657901	514	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	515	}
mbed_official	87:085cde657901	516
mbed_official	87:085cde657901	517	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	518	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	519	{
mbed_official	87:085cde657901	520	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	521	{
mbed_official	87:085cde657901	522	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	523	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	524	{
mbed_official	87:085cde657901	525	return HAL_TIMEOUT;
mbed_official	87:085cde657901	526	}
mbed_official	87:085cde657901	527
mbed_official	87:085cde657901	528	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	529	hspi->RxXferCount--;
mbed_official	87:085cde657901	530	}
mbed_official	87:085cde657901	531	/* Enable CRC Transmission */
mbed_official	87:085cde657901	532	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	533	{
mbed_official	87:085cde657901	534	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	535	}
mbed_official	87:085cde657901	536	}
mbed_official	87:085cde657901	537	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	538	else
mbed_official	87:085cde657901	539	{
mbed_official	87:085cde657901	540	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	541	{
mbed_official	87:085cde657901	542	/* Wait until RXNE flag is set to read data */
mbed_official	87:085cde657901	543	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	544	{
mbed_official	87:085cde657901	545	return HAL_TIMEOUT;
mbed_official	87:085cde657901	546	}
mbed_official	87:085cde657901	547
mbed_official	87:085cde657901	548	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	549	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	550	hspi->RxXferCount--;
mbed_official	87:085cde657901	551	}
mbed_official	87:085cde657901	552	/* Enable CRC Transmission */
mbed_official	87:085cde657901	553	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	554	{
mbed_official	87:085cde657901	555	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	556	}
mbed_official	87:085cde657901	557	}
mbed_official	87:085cde657901	558
mbed_official	87:085cde657901	559	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	560	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	561	{
mbed_official	87:085cde657901	562	return HAL_TIMEOUT;
mbed_official	87:085cde657901	563	}
mbed_official	87:085cde657901	564
mbed_official	87:085cde657901	565	/* Receive last data in 8 Bit mode */
mbed_official	87:085cde657901	566	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	567	{
mbed_official	87:085cde657901	568	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	569	}
mbed_official	87:085cde657901	570	/* Receive last data in 16 Bit mode */
mbed_official	87:085cde657901	571	else
mbed_official	87:085cde657901	572	{
mbed_official	87:085cde657901	573	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	574	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	575	}
mbed_official	87:085cde657901	576	hspi->RxXferCount--;
mbed_official	87:085cde657901	577
mbed_official	87:085cde657901	578	/* Wait until RXNE flag is set: CRC Received */
mbed_official	87:085cde657901	579	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	580	{
mbed_official	87:085cde657901	581	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	582	{
mbed_official	87:085cde657901	583	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	584	return HAL_TIMEOUT;
mbed_official	87:085cde657901	585	}
mbed_official	87:085cde657901	586
mbed_official	87:085cde657901	587	/* Read CRC to Flush RXNE flag */
mbed_official	87:085cde657901	588	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	589	}
mbed_official	87:085cde657901	590
mbed_official	87:085cde657901	591	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	592	{
mbed_official	87:085cde657901	593	/* Disable SPI peripheral */
mbed_official	87:085cde657901	594	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	595	}
mbed_official	87:085cde657901	596
mbed_official	87:085cde657901	597	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	598
mbed_official	87:085cde657901	599	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	600	/* Check if CRC error occurred */
mbed_official	87:085cde657901	601	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	602	{
mbed_official	87:085cde657901	603	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	604
mbed_official	87:085cde657901	605	/* Reset CRC Calculation */
mbed_official	87:085cde657901	606	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	607
mbed_official	87:085cde657901	608	/* Process Unlocked */
mbed_official	87:085cde657901	609	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	610
mbed_official	87:085cde657901	611	return HAL_ERROR;
mbed_official	87:085cde657901	612	}
mbed_official	87:085cde657901	613
mbed_official	87:085cde657901	614	/* Process Unlocked */
mbed_official	87:085cde657901	615	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	616
mbed_official	87:085cde657901	617	return HAL_OK;
mbed_official	87:085cde657901	618	}
mbed_official	87:085cde657901	619	else
mbed_official	87:085cde657901	620	{
mbed_official	87:085cde657901	621	return HAL_BUSY;
mbed_official	87:085cde657901	622	}
mbed_official	87:085cde657901	623	}
mbed_official	87:085cde657901	624
mbed_official	87:085cde657901	625	/**
mbed_official	87:085cde657901	626	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	87:085cde657901	627	* @param hspi: SPI handle
mbed_official	87:085cde657901	628	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	629	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	630	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	631	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	632	* @retval HAL status
mbed_official	87:085cde657901	633	*/
mbed_official	87:085cde657901	634	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	635	{
mbed_official	87:085cde657901	636	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	637	uint32_t tmp = 0;
mbed_official	87:085cde657901	638
mbed_official	87:085cde657901	639	tmp = hspi->State;
mbed_official	87:085cde657901	640	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	641	{
mbed_official	87:085cde657901	642	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	643	{
mbed_official	87:085cde657901	644	return HAL_ERROR;
mbed_official	87:085cde657901	645	}
mbed_official	87:085cde657901	646
mbed_official	87:085cde657901	647	/* Check the parameters */
mbed_official	87:085cde657901	648	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	649
mbed_official	87:085cde657901	650	/* Process Locked */
mbed_official	87:085cde657901	651	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	652
mbed_official	87:085cde657901	653	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	654	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	655	{
mbed_official	87:085cde657901	656	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	657	}
mbed_official	87:085cde657901	658
mbed_official	87:085cde657901	659	/* Configure communication */
mbed_official	87:085cde657901	660	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	661
mbed_official	87:085cde657901	662	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	663	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	664	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	665
mbed_official	87:085cde657901	666	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	667	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	668	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	669
mbed_official	87:085cde657901	670	/Init field not used in handle to zero /
mbed_official	87:085cde657901	671	hspi->RxISR = 0;
mbed_official	87:085cde657901	672	hspi->TxISR = 0;
mbed_official	87:085cde657901	673
mbed_official	87:085cde657901	674	/* Reset CRC Calculation */
mbed_official	87:085cde657901	675	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	676	{
mbed_official	87:085cde657901	677	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	678	}
mbed_official	87:085cde657901	679
mbed_official	87:085cde657901	680	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	681	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	682	{
mbed_official	87:085cde657901	683	/* Enable SPI peripheral */
mbed_official	87:085cde657901	684	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	685	}
mbed_official	87:085cde657901	686
mbed_official	87:085cde657901	687	/* Transmit and Receive data in 16 Bit mode */
mbed_official	87:085cde657901	688	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	87:085cde657901	689	{
mbed_official	87:085cde657901	690	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	691	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	692	hspi->TxXferCount--;
mbed_official	87:085cde657901	693
mbed_official	87:085cde657901	694	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	695	{
mbed_official	87:085cde657901	696	/* Enable CRC Transmission */
mbed_official	87:085cde657901	697	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	698	{
mbed_official	87:085cde657901	699	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	700	}
mbed_official	87:085cde657901	701
mbed_official	87:085cde657901	702	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	703	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	704	{
mbed_official	87:085cde657901	705	return HAL_TIMEOUT;
mbed_official	87:085cde657901	706	}
mbed_official	87:085cde657901	707
mbed_official	87:085cde657901	708	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	709	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	710	hspi->RxXferCount--;
mbed_official	87:085cde657901	711	}
mbed_official	87:085cde657901	712	else
mbed_official	87:085cde657901	713	{
mbed_official	87:085cde657901	714	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	715	{
mbed_official	87:085cde657901	716	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	717	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	718	{
mbed_official	87:085cde657901	719	return HAL_TIMEOUT;
mbed_official	87:085cde657901	720	}
mbed_official	87:085cde657901	721
mbed_official	87:085cde657901	722	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	723	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	724	hspi->TxXferCount--;
mbed_official	87:085cde657901	725
mbed_official	87:085cde657901	726	/* Enable CRC Transmission */
mbed_official	87:085cde657901	727	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	728	{
mbed_official	87:085cde657901	729	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	730	}
mbed_official	87:085cde657901	731
mbed_official	87:085cde657901	732	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	733	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	734	{
mbed_official	87:085cde657901	735	return HAL_TIMEOUT;
mbed_official	87:085cde657901	736	}
mbed_official	87:085cde657901	737
mbed_official	87:085cde657901	738	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	739	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	740	hspi->RxXferCount--;
mbed_official	87:085cde657901	741	}
mbed_official	87:085cde657901	742
mbed_official	87:085cde657901	743	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	744	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	745	{
mbed_official	87:085cde657901	746	return HAL_TIMEOUT;
mbed_official	87:085cde657901	747	}
mbed_official	87:085cde657901	748
mbed_official	87:085cde657901	749	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	750	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	751	hspi->RxXferCount--;
mbed_official	87:085cde657901	752	}
mbed_official	87:085cde657901	753	}
mbed_official	87:085cde657901	754	/* Transmit and Receive data in 8 Bit mode */
mbed_official	87:085cde657901	755	else
mbed_official	87:085cde657901	756	{
mbed_official	87:085cde657901	757
mbed_official	87:085cde657901	758	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	759	hspi->TxXferCount--;
mbed_official	87:085cde657901	760
mbed_official	87:085cde657901	761	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	762	{
mbed_official	87:085cde657901	763	/* Enable CRC Transmission */
mbed_official	87:085cde657901	764	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	765	{
mbed_official	87:085cde657901	766	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	767	}
mbed_official	87:085cde657901	768
mbed_official	87:085cde657901	769	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	770	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	771	{
mbed_official	87:085cde657901	772	return HAL_TIMEOUT;
mbed_official	87:085cde657901	773	}
mbed_official	87:085cde657901	774
mbed_official	87:085cde657901	775	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	776	hspi->RxXferCount--;
mbed_official	87:085cde657901	777	}
mbed_official	87:085cde657901	778	else
mbed_official	87:085cde657901	779	{
mbed_official	87:085cde657901	780	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	781	{
mbed_official	87:085cde657901	782	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	783	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	784	{
mbed_official	87:085cde657901	785	return HAL_TIMEOUT;
mbed_official	87:085cde657901	786	}
mbed_official	87:085cde657901	787
mbed_official	87:085cde657901	788	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	789	hspi->TxXferCount--;
mbed_official	87:085cde657901	790
mbed_official	87:085cde657901	791	/* Enable CRC Transmission */
mbed_official	87:085cde657901	792	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	793	{
mbed_official	87:085cde657901	794	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	795	}
mbed_official	87:085cde657901	796
mbed_official	87:085cde657901	797	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	798	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	799	{
mbed_official	87:085cde657901	800	return HAL_TIMEOUT;
mbed_official	87:085cde657901	801	}
mbed_official	87:085cde657901	802
mbed_official	87:085cde657901	803	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	804	hspi->RxXferCount--;
mbed_official	87:085cde657901	805	}
mbed_official	87:085cde657901	806
mbed_official	87:085cde657901	807	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	808	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	809	{
mbed_official	87:085cde657901	810	return HAL_TIMEOUT;
mbed_official	87:085cde657901	811	}
mbed_official	87:085cde657901	812
mbed_official	87:085cde657901	813	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	814	hspi->RxXferCount--;
mbed_official	87:085cde657901	815	}
mbed_official	87:085cde657901	816	}
mbed_official	87:085cde657901	817
mbed_official	87:085cde657901	818	/* Read CRC from DR to close CRC calculation process */
mbed_official	87:085cde657901	819	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	820	{
mbed_official	87:085cde657901	821	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	822	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	823	{
mbed_official	87:085cde657901	824	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	825	return HAL_TIMEOUT;
mbed_official	87:085cde657901	826	}
mbed_official	87:085cde657901	827	/* Read CRC */
mbed_official	87:085cde657901	828	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	829	}
mbed_official	87:085cde657901	830
mbed_official	87:085cde657901	831	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	832	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	833	{
mbed_official	87:085cde657901	834	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	835	return HAL_TIMEOUT;
mbed_official	87:085cde657901	836	}
mbed_official	87:085cde657901	837
mbed_official	87:085cde657901	838	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	839
mbed_official	87:085cde657901	840	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	841	/* Check if CRC error occurred */
mbed_official	87:085cde657901	842	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	843	{
mbed_official	87:085cde657901	844	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	845
mbed_official	87:085cde657901	846	/* Reset CRC Calculation */
mbed_official	87:085cde657901	847	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	848	{
mbed_official	87:085cde657901	849	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	850	}
mbed_official	87:085cde657901	851
mbed_official	87:085cde657901	852	/* Process Unlocked */
mbed_official	87:085cde657901	853	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	854
mbed_official	87:085cde657901	855	return HAL_ERROR;
mbed_official	87:085cde657901	856	}
mbed_official	87:085cde657901	857
mbed_official	87:085cde657901	858	/* Process Unlocked */
mbed_official	87:085cde657901	859	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	860
mbed_official	87:085cde657901	861	return HAL_OK;
mbed_official	87:085cde657901	862	}
mbed_official	87:085cde657901	863	else
mbed_official	87:085cde657901	864	{
mbed_official	87:085cde657901	865	return HAL_BUSY;
mbed_official	87:085cde657901	866	}
mbed_official	87:085cde657901	867	}
mbed_official	87:085cde657901	868
mbed_official	87:085cde657901	869	/**
mbed_official	87:085cde657901	870	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	87:085cde657901	871	* @param hspi: SPI handle
mbed_official	87:085cde657901	872	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	873	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	874	* @retval HAL status
mbed_official	87:085cde657901	875	*/
mbed_official	87:085cde657901	876	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	877	{
mbed_official	87:085cde657901	878	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	879	{
mbed_official	87:085cde657901	880	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	881	{
mbed_official	87:085cde657901	882	return HAL_ERROR;
mbed_official	87:085cde657901	883	}
mbed_official	87:085cde657901	884
mbed_official	87:085cde657901	885	/* Check the parameters */
mbed_official	87:085cde657901	886	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	887
mbed_official	87:085cde657901	888	/* Process Locked */
mbed_official	87:085cde657901	889	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	890
mbed_official	87:085cde657901	891	/* Configure communication */
mbed_official	87:085cde657901	892	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	893	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	894
mbed_official	87:085cde657901	895	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	896	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	897	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	898	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	899
mbed_official	87:085cde657901	900	/Init field not used in handle to zero /
mbed_official	87:085cde657901	901	hspi->RxISR = 0;
mbed_official	87:085cde657901	902	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	903	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	904
mbed_official	87:085cde657901	905	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	906	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	907	{
mbed_official	87:085cde657901	908	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	909	}
mbed_official	87:085cde657901	910
mbed_official	87:085cde657901	911	/* Reset CRC Calculation */
mbed_official	87:085cde657901	912	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	913	{
mbed_official	87:085cde657901	914	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	915	}
mbed_official	87:085cde657901	916
mbed_official	87:085cde657901	917	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	918	{
mbed_official	87:085cde657901	919	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	87:085cde657901	920	}else
mbed_official	87:085cde657901	921	{
mbed_official	87:085cde657901	922	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	923	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	87:085cde657901	924	}
mbed_official	87:085cde657901	925	/* Process Unlocked */
mbed_official	87:085cde657901	926	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	927
mbed_official	87:085cde657901	928	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	929	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	930	{
mbed_official	87:085cde657901	931	/* Enable SPI peripheral */
mbed_official	87:085cde657901	932	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	933	}
mbed_official	87:085cde657901	934
mbed_official	87:085cde657901	935	return HAL_OK;
mbed_official	87:085cde657901	936	}
mbed_official	87:085cde657901	937	else
mbed_official	87:085cde657901	938	{
mbed_official	87:085cde657901	939	return HAL_BUSY;
mbed_official	87:085cde657901	940	}
mbed_official	87:085cde657901	941	}
mbed_official	87:085cde657901	942
mbed_official	87:085cde657901	943	/**
mbed_official	87:085cde657901	944	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	87:085cde657901	945	* @param hspi: SPI handle
mbed_official	87:085cde657901	946	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	947	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	948	* @retval HAL status
mbed_official	87:085cde657901	949	*/
mbed_official	87:085cde657901	950	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	951	{
mbed_official	87:085cde657901	952	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	953	{
mbed_official	87:085cde657901	954	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	955	{
mbed_official	87:085cde657901	956	return HAL_ERROR;
mbed_official	87:085cde657901	957	}
mbed_official	87:085cde657901	958
mbed_official	87:085cde657901	959	/* Process Locked */
mbed_official	87:085cde657901	960	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	961
mbed_official	87:085cde657901	962	/* Configure communication */
mbed_official	87:085cde657901	963	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	964	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	965
mbed_official	87:085cde657901	966	hspi->RxISR = &SPI_RxISR;
mbed_official	87:085cde657901	967	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	968	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	969	hspi->RxXferCount = Size ;
mbed_official	87:085cde657901	970
mbed_official	87:085cde657901	971	/Init field not used in handle to zero /
mbed_official	87:085cde657901	972	hspi->TxISR = 0;
mbed_official	87:085cde657901	973	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	974	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	975
mbed_official	87:085cde657901	976	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	977	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	978	{
mbed_official	87:085cde657901	979	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	980	}
mbed_official	87:085cde657901	981	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	982	{
mbed_official	87:085cde657901	983	/* Process Unlocked */
mbed_official	87:085cde657901	984	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	985
mbed_official	87:085cde657901	986	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	987	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	87:085cde657901	988	}
mbed_official	87:085cde657901	989
mbed_official	87:085cde657901	990	/* Reset CRC Calculation */
mbed_official	87:085cde657901	991	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	992	{
mbed_official	87:085cde657901	993	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	994	}
mbed_official	87:085cde657901	995
mbed_official	87:085cde657901	996	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	997	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	998
mbed_official	87:085cde657901	999	/* Process Unlocked */
mbed_official	87:085cde657901	1000	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1001
mbed_official	87:085cde657901	1002	/* Note : The SPI must be enabled after unlocking current process
mbed_official	87:085cde657901	1003	to avoid the risk of SPI interrupt handle execution before current
mbed_official	87:085cde657901	1004	process unlock */
mbed_official	87:085cde657901	1005
mbed_official	87:085cde657901	1006	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1007	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1008	{
mbed_official	87:085cde657901	1009	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1010	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1011	}
mbed_official	87:085cde657901	1012
mbed_official	87:085cde657901	1013	return HAL_OK;
mbed_official	87:085cde657901	1014	}
mbed_official	87:085cde657901	1015	else
mbed_official	87:085cde657901	1016	{
mbed_official	87:085cde657901	1017	return HAL_BUSY;
mbed_official	87:085cde657901	1018	}
mbed_official	87:085cde657901	1019	}
mbed_official	87:085cde657901	1020
mbed_official	87:085cde657901	1021	/**
mbed_official	87:085cde657901	1022	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	87:085cde657901	1023	* @param hspi: SPI handle
mbed_official	87:085cde657901	1024	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1025	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	1026	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1027	* @retval HAL status
mbed_official	87:085cde657901	1028	*/
mbed_official	87:085cde657901	1029	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1030	{
mbed_official	87:085cde657901	1031	uint32_t tmp = 0;
mbed_official	87:085cde657901	1032
mbed_official	87:085cde657901	1033	tmp = hspi->State;
mbed_official	87:085cde657901	1034	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	1035	{
mbed_official	87:085cde657901	1036	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1037	{
mbed_official	87:085cde657901	1038	return HAL_ERROR;
mbed_official	87:085cde657901	1039	}
mbed_official	87:085cde657901	1040
mbed_official	87:085cde657901	1041	/* Check the parameters */
mbed_official	87:085cde657901	1042	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1043
mbed_official	87:085cde657901	1044	/* Process locked */
mbed_official	87:085cde657901	1045	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1046
mbed_official	87:085cde657901	1047	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	1048	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1049	{
mbed_official	87:085cde657901	1050	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1051	}
mbed_official	87:085cde657901	1052
mbed_official	87:085cde657901	1053	/* Configure communication */
mbed_official	87:085cde657901	1054	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1055
mbed_official	87:085cde657901	1056	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	1057	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	1058	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1059	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1060
mbed_official	87:085cde657901	1061	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	87:085cde657901	1062	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	1063	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1064	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1065
mbed_official	87:085cde657901	1066	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1067	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1068	{
mbed_official	87:085cde657901	1069	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1070	}
mbed_official	87:085cde657901	1071
mbed_official	87:085cde657901	1072	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	87:085cde657901	1073	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1074
mbed_official	87:085cde657901	1075	/* Process Unlocked */
mbed_official	87:085cde657901	1076	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1077
mbed_official	87:085cde657901	1078	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1079	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1080	{
mbed_official	87:085cde657901	1081	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1082	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1083	}
mbed_official	87:085cde657901	1084
mbed_official	87:085cde657901	1085	return HAL_OK;
mbed_official	87:085cde657901	1086	}
mbed_official	87:085cde657901	1087	else
mbed_official	87:085cde657901	1088	{
mbed_official	87:085cde657901	1089	return HAL_BUSY;
mbed_official	87:085cde657901	1090	}
mbed_official	87:085cde657901	1091	}
mbed_official	87:085cde657901	1092
mbed_official	87:085cde657901	1093	/**
mbed_official	87:085cde657901	1094	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	87:085cde657901	1095	* @param hspi: SPI handle
mbed_official	87:085cde657901	1096	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1097	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1098	* @retval HAL status
mbed_official	87:085cde657901	1099	*/
mbed_official	87:085cde657901	1100	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1101	{
mbed_official	87:085cde657901	1102	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1103	{
mbed_official	87:085cde657901	1104	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1105	{
mbed_official	87:085cde657901	1106	return HAL_ERROR;
mbed_official	87:085cde657901	1107	}
mbed_official	87:085cde657901	1108
mbed_official	87:085cde657901	1109	/* Check the parameters */
mbed_official	87:085cde657901	1110	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	1111
mbed_official	87:085cde657901	1112	/* Process Locked */
mbed_official	87:085cde657901	1113	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1114
mbed_official	87:085cde657901	1115	/* Configure communication */
mbed_official	87:085cde657901	1116	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	1117	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1118
mbed_official	87:085cde657901	1119	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	1120	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1121	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1122
mbed_official	87:085cde657901	1123	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1124	hspi->TxISR = 0;
mbed_official	87:085cde657901	1125	hspi->RxISR = 0;
mbed_official	87:085cde657901	1126	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	1127	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1128
mbed_official	87:085cde657901	1129	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1130	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1131	{
mbed_official	87:085cde657901	1132	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	1133	}
mbed_official	87:085cde657901	1134
mbed_official	87:085cde657901	1135	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1136	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1137	{
mbed_official	87:085cde657901	1138	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1139	}
mbed_official	87:085cde657901	1140
mbed_official	87:085cde657901	1141	/* Set the SPI TxDMA transfer complete callback */
mbed_official	87:085cde657901	1142	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	87:085cde657901	1143
mbed_official	87:085cde657901	1144	/* Set the DMA error callback */
mbed_official	87:085cde657901	1145	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1146
mbed_official	87:085cde657901	1147	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1148	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1149
mbed_official	87:085cde657901	1150	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1151	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1152
mbed_official	87:085cde657901	1153	/* Process Unlocked */
mbed_official	87:085cde657901	1154	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1155
mbed_official	87:085cde657901	1156	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1157	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1158	{
mbed_official	87:085cde657901	1159	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1160	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1161	}
mbed_official	87:085cde657901	1162
mbed_official	87:085cde657901	1163	return HAL_OK;
mbed_official	87:085cde657901	1164	}
mbed_official	87:085cde657901	1165	else
mbed_official	87:085cde657901	1166	{
mbed_official	87:085cde657901	1167	return HAL_BUSY;
mbed_official	87:085cde657901	1168	}
mbed_official	87:085cde657901	1169	}
mbed_official	87:085cde657901	1170
mbed_official	87:085cde657901	1171	/**
mbed_official	87:085cde657901	1172	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	87:085cde657901	1173	* @param hspi: SPI handle
mbed_official	87:085cde657901	1174	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1175	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	87:085cde657901	1176	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1177	* @retval HAL status
mbed_official	87:085cde657901	1178	*/
mbed_official	87:085cde657901	1179	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1180	{
mbed_official	87:085cde657901	1181	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1182	{
mbed_official	87:085cde657901	1183	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1184	{
mbed_official	87:085cde657901	1185	return HAL_ERROR;
mbed_official	87:085cde657901	1186	}
mbed_official	87:085cde657901	1187
mbed_official	87:085cde657901	1188	/* Process Locked */
mbed_official	87:085cde657901	1189	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1190
mbed_official	87:085cde657901	1191	/* Configure communication */
mbed_official	87:085cde657901	1192	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	1193	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1194
mbed_official	87:085cde657901	1195	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	1196	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1197	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1198
mbed_official	87:085cde657901	1199	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1200	hspi->RxISR = 0;
mbed_official	87:085cde657901	1201	hspi->TxISR = 0;
mbed_official	87:085cde657901	1202	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	1203	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1204
mbed_official	87:085cde657901	1205	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1206	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1207	{
mbed_official	87:085cde657901	1208	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	1209	}
mbed_official	87:085cde657901	1210	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	1211	{
mbed_official	87:085cde657901	1212	/* Process Unlocked */
mbed_official	87:085cde657901	1213	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1214
mbed_official	87:085cde657901	1215	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	1216	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	87:085cde657901	1217	}
mbed_official	87:085cde657901	1218
mbed_official	87:085cde657901	1219	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1220	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1221	{
mbed_official	87:085cde657901	1222	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1223	}
mbed_official	87:085cde657901	1224
mbed_official	87:085cde657901	1225	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	87:085cde657901	1226	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	87:085cde657901	1227
mbed_official	87:085cde657901	1228	/* Set the DMA error callback */
mbed_official	87:085cde657901	1229	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1230
mbed_official	87:085cde657901	1231	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1232	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1233
mbed_official	87:085cde657901	1234	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1235	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1236
mbed_official	87:085cde657901	1237	/* Process Unlocked */
mbed_official	87:085cde657901	1238	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1239
mbed_official	87:085cde657901	1240	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1241	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1242	{
mbed_official	87:085cde657901	1243	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1244	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1245	}
mbed_official	87:085cde657901	1246
mbed_official	87:085cde657901	1247	return HAL_OK;
mbed_official	87:085cde657901	1248	}
mbed_official	87:085cde657901	1249	else
mbed_official	87:085cde657901	1250	{
mbed_official	87:085cde657901	1251	return HAL_BUSY;
mbed_official	87:085cde657901	1252	}
mbed_official	87:085cde657901	1253	}
mbed_official	87:085cde657901	1254
mbed_official	87:085cde657901	1255	/**
mbed_official	87:085cde657901	1256	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	87:085cde657901	1257	* @param hspi: SPI handle
mbed_official	87:085cde657901	1258	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1259	* @param pRxData: pointer to reception data buffer
mbed_official	87:085cde657901	1260	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	87:085cde657901	1261	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1262	* @retval HAL status
mbed_official	87:085cde657901	1263	*/
mbed_official	87:085cde657901	1264	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1265	{
mbed_official	87:085cde657901	1266	uint32_t tmpstate = 0;
mbed_official	87:085cde657901	1267	tmpstate = hspi->State;
mbed_official	87:085cde657901	1268	if((tmpstate == HAL_SPI_STATE_READY) \|\| (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	1269	{
mbed_official	87:085cde657901	1270	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1271	{
mbed_official	87:085cde657901	1272	return HAL_ERROR;
mbed_official	87:085cde657901	1273	}
mbed_official	87:085cde657901	1274
mbed_official	87:085cde657901	1275	/* Check the parameters */
mbed_official	87:085cde657901	1276	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1277
mbed_official	87:085cde657901	1278	/* Process locked */
mbed_official	87:085cde657901	1279	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1280
mbed_official	87:085cde657901	1281	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	1282	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1283	{
mbed_official	87:085cde657901	1284	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1285	}
mbed_official	87:085cde657901	1286
mbed_official	87:085cde657901	1287	/* Configure communication */
mbed_official	87:085cde657901	1288	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1289
mbed_official	87:085cde657901	1290	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	87:085cde657901	1291	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1292	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1293
mbed_official	87:085cde657901	1294	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	87:085cde657901	1295	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1296	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1297
mbed_official	87:085cde657901	1298	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1299	hspi->RxISR = 0;
mbed_official	87:085cde657901	1300	hspi->TxISR = 0;
mbed_official	87:085cde657901	1301
mbed_official	87:085cde657901	1302	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1303	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1304	{
mbed_official	87:085cde657901	1305	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1306	}
mbed_official	87:085cde657901	1307
mbed_official	87:085cde657901	1308	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
mbed_official	87:085cde657901	1309	the reception request (RXNE) */
mbed_official	87:085cde657901	1310	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	87:085cde657901	1311
mbed_official	87:085cde657901	1312	/* Set the DMA error callback */
mbed_official	87:085cde657901	1313	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1314
mbed_official	87:085cde657901	1315	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1316	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1317
mbed_official	87:085cde657901	1318	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1319	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1320
mbed_official	87:085cde657901	1321	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	87:085cde657901	1322	is performed in DMA reception complete callback */
mbed_official	87:085cde657901	1323	hspi->hdmatx->XferCpltCallback = NULL;
mbed_official	87:085cde657901	1324
mbed_official	87:085cde657901	1325	/* Set the DMA error callback */
mbed_official	87:085cde657901	1326	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1327
mbed_official	87:085cde657901	1328	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1329	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1330
mbed_official	87:085cde657901	1331	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1332	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1333
mbed_official	87:085cde657901	1334	/* Process Unlocked */
mbed_official	87:085cde657901	1335	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1336
mbed_official	87:085cde657901	1337	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1338	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1339	{
mbed_official	87:085cde657901	1340	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1341	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1342	}
mbed_official	87:085cde657901	1343
mbed_official	87:085cde657901	1344	return HAL_OK;
mbed_official	87:085cde657901	1345	}
mbed_official	87:085cde657901	1346	else
mbed_official	87:085cde657901	1347	{
mbed_official	87:085cde657901	1348	return HAL_BUSY;
mbed_official	87:085cde657901	1349	}
mbed_official	87:085cde657901	1350	}
mbed_official	87:085cde657901	1351
mbed_official	87:085cde657901	1352	/**
mbed_official	87:085cde657901	1353	* @brief This function handles SPI interrupt request.
mbed_official	87:085cde657901	1354	* @param hspi: SPI handle
mbed_official	87:085cde657901	1355	* @retval HAL status
mbed_official	87:085cde657901	1356	*/
mbed_official	87:085cde657901	1357	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1358	{
mbed_official	87:085cde657901	1359	uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official	87:085cde657901	1360
mbed_official	87:085cde657901	1361	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official	87:085cde657901	1362	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official	87:085cde657901	1363	tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official	87:085cde657901	1364	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	87:085cde657901	1365	if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official	87:085cde657901	1366	{
mbed_official	87:085cde657901	1367	hspi->RxISR(hspi);
mbed_official	87:085cde657901	1368	return;
mbed_official	87:085cde657901	1369	}
mbed_official	87:085cde657901	1370
mbed_official	87:085cde657901	1371	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official	87:085cde657901	1372	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official	87:085cde657901	1373	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	87:085cde657901	1374	if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official	87:085cde657901	1375	{
mbed_official	87:085cde657901	1376	hspi->TxISR(hspi);
mbed_official	87:085cde657901	1377	return;
mbed_official	87:085cde657901	1378	}
mbed_official	87:085cde657901	1379
mbed_official	87:085cde657901	1380	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	87:085cde657901	1381	{
mbed_official	87:085cde657901	1382	/* SPI CRC error interrupt occured ---------------------------------------*/
mbed_official	87:085cde657901	1383	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1384	{
mbed_official	87:085cde657901	1385	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1386	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1387	}
mbed_official	87:085cde657901	1388	/* SPI Mode Fault error interrupt occured --------------------------------*/
mbed_official	87:085cde657901	1389	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	87:085cde657901	1390	{
mbed_official	87:085cde657901	1391	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	87:085cde657901	1392	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	87:085cde657901	1393	}
mbed_official	87:085cde657901	1394
mbed_official	87:085cde657901	1395	/* SPI Overrun error interrupt occured -----------------------------------*/
mbed_official	87:085cde657901	1396	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	87:085cde657901	1397	{
mbed_official	87:085cde657901	1398	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	87:085cde657901	1399	{
mbed_official	87:085cde657901	1400	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	87:085cde657901	1401	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1402	}
mbed_official	87:085cde657901	1403	}
mbed_official	87:085cde657901	1404
mbed_official	87:085cde657901	1405	/* SPI Frame error interrupt occured -------------------------------------*/
mbed_official	87:085cde657901	1406	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	87:085cde657901	1407	{
mbed_official	87:085cde657901	1408	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	87:085cde657901	1409	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	87:085cde657901	1410	}
mbed_official	87:085cde657901	1411
mbed_official	87:085cde657901	1412	/* Call the Error call Back in case of Errors */
mbed_official	87:085cde657901	1413	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1414	{
mbed_official	87:085cde657901	1415	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1416	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1417	}
mbed_official	87:085cde657901	1418	}
mbed_official	87:085cde657901	1419	}
mbed_official	87:085cde657901	1420
mbed_official	87:085cde657901	1421	/**
mbed_official	87:085cde657901	1422	* @brief Tx Transfer completed callbacks
mbed_official	87:085cde657901	1423	* @param hspi: SPI handle
mbed_official	87:085cde657901	1424	* @retval None
mbed_official	87:085cde657901	1425	*/
mbed_official	87:085cde657901	1426	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1427	{
mbed_official	87:085cde657901	1428	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1429	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	87:085cde657901	1430	*/
mbed_official	87:085cde657901	1431	}
mbed_official	87:085cde657901	1432
mbed_official	87:085cde657901	1433	/**
mbed_official	87:085cde657901	1434	* @brief Rx Transfer completed callbacks
mbed_official	87:085cde657901	1435	* @param hspi: SPI handle
mbed_official	87:085cde657901	1436	* @retval None
mbed_official	87:085cde657901	1437	*/
mbed_official	87:085cde657901	1438	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1439	{
mbed_official	87:085cde657901	1440	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1441	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1442	*/
mbed_official	87:085cde657901	1443	}
mbed_official	87:085cde657901	1444
mbed_official	87:085cde657901	1445	/**
mbed_official	87:085cde657901	1446	* @brief Tx and Rx Transfer completed callbacks
mbed_official	87:085cde657901	1447	* @param hspi: SPI handle
mbed_official	87:085cde657901	1448	* @retval None
mbed_official	87:085cde657901	1449	*/
mbed_official	87:085cde657901	1450	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1451	{
mbed_official	87:085cde657901	1452	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1453	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1454	*/
mbed_official	87:085cde657901	1455	}
mbed_official	87:085cde657901	1456
mbed_official	87:085cde657901	1457	/**
mbed_official	87:085cde657901	1458	* @brief SPI error callbacks
mbed_official	87:085cde657901	1459	* @param hspi: SPI handle
mbed_official	87:085cde657901	1460	* @retval None
mbed_official	87:085cde657901	1461	*/
mbed_official	87:085cde657901	1462	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1463	{
mbed_official	87:085cde657901	1464	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1465	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	87:085cde657901	1466	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	87:085cde657901	1467	and user can use HAL_SPI_GetError() API to check the latest error occured.
mbed_official	87:085cde657901	1468	*/
mbed_official	87:085cde657901	1469	}
mbed_official	87:085cde657901	1470
mbed_official	87:085cde657901	1471	/**
mbed_official	87:085cde657901	1472	* @}
mbed_official	87:085cde657901	1473	*/
mbed_official	87:085cde657901	1474
mbed_official	87:085cde657901	1475	/** @defgroup SPI_Group3 Peripheral State and Errors functions
mbed_official	87:085cde657901	1476	* @brief SPI control functions
mbed_official	87:085cde657901	1477	*
mbed_official	87:085cde657901	1478	@verbatim
mbed_official	87:085cde657901	1479	===============================================================================
mbed_official	87:085cde657901	1480	##### Peripheral State and Errors functions #####
mbed_official	87:085cde657901	1481	===============================================================================
mbed_official	87:085cde657901	1482	[..]
mbed_official	87:085cde657901	1483	This subsection provides a set of functions allowing to control the SPI.
mbed_official	87:085cde657901	1484	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	87:085cde657901	1485	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	87:085cde657901	1486	@endverbatim
mbed_official	87:085cde657901	1487	* @{
mbed_official	87:085cde657901	1488	*/
mbed_official	87:085cde657901	1489
mbed_official	87:085cde657901	1490	/**
mbed_official	87:085cde657901	1491	* @brief Return the SPI state
mbed_official	87:085cde657901	1492	* @param hspi : SPI handle
mbed_official	87:085cde657901	1493	* @retval SPI state
mbed_official	87:085cde657901	1494	*/
mbed_official	87:085cde657901	1495	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1496	{
mbed_official	87:085cde657901	1497	return hspi->State;
mbed_official	87:085cde657901	1498	}
mbed_official	87:085cde657901	1499
mbed_official	87:085cde657901	1500	/**
mbed_official	87:085cde657901	1501	* @brief Return the SPI error code
mbed_official	87:085cde657901	1502	* @param hspi : SPI handle
mbed_official	87:085cde657901	1503	* @retval SPI Error Code
mbed_official	87:085cde657901	1504	*/
mbed_official	87:085cde657901	1505	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1506	{
mbed_official	87:085cde657901	1507	return hspi->ErrorCode;
mbed_official	87:085cde657901	1508	}
mbed_official	87:085cde657901	1509
mbed_official	87:085cde657901	1510	/**
mbed_official	87:085cde657901	1511	* @}
mbed_official	87:085cde657901	1512	*/
mbed_official	87:085cde657901	1513
mbed_official	87:085cde657901	1514	/**
mbed_official	87:085cde657901	1515	* @brief Interrupt Handler to close Tx transfer
mbed_official	87:085cde657901	1516	* @param hspi: SPI handle
mbed_official	87:085cde657901	1517	* @retval void
mbed_official	87:085cde657901	1518	*/
mbed_official	87:085cde657901	1519	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1520	{
mbed_official	87:085cde657901	1521	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1522	{
mbed_official	87:085cde657901	1523	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1524	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1525	{
mbed_official	87:085cde657901	1526	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1527	}
mbed_official	87:085cde657901	1528	}
mbed_official	87:085cde657901	1529
mbed_official	87:085cde657901	1530	/* Disable TXE interrupt */
mbed_official	87:085cde657901	1531	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
mbed_official	87:085cde657901	1532
mbed_official	87:085cde657901	1533	/* Disable ERR interrupt if Receive process is finished */
mbed_official	87:085cde657901	1534	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	87:085cde657901	1535	{
mbed_official	87:085cde657901	1536	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1537
mbed_official	87:085cde657901	1538	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1539	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1540	{
mbed_official	87:085cde657901	1541	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1542	}
mbed_official	87:085cde657901	1543
mbed_official	87:085cde657901	1544	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1545	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1546	{
mbed_official	87:085cde657901	1547	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1548	}
mbed_official	87:085cde657901	1549
mbed_official	87:085cde657901	1550	/* Set state to READY before run the Callback Complete */
mbed_official	87:085cde657901	1551	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1552
mbed_official	87:085cde657901	1553	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1554	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1555	{
mbed_official	87:085cde657901	1556	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1557	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1558	{
mbed_official	87:085cde657901	1559	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1560	}
mbed_official	87:085cde657901	1561	else
mbed_official	87:085cde657901	1562	{
mbed_official	87:085cde657901	1563	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1564	}
mbed_official	87:085cde657901	1565	}
mbed_official	87:085cde657901	1566	else
mbed_official	87:085cde657901	1567	{
mbed_official	87:085cde657901	1568	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1569	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1570	}
mbed_official	87:085cde657901	1571	}
mbed_official	87:085cde657901	1572	}
mbed_official	87:085cde657901	1573
mbed_official	87:085cde657901	1574	/**
mbed_official	87:085cde657901	1575	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	87:085cde657901	1576	* @param hspi: SPI handle
mbed_official	87:085cde657901	1577	* @retval void
mbed_official	87:085cde657901	1578	*/
mbed_official	87:085cde657901	1579	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1580	{
mbed_official	87:085cde657901	1581	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	1582	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1583	{
mbed_official	87:085cde657901	1584	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	1585	}
mbed_official	87:085cde657901	1586	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	1587	else
mbed_official	87:085cde657901	1588	{
mbed_official	87:085cde657901	1589	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	1590	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	1591	}
mbed_official	87:085cde657901	1592	hspi->TxXferCount--;
mbed_official	87:085cde657901	1593
mbed_official	87:085cde657901	1594	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	1595	{
mbed_official	87:085cde657901	1596	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1597	{
mbed_official	87:085cde657901	1598	/* calculate and transfer CRC on Tx line */
mbed_official	87:085cde657901	1599	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1600	}
mbed_official	87:085cde657901	1601	SPI_TxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1602	}
mbed_official	87:085cde657901	1603	}
mbed_official	87:085cde657901	1604
mbed_official	87:085cde657901	1605	/**
mbed_official	87:085cde657901	1606	* @brief Interrupt Handler to close Rx transfer
mbed_official	87:085cde657901	1607	* @param hspi: SPI handle
mbed_official	87:085cde657901	1608	* @retval void
mbed_official	87:085cde657901	1609	*/
mbed_official	87:085cde657901	1610	static void SPI_RxClose_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1611	{
mbed_official	87:085cde657901	1612	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1613
mbed_official	87:085cde657901	1614	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1615	{
mbed_official	87:085cde657901	1616	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1617	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1618	{
mbed_official	87:085cde657901	1619	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1620	}
mbed_official	87:085cde657901	1621
mbed_official	87:085cde657901	1622	/* Read CRC to reset RXNE flag */
mbed_official	87:085cde657901	1623	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1624
mbed_official	87:085cde657901	1625	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1626	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1627	{
mbed_official	87:085cde657901	1628	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1629	}
mbed_official	87:085cde657901	1630
mbed_official	87:085cde657901	1631	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1632	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1633	{
mbed_official	87:085cde657901	1634	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1635
mbed_official	87:085cde657901	1636	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1637	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1638	}
mbed_official	87:085cde657901	1639	}
mbed_official	87:085cde657901	1640
mbed_official	87:085cde657901	1641	/* Disable RXNE and ERR interrupt */
mbed_official	87:085cde657901	1642	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official	87:085cde657901	1643
mbed_official	87:085cde657901	1644	/* if Transmit process is finished */
mbed_official	87:085cde657901	1645	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	87:085cde657901	1646	{
mbed_official	87:085cde657901	1647	/* Disable ERR interrupt */
mbed_official	87:085cde657901	1648	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1649
mbed_official	87:085cde657901	1650	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1651	{
mbed_official	87:085cde657901	1652	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1653	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1654	}
mbed_official	87:085cde657901	1655
mbed_official	87:085cde657901	1656	/* Set state to READY before run the Callback Complete */
mbed_official	87:085cde657901	1657	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1658	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1659	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1660	{
mbed_official	87:085cde657901	1661	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1662	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1663	{
mbed_official	87:085cde657901	1664	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1665	}else
mbed_official	87:085cde657901	1666	{
mbed_official	87:085cde657901	1667	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1668	}
mbed_official	87:085cde657901	1669	}
mbed_official	87:085cde657901	1670	else
mbed_official	87:085cde657901	1671	{
mbed_official	87:085cde657901	1672	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1673	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1674	}
mbed_official	87:085cde657901	1675	}
mbed_official	87:085cde657901	1676	}
mbed_official	87:085cde657901	1677
mbed_official	87:085cde657901	1678	/**
mbed_official	87:085cde657901	1679	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	87:085cde657901	1680	* @param hspi: SPI handle
mbed_official	87:085cde657901	1681	* @retval void
mbed_official	87:085cde657901	1682	*/
mbed_official	87:085cde657901	1683	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1684	{
mbed_official	87:085cde657901	1685	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1686	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1687	{
mbed_official	87:085cde657901	1688	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1689	}
mbed_official	87:085cde657901	1690	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1691	else
mbed_official	87:085cde657901	1692	{
mbed_official	87:085cde657901	1693	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1694	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1695	}
mbed_official	87:085cde657901	1696	hspi->RxXferCount--;
mbed_official	87:085cde657901	1697
mbed_official	87:085cde657901	1698	if(hspi->RxXferCount==0)
mbed_official	87:085cde657901	1699	{
mbed_official	87:085cde657901	1700	SPI_RxClose_IRQHandler(hspi);
mbed_official	87:085cde657901	1701	}
mbed_official	87:085cde657901	1702	}
mbed_official	87:085cde657901	1703
mbed_official	87:085cde657901	1704	/**
mbed_official	87:085cde657901	1705	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	87:085cde657901	1706	* @param hspi: SPI handle
mbed_official	87:085cde657901	1707	* @retval void
mbed_official	87:085cde657901	1708	*/
mbed_official	87:085cde657901	1709	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1710	{
mbed_official	87:085cde657901	1711	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1712	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1713	{
mbed_official	87:085cde657901	1714	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1715	}
mbed_official	87:085cde657901	1716	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1717	else
mbed_official	87:085cde657901	1718	{
mbed_official	87:085cde657901	1719	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1720	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1721	}
mbed_official	87:085cde657901	1722	hspi->RxXferCount--;
mbed_official	87:085cde657901	1723
mbed_official	87:085cde657901	1724	/* Enable CRC Transmission */
mbed_official	87:085cde657901	1725	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	1726	{
mbed_official	87:085cde657901	1727	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	87:085cde657901	1728	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1729	}
mbed_official	87:085cde657901	1730
mbed_official	87:085cde657901	1731	if(hspi->RxXferCount == 0)
mbed_official	87:085cde657901	1732	{
mbed_official	87:085cde657901	1733	SPI_RxClose_IRQHandler(hspi);
mbed_official	87:085cde657901	1734	}
mbed_official	87:085cde657901	1735	}
mbed_official	87:085cde657901	1736
mbed_official	87:085cde657901	1737	/**
mbed_official	87:085cde657901	1738	* @brief DMA SPI transmit process complete callback
mbed_official	87:085cde657901	1739	* @param hdma : DMA handle
mbed_official	87:085cde657901	1740	* @retval None
mbed_official	87:085cde657901	1741	*/
mbed_official	87:085cde657901	1742	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1743	{
mbed_official	87:085cde657901	1744	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1745
mbed_official	87:085cde657901	1746	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1747	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1748	{
mbed_official	87:085cde657901	1749	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1750	}
mbed_official	87:085cde657901	1751
mbed_official	87:085cde657901	1752	/* Disable Tx DMA Request */
mbed_official	87:085cde657901	1753	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1754
mbed_official	87:085cde657901	1755	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1756	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1757	{
mbed_official	87:085cde657901	1758	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1759	}
mbed_official	87:085cde657901	1760
mbed_official	87:085cde657901	1761	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1762
mbed_official	87:085cde657901	1763	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1764
mbed_official	87:085cde657901	1765	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1766	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1767	{
mbed_official	87:085cde657901	1768	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1769	}
mbed_official	87:085cde657901	1770
mbed_official	87:085cde657901	1771	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1772	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1773	{
mbed_official	87:085cde657901	1774	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1775	}
mbed_official	87:085cde657901	1776	else
mbed_official	87:085cde657901	1777	{
mbed_official	87:085cde657901	1778	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1779	}
mbed_official	87:085cde657901	1780	}
mbed_official	87:085cde657901	1781
mbed_official	87:085cde657901	1782	/**
mbed_official	87:085cde657901	1783	* @brief DMA SPI receive process complete callback
mbed_official	87:085cde657901	1784	* @param hdma : DMA handle
mbed_official	87:085cde657901	1785	* @retval None
mbed_official	87:085cde657901	1786	*/
mbed_official	87:085cde657901	1787	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1788	{
mbed_official	87:085cde657901	1789	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1790
mbed_official	87:085cde657901	1791	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1792
mbed_official	87:085cde657901	1793	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1794	{
mbed_official	87:085cde657901	1795	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1796	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1797	}
mbed_official	87:085cde657901	1798
mbed_official	87:085cde657901	1799	/* Disable Rx DMA Request */
mbed_official	87:085cde657901	1800	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	87:085cde657901	1801
mbed_official	87:085cde657901	1802	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1803	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1804	{
mbed_official	87:085cde657901	1805	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1806	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1807	{
mbed_official	87:085cde657901	1808	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1809	}
mbed_official	87:085cde657901	1810
mbed_official	87:085cde657901	1811	/* Read CRC */
mbed_official	87:085cde657901	1812	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1813
mbed_official	87:085cde657901	1814	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1815	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1816	{
mbed_official	87:085cde657901	1817	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1818	}
mbed_official	87:085cde657901	1819	}
mbed_official	87:085cde657901	1820
mbed_official	87:085cde657901	1821	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1822	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1823
mbed_official	87:085cde657901	1824	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1825	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1826	{
mbed_official	87:085cde657901	1827	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1828	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1829	}
mbed_official	87:085cde657901	1830
mbed_official	87:085cde657901	1831	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1832	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1833	{
mbed_official	87:085cde657901	1834	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1835	}
mbed_official	87:085cde657901	1836	else
mbed_official	87:085cde657901	1837	{
mbed_official	87:085cde657901	1838	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1839	}
mbed_official	87:085cde657901	1840	}
mbed_official	87:085cde657901	1841
mbed_official	87:085cde657901	1842	/**
mbed_official	87:085cde657901	1843	* @brief DMA SPI transmit receive process complete callback
mbed_official	87:085cde657901	1844	* @param hdma : DMA handle
mbed_official	87:085cde657901	1845	* @retval None
mbed_official	87:085cde657901	1846	*/
mbed_official	87:085cde657901	1847	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1848	{
mbed_official	87:085cde657901	1849	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1850
mbed_official	87:085cde657901	1851	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1852
mbed_official	87:085cde657901	1853	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1854	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1855	{
mbed_official	87:085cde657901	1856	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	87:085cde657901	1857	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	87:085cde657901	1858	{
mbed_official	87:085cde657901	1859	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1860	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1861	{
mbed_official	87:085cde657901	1862	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1863	}
mbed_official	87:085cde657901	1864	}
mbed_official	87:085cde657901	1865	/* Read CRC */
mbed_official	87:085cde657901	1866	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1867	}
mbed_official	87:085cde657901	1868
mbed_official	87:085cde657901	1869	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1870	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1871	{
mbed_official	87:085cde657901	1872	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1873	}
mbed_official	87:085cde657901	1874	/* Disable Tx DMA Request */
mbed_official	87:085cde657901	1875	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1876
mbed_official	87:085cde657901	1877	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1878	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1879	{
mbed_official	87:085cde657901	1880	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1881	}
mbed_official	87:085cde657901	1882
mbed_official	87:085cde657901	1883	/* Disable Rx DMA Request */
mbed_official	87:085cde657901	1884	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	87:085cde657901	1885
mbed_official	87:085cde657901	1886	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1887	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1888
mbed_official	87:085cde657901	1889	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1890
mbed_official	87:085cde657901	1891	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1892	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1893	{
mbed_official	87:085cde657901	1894	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1895	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1896	}
mbed_official	87:085cde657901	1897
mbed_official	87:085cde657901	1898	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1899	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1900	{
mbed_official	87:085cde657901	1901	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1902	}
mbed_official	87:085cde657901	1903	else
mbed_official	87:085cde657901	1904	{
mbed_official	87:085cde657901	1905	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1906	}
mbed_official	87:085cde657901	1907	}
mbed_official	87:085cde657901	1908
mbed_official	87:085cde657901	1909	/**
mbed_official	87:085cde657901	1910	* @brief DMA SPI communication error callback
mbed_official	87:085cde657901	1911	* @param hdma : DMA handle
mbed_official	87:085cde657901	1912	* @retval None
mbed_official	87:085cde657901	1913	*/
mbed_official	87:085cde657901	1914	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1915	{
mbed_official	87:085cde657901	1916	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1917	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1918	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1919	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1920	hspi->ErrorCode \|= HAL_SPI_ERROR_DMA;
mbed_official	87:085cde657901	1921	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1922	}
mbed_official	87:085cde657901	1923
mbed_official	87:085cde657901	1924	/**
mbed_official	87:085cde657901	1925	* @brief This function handles SPI Communication Timeout.
mbed_official	87:085cde657901	1926	* @param hspi: SPI handle
mbed_official	87:085cde657901	1927	* @retval HAL status
mbed_official	87:085cde657901	1928	*/
mbed_official	87:085cde657901	1929	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	87:085cde657901	1930	{
mbed_official	87:085cde657901	1931	uint32_t timeout = 0;
mbed_official	87:085cde657901	1932
mbed_official	87:085cde657901	1933	timeout = HAL_GetTick() + Timeout;
mbed_official	87:085cde657901	1934
mbed_official	87:085cde657901	1935	/* Wait until flag is set */
mbed_official	87:085cde657901	1936	if(Status == RESET)
mbed_official	87:085cde657901	1937	{
mbed_official	87:085cde657901	1938	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	87:085cde657901	1939	{
mbed_official	87:085cde657901	1940	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	1941	{
mbed_official	87:085cde657901	1942	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	1943	{
mbed_official	87:085cde657901	1944	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	1945	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	1946	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	1947
mbed_official	87:085cde657901	1948	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	1949	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1950
mbed_official	87:085cde657901	1951	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1952	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1953
mbed_official	87:085cde657901	1954	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1955	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1956	{
mbed_official	87:085cde657901	1957	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1958	}
mbed_official	87:085cde657901	1959
mbed_official	87:085cde657901	1960	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1961
mbed_official	87:085cde657901	1962	/* Process Unlocked */
mbed_official	87:085cde657901	1963	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1964
mbed_official	87:085cde657901	1965	return HAL_TIMEOUT;
mbed_official	87:085cde657901	1966	}
mbed_official	87:085cde657901	1967	}
mbed_official	87:085cde657901	1968	}
mbed_official	87:085cde657901	1969	}
mbed_official	87:085cde657901	1970	else
mbed_official	87:085cde657901	1971	{
mbed_official	87:085cde657901	1972	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	87:085cde657901	1973	{
mbed_official	87:085cde657901	1974	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	1975	{
mbed_official	87:085cde657901	1976	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	1977	{
mbed_official	87:085cde657901	1978	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	1979	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	1980	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	1981
mbed_official	87:085cde657901	1982	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	1983	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1984
mbed_official	87:085cde657901	1985	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1986	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1987
mbed_official	87:085cde657901	1988	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1989	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1990	{
mbed_official	87:085cde657901	1991	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1992	}
mbed_official	87:085cde657901	1993
mbed_official	87:085cde657901	1994	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1995
mbed_official	87:085cde657901	1996	/* Process Unlocked */
mbed_official	87:085cde657901	1997	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1998
mbed_official	87:085cde657901	1999	return HAL_TIMEOUT;
mbed_official	87:085cde657901	2000	}
mbed_official	87:085cde657901	2001	}
mbed_official	87:085cde657901	2002	}
mbed_official	87:085cde657901	2003	}
mbed_official	87:085cde657901	2004	return HAL_OK;
mbed_official	87:085cde657901	2005	}
mbed_official	87:085cde657901	2006
mbed_official	87:085cde657901	2007
mbed_official	87:085cde657901	2008	/**
mbed_official	87:085cde657901	2009	* @}
mbed_official	87:085cde657901	2010	*/
mbed_official	87:085cde657901	2011
mbed_official	87:085cde657901	2012	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	87:085cde657901	2013	/**
mbed_official	87:085cde657901	2014	* @}
mbed_official	87:085cde657901	2015	*/
mbed_official	87:085cde657901	2016
mbed_official	87:085cde657901	2017	/**
mbed_official	87:085cde657901	2018	* @}
mbed_official	87:085cde657901	2019	*/
mbed_official	87:085cde657901	2020
mbed_official	87:085cde657901	2021	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	09 Aug 2015
Imports:	2
Forks:	0
Commits:	604
Dependents:	0
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@87:085cde657901, 2014-02-08 (annotated)

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