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nRF51822
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nrf51_bitfields.h
00001 /* Copyright (c) 2013, Nordic Semiconductor ASA 00002 * All rights reserved. 00003 * 00004 * Redistribution and use in source and binary forms, with or without 00005 * modification, are permitted provided that the following conditions are met: 00006 * 00007 * * Redistributions of source code must retain the above copyright notice, this 00008 * list of conditions and the following disclaimer. 00009 * 00010 * * Redistributions in binary form must reproduce the above copyright notice, 00011 * this list of conditions and the following disclaimer in the documentation 00012 * and/or other materials provided with the distribution. 00013 * 00014 * * Neither the name of Nordic Semiconductor ASA nor the names of its 00015 * contributors may be used to endorse or promote products derived from 00016 * this software without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00019 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00021 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00024 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00025 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00026 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00027 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00028 * 00029 */ 00030 #ifndef __NRF51_BITS_H 00031 #define __NRF51_BITS_H 00032 00033 /*lint ++flb "Enter library region */ 00034 00035 #include <core_cm0.h> 00036 00037 /* Peripheral: AAR */ 00038 /* Description: Accelerated Address Resolver. */ 00039 00040 /* Register: AAR_INTENSET */ 00041 /* Description: Interrupt enable set register. */ 00042 00043 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */ 00044 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 00045 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 00046 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 00047 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 00048 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ 00049 00050 /* Bit 1 : Enable interrupt on RESOLVED event. */ 00051 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 00052 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 00053 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 00054 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 00055 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ 00056 00057 /* Bit 0 : Enable interrupt on END event. */ 00058 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 00059 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 00060 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 00061 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 00062 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 00063 00064 /* Register: AAR_INTENCLR */ 00065 /* Description: Interrupt enable clear register. */ 00066 00067 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */ 00068 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 00069 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 00070 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 00071 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 00072 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ 00073 00074 /* Bit 1 : Disable interrupt on RESOLVED event. */ 00075 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 00076 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 00077 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 00078 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 00079 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ 00080 00081 /* Bit 0 : Disable interrupt on ENDKSGEN event. */ 00082 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 00083 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 00084 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 00085 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 00086 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 00087 00088 /* Register: AAR_STATUS */ 00089 /* Description: Resolution status. */ 00090 00091 /* Bits 3..0 : The IRK used last time an address was resolved. */ 00092 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 00093 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 00094 00095 /* Register: AAR_ENABLE */ 00096 /* Description: Enable AAR. */ 00097 00098 /* Bits 1..0 : Enable AAR. */ 00099 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 00100 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 00101 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ 00102 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ 00103 00104 /* Register: AAR_NIRK */ 00105 /* Description: Number of Identity root Keys in the IRK data structure. */ 00106 00107 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ 00108 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 00109 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 00110 00111 /* Register: AAR_POWER */ 00112 /* Description: Peripheral power control. */ 00113 00114 /* Bit 0 : Peripheral power control. */ 00115 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 00116 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 00117 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 00118 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 00119 00120 00121 /* Peripheral: ADC */ 00122 /* Description: Analog to digital converter. */ 00123 00124 /* Register: ADC_INTENSET */ 00125 /* Description: Interrupt enable set register. */ 00126 00127 /* Bit 0 : Enable interrupt on END event. */ 00128 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 00129 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 00130 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 00131 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 00132 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 00133 00134 /* Register: ADC_INTENCLR */ 00135 /* Description: Interrupt enable clear register. */ 00136 00137 /* Bit 0 : Disable interrupt on END event. */ 00138 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 00139 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 00140 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 00141 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 00142 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 00143 00144 /* Register: ADC_BUSY */ 00145 /* Description: ADC busy register. */ 00146 00147 /* Bit 0 : ADC busy register. */ 00148 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ 00149 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ 00150 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ 00151 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ 00152 00153 /* Register: ADC_ENABLE */ 00154 /* Description: ADC enable. */ 00155 00156 /* Bits 1..0 : ADC enable. */ 00157 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 00158 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 00159 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ 00160 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ 00161 00162 /* Register: ADC_CONFIG */ 00163 /* Description: ADC configuration register. */ 00164 00165 /* Bits 17..16 : ADC external reference pin selection. */ 00166 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ 00167 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 00168 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ 00169 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ 00170 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ 00171 00172 /* Bits 15..8 : ADC analog pin selection. */ 00173 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 00174 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 00175 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ 00176 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ 00177 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ 00178 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ 00179 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ 00180 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ 00181 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ 00182 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ 00183 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ 00184 00185 /* Bits 6..5 : ADC reference selection. */ 00186 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ 00187 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 00188 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ 00189 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ 00190 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ 00191 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ 00192 00193 /* Bits 4..2 : ADC input selection. */ 00194 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ 00195 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ 00196 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ 00197 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ 00198 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ 00199 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ 00200 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ 00201 00202 /* Bits 1..0 : ADC resolution. */ 00203 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ 00204 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ 00205 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ 00206 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ 00207 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ 00208 00209 /* Register: ADC_RESULT */ 00210 /* Description: Result of ADC conversion. */ 00211 00212 /* Bits 9..0 : Result of ADC conversion. */ 00213 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 00214 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 00215 00216 /* Register: ADC_POWER */ 00217 /* Description: Peripheral power control. */ 00218 00219 /* Bit 0 : Peripheral power control. */ 00220 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 00221 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 00222 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 00223 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 00224 00225 00226 /* Peripheral: AMLI */ 00227 /* Description: AHB Multi-Layer Interface. */ 00228 00229 /* Register: AMLI_RAMPRI_CPU0 */ 00230 /* Description: Configurable priority configuration register for CPU0. */ 00231 00232 /* Bits 31..28 : Configuration field for RAM block 7. */ 00233 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00234 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00235 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 00236 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 00237 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 00238 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 00239 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 00240 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 00241 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 00242 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 00243 00244 /* Bits 27..24 : Configuration field for RAM block 6. */ 00245 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00246 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00247 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 00248 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 00249 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 00250 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 00251 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 00252 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 00253 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 00254 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 00255 00256 /* Bits 23..20 : Configuration field for RAM block 5. */ 00257 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00258 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00259 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 00260 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 00261 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 00262 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 00263 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 00264 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 00265 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 00266 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 00267 00268 /* Bits 19..16 : Configuration field for RAM block 4. */ 00269 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00270 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00271 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 00272 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 00273 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 00274 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 00275 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 00276 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 00277 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 00278 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 00279 00280 /* Bits 15..12 : Configuration field for RAM block 3. */ 00281 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00282 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00283 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 00284 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 00285 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 00286 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 00287 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 00288 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 00289 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 00290 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 00291 00292 /* Bits 11..8 : Configuration field for RAM block 2. */ 00293 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00294 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00295 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 00296 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 00297 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 00298 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 00299 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 00300 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 00301 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 00302 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 00303 00304 /* Bits 7..4 : Configuration field for RAM block 1. */ 00305 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00306 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00307 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 00308 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 00309 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 00310 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 00311 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 00312 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 00313 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 00314 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 00315 00316 /* Bits 3..0 : Configuration field for RAM block 0. */ 00317 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00318 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00319 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 00320 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 00321 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 00322 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 00323 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 00324 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 00325 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 00326 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 00327 00328 /* Register: AMLI_RAMPRI_SPIS1 */ 00329 /* Description: Configurable priority configuration register for SPIS1. */ 00330 00331 /* Bits 31..28 : Configuration field for RAM block 7. */ 00332 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00333 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00334 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 00335 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 00336 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 00337 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 00338 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 00339 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 00340 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 00341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 00342 00343 /* Bits 27..24 : Configuration field for RAM block 6. */ 00344 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00345 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 00347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 00348 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 00349 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 00350 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 00351 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 00352 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 00353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 00354 00355 /* Bits 23..20 : Configuration field for RAM block 5. */ 00356 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00357 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 00359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 00360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 00361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 00362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 00363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 00364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 00365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 00366 00367 /* Bits 19..16 : Configuration field for RAM block 4. */ 00368 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00369 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00370 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 00371 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 00372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 00373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 00374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 00375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 00376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 00377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 00378 00379 /* Bits 15..12 : Configuration field for RAM block 3. */ 00380 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00381 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00382 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 00383 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 00384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 00385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 00386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 00387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 00388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 00389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 00390 00391 /* Bits 11..8 : Configuration field for RAM block 2. */ 00392 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00393 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00394 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 00395 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 00396 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 00397 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 00398 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 00399 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 00400 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 00401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 00402 00403 /* Bits 7..4 : Configuration field for RAM block 1. */ 00404 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00405 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00406 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 00407 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 00408 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 00409 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 00410 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 00411 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 00412 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 00413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 00414 00415 /* Bits 3..0 : Configuration field for RAM block 0. */ 00416 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00417 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00418 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 00419 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 00420 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 00421 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 00422 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 00423 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 00424 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 00425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 00426 00427 /* Register: AMLI_RAMPRI_RADIO */ 00428 /* Description: Configurable priority configuration register for RADIO. */ 00429 00430 /* Bits 31..28 : Configuration field for RAM block 7. */ 00431 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00432 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00433 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 00434 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 00435 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 00436 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 00437 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 00438 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 00439 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 00440 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 00441 00442 /* Bits 27..24 : Configuration field for RAM block 6. */ 00443 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00444 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00445 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 00446 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 00447 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 00448 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 00449 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 00450 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 00451 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 00452 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 00453 00454 /* Bits 23..20 : Configuration field for RAM block 5. */ 00455 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00456 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00457 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 00458 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 00459 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 00460 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 00461 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 00462 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 00463 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 00464 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 00465 00466 /* Bits 19..16 : Configuration field for RAM block 4. */ 00467 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00468 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00469 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 00470 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 00471 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 00472 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 00473 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 00474 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 00475 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 00476 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 00477 00478 /* Bits 15..12 : Configuration field for RAM block 3. */ 00479 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00480 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00481 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 00482 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 00483 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 00484 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 00485 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 00486 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 00487 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 00488 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 00489 00490 /* Bits 11..8 : Configuration field for RAM block 2. */ 00491 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00492 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00493 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 00494 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 00495 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 00496 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 00497 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 00498 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 00499 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 00500 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 00501 00502 /* Bits 7..4 : Configuration field for RAM block 1. */ 00503 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00504 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00505 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 00506 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 00507 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 00508 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 00509 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 00510 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 00511 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 00512 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 00513 00514 /* Bits 3..0 : Configuration field for RAM block 0. */ 00515 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00516 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00517 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 00518 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 00519 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 00520 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 00521 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 00522 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 00523 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 00524 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 00525 00526 /* Register: AMLI_RAMPRI_ECB */ 00527 /* Description: Configurable priority configuration register for ECB. */ 00528 00529 /* Bits 31..28 : Configuration field for RAM block 7. */ 00530 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00531 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00532 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 00533 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 00534 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 00535 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 00536 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 00537 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 00538 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 00539 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 00540 00541 /* Bits 27..24 : Configuration field for RAM block 6. */ 00542 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00543 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00544 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 00545 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 00546 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 00547 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 00548 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 00549 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 00550 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 00551 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 00552 00553 /* Bits 23..20 : Configuration field for RAM block 5. */ 00554 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00555 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00556 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 00557 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 00558 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 00559 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 00560 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 00561 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 00562 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 00563 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 00564 00565 /* Bits 19..16 : Configuration field for RAM block 4. */ 00566 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00567 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00568 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 00569 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 00570 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 00571 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 00572 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 00573 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 00574 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 00575 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 00576 00577 /* Bits 15..12 : Configuration field for RAM block 3. */ 00578 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00579 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00580 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 00581 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 00582 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 00583 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 00584 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 00585 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 00586 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 00587 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 00588 00589 /* Bits 11..8 : Configuration field for RAM block 2. */ 00590 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00591 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00592 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 00593 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 00594 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 00595 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 00596 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 00597 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 00598 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 00599 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 00600 00601 /* Bits 7..4 : Configuration field for RAM block 1. */ 00602 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00603 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00604 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 00605 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 00606 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 00607 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 00608 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 00609 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 00610 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 00611 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 00612 00613 /* Bits 3..0 : Configuration field for RAM block 0. */ 00614 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00615 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00616 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 00617 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 00618 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 00619 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 00620 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 00621 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 00622 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 00623 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 00624 00625 /* Register: AMLI_RAMPRI_CCM */ 00626 /* Description: Configurable priority configuration register for CCM. */ 00627 00628 /* Bits 31..28 : Configuration field for RAM block 7. */ 00629 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00630 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00631 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 00632 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 00633 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 00634 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 00635 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 00636 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 00637 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 00638 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 00639 00640 /* Bits 27..24 : Configuration field for RAM block 6. */ 00641 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00642 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00643 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 00644 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 00645 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 00646 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 00647 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 00648 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 00649 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 00650 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 00651 00652 /* Bits 23..20 : Configuration field for RAM block 5. */ 00653 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00654 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00655 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 00656 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 00657 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 00658 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 00659 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 00660 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 00661 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 00662 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 00663 00664 /* Bits 19..16 : Configuration field for RAM block 4. */ 00665 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00666 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00667 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 00668 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 00669 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 00670 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 00671 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 00672 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 00673 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 00674 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 00675 00676 /* Bits 15..12 : Configuration field for RAM block 3. */ 00677 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00678 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00679 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 00680 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 00681 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 00682 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 00683 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 00684 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 00685 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 00686 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 00687 00688 /* Bits 11..8 : Configuration field for RAM block 2. */ 00689 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00690 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00691 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 00692 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 00693 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 00694 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 00695 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 00696 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 00697 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 00698 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 00699 00700 /* Bits 7..4 : Configuration field for RAM block 1. */ 00701 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00702 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00703 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 00704 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 00705 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 00706 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 00707 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 00708 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 00709 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 00710 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 00711 00712 /* Bits 3..0 : Configuration field for RAM block 0. */ 00713 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00714 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00715 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 00716 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 00717 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 00718 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 00719 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 00720 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 00721 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 00722 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 00723 00724 /* Register: AMLI_RAMPRI_AAR */ 00725 /* Description: Configurable priority configuration register for AAR. */ 00726 00727 /* Bits 31..28 : Configuration field for RAM block 7. */ 00728 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00729 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00730 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 00731 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 00732 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 00733 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 00734 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 00735 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 00736 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 00737 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 00738 00739 /* Bits 27..24 : Configuration field for RAM block 6. */ 00740 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00741 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00742 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 00743 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 00744 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 00745 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 00746 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 00747 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 00748 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 00749 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 00750 00751 /* Bits 23..20 : Configuration field for RAM block 5. */ 00752 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00753 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00754 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 00755 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 00756 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 00757 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 00758 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 00759 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 00760 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 00761 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 00762 00763 /* Bits 19..16 : Configuration field for RAM block 4. */ 00764 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00765 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00766 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 00767 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 00768 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 00769 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 00770 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 00771 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 00772 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 00773 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 00774 00775 /* Bits 15..12 : Configuration field for RAM block 3. */ 00776 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00777 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00778 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 00779 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 00780 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 00781 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 00782 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 00783 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 00784 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 00785 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 00786 00787 /* Bits 11..8 : Configuration field for RAM block 2. */ 00788 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00789 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00790 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 00791 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 00792 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 00793 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 00794 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 00795 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 00796 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 00797 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 00798 00799 /* Bits 7..4 : Configuration field for RAM block 1. */ 00800 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00801 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00802 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 00803 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 00804 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 00805 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 00806 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 00807 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 00808 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 00809 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 00810 00811 /* Bits 3..0 : Configuration field for RAM block 0. */ 00812 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00813 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00814 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 00815 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 00816 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 00817 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 00818 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 00819 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 00820 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 00821 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 00822 00823 /* Peripheral: CCM */ 00824 /* Description: AES CCM Mode Encryption. */ 00825 00826 /* Register: CCM_SHORTS */ 00827 /* Description: Shortcuts for the CCM. */ 00828 00829 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ 00830 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 00831 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 00832 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ 00833 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ 00834 00835 /* Register: CCM_INTENSET */ 00836 /* Description: Interrupt enable set register. */ 00837 00838 /* Bit 2 : Enable interrupt on ERROR event. */ 00839 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 00840 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 00841 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 00842 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 00843 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 00844 00845 /* Bit 1 : Enable interrupt on ENDCRYPT event. */ 00846 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 00847 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 00848 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ 00849 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ 00850 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ 00851 00852 /* Bit 0 : Enable interrupt on ENDKSGEN event. */ 00853 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 00854 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 00855 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ 00856 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ 00857 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ 00858 00859 /* Register: CCM_INTENCLR */ 00860 /* Description: Interrupt enable clear register. */ 00861 00862 /* Bit 2 : Disable interrupt on ERROR event. */ 00863 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 00864 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 00865 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 00866 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 00867 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 00868 00869 /* Bit 1 : Disable interrupt on ENDCRYPT event. */ 00870 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 00871 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 00872 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ 00873 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ 00874 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ 00875 00876 /* Bit 0 : Disable interrupt on ENDKSGEN event. */ 00877 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 00878 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 00879 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ 00880 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ 00881 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ 00882 00883 /* Register: CCM_MICSTATUS */ 00884 /* Description: CCM RX MIC check result. */ 00885 00886 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ 00887 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 00888 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 00889 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ 00890 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ 00891 00892 /* Register: CCM_ENABLE */ 00893 /* Description: CCM enable. */ 00894 00895 /* Bits 1..0 : CCM enable. */ 00896 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 00897 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 00898 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ 00899 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ 00900 00901 /* Register: CCM_MODE */ 00902 /* Description: Operation mode. */ 00903 00904 /* Bit 0 : CCM mode operation. */ 00905 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 00906 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 00907 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ 00908 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ 00909 00910 /* Register: CCM_POWER */ 00911 /* Description: Peripheral power control. */ 00912 00913 /* Bit 0 : Peripheral power control. */ 00914 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 00915 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 00916 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 00917 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 00918 00919 00920 /* Peripheral: CLOCK */ 00921 /* Description: Clock control. */ 00922 00923 /* Register: CLOCK_INTENSET */ 00924 /* Description: Interrupt enable set register. */ 00925 00926 /* Bit 4 : Enable interrupt on CTTO event. */ 00927 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 00928 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ 00929 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ 00930 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ 00931 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ 00932 00933 /* Bit 3 : Enable interrupt on DONE event. */ 00934 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ 00935 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 00936 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ 00937 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ 00938 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ 00939 00940 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ 00941 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 00942 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 00943 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 00944 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 00945 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ 00946 00947 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ 00948 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 00949 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 00950 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 00951 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 00952 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ 00953 00954 /* Register: CLOCK_INTENCLR */ 00955 /* Description: Interrupt enable clear register. */ 00956 00957 /* Bit 4 : Disable interrupt on CTTO event. */ 00958 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 00959 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ 00960 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ 00961 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ 00962 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ 00963 00964 /* Bit 3 : Disable interrupt on DONE event. */ 00965 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ 00966 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 00967 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ 00968 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ 00969 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ 00970 00971 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ 00972 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 00973 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 00974 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 00975 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 00976 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ 00977 00978 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ 00979 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 00980 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 00981 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 00982 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 00983 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ 00984 00985 /* Register: CLOCK_HFCLKRUN */ 00986 /* Description: Task HFCLKSTART trigger status. */ 00987 00988 /* Bit 0 : Task HFCLKSTART trigger status. */ 00989 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 00990 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 00991 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ 00992 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ 00993 00994 /* Register: CLOCK_HFCLKSTAT */ 00995 /* Description: High frequency clock status. */ 00996 00997 /* Bit 16 : State for the HFCLK. */ 00998 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 00999 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 01000 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ 01001 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ 01002 01003 /* Bit 0 : Active clock source for the HF clock. */ 01004 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 01005 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 01006 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ 01007 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ 01008 01009 /* Register: CLOCK_LFCLKRUN */ 01010 /* Description: Task LFCLKSTART triggered status. */ 01011 01012 /* Bit 0 : Task LFCLKSTART triggered status. */ 01013 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 01014 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 01015 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ 01016 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ 01017 01018 /* Register: CLOCK_LFCLKSTAT */ 01019 /* Description: Low frequency clock status. */ 01020 01021 /* Bit 16 : State for the LF clock. */ 01022 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 01023 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 01024 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ 01025 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ 01026 01027 /* Bits 1..0 : Active clock source for the LF clock. */ 01028 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 01029 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 01030 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ 01031 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ 01032 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ 01033 01034 /* Register: CLOCK_LFCLKSRCCOPY */ 01035 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ 01036 01037 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ 01038 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 01039 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 01040 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ 01041 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ 01042 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ 01043 01044 /* Register: CLOCK_LFCLKSRC */ 01045 /* Description: Clock source for the LFCLK clock. */ 01046 01047 /* Bits 1..0 : Clock source. */ 01048 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 01049 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 01050 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ 01051 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ 01052 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ 01053 01054 /* Register: CLOCK_CTIV */ 01055 /* Description: Calibration timer interval. */ 01056 01057 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ 01058 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ 01059 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ 01060 01061 /* Register: CLOCK_XTALFREQ */ 01062 /* Description: Crystal frequency. */ 01063 01064 /* Bits 7..0 : External Xtal frequency selection. */ 01065 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ 01066 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ 01067 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ 01068 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ 01069 01070 01071 /* Peripheral: ECB */ 01072 /* Description: AES ECB Mode Encryption. */ 01073 01074 /* Register: ECB_INTENSET */ 01075 /* Description: Interrupt enable set register. */ 01076 01077 /* Bit 1 : Enable interrupt on ERRORECB event. */ 01078 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 01079 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 01080 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ 01081 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ 01082 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ 01083 01084 /* Bit 0 : Enable interrupt on ENDECB event. */ 01085 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 01086 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 01087 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ 01088 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ 01089 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ 01090 01091 /* Register: ECB_INTENCLR */ 01092 /* Description: Interrupt enable clear register. */ 01093 01094 /* Bit 1 : Disable interrupt on ERRORECB event. */ 01095 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 01096 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 01097 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ 01098 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ 01099 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ 01100 01101 /* Bit 0 : Disable interrupt on ENDECB event. */ 01102 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 01103 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 01104 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ 01105 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ 01106 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ 01107 01108 /* Register: ECB_POWER */ 01109 /* Description: Peripheral power control. */ 01110 01111 /* Bit 0 : Peripheral power control. */ 01112 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 01113 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 01114 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 01115 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 01116 01117 01118 /* Peripheral: FICR */ 01119 /* Description: Factory Information Configuration. */ 01120 01121 /* Register: FICR_PPFC */ 01122 /* Description: Pre-programmed factory code present. */ 01123 01124 /* Bits 7..0 : Pre-programmed factory code present. */ 01125 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ 01126 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ 01127 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ 01128 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ 01129 01130 /* Register: FICR_CONFIGID */ 01131 /* Description: Configuration identifier. */ 01132 01133 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ 01134 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ 01135 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ 01136 01137 /* Bits 15..0 : Hardware Identification Number. */ 01138 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ 01139 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ 01140 01141 /* Register: FICR_DEVICEADDRTYPE */ 01142 /* Description: Device address type. */ 01143 01144 /* Bit 0 : Device address type. */ 01145 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ 01146 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ 01147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ 01148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ 01149 01150 /* Register: FICR_OVERRIDEEN */ 01151 /* Description: Radio calibration override enable. */ 01152 01153 /* Bit 3 : Override default values for BLE_1Mbit mode. */ 01154 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ 01155 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ 01156 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ 01157 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ 01158 01159 /* Bit 0 : Override default values for NRF_1Mbit mode. */ 01160 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ 01161 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ 01162 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ 01163 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ 01164 01165 /* Register: FICR_INFO_PART */ 01166 /* Description: Part code */ 01167 01168 /* Bits 31..0 : Part code */ 01169 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ 01170 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ 01171 #define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */ 01172 #define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */ 01173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 01174 01175 /* Register: FICR_INFO_VARIANT */ 01176 /* Description: Part variant */ 01177 01178 /* Bits 31..0 : Part variant */ 01179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 01180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 01181 #define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */ 01182 #define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */ 01183 #define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */ 01184 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 01185 01186 /* Register: FICR_INFO_PACKAGE */ 01187 /* Description: Package option */ 01188 01189 /* Bits 31..0 : Package option */ 01190 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ 01191 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ 01192 #define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */ 01193 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */ 01194 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */ 01195 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */ 01196 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */ 01197 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 01198 01199 /* Register: FICR_INFO_RAM */ 01200 /* Description: RAM variant */ 01201 01202 /* Bits 31..0 : RAM variant */ 01203 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 01204 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 01205 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 01206 #define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */ 01207 #define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */ 01208 01209 /* Register: FICR_INFO_FLASH */ 01210 /* Description: Flash variant */ 01211 01212 /* Bits 31..0 : Flash variant */ 01213 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 01214 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 01215 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 01216 #define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */ 01217 #define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */ 01218 01219 01220 /* Peripheral: GPIO */ 01221 /* Description: General purpose input and output. */ 01222 01223 /* Register: GPIO_OUT */ 01224 /* Description: Write GPIO port. */ 01225 01226 /* Bit 31 : Pin 31. */ 01227 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 01228 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 01229 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ 01230 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ 01231 01232 /* Bit 30 : Pin 30. */ 01233 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 01234 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 01235 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ 01236 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ 01237 01238 /* Bit 29 : Pin 29. */ 01239 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 01240 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 01241 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ 01242 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ 01243 01244 /* Bit 28 : Pin 28. */ 01245 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 01246 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 01247 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ 01248 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ 01249 01250 /* Bit 27 : Pin 27. */ 01251 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 01252 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 01253 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ 01254 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ 01255 01256 /* Bit 26 : Pin 26. */ 01257 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 01258 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 01259 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ 01260 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ 01261 01262 /* Bit 25 : Pin 25. */ 01263 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 01264 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 01265 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ 01266 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ 01267 01268 /* Bit 24 : Pin 24. */ 01269 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 01270 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 01271 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ 01272 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ 01273 01274 /* Bit 23 : Pin 23. */ 01275 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 01276 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 01277 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ 01278 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ 01279 01280 /* Bit 22 : Pin 22. */ 01281 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 01282 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 01283 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ 01284 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ 01285 01286 /* Bit 21 : Pin 21. */ 01287 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 01288 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 01289 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ 01290 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ 01291 01292 /* Bit 20 : Pin 20. */ 01293 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 01294 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 01295 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ 01296 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ 01297 01298 /* Bit 19 : Pin 19. */ 01299 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 01300 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 01301 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ 01302 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ 01303 01304 /* Bit 18 : Pin 18. */ 01305 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 01306 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 01307 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ 01308 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ 01309 01310 /* Bit 17 : Pin 17. */ 01311 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 01312 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 01313 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ 01314 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ 01315 01316 /* Bit 16 : Pin 16. */ 01317 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 01318 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 01319 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ 01320 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ 01321 01322 /* Bit 15 : Pin 15. */ 01323 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 01324 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 01325 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ 01326 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ 01327 01328 /* Bit 14 : Pin 14. */ 01329 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 01330 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 01331 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ 01332 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ 01333 01334 /* Bit 13 : Pin 13. */ 01335 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 01336 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 01337 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ 01338 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ 01339 01340 /* Bit 12 : Pin 12. */ 01341 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 01342 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 01343 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ 01344 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ 01345 01346 /* Bit 11 : Pin 11. */ 01347 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 01348 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 01349 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ 01350 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ 01351 01352 /* Bit 10 : Pin 10. */ 01353 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 01354 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 01355 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ 01356 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ 01357 01358 /* Bit 9 : Pin 9. */ 01359 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 01360 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 01361 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ 01362 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ 01363 01364 /* Bit 8 : Pin 8. */ 01365 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 01366 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 01367 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ 01368 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ 01369 01370 /* Bit 7 : Pin 7. */ 01371 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 01372 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 01373 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ 01374 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ 01375 01376 /* Bit 6 : Pin 6. */ 01377 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 01378 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 01379 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ 01380 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ 01381 01382 /* Bit 5 : Pin 5. */ 01383 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 01384 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 01385 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ 01386 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ 01387 01388 /* Bit 4 : Pin 4. */ 01389 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 01390 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 01391 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ 01392 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ 01393 01394 /* Bit 3 : Pin 3. */ 01395 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 01396 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 01397 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ 01398 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ 01399 01400 /* Bit 2 : Pin 2. */ 01401 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 01402 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 01403 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ 01404 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ 01405 01406 /* Bit 1 : Pin 1. */ 01407 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 01408 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 01409 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ 01410 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ 01411 01412 /* Bit 0 : Pin 0. */ 01413 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 01414 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 01415 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ 01416 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ 01417 01418 /* Register: GPIO_OUTSET */ 01419 /* Description: Set individual bits in GPIO port. */ 01420 01421 /* Bit 31 : Pin 31. */ 01422 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 01423 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 01424 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ 01425 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ 01426 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ 01427 01428 /* Bit 30 : Pin 30. */ 01429 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 01430 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 01431 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ 01432 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ 01433 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ 01434 01435 /* Bit 29 : Pin 29. */ 01436 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 01437 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 01438 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ 01439 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ 01440 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ 01441 01442 /* Bit 28 : Pin 28. */ 01443 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 01444 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 01445 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ 01446 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ 01447 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ 01448 01449 /* Bit 27 : Pin 27. */ 01450 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 01451 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 01452 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ 01453 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ 01454 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ 01455 01456 /* Bit 26 : Pin 26. */ 01457 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 01458 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 01459 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ 01460 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ 01461 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ 01462 01463 /* Bit 25 : Pin 25. */ 01464 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 01465 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 01466 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ 01467 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ 01468 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ 01469 01470 /* Bit 24 : Pin 24. */ 01471 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 01472 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 01473 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ 01474 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ 01475 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ 01476 01477 /* Bit 23 : Pin 23. */ 01478 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 01479 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 01480 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ 01481 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ 01482 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ 01483 01484 /* Bit 22 : Pin 22. */ 01485 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 01486 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 01487 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ 01488 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ 01489 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ 01490 01491 /* Bit 21 : Pin 21. */ 01492 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 01493 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 01494 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ 01495 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ 01496 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ 01497 01498 /* Bit 20 : Pin 20. */ 01499 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 01500 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 01501 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ 01502 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ 01503 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ 01504 01505 /* Bit 19 : Pin 19. */ 01506 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 01507 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 01508 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ 01509 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ 01510 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ 01511 01512 /* Bit 18 : Pin 18. */ 01513 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 01514 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 01515 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ 01516 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ 01517 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ 01518 01519 /* Bit 17 : Pin 17. */ 01520 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 01521 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 01522 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ 01523 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ 01524 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ 01525 01526 /* Bit 16 : Pin 16. */ 01527 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 01528 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 01529 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ 01530 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ 01531 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ 01532 01533 /* Bit 15 : Pin 15. */ 01534 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 01535 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 01536 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ 01537 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ 01538 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ 01539 01540 /* Bit 14 : Pin 14. */ 01541 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 01542 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 01543 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ 01544 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ 01545 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ 01546 01547 /* Bit 13 : Pin 13. */ 01548 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 01549 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 01550 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ 01551 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ 01552 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ 01553 01554 /* Bit 12 : Pin 12. */ 01555 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 01556 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 01557 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ 01558 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ 01559 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ 01560 01561 /* Bit 11 : Pin 11. */ 01562 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 01563 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 01564 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ 01565 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ 01566 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ 01567 01568 /* Bit 10 : Pin 10. */ 01569 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 01570 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 01571 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ 01572 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ 01573 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ 01574 01575 /* Bit 9 : Pin 9. */ 01576 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 01577 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 01578 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ 01579 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ 01580 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ 01581 01582 /* Bit 8 : Pin 8. */ 01583 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 01584 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 01585 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ 01586 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ 01587 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ 01588 01589 /* Bit 7 : Pin 7. */ 01590 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 01591 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 01592 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ 01593 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ 01594 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ 01595 01596 /* Bit 6 : Pin 6. */ 01597 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 01598 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 01599 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ 01600 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ 01601 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ 01602 01603 /* Bit 5 : Pin 5. */ 01604 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 01605 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 01606 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ 01607 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ 01608 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ 01609 01610 /* Bit 4 : Pin 4. */ 01611 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 01612 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 01613 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ 01614 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ 01615 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ 01616 01617 /* Bit 3 : Pin 3. */ 01618 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 01619 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 01620 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ 01621 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ 01622 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ 01623 01624 /* Bit 2 : Pin 2. */ 01625 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 01626 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 01627 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ 01628 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ 01629 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ 01630 01631 /* Bit 1 : Pin 1. */ 01632 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 01633 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 01634 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ 01635 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ 01636 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ 01637 01638 /* Bit 0 : Pin 0. */ 01639 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 01640 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 01641 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ 01642 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ 01643 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ 01644 01645 /* Register: GPIO_OUTCLR */ 01646 /* Description: Clear individual bits in GPIO port. */ 01647 01648 /* Bit 31 : Pin 31. */ 01649 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 01650 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 01651 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ 01652 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ 01653 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ 01654 01655 /* Bit 30 : Pin 30. */ 01656 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 01657 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 01658 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ 01659 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ 01660 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ 01661 01662 /* Bit 29 : Pin 29. */ 01663 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 01664 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 01665 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ 01666 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ 01667 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ 01668 01669 /* Bit 28 : Pin 28. */ 01670 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 01671 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 01672 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ 01673 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ 01674 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ 01675 01676 /* Bit 27 : Pin 27. */ 01677 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 01678 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 01679 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ 01680 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ 01681 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ 01682 01683 /* Bit 26 : Pin 26. */ 01684 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 01685 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 01686 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ 01687 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ 01688 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ 01689 01690 /* Bit 25 : Pin 25. */ 01691 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 01692 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 01693 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ 01694 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ 01695 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ 01696 01697 /* Bit 24 : Pin 24. */ 01698 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 01699 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 01700 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ 01701 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ 01702 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ 01703 01704 /* Bit 23 : Pin 23. */ 01705 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 01706 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 01707 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ 01708 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ 01709 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ 01710 01711 /* Bit 22 : Pin 22. */ 01712 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 01713 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 01714 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ 01715 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ 01716 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ 01717 01718 /* Bit 21 : Pin 21. */ 01719 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 01720 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 01721 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ 01722 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ 01723 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ 01724 01725 /* Bit 20 : Pin 20. */ 01726 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 01727 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 01728 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ 01729 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ 01730 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ 01731 01732 /* Bit 19 : Pin 19. */ 01733 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 01734 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 01735 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ 01736 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ 01737 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ 01738 01739 /* Bit 18 : Pin 18. */ 01740 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 01741 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 01742 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ 01743 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ 01744 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ 01745 01746 /* Bit 17 : Pin 17. */ 01747 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 01748 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 01749 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ 01750 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ 01751 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ 01752 01753 /* Bit 16 : Pin 16. */ 01754 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 01755 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 01756 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ 01757 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ 01758 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ 01759 01760 /* Bit 15 : Pin 15. */ 01761 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 01762 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 01763 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ 01764 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ 01765 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ 01766 01767 /* Bit 14 : Pin 14. */ 01768 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 01769 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 01770 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ 01771 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ 01772 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ 01773 01774 /* Bit 13 : Pin 13. */ 01775 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 01776 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 01777 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ 01778 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ 01779 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ 01780 01781 /* Bit 12 : Pin 12. */ 01782 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 01783 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 01784 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ 01785 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ 01786 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ 01787 01788 /* Bit 11 : Pin 11. */ 01789 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 01790 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 01791 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ 01792 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ 01793 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ 01794 01795 /* Bit 10 : Pin 10. */ 01796 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 01797 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 01798 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ 01799 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ 01800 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ 01801 01802 /* Bit 9 : Pin 9. */ 01803 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 01804 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 01805 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ 01806 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ 01807 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ 01808 01809 /* Bit 8 : Pin 8. */ 01810 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 01811 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 01812 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ 01813 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ 01814 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ 01815 01816 /* Bit 7 : Pin 7. */ 01817 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 01818 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 01819 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ 01820 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ 01821 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ 01822 01823 /* Bit 6 : Pin 6. */ 01824 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 01825 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 01826 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ 01827 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ 01828 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ 01829 01830 /* Bit 5 : Pin 5. */ 01831 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 01832 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 01833 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ 01834 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ 01835 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ 01836 01837 /* Bit 4 : Pin 4. */ 01838 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 01839 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 01840 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ 01841 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ 01842 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ 01843 01844 /* Bit 3 : Pin 3. */ 01845 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 01846 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 01847 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ 01848 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ 01849 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ 01850 01851 /* Bit 2 : Pin 2. */ 01852 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 01853 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 01854 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ 01855 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ 01856 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ 01857 01858 /* Bit 1 : Pin 1. */ 01859 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 01860 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 01861 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ 01862 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ 01863 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ 01864 01865 /* Bit 0 : Pin 0. */ 01866 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 01867 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 01868 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ 01869 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ 01870 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ 01871 01872 /* Register: GPIO_IN */ 01873 /* Description: Read GPIO port. */ 01874 01875 /* Bit 31 : Pin 31. */ 01876 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 01877 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 01878 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ 01879 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ 01880 01881 /* Bit 30 : Pin 30. */ 01882 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 01883 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 01884 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ 01885 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ 01886 01887 /* Bit 29 : Pin 29. */ 01888 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 01889 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 01890 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ 01891 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ 01892 01893 /* Bit 28 : Pin 28. */ 01894 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 01895 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 01896 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ 01897 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ 01898 01899 /* Bit 27 : Pin 27. */ 01900 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 01901 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 01902 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ 01903 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ 01904 01905 /* Bit 26 : Pin 26. */ 01906 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 01907 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 01908 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ 01909 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ 01910 01911 /* Bit 25 : Pin 25. */ 01912 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 01913 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 01914 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ 01915 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ 01916 01917 /* Bit 24 : Pin 24. */ 01918 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 01919 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 01920 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ 01921 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ 01922 01923 /* Bit 23 : Pin 23. */ 01924 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 01925 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 01926 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ 01927 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ 01928 01929 /* Bit 22 : Pin 22. */ 01930 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 01931 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 01932 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ 01933 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ 01934 01935 /* Bit 21 : Pin 21. */ 01936 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 01937 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 01938 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ 01939 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ 01940 01941 /* Bit 20 : Pin 20. */ 01942 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 01943 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 01944 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ 01945 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ 01946 01947 /* Bit 19 : Pin 19. */ 01948 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 01949 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 01950 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ 01951 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ 01952 01953 /* Bit 18 : Pin 18. */ 01954 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 01955 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 01956 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ 01957 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ 01958 01959 /* Bit 17 : Pin 17. */ 01960 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 01961 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 01962 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ 01963 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ 01964 01965 /* Bit 16 : Pin 16. */ 01966 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 01967 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 01968 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ 01969 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ 01970 01971 /* Bit 15 : Pin 15. */ 01972 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 01973 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 01974 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ 01975 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ 01976 01977 /* Bit 14 : Pin 14. */ 01978 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 01979 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 01980 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ 01981 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ 01982 01983 /* Bit 13 : Pin 13. */ 01984 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 01985 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 01986 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ 01987 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ 01988 01989 /* Bit 12 : Pin 12. */ 01990 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 01991 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 01992 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ 01993 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ 01994 01995 /* Bit 11 : Pin 11. */ 01996 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 01997 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 01998 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ 01999 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ 02000 02001 /* Bit 10 : Pin 10. */ 02002 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 02003 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 02004 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ 02005 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ 02006 02007 /* Bit 9 : Pin 9. */ 02008 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 02009 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 02010 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ 02011 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ 02012 02013 /* Bit 8 : Pin 8. */ 02014 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 02015 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 02016 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ 02017 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ 02018 02019 /* Bit 7 : Pin 7. */ 02020 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 02021 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 02022 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ 02023 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ 02024 02025 /* Bit 6 : Pin 6. */ 02026 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 02027 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 02028 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ 02029 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ 02030 02031 /* Bit 5 : Pin 5. */ 02032 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 02033 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 02034 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ 02035 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ 02036 02037 /* Bit 4 : Pin 4. */ 02038 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 02039 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 02040 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ 02041 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ 02042 02043 /* Bit 3 : Pin 3. */ 02044 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 02045 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 02046 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ 02047 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ 02048 02049 /* Bit 2 : Pin 2. */ 02050 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 02051 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 02052 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ 02053 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ 02054 02055 /* Bit 1 : Pin 1. */ 02056 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 02057 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 02058 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ 02059 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ 02060 02061 /* Bit 0 : Pin 0. */ 02062 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 02063 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 02064 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ 02065 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ 02066 02067 /* Register: GPIO_DIR */ 02068 /* Description: Direction of GPIO pins. */ 02069 02070 /* Bit 31 : Pin 31. */ 02071 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 02072 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 02073 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ 02074 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ 02075 02076 /* Bit 30 : Pin 30. */ 02077 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 02078 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 02079 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ 02080 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ 02081 02082 /* Bit 29 : Pin 29. */ 02083 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 02084 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 02085 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ 02086 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ 02087 02088 /* Bit 28 : Pin 28. */ 02089 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 02090 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 02091 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ 02092 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ 02093 02094 /* Bit 27 : Pin 27. */ 02095 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 02096 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 02097 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ 02098 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ 02099 02100 /* Bit 26 : Pin 26. */ 02101 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 02102 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 02103 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ 02104 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ 02105 02106 /* Bit 25 : Pin 25. */ 02107 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 02108 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 02109 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ 02110 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ 02111 02112 /* Bit 24 : Pin 24. */ 02113 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 02114 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 02115 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ 02116 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ 02117 02118 /* Bit 23 : Pin 23. */ 02119 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 02120 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 02121 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ 02122 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ 02123 02124 /* Bit 22 : Pin 22. */ 02125 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 02126 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 02127 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ 02128 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ 02129 02130 /* Bit 21 : Pin 21. */ 02131 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 02132 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 02133 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ 02134 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ 02135 02136 /* Bit 20 : Pin 20. */ 02137 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 02138 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 02139 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ 02140 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ 02141 02142 /* Bit 19 : Pin 19. */ 02143 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 02144 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 02145 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ 02146 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ 02147 02148 /* Bit 18 : Pin 18. */ 02149 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 02150 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 02151 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ 02152 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ 02153 02154 /* Bit 17 : Pin 17. */ 02155 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 02156 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 02157 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ 02158 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ 02159 02160 /* Bit 16 : Pin 16. */ 02161 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 02162 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 02163 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ 02164 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ 02165 02166 /* Bit 15 : Pin 15. */ 02167 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 02168 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 02169 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ 02170 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ 02171 02172 /* Bit 14 : Pin 14. */ 02173 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 02174 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 02175 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ 02176 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ 02177 02178 /* Bit 13 : Pin 13. */ 02179 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 02180 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 02181 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ 02182 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ 02183 02184 /* Bit 12 : Pin 12. */ 02185 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 02186 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 02187 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ 02188 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ 02189 02190 /* Bit 11 : Pin 11. */ 02191 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 02192 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 02193 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ 02194 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ 02195 02196 /* Bit 10 : Pin 10. */ 02197 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 02198 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 02199 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ 02200 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ 02201 02202 /* Bit 9 : Pin 9. */ 02203 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 02204 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 02205 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ 02206 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ 02207 02208 /* Bit 8 : Pin 8. */ 02209 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 02210 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 02211 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ 02212 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ 02213 02214 /* Bit 7 : Pin 7. */ 02215 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 02216 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 02217 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ 02218 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ 02219 02220 /* Bit 6 : Pin 6. */ 02221 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 02222 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 02223 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ 02224 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ 02225 02226 /* Bit 5 : Pin 5. */ 02227 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 02228 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 02229 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ 02230 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ 02231 02232 /* Bit 4 : Pin 4. */ 02233 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 02234 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 02235 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ 02236 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ 02237 02238 /* Bit 3 : Pin 3. */ 02239 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 02240 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 02241 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ 02242 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ 02243 02244 /* Bit 2 : Pin 2. */ 02245 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 02246 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 02247 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ 02248 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ 02249 02250 /* Bit 1 : Pin 1. */ 02251 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 02252 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 02253 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ 02254 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ 02255 02256 /* Bit 0 : Pin 0. */ 02257 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 02258 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 02259 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ 02260 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ 02261 02262 /* Register: GPIO_DIRSET */ 02263 /* Description: DIR set register. */ 02264 02265 /* Bit 31 : Set as output pin 31. */ 02266 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 02267 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 02268 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ 02269 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ 02270 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ 02271 02272 /* Bit 30 : Set as output pin 30. */ 02273 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 02274 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 02275 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ 02276 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ 02277 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ 02278 02279 /* Bit 29 : Set as output pin 29. */ 02280 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 02281 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 02282 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ 02283 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ 02284 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ 02285 02286 /* Bit 28 : Set as output pin 28. */ 02287 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 02288 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 02289 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ 02290 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ 02291 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ 02292 02293 /* Bit 27 : Set as output pin 27. */ 02294 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 02295 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 02296 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ 02297 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ 02298 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ 02299 02300 /* Bit 26 : Set as output pin 26. */ 02301 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 02302 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 02303 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ 02304 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ 02305 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ 02306 02307 /* Bit 25 : Set as output pin 25. */ 02308 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 02309 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 02310 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ 02311 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ 02312 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ 02313 02314 /* Bit 24 : Set as output pin 24. */ 02315 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 02316 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 02317 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ 02318 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ 02319 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ 02320 02321 /* Bit 23 : Set as output pin 23. */ 02322 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 02323 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 02324 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ 02325 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ 02326 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ 02327 02328 /* Bit 22 : Set as output pin 22. */ 02329 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 02330 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 02331 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ 02332 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ 02333 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ 02334 02335 /* Bit 21 : Set as output pin 21. */ 02336 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 02337 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 02338 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ 02339 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ 02340 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ 02341 02342 /* Bit 20 : Set as output pin 20. */ 02343 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 02344 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 02345 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ 02346 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ 02347 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ 02348 02349 /* Bit 19 : Set as output pin 19. */ 02350 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 02351 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 02352 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ 02353 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ 02354 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ 02355 02356 /* Bit 18 : Set as output pin 18. */ 02357 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 02358 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 02359 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ 02360 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ 02361 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ 02362 02363 /* Bit 17 : Set as output pin 17. */ 02364 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 02365 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 02366 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ 02367 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ 02368 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ 02369 02370 /* Bit 16 : Set as output pin 16. */ 02371 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 02372 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 02373 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ 02374 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ 02375 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ 02376 02377 /* Bit 15 : Set as output pin 15. */ 02378 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 02379 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 02380 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ 02381 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ 02382 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ 02383 02384 /* Bit 14 : Set as output pin 14. */ 02385 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 02386 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 02387 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ 02388 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ 02389 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ 02390 02391 /* Bit 13 : Set as output pin 13. */ 02392 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 02393 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 02394 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ 02395 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ 02396 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ 02397 02398 /* Bit 12 : Set as output pin 12. */ 02399 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 02400 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 02401 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ 02402 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ 02403 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ 02404 02405 /* Bit 11 : Set as output pin 11. */ 02406 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 02407 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 02408 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ 02409 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ 02410 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ 02411 02412 /* Bit 10 : Set as output pin 10. */ 02413 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 02414 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 02415 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ 02416 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ 02417 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ 02418 02419 /* Bit 9 : Set as output pin 9. */ 02420 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 02421 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 02422 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ 02423 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ 02424 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ 02425 02426 /* Bit 8 : Set as output pin 8. */ 02427 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 02428 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 02429 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ 02430 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ 02431 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ 02432 02433 /* Bit 7 : Set as output pin 7. */ 02434 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 02435 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 02436 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ 02437 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ 02438 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ 02439 02440 /* Bit 6 : Set as output pin 6. */ 02441 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 02442 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 02443 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ 02444 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ 02445 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ 02446 02447 /* Bit 5 : Set as output pin 5. */ 02448 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 02449 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 02450 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ 02451 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ 02452 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ 02453 02454 /* Bit 4 : Set as output pin 4. */ 02455 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 02456 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 02457 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ 02458 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ 02459 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ 02460 02461 /* Bit 3 : Set as output pin 3. */ 02462 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 02463 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 02464 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ 02465 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ 02466 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ 02467 02468 /* Bit 2 : Set as output pin 2. */ 02469 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 02470 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 02471 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ 02472 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ 02473 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ 02474 02475 /* Bit 1 : Set as output pin 1. */ 02476 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 02477 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 02478 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ 02479 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ 02480 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ 02481 02482 /* Bit 0 : Set as output pin 0. */ 02483 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 02484 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 02485 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ 02486 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ 02487 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ 02488 02489 /* Register: GPIO_DIRCLR */ 02490 /* Description: DIR clear register. */ 02491 02492 /* Bit 31 : Set as input pin 31. */ 02493 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 02494 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 02495 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ 02496 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ 02497 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ 02498 02499 /* Bit 30 : Set as input pin 30. */ 02500 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 02501 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 02502 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ 02503 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ 02504 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ 02505 02506 /* Bit 29 : Set as input pin 29. */ 02507 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 02508 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 02509 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ 02510 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ 02511 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ 02512 02513 /* Bit 28 : Set as input pin 28. */ 02514 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 02515 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 02516 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ 02517 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ 02518 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ 02519 02520 /* Bit 27 : Set as input pin 27. */ 02521 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 02522 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 02523 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ 02524 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ 02525 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ 02526 02527 /* Bit 26 : Set as input pin 26. */ 02528 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 02529 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 02530 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ 02531 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ 02532 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ 02533 02534 /* Bit 25 : Set as input pin 25. */ 02535 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 02536 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 02537 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ 02538 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ 02539 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ 02540 02541 /* Bit 24 : Set as input pin 24. */ 02542 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 02543 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 02544 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ 02545 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ 02546 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ 02547 02548 /* Bit 23 : Set as input pin 23. */ 02549 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 02550 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 02551 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ 02552 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ 02553 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ 02554 02555 /* Bit 22 : Set as input pin 22. */ 02556 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 02557 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 02558 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ 02559 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ 02560 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ 02561 02562 /* Bit 21 : Set as input pin 21. */ 02563 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 02564 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 02565 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ 02566 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ 02567 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ 02568 02569 /* Bit 20 : Set as input pin 20. */ 02570 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 02571 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 02572 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ 02573 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ 02574 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ 02575 02576 /* Bit 19 : Set as input pin 19. */ 02577 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 02578 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 02579 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ 02580 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ 02581 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ 02582 02583 /* Bit 18 : Set as input pin 18. */ 02584 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 02585 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 02586 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ 02587 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ 02588 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ 02589 02590 /* Bit 17 : Set as input pin 17. */ 02591 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 02592 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 02593 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ 02594 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ 02595 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ 02596 02597 /* Bit 16 : Set as input pin 16. */ 02598 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 02599 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 02600 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ 02601 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ 02602 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ 02603 02604 /* Bit 15 : Set as input pin 15. */ 02605 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 02606 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 02607 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ 02608 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ 02609 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ 02610 02611 /* Bit 14 : Set as input pin 14. */ 02612 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 02613 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 02614 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ 02615 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ 02616 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ 02617 02618 /* Bit 13 : Set as input pin 13. */ 02619 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 02620 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 02621 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ 02622 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ 02623 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ 02624 02625 /* Bit 12 : Set as input pin 12. */ 02626 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 02627 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 02628 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ 02629 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ 02630 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ 02631 02632 /* Bit 11 : Set as input pin 11. */ 02633 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 02634 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 02635 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ 02636 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ 02637 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ 02638 02639 /* Bit 10 : Set as input pin 10. */ 02640 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 02641 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 02642 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ 02643 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ 02644 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ 02645 02646 /* Bit 9 : Set as input pin 9. */ 02647 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 02648 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 02649 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ 02650 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ 02651 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ 02652 02653 /* Bit 8 : Set as input pin 8. */ 02654 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 02655 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 02656 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ 02657 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ 02658 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ 02659 02660 /* Bit 7 : Set as input pin 7. */ 02661 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 02662 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 02663 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ 02664 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ 02665 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ 02666 02667 /* Bit 6 : Set as input pin 6. */ 02668 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 02669 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 02670 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ 02671 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ 02672 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ 02673 02674 /* Bit 5 : Set as input pin 5. */ 02675 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 02676 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 02677 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ 02678 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ 02679 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ 02680 02681 /* Bit 4 : Set as input pin 4. */ 02682 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 02683 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 02684 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ 02685 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ 02686 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ 02687 02688 /* Bit 3 : Set as input pin 3. */ 02689 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 02690 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 02691 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ 02692 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ 02693 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ 02694 02695 /* Bit 2 : Set as input pin 2. */ 02696 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 02697 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 02698 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ 02699 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ 02700 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ 02701 02702 /* Bit 1 : Set as input pin 1. */ 02703 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 02704 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 02705 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ 02706 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ 02707 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ 02708 02709 /* Bit 0 : Set as input pin 0. */ 02710 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 02711 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 02712 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ 02713 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ 02714 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ 02715 02716 /* Register: GPIO_PIN_CNF */ 02717 /* Description: Configuration of GPIO pins. */ 02718 02719 /* Bits 17..16 : Pin sensing mechanism. */ 02720 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 02721 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 02722 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ 02723 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ 02724 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ 02725 02726 /* Bits 10..8 : Drive configuration. */ 02727 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 02728 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 02729 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ 02730 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ 02731 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ 02732 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ 02733 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ 02734 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ 02735 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ 02736 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ 02737 02738 /* Bits 3..2 : Pull-up or -down configuration. */ 02739 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 02740 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 02741 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ 02742 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ 02743 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ 02744 02745 /* Bit 1 : Connect or disconnect input path. */ 02746 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 02747 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 02748 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ 02749 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ 02750 02751 /* Bit 0 : Pin direction. */ 02752 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 02753 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 02754 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ 02755 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ 02756 02757 02758 /* Peripheral: GPIOTE */ 02759 /* Description: GPIO tasks and events. */ 02760 02761 /* Register: GPIOTE_INTENSET */ 02762 /* Description: Interrupt enable set register. */ 02763 02764 /* Bit 31 : Enable interrupt on PORT event. */ 02765 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 02766 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 02767 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ 02768 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ 02769 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ 02770 02771 /* Bit 3 : Enable interrupt on IN[3] event. */ 02772 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 02773 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 02774 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ 02775 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ 02776 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ 02777 02778 /* Bit 2 : Enable interrupt on IN[2] event. */ 02779 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 02780 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 02781 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ 02782 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ 02783 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ 02784 02785 /* Bit 1 : Enable interrupt on IN[1] event. */ 02786 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 02787 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 02788 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ 02789 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ 02790 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ 02791 02792 /* Bit 0 : Enable interrupt on IN[0] event. */ 02793 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 02794 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 02795 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ 02796 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ 02797 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ 02798 02799 /* Register: GPIOTE_INTENCLR */ 02800 /* Description: Interrupt enable clear register. */ 02801 02802 /* Bit 31 : Disable interrupt on PORT event. */ 02803 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 02804 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 02805 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ 02806 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ 02807 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ 02808 02809 /* Bit 3 : Disable interrupt on IN[3] event. */ 02810 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 02811 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 02812 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ 02813 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ 02814 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ 02815 02816 /* Bit 2 : Disable interrupt on IN[2] event. */ 02817 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 02818 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 02819 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ 02820 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ 02821 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ 02822 02823 /* Bit 1 : Disable interrupt on IN[1] event. */ 02824 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 02825 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 02826 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ 02827 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ 02828 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ 02829 02830 /* Bit 0 : Disable interrupt on IN[0] event. */ 02831 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 02832 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 02833 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ 02834 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ 02835 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ 02836 02837 /* Register: GPIOTE_CONFIG */ 02838 /* Description: Channel configuration registers. */ 02839 02840 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ 02841 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 02842 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 02843 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ 02844 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ 02845 02846 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ 02847 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 02848 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 02849 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ 02850 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ 02851 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ 02852 02853 /* Bits 12..8 : Pin select. */ 02854 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 02855 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 02856 02857 /* Bits 1..0 : Mode */ 02858 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 02859 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 02860 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ 02861 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ 02862 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ 02863 02864 /* Register: GPIOTE_POWER */ 02865 /* Description: Peripheral power control. */ 02866 02867 /* Bit 0 : Peripheral power control. */ 02868 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 02869 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 02870 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 02871 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 02872 02873 02874 /* Peripheral: LPCOMP */ 02875 /* Description: Low power comparator. */ 02876 02877 /* Register: LPCOMP_SHORTS */ 02878 /* Description: Shortcuts for the LPCOMP. */ 02879 02880 /* Bit 4 : Shortcut between CROSS event and STOP task. */ 02881 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ 02882 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ 02883 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 02884 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 02885 02886 /* Bit 3 : Shortcut between UP event and STOP task. */ 02887 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ 02888 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ 02889 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 02890 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 02891 02892 /* Bit 2 : Shortcut between DOWN event and STOP task. */ 02893 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ 02894 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ 02895 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 02896 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 02897 02898 /* Bit 1 : Shortcut between RADY event and STOP task. */ 02899 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ 02900 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ 02901 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 02902 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 02903 02904 /* Bit 0 : Shortcut between READY event and SAMPLE task. */ 02905 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ 02906 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ 02907 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ 02908 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ 02909 02910 /* Register: LPCOMP_INTENSET */ 02911 /* Description: Interrupt enable set register. */ 02912 02913 /* Bit 3 : Enable interrupt on CROSS event. */ 02914 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 02915 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ 02916 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ 02917 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ 02918 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ 02919 02920 /* Bit 2 : Enable interrupt on UP event. */ 02921 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ 02922 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ 02923 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ 02924 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ 02925 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ 02926 02927 /* Bit 1 : Enable interrupt on DOWN event. */ 02928 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 02929 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ 02930 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ 02931 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ 02932 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ 02933 02934 /* Bit 0 : Enable interrupt on READY event. */ 02935 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 02936 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 02937 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 02938 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 02939 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 02940 02941 /* Register: LPCOMP_INTENCLR */ 02942 /* Description: Interrupt enable clear register. */ 02943 02944 /* Bit 3 : Disable interrupt on CROSS event. */ 02945 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 02946 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ 02947 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ 02948 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ 02949 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ 02950 02951 /* Bit 2 : Disable interrupt on UP event. */ 02952 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ 02953 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ 02954 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ 02955 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ 02956 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ 02957 02958 /* Bit 1 : Disable interrupt on DOWN event. */ 02959 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 02960 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ 02961 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ 02962 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ 02963 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ 02964 02965 /* Bit 0 : Disable interrupt on READY event. */ 02966 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 02967 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 02968 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 02969 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 02970 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 02971 02972 /* Register: LPCOMP_RESULT */ 02973 /* Description: Result of last compare. */ 02974 02975 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ 02976 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 02977 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 02978 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ 02979 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ 02980 02981 /* Register: LPCOMP_ENABLE */ 02982 /* Description: Enable the LPCOMP. */ 02983 02984 /* Bits 1..0 : Enable or disable LPCOMP. */ 02985 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 02986 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 02987 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ 02988 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ 02989 02990 /* Register: LPCOMP_PSEL */ 02991 /* Description: Input pin select. */ 02992 02993 /* Bits 2..0 : Analog input pin select. */ 02994 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ 02995 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ 02996 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ 02997 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ 02998 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ 02999 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ 03000 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ 03001 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ 03002 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ 03003 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ 03004 03005 /* Register: LPCOMP_REFSEL */ 03006 /* Description: Reference select. */ 03007 03008 /* Bits 2..0 : Reference select. */ 03009 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ 03010 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 03011 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ 03012 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ 03013 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ 03014 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ 03015 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ 03016 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ 03017 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ 03018 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ 03019 03020 /* Register: LPCOMP_EXTREFSEL */ 03021 /* Description: External reference select. */ 03022 03023 /* Bit 0 : External analog reference pin selection. */ 03024 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ 03025 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 03026 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ 03027 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ 03028 03029 /* Register: LPCOMP_ANADETECT */ 03030 /* Description: Analog detect configuration. */ 03031 03032 /* Bits 1..0 : Analog detect configuration. */ 03033 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ 03034 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ 03035 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ 03036 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ 03037 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ 03038 03039 /* Register: LPCOMP_POWER */ 03040 /* Description: Peripheral power control. */ 03041 03042 /* Bit 0 : Peripheral power control. */ 03043 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 03044 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 03045 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 03046 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 03047 03048 03049 /* Peripheral: MPU */ 03050 /* Description: Memory Protection Unit. */ 03051 03052 /* Register: MPU_PERR0 */ 03053 /* Description: Configuration of peripherals in mpu regions. */ 03054 03055 /* Bit 31 : PPI region configuration. */ 03056 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ 03057 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ 03058 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03059 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03060 03061 /* Bit 30 : NVMC region configuration. */ 03062 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ 03063 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ 03064 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03065 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03066 03067 /* Bit 19 : LPCOMP region configuration. */ 03068 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ 03069 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 03070 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03071 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03072 03073 /* Bit 18 : QDEC region configuration. */ 03074 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ 03075 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ 03076 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03077 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03078 03079 /* Bit 17 : RTC1 region configuration. */ 03080 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ 03081 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ 03082 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03083 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03084 03085 /* Bit 16 : WDT region configuration. */ 03086 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ 03087 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ 03088 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03089 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03090 03091 /* Bit 15 : CCM and AAR region configuration. */ 03092 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ 03093 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ 03094 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03095 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03096 03097 /* Bit 14 : ECB region configuration. */ 03098 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ 03099 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ 03100 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03101 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03102 03103 /* Bit 13 : RNG region configuration. */ 03104 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ 03105 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ 03106 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03107 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03108 03109 /* Bit 12 : TEMP region configuration. */ 03110 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ 03111 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ 03112 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03113 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03114 03115 /* Bit 11 : RTC0 region configuration. */ 03116 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ 03117 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ 03118 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03119 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03120 03121 /* Bit 10 : TIMER2 region configuration. */ 03122 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ 03123 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ 03124 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03125 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03126 03127 /* Bit 9 : TIMER1 region configuration. */ 03128 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ 03129 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ 03130 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03131 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03132 03133 /* Bit 8 : TIMER0 region configuration. */ 03134 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ 03135 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ 03136 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03137 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03138 03139 /* Bit 7 : ADC region configuration. */ 03140 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ 03141 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ 03142 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03143 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03144 03145 /* Bit 6 : GPIOTE region configuration. */ 03146 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ 03147 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ 03148 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03149 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03150 03151 /* Bit 4 : SPI1 and TWI1 region configuration. */ 03152 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ 03153 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ 03154 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03155 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03156 03157 /* Bit 3 : SPI0 and TWI0 region configuration. */ 03158 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ 03159 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ 03160 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03161 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03162 03163 /* Bit 2 : UART0 region configuration. */ 03164 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ 03165 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ 03166 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03167 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03168 03169 /* Bit 1 : RADIO region configuration. */ 03170 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ 03171 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ 03172 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03173 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03174 03175 /* Bit 0 : POWER_CLOCK region configuration. */ 03176 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ 03177 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ 03178 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 03179 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 03180 03181 /* Register: MPU_PROTENSET0 */ 03182 /* Description: Erase and write protection bit enable set register. */ 03183 03184 /* Bit 31 : Protection enable for region 31. */ 03185 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ 03186 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ 03187 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ 03188 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ 03189 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ 03190 03191 /* Bit 30 : Protection enable for region 30. */ 03192 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ 03193 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ 03194 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ 03195 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ 03196 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ 03197 03198 /* Bit 29 : Protection enable for region 29. */ 03199 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ 03200 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ 03201 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ 03202 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ 03203 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ 03204 03205 /* Bit 28 : Protection enable for region 28. */ 03206 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ 03207 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ 03208 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ 03209 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ 03210 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ 03211 03212 /* Bit 27 : Protection enable for region 27. */ 03213 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ 03214 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ 03215 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ 03216 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ 03217 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ 03218 03219 /* Bit 26 : Protection enable for region 26. */ 03220 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ 03221 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ 03222 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ 03223 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ 03224 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ 03225 03226 /* Bit 25 : Protection enable for region 25. */ 03227 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ 03228 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ 03229 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ 03230 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ 03231 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ 03232 03233 /* Bit 24 : Protection enable for region 24. */ 03234 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ 03235 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ 03236 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ 03237 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ 03238 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ 03239 03240 /* Bit 23 : Protection enable for region 23. */ 03241 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ 03242 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ 03243 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ 03244 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ 03245 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ 03246 03247 /* Bit 22 : Protection enable for region 22. */ 03248 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ 03249 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ 03250 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ 03251 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ 03252 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ 03253 03254 /* Bit 21 : Protection enable for region 21. */ 03255 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ 03256 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ 03257 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ 03258 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ 03259 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ 03260 03261 /* Bit 20 : Protection enable for region 20. */ 03262 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ 03263 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ 03264 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ 03265 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ 03266 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ 03267 03268 /* Bit 19 : Protection enable for region 19. */ 03269 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ 03270 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ 03271 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ 03272 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ 03273 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ 03274 03275 /* Bit 18 : Protection enable for region 18. */ 03276 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ 03277 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ 03278 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ 03279 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ 03280 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ 03281 03282 /* Bit 17 : Protection enable for region 17. */ 03283 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ 03284 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ 03285 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ 03286 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ 03287 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ 03288 03289 /* Bit 16 : Protection enable for region 16. */ 03290 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ 03291 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ 03292 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ 03293 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ 03294 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ 03295 03296 /* Bit 15 : Protection enable for region 15. */ 03297 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ 03298 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ 03299 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ 03300 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ 03301 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ 03302 03303 /* Bit 14 : Protection enable for region 14. */ 03304 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ 03305 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ 03306 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ 03307 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ 03308 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ 03309 03310 /* Bit 13 : Protection enable for region 13. */ 03311 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ 03312 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ 03313 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ 03314 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ 03315 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ 03316 03317 /* Bit 12 : Protection enable for region 12. */ 03318 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ 03319 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ 03320 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ 03321 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ 03322 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ 03323 03324 /* Bit 11 : Protection enable for region 11. */ 03325 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ 03326 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ 03327 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ 03328 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ 03329 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ 03330 03331 /* Bit 10 : Protection enable for region 10. */ 03332 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ 03333 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ 03334 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ 03335 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ 03336 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ 03337 03338 /* Bit 9 : Protection enable for region 9. */ 03339 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ 03340 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ 03341 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ 03342 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ 03343 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ 03344 03345 /* Bit 8 : Protection enable for region 8. */ 03346 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ 03347 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ 03348 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ 03349 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ 03350 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ 03351 03352 /* Bit 7 : Protection enable for region 7. */ 03353 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ 03354 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ 03355 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ 03356 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ 03357 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ 03358 03359 /* Bit 6 : Protection enable for region 6. */ 03360 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ 03361 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ 03362 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ 03363 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ 03364 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ 03365 03366 /* Bit 5 : Protection enable for region 5. */ 03367 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ 03368 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ 03369 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ 03370 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ 03371 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ 03372 03373 /* Bit 4 : Protection enable for region 4. */ 03374 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ 03375 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ 03376 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ 03377 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ 03378 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ 03379 03380 /* Bit 3 : Protection enable for region 3. */ 03381 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ 03382 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ 03383 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ 03384 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ 03385 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ 03386 03387 /* Bit 2 : Protection enable for region 2. */ 03388 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ 03389 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ 03390 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ 03391 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ 03392 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ 03393 03394 /* Bit 1 : Protection enable for region 1. */ 03395 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ 03396 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ 03397 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ 03398 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ 03399 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ 03400 03401 /* Bit 0 : Protection enable for region 0. */ 03402 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ 03403 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ 03404 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ 03405 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ 03406 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ 03407 03408 /* Register: MPU_PROTENSET1 */ 03409 /* Description: Erase and write protection bit enable set register. */ 03410 03411 /* Bit 31 : Protection enable for region 63. */ 03412 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ 03413 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ 03414 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ 03415 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ 03416 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ 03417 03418 /* Bit 30 : Protection enable for region 62. */ 03419 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ 03420 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ 03421 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ 03422 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ 03423 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ 03424 03425 /* Bit 29 : Protection enable for region 61. */ 03426 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ 03427 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ 03428 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ 03429 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ 03430 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ 03431 03432 /* Bit 28 : Protection enable for region 60. */ 03433 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ 03434 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ 03435 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ 03436 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ 03437 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ 03438 03439 /* Bit 27 : Protection enable for region 59. */ 03440 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ 03441 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ 03442 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ 03443 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ 03444 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ 03445 03446 /* Bit 26 : Protection enable for region 58. */ 03447 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ 03448 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ 03449 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ 03450 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ 03451 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ 03452 03453 /* Bit 25 : Protection enable for region 57. */ 03454 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ 03455 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ 03456 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ 03457 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ 03458 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ 03459 03460 /* Bit 24 : Protection enable for region 56. */ 03461 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ 03462 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ 03463 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ 03464 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ 03465 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ 03466 03467 /* Bit 23 : Protection enable for region 55. */ 03468 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ 03469 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ 03470 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ 03471 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ 03472 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ 03473 03474 /* Bit 22 : Protection enable for region 54. */ 03475 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ 03476 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ 03477 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ 03478 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ 03479 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ 03480 03481 /* Bit 21 : Protection enable for region 53. */ 03482 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ 03483 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ 03484 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ 03485 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ 03486 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ 03487 03488 /* Bit 20 : Protection enable for region 52. */ 03489 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ 03490 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ 03491 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ 03492 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ 03493 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ 03494 03495 /* Bit 19 : Protection enable for region 51. */ 03496 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ 03497 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ 03498 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ 03499 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ 03500 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ 03501 03502 /* Bit 18 : Protection enable for region 50. */ 03503 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ 03504 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ 03505 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ 03506 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ 03507 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ 03508 03509 /* Bit 17 : Protection enable for region 49. */ 03510 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ 03511 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ 03512 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ 03513 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ 03514 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ 03515 03516 /* Bit 16 : Protection enable for region 48. */ 03517 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ 03518 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ 03519 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ 03520 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ 03521 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ 03522 03523 /* Bit 15 : Protection enable for region 47. */ 03524 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ 03525 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ 03526 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ 03527 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ 03528 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ 03529 03530 /* Bit 14 : Protection enable for region 46. */ 03531 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ 03532 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ 03533 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ 03534 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ 03535 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ 03536 03537 /* Bit 13 : Protection enable for region 45. */ 03538 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ 03539 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ 03540 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ 03541 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ 03542 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ 03543 03544 /* Bit 12 : Protection enable for region 44. */ 03545 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ 03546 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ 03547 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ 03548 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ 03549 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ 03550 03551 /* Bit 11 : Protection enable for region 43. */ 03552 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ 03553 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ 03554 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ 03555 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ 03556 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ 03557 03558 /* Bit 10 : Protection enable for region 42. */ 03559 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ 03560 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ 03561 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ 03562 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ 03563 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ 03564 03565 /* Bit 9 : Protection enable for region 41. */ 03566 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ 03567 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ 03568 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ 03569 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ 03570 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ 03571 03572 /* Bit 8 : Protection enable for region 40. */ 03573 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ 03574 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ 03575 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ 03576 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ 03577 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ 03578 03579 /* Bit 7 : Protection enable for region 39. */ 03580 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ 03581 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ 03582 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ 03583 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ 03584 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ 03585 03586 /* Bit 6 : Protection enable for region 38. */ 03587 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ 03588 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ 03589 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ 03590 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ 03591 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ 03592 03593 /* Bit 5 : Protection enable for region 37. */ 03594 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ 03595 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ 03596 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ 03597 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ 03598 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ 03599 03600 /* Bit 4 : Protection enable for region 36. */ 03601 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ 03602 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ 03603 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ 03604 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ 03605 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ 03606 03607 /* Bit 3 : Protection enable for region 35. */ 03608 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ 03609 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ 03610 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ 03611 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ 03612 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ 03613 03614 /* Bit 2 : Protection enable for region 34. */ 03615 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ 03616 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ 03617 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ 03618 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ 03619 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ 03620 03621 /* Bit 1 : Protection enable for region 33. */ 03622 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ 03623 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ 03624 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ 03625 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ 03626 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ 03627 03628 /* Bit 0 : Protection enable for region 32. */ 03629 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ 03630 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ 03631 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ 03632 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ 03633 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ 03634 03635 /* Register: MPU_DISABLEINDEBUG */ 03636 /* Description: Disable erase and write protection mechanism in debug mode. */ 03637 03638 /* Bit 0 : Disable protection mechanism in debug mode. */ 03639 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ 03640 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ 03641 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ 03642 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ 03643 03644 /* Register: MPU_PROTBLOCKSIZE */ 03645 /* Description: Erase and write protection block size. */ 03646 03647 /* Bits 1..0 : Erase and write protection block size. */ 03648 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ 03649 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ 03650 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ 03651 03652 03653 /* Peripheral: NVMC */ 03654 /* Description: Non Volatile Memory Controller. */ 03655 03656 /* Register: NVMC_READY */ 03657 /* Description: Ready flag. */ 03658 03659 /* Bit 0 : NVMC ready. */ 03660 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 03661 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 03662 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ 03663 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ 03664 03665 /* Register: NVMC_CONFIG */ 03666 /* Description: Configuration register. */ 03667 03668 /* Bits 1..0 : Program write enable. */ 03669 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 03670 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 03671 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ 03672 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ 03673 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ 03674 03675 /* Register: NVMC_ERASEALL */ 03676 /* Description: Register for erasing all non-volatile user memory. */ 03677 03678 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ 03679 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 03680 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 03681 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ 03682 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ 03683 03684 /* Register: NVMC_ERASEUICR */ 03685 /* Description: Register for start erasing User Information Congfiguration Registers. */ 03686 03687 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */ 03688 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ 03689 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ 03690 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ 03691 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ 03692 03693 03694 /* Peripheral: POWER */ 03695 /* Description: Power Control. */ 03696 03697 /* Register: POWER_INTENSET */ 03698 /* Description: Interrupt enable set register. */ 03699 03700 /* Bit 2 : Enable interrupt on POFWARN event. */ 03701 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 03702 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 03703 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ 03704 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ 03705 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ 03706 03707 /* Register: POWER_INTENCLR */ 03708 /* Description: Interrupt enable clear register. */ 03709 03710 /* Bit 2 : Disable interrupt on POFWARN event. */ 03711 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 03712 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 03713 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ 03714 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ 03715 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ 03716 03717 /* Register: POWER_RESETREAS */ 03718 /* Description: Reset reason. */ 03719 03720 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ 03721 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ 03722 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 03723 03724 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ 03725 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ 03726 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 03727 03728 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ 03729 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ 03730 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 03731 03732 /* Bit 3 : Reset from CPU lock-up detected. */ 03733 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ 03734 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 03735 03736 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ 03737 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ 03738 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 03739 03740 /* Bit 1 : Reset from watchdog detected. */ 03741 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 03742 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 03743 03744 /* Bit 0 : Reset from pin-reset detected. */ 03745 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 03746 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 03747 03748 /* Register: POWER_RAMSTATUS */ 03749 /* Description: Ram status register. */ 03750 03751 /* Bit 3 : RAM block 3 status. */ 03752 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ 03753 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ 03754 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ 03755 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ 03756 03757 /* Bit 2 : RAM block 2 status. */ 03758 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ 03759 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ 03760 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ 03761 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ 03762 03763 /* Bit 1 : RAM block 1 status. */ 03764 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ 03765 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ 03766 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ 03767 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ 03768 03769 /* Bit 0 : RAM block 0 status. */ 03770 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ 03771 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ 03772 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ 03773 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ 03774 03775 /* Register: POWER_SYSTEMOFF */ 03776 /* Description: System off register. */ 03777 03778 /* Bit 0 : Enter system off mode. */ 03779 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 03780 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 03781 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ 03782 03783 /* Register: POWER_POFCON */ 03784 /* Description: Power failure configuration. */ 03785 03786 /* Bits 2..1 : Set threshold level. */ 03787 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ 03788 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 03789 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ 03790 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ 03791 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ 03792 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ 03793 03794 /* Bit 0 : Power failure comparator enable. */ 03795 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ 03796 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ 03797 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ 03798 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ 03799 03800 /* Register: POWER_GPREGRET */ 03801 /* Description: General purpose retention register. This register is a retained register. */ 03802 03803 /* Bits 7..0 : General purpose retention register. */ 03804 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 03805 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 03806 03807 /* Register: POWER_RAMON */ 03808 /* Description: Ram on/off. */ 03809 03810 /* Bit 17 : RAM block 1 behaviour in OFF mode. */ 03811 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ 03812 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ 03813 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ 03814 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ 03815 03816 /* Bit 16 : RAM block 0 behaviour in OFF mode. */ 03817 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ 03818 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ 03819 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ 03820 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ 03821 03822 /* Bit 1 : RAM block 1 behaviour in ON mode. */ 03823 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ 03824 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ 03825 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ 03826 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ 03827 03828 /* Bit 0 : RAM block 0 behaviour in ON mode. */ 03829 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ 03830 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ 03831 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ 03832 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ 03833 03834 /* Register: POWER_RESET */ 03835 /* Description: Pin reset functionality configuration register. This register is a retained register. */ 03836 03837 /* Bit 0 : Enable or disable pin reset in debug interface mode. */ 03838 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 03839 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 03840 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ 03841 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ 03842 03843 /* Register: POWER_RAMONB */ 03844 /* Description: Ram on/off. */ 03845 03846 /* Bit 17 : RAM block 3 behaviour in OFF mode. */ 03847 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ 03848 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ 03849 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ 03850 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ 03851 03852 /* Bit 16 : RAM block 2 behaviour in OFF mode. */ 03853 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ 03854 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ 03855 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ 03856 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ 03857 03858 /* Bit 1 : RAM block 3 behaviour in ON mode. */ 03859 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ 03860 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ 03861 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ 03862 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ 03863 03864 /* Bit 0 : RAM block 2 behaviour in ON mode. */ 03865 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ 03866 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ 03867 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ 03868 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ 03869 03870 /* Register: POWER_DCDCEN */ 03871 /* Description: DCDC converter enable configuration register. */ 03872 03873 /* Bit 0 : Enable DCDC converter. */ 03874 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 03875 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 03876 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ 03877 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ 03878 03879 /* Register: POWER_DCDCFORCE */ 03880 /* Description: DCDC power-up force register. */ 03881 03882 /* Bit 1 : DCDC power-up force on. */ 03883 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ 03884 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ 03885 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ 03886 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ 03887 03888 /* Bit 0 : DCDC power-up force off. */ 03889 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ 03890 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ 03891 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ 03892 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ 03893 03894 03895 /* Peripheral: PPI */ 03896 /* Description: PPI controller. */ 03897 03898 /* Register: PPI_CHEN */ 03899 /* Description: Channel enable. */ 03900 03901 /* Bit 31 : Enable PPI channel 31. */ 03902 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 03903 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 03904 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ 03905 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ 03906 03907 /* Bit 30 : Enable PPI channel 30. */ 03908 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ 03909 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ 03910 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ 03911 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ 03912 03913 /* Bit 29 : Enable PPI channel 29. */ 03914 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ 03915 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ 03916 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ 03917 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ 03918 03919 /* Bit 28 : Enable PPI channel 28. */ 03920 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ 03921 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ 03922 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ 03923 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ 03924 03925 /* Bit 27 : Enable PPI channel 27. */ 03926 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ 03927 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ 03928 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ 03929 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ 03930 03931 /* Bit 26 : Enable PPI channel 26. */ 03932 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ 03933 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ 03934 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ 03935 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ 03936 03937 /* Bit 25 : Enable PPI channel 25. */ 03938 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ 03939 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ 03940 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ 03941 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ 03942 03943 /* Bit 24 : Enable PPI channel 24. */ 03944 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ 03945 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ 03946 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ 03947 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ 03948 03949 /* Bit 23 : Enable PPI channel 23. */ 03950 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ 03951 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ 03952 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ 03953 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ 03954 03955 /* Bit 22 : Enable PPI channel 22. */ 03956 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ 03957 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ 03958 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ 03959 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ 03960 03961 /* Bit 21 : Enable PPI channel 21. */ 03962 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ 03963 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ 03964 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ 03965 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ 03966 03967 /* Bit 20 : Enable PPI channel 20. */ 03968 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ 03969 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ 03970 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ 03971 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ 03972 03973 /* Bit 15 : Enable PPI channel 15. */ 03974 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 03975 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 03976 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ 03977 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ 03978 03979 /* Bit 14 : Enable PPI channel 14. */ 03980 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 03981 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 03982 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ 03983 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ 03984 03985 /* Bit 13 : Enable PPI channel 13. */ 03986 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 03987 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 03988 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ 03989 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ 03990 03991 /* Bit 12 : Enable PPI channel 12. */ 03992 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 03993 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 03994 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ 03995 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ 03996 03997 /* Bit 11 : Enable PPI channel 11. */ 03998 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 03999 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 04000 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ 04001 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ 04002 04003 /* Bit 10 : Enable PPI channel 10. */ 04004 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 04005 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 04006 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ 04007 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ 04008 04009 /* Bit 9 : Enable PPI channel 9. */ 04010 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 04011 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 04012 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ 04013 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ 04014 04015 /* Bit 8 : Enable PPI channel 8. */ 04016 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 04017 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 04018 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ 04019 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ 04020 04021 /* Bit 7 : Enable PPI channel 7. */ 04022 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 04023 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 04024 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ 04025 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ 04026 04027 /* Bit 6 : Enable PPI channel 6. */ 04028 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 04029 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 04030 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ 04031 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ 04032 04033 /* Bit 5 : Enable PPI channel 5. */ 04034 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 04035 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 04036 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ 04037 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ 04038 04039 /* Bit 4 : Enable PPI channel 4. */ 04040 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 04041 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 04042 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ 04043 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ 04044 04045 /* Bit 3 : Enable PPI channel 3. */ 04046 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 04047 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 04048 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ 04049 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ 04050 04051 /* Bit 2 : Enable PPI channel 2. */ 04052 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 04053 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 04054 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ 04055 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ 04056 04057 /* Bit 1 : Enable PPI channel 1. */ 04058 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 04059 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 04060 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ 04061 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ 04062 04063 /* Bit 0 : Enable PPI channel 0. */ 04064 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 04065 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 04066 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ 04067 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ 04068 04069 /* Register: PPI_CHENSET */ 04070 /* Description: Channel enable set. */ 04071 04072 /* Bit 31 : Enable PPI channel 31. */ 04073 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 04074 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 04075 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ 04076 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ 04077 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ 04078 04079 /* Bit 30 : Enable PPI channel 30. */ 04080 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ 04081 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ 04082 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ 04083 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ 04084 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ 04085 04086 /* Bit 29 : Enable PPI channel 29. */ 04087 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ 04088 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ 04089 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ 04090 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ 04091 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ 04092 04093 /* Bit 28 : Enable PPI channel 28. */ 04094 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ 04095 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ 04096 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ 04097 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ 04098 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ 04099 04100 /* Bit 27 : Enable PPI channel 27. */ 04101 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ 04102 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ 04103 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ 04104 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ 04105 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ 04106 04107 /* Bit 26 : Enable PPI channel 26. */ 04108 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ 04109 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ 04110 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ 04111 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ 04112 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ 04113 04114 /* Bit 25 : Enable PPI channel 25. */ 04115 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ 04116 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ 04117 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ 04118 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ 04119 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ 04120 04121 /* Bit 24 : Enable PPI channel 24. */ 04122 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ 04123 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ 04124 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ 04125 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ 04126 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ 04127 04128 /* Bit 23 : Enable PPI channel 23. */ 04129 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ 04130 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ 04131 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ 04132 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ 04133 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ 04134 04135 /* Bit 22 : Enable PPI channel 22. */ 04136 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ 04137 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ 04138 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ 04139 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ 04140 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ 04141 04142 /* Bit 21 : Enable PPI channel 21. */ 04143 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ 04144 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ 04145 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ 04146 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ 04147 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ 04148 04149 /* Bit 20 : Enable PPI channel 20. */ 04150 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ 04151 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ 04152 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ 04153 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ 04154 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ 04155 04156 /* Bit 15 : Enable PPI channel 15. */ 04157 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 04158 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 04159 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ 04160 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ 04161 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ 04162 04163 /* Bit 14 : Enable PPI channel 14. */ 04164 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 04165 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 04166 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ 04167 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ 04168 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ 04169 04170 /* Bit 13 : Enable PPI channel 13. */ 04171 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 04172 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 04173 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ 04174 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ 04175 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ 04176 04177 /* Bit 12 : Enable PPI channel 12. */ 04178 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 04179 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 04180 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ 04181 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ 04182 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ 04183 04184 /* Bit 11 : Enable PPI channel 11. */ 04185 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 04186 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 04187 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ 04188 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ 04189 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ 04190 04191 /* Bit 10 : Enable PPI channel 10. */ 04192 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 04193 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 04194 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ 04195 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ 04196 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ 04197 04198 /* Bit 9 : Enable PPI channel 9. */ 04199 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 04200 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 04201 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ 04202 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ 04203 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ 04204 04205 /* Bit 8 : Enable PPI channel 8. */ 04206 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 04207 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 04208 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ 04209 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ 04210 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ 04211 04212 /* Bit 7 : Enable PPI channel 7. */ 04213 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 04214 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 04215 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ 04216 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ 04217 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ 04218 04219 /* Bit 6 : Enable PPI channel 6. */ 04220 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 04221 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 04222 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ 04223 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ 04224 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ 04225 04226 /* Bit 5 : Enable PPI channel 5. */ 04227 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 04228 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 04229 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ 04230 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ 04231 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ 04232 04233 /* Bit 4 : Enable PPI channel 4. */ 04234 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 04235 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 04236 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ 04237 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ 04238 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ 04239 04240 /* Bit 3 : Enable PPI channel 3. */ 04241 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 04242 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 04243 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ 04244 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ 04245 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ 04246 04247 /* Bit 2 : Enable PPI channel 2. */ 04248 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 04249 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 04250 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ 04251 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ 04252 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ 04253 04254 /* Bit 1 : Enable PPI channel 1. */ 04255 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 04256 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 04257 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ 04258 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ 04259 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ 04260 04261 /* Bit 0 : Enable PPI channel 0. */ 04262 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 04263 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 04264 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ 04265 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ 04266 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ 04267 04268 /* Register: PPI_CHENCLR */ 04269 /* Description: Channel enable clear. */ 04270 04271 /* Bit 31 : Disable PPI channel 31. */ 04272 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 04273 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 04274 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ 04275 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ 04276 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ 04277 04278 /* Bit 30 : Disable PPI channel 30. */ 04279 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ 04280 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ 04281 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ 04282 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ 04283 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ 04284 04285 /* Bit 29 : Disable PPI channel 29. */ 04286 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ 04287 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ 04288 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ 04289 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ 04290 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ 04291 04292 /* Bit 28 : Disable PPI channel 28. */ 04293 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ 04294 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ 04295 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ 04296 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ 04297 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ 04298 04299 /* Bit 27 : Disable PPI channel 27. */ 04300 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ 04301 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ 04302 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ 04303 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ 04304 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ 04305 04306 /* Bit 26 : Disable PPI channel 26. */ 04307 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ 04308 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ 04309 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ 04310 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ 04311 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ 04312 04313 /* Bit 25 : Disable PPI channel 25. */ 04314 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ 04315 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ 04316 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ 04317 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ 04318 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ 04319 04320 /* Bit 24 : Disable PPI channel 24. */ 04321 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ 04322 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ 04323 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ 04324 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ 04325 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ 04326 04327 /* Bit 23 : Disable PPI channel 23. */ 04328 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ 04329 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ 04330 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ 04331 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ 04332 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ 04333 04334 /* Bit 22 : Disable PPI channel 22. */ 04335 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ 04336 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ 04337 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ 04338 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ 04339 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ 04340 04341 /* Bit 21 : Disable PPI channel 21. */ 04342 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ 04343 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ 04344 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ 04345 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ 04346 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ 04347 04348 /* Bit 20 : Disable PPI channel 20. */ 04349 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ 04350 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ 04351 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ 04352 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ 04353 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ 04354 04355 /* Bit 15 : Disable PPI channel 15. */ 04356 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 04357 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 04358 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ 04359 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ 04360 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ 04361 04362 /* Bit 14 : Disable PPI channel 14. */ 04363 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 04364 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 04365 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ 04366 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ 04367 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ 04368 04369 /* Bit 13 : Disable PPI channel 13. */ 04370 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 04371 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 04372 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ 04373 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ 04374 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ 04375 04376 /* Bit 12 : Disable PPI channel 12. */ 04377 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 04378 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 04379 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ 04380 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ 04381 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ 04382 04383 /* Bit 11 : Disable PPI channel 11. */ 04384 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 04385 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 04386 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ 04387 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ 04388 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ 04389 04390 /* Bit 10 : Disable PPI channel 10. */ 04391 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 04392 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 04393 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ 04394 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ 04395 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ 04396 04397 /* Bit 9 : Disable PPI channel 9. */ 04398 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 04399 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 04400 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ 04401 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ 04402 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ 04403 04404 /* Bit 8 : Disable PPI channel 8. */ 04405 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 04406 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 04407 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ 04408 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ 04409 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ 04410 04411 /* Bit 7 : Disable PPI channel 7. */ 04412 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 04413 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 04414 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ 04415 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ 04416 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ 04417 04418 /* Bit 6 : Disable PPI channel 6. */ 04419 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 04420 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 04421 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ 04422 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ 04423 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ 04424 04425 /* Bit 5 : Disable PPI channel 5. */ 04426 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 04427 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 04428 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ 04429 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ 04430 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ 04431 04432 /* Bit 4 : Disable PPI channel 4. */ 04433 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 04434 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 04435 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ 04436 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ 04437 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ 04438 04439 /* Bit 3 : Disable PPI channel 3. */ 04440 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 04441 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 04442 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ 04443 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ 04444 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ 04445 04446 /* Bit 2 : Disable PPI channel 2. */ 04447 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 04448 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 04449 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ 04450 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ 04451 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ 04452 04453 /* Bit 1 : Disable PPI channel 1. */ 04454 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 04455 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 04456 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ 04457 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ 04458 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ 04459 04460 /* Bit 0 : Disable PPI channel 0. */ 04461 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 04462 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 04463 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ 04464 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ 04465 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ 04466 04467 /* Register: PPI_CHG */ 04468 /* Description: Channel group configuration. */ 04469 04470 /* Bit 31 : Include CH31 in channel group. */ 04471 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 04472 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 04473 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ 04474 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ 04475 04476 /* Bit 30 : Include CH30 in channel group. */ 04477 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ 04478 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ 04479 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ 04480 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ 04481 04482 /* Bit 29 : Include CH29 in channel group. */ 04483 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ 04484 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ 04485 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ 04486 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ 04487 04488 /* Bit 28 : Include CH28 in channel group. */ 04489 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ 04490 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ 04491 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ 04492 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ 04493 04494 /* Bit 27 : Include CH27 in channel group. */ 04495 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ 04496 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ 04497 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ 04498 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ 04499 04500 /* Bit 26 : Include CH26 in channel group. */ 04501 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ 04502 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ 04503 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ 04504 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ 04505 04506 /* Bit 25 : Include CH25 in channel group. */ 04507 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ 04508 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ 04509 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ 04510 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ 04511 04512 /* Bit 24 : Include CH24 in channel group. */ 04513 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ 04514 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ 04515 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ 04516 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ 04517 04518 /* Bit 23 : Include CH23 in channel group. */ 04519 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ 04520 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ 04521 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ 04522 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ 04523 04524 /* Bit 22 : Include CH22 in channel group. */ 04525 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ 04526 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ 04527 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ 04528 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ 04529 04530 /* Bit 21 : Include CH21 in channel group. */ 04531 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ 04532 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ 04533 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ 04534 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ 04535 04536 /* Bit 20 : Include CH20 in channel group. */ 04537 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ 04538 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ 04539 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ 04540 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ 04541 04542 /* Bit 15 : Include CH15 in channel group. */ 04543 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 04544 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 04545 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ 04546 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ 04547 04548 /* Bit 14 : Include CH14 in channel group. */ 04549 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 04550 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 04551 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ 04552 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ 04553 04554 /* Bit 13 : Include CH13 in channel group. */ 04555 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 04556 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 04557 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ 04558 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ 04559 04560 /* Bit 12 : Include CH12 in channel group. */ 04561 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 04562 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 04563 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ 04564 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ 04565 04566 /* Bit 11 : Include CH11 in channel group. */ 04567 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 04568 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 04569 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ 04570 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ 04571 04572 /* Bit 10 : Include CH10 in channel group. */ 04573 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 04574 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 04575 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ 04576 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ 04577 04578 /* Bit 9 : Include CH9 in channel group. */ 04579 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 04580 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 04581 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ 04582 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ 04583 04584 /* Bit 8 : Include CH8 in channel group. */ 04585 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 04586 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 04587 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ 04588 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ 04589 04590 /* Bit 7 : Include CH7 in channel group. */ 04591 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 04592 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 04593 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ 04594 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ 04595 04596 /* Bit 6 : Include CH6 in channel group. */ 04597 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 04598 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 04599 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ 04600 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ 04601 04602 /* Bit 5 : Include CH5 in channel group. */ 04603 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 04604 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 04605 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ 04606 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ 04607 04608 /* Bit 4 : Include CH4 in channel group. */ 04609 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 04610 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 04611 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ 04612 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ 04613 04614 /* Bit 3 : Include CH3 in channel group. */ 04615 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 04616 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 04617 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ 04618 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ 04619 04620 /* Bit 2 : Include CH2 in channel group. */ 04621 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 04622 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 04623 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ 04624 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ 04625 04626 /* Bit 1 : Include CH1 in channel group. */ 04627 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 04628 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 04629 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ 04630 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ 04631 04632 /* Bit 0 : Include CH0 in channel group. */ 04633 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 04634 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 04635 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ 04636 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ 04637 04638 04639 /* Peripheral: PU */ 04640 /* Description: Patch unit. */ 04641 04642 /* Register: PU_PATCHADDR */ 04643 /* Description: Relative address of patch instructions. */ 04644 04645 /* Bits 24..0 : Relative address of patch instructions. */ 04646 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */ 04647 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */ 04648 04649 /* Register: PU_PATCHEN */ 04650 /* Description: Patch enable register. */ 04651 04652 /* Bit 7 : Patch 7 enabled. */ 04653 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ 04654 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ 04655 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */ 04656 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */ 04657 04658 /* Bit 6 : Patch 6 enabled. */ 04659 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ 04660 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ 04661 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */ 04662 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */ 04663 04664 /* Bit 5 : Patch 5 enabled. */ 04665 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ 04666 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ 04667 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */ 04668 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */ 04669 04670 /* Bit 4 : Patch 4 enabled. */ 04671 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ 04672 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ 04673 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */ 04674 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */ 04675 04676 /* Bit 3 : Patch 3 enabled. */ 04677 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ 04678 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ 04679 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */ 04680 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */ 04681 04682 /* Bit 2 : Patch 2 enabled. */ 04683 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ 04684 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ 04685 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */ 04686 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */ 04687 04688 /* Bit 1 : Patch 1 enabled. */ 04689 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ 04690 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ 04691 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */ 04692 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */ 04693 04694 /* Bit 0 : Patch 0 enabled. */ 04695 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ 04696 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ 04697 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */ 04698 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */ 04699 04700 /* Register: PU_PATCHENSET */ 04701 /* Description: Patch enable register. */ 04702 04703 /* Bit 7 : Patch 7 enabled. */ 04704 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ 04705 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ 04706 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */ 04707 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */ 04708 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */ 04709 04710 /* Bit 6 : Patch 6 enabled. */ 04711 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ 04712 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ 04713 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */ 04714 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */ 04715 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */ 04716 04717 /* Bit 5 : Patch 5 enabled. */ 04718 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ 04719 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ 04720 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */ 04721 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */ 04722 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */ 04723 04724 /* Bit 4 : Patch 4 enabled. */ 04725 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ 04726 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ 04727 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */ 04728 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */ 04729 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */ 04730 04731 /* Bit 3 : Patch 3 enabled. */ 04732 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ 04733 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ 04734 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */ 04735 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */ 04736 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */ 04737 04738 /* Bit 2 : Patch 2 enabled. */ 04739 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ 04740 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ 04741 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */ 04742 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */ 04743 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */ 04744 04745 /* Bit 1 : Patch 1 enabled. */ 04746 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ 04747 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ 04748 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */ 04749 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */ 04750 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */ 04751 04752 /* Bit 0 : Patch 0 enabled. */ 04753 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ 04754 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ 04755 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */ 04756 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */ 04757 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */ 04758 04759 /* Register: PU_PATCHENCLR */ 04760 /* Description: Patch disable register. */ 04761 04762 /* Bit 7 : Patch 7 enabled. */ 04763 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ 04764 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ 04765 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */ 04766 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */ 04767 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */ 04768 04769 /* Bit 6 : Patch 6 enabled. */ 04770 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ 04771 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ 04772 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */ 04773 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */ 04774 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */ 04775 04776 /* Bit 5 : Patch 5 enabled. */ 04777 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ 04778 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ 04779 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */ 04780 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */ 04781 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */ 04782 04783 /* Bit 4 : Patch 4 enabled. */ 04784 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ 04785 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ 04786 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */ 04787 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */ 04788 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */ 04789 04790 /* Bit 3 : Patch 3 enabled. */ 04791 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ 04792 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ 04793 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */ 04794 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */ 04795 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */ 04796 04797 /* Bit 2 : Patch 2 enabled. */ 04798 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ 04799 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ 04800 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */ 04801 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */ 04802 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */ 04803 04804 /* Bit 1 : Patch 1 enabled. */ 04805 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ 04806 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ 04807 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */ 04808 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */ 04809 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */ 04810 04811 /* Bit 0 : Patch 0 enabled. */ 04812 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ 04813 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ 04814 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */ 04815 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */ 04816 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */ 04817 04818 04819 /* Peripheral: QDEC */ 04820 /* Description: Rotary decoder. */ 04821 04822 /* Register: QDEC_SHORTS */ 04823 /* Description: Shortcuts for the QDEC. */ 04824 04825 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ 04826 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ 04827 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ 04828 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 04829 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 04830 04831 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ 04832 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ 04833 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ 04834 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ 04835 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ 04836 04837 /* Register: QDEC_INTENSET */ 04838 /* Description: Interrupt enable set register. */ 04839 04840 /* Bit 2 : Enable interrupt on ACCOF event. */ 04841 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 04842 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 04843 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ 04844 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ 04845 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ 04846 04847 /* Bit 1 : Enable interrupt on REPORTRDY event. */ 04848 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 04849 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 04850 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ 04851 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ 04852 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ 04853 04854 /* Bit 0 : Enable interrupt on SAMPLERDY event. */ 04855 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 04856 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 04857 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ 04858 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ 04859 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ 04860 04861 /* Register: QDEC_INTENCLR */ 04862 /* Description: Interrupt enable clear register. */ 04863 04864 /* Bit 2 : Disable interrupt on ACCOF event. */ 04865 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 04866 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 04867 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ 04868 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ 04869 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ 04870 04871 /* Bit 1 : Disable interrupt on REPORTRDY event. */ 04872 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 04873 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 04874 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ 04875 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ 04876 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ 04877 04878 /* Bit 0 : Disable interrupt on SAMPLERDY event. */ 04879 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 04880 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 04881 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ 04882 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ 04883 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ 04884 04885 /* Register: QDEC_ENABLE */ 04886 /* Description: Enable the QDEC. */ 04887 04888 /* Bit 0 : Enable or disable QDEC. */ 04889 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 04890 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 04891 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ 04892 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ 04893 04894 /* Register: QDEC_LEDPOL */ 04895 /* Description: LED output pin polarity. */ 04896 04897 /* Bit 0 : LED output pin polarity. */ 04898 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ 04899 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ 04900 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ 04901 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ 04902 04903 /* Register: QDEC_SAMPLEPER */ 04904 /* Description: Sample period. */ 04905 04906 /* Bits 2..0 : Sample period. */ 04907 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ 04908 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ 04909 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ 04910 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ 04911 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ 04912 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ 04913 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ 04914 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ 04915 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ 04916 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ 04917 04918 /* Register: QDEC_SAMPLE */ 04919 /* Description: Motion sample value. */ 04920 04921 /* Bits 31..0 : Last sample taken in compliment to 2. */ 04922 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ 04923 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ 04924 04925 /* Register: QDEC_REPORTPER */ 04926 /* Description: Number of samples to generate an EVENT_REPORTRDY. */ 04927 04928 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ 04929 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ 04930 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ 04931 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ 04932 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ 04933 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ 04934 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ 04935 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ 04936 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ 04937 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ 04938 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ 04939 04940 /* Register: QDEC_DBFEN */ 04941 /* Description: Enable debouncer input filters. */ 04942 04943 /* Bit 0 : Enable debounce input filters. */ 04944 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ 04945 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ 04946 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ 04947 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ 04948 04949 /* Register: QDEC_LEDPRE */ 04950 /* Description: Time LED is switched ON before the sample. */ 04951 04952 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ 04953 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ 04954 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ 04955 04956 /* Register: QDEC_ACCDBL */ 04957 /* Description: Accumulated double (error) transitions register. */ 04958 04959 /* Bits 3..0 : Accumulated double (error) transitions. */ 04960 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ 04961 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ 04962 04963 /* Register: QDEC_ACCDBLREAD */ 04964 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ 04965 04966 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ 04967 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ 04968 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ 04969 04970 /* Register: QDEC_POWER */ 04971 /* Description: Peripheral power control. */ 04972 04973 /* Bit 0 : Peripheral power control. */ 04974 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 04975 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 04976 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 04977 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 04978 04979 04980 /* Peripheral: RADIO */ 04981 /* Description: The radio. */ 04982 04983 /* Register: RADIO_SHORTS */ 04984 /* Description: Shortcuts for the radio. */ 04985 04986 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ 04987 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 04988 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 04989 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ 04990 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ 04991 04992 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ 04993 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 04994 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 04995 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ 04996 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ 04997 04998 /* Bit 5 : Shortcut between END event and START task. */ 04999 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 05000 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 05001 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ 05002 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ 05003 05004 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ 05005 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 05006 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 05007 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ 05008 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ 05009 05010 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */ 05011 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 05012 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 05013 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ 05014 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ 05015 05016 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */ 05017 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 05018 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 05019 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ 05020 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ 05021 05022 /* Bit 1 : Shortcut between END event and DISABLE task. */ 05023 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 05024 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 05025 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ 05026 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ 05027 05028 /* Bit 0 : Shortcut between READY event and START task. */ 05029 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 05030 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 05031 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ 05032 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ 05033 05034 /* Register: RADIO_INTENSET */ 05035 /* Description: Interrupt enable set register. */ 05036 05037 /* Bit 10 : Enable interrupt on BCMATCH event. */ 05038 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 05039 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 05040 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 05041 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 05042 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ 05043 05044 /* Bit 7 : Enable interrupt on RSSIEND event. */ 05045 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 05046 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 05047 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ 05048 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ 05049 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ 05050 05051 /* Bit 6 : Enable interrupt on DEVMISS event. */ 05052 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 05053 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 05054 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ 05055 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ 05056 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ 05057 05058 /* Bit 5 : Enable interrupt on DEVMATCH event. */ 05059 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 05060 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 05061 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 05062 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 05063 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ 05064 05065 /* Bit 4 : Enable interrupt on DISABLED event. */ 05066 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 05067 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 05068 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ 05069 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ 05070 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ 05071 05072 /* Bit 3 : Enable interrupt on END event. */ 05073 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 05074 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 05075 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 05076 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 05077 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 05078 05079 /* Bit 2 : Enable interrupt on PAYLOAD event. */ 05080 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 05081 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 05082 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ 05083 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ 05084 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ 05085 05086 /* Bit 1 : Enable interrupt on ADDRESS event. */ 05087 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 05088 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 05089 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ 05090 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ 05091 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ 05092 05093 /* Bit 0 : Enable interrupt on READY event. */ 05094 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 05095 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 05096 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 05097 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 05098 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 05099 05100 /* Register: RADIO_INTENCLR */ 05101 /* Description: Interrupt enable clear register. */ 05102 05103 /* Bit 10 : Disable interrupt on BCMATCH event. */ 05104 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 05105 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 05106 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 05107 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 05108 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ 05109 05110 /* Bit 7 : Disable interrupt on RSSIEND event. */ 05111 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 05112 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 05113 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ 05114 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ 05115 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ 05116 05117 /* Bit 6 : Disable interrupt on DEVMISS event. */ 05118 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 05119 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 05120 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ 05121 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ 05122 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ 05123 05124 /* Bit 5 : Disable interrupt on DEVMATCH event. */ 05125 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 05126 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 05127 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 05128 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 05129 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ 05130 05131 /* Bit 4 : Disable interrupt on DISABLED event. */ 05132 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 05133 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 05134 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ 05135 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ 05136 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ 05137 05138 /* Bit 3 : Disable interrupt on END event. */ 05139 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 05140 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 05141 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 05142 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 05143 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 05144 05145 /* Bit 2 : Disable interrupt on PAYLOAD event. */ 05146 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 05147 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 05148 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ 05149 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ 05150 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ 05151 05152 /* Bit 1 : Disable interrupt on ADDRESS event. */ 05153 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 05154 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 05155 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ 05156 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ 05157 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ 05158 05159 /* Bit 0 : Disable interrupt on READY event. */ 05160 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 05161 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 05162 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 05163 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 05164 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 05165 05166 /* Register: RADIO_CRCSTATUS */ 05167 /* Description: CRC status of received packet. */ 05168 05169 /* Bit 0 : CRC status of received packet. */ 05170 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 05171 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 05172 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ 05173 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ 05174 05175 /* Register: RADIO_CD */ 05176 /* Description: Carrier detect. */ 05177 05178 /* Bit 0 : Carrier detect. */ 05179 #define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ 05180 #define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ 05181 05182 /* Register: RADIO_RXMATCH */ 05183 /* Description: Received address. */ 05184 05185 /* Bits 2..0 : Logical address in which previous packet was received. */ 05186 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 05187 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 05188 05189 /* Register: RADIO_RXCRC */ 05190 /* Description: Received CRC. */ 05191 05192 /* Bits 23..0 : CRC field of previously received packet. */ 05193 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 05194 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 05195 05196 /* Register: RADIO_DAI */ 05197 /* Description: Device address match index. */ 05198 05199 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ 05200 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 05201 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 05202 05203 /* Register: RADIO_FREQUENCY */ 05204 /* Description: Frequency. */ 05205 05206 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ 05207 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 05208 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 05209 05210 /* Register: RADIO_TXPOWER */ 05211 /* Description: Output power. */ 05212 05213 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */ 05214 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 05215 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 05216 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ 05217 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ 05218 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ 05219 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ 05220 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ 05221 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ 05222 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ 05223 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ 05224 05225 /* Register: RADIO_MODE */ 05226 /* Description: Data rate and modulation. */ 05227 05228 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ 05229 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 05230 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 05231 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ 05232 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ 05233 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ 05234 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ 05235 05236 /* Register: RADIO_PCNF0 */ 05237 /* Description: Packet configuration 0. */ 05238 05239 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ 05240 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 05241 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 05242 05243 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ 05244 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 05245 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 05246 05247 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ 05248 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 05249 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 05250 05251 /* Register: RADIO_PCNF1 */ 05252 /* Description: Packet configuration 1. */ 05253 05254 /* Bit 25 : Packet whitening enable. */ 05255 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 05256 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 05257 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ 05258 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ 05259 05260 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */ 05261 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 05262 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 05263 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ 05264 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 05265 05266 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ 05267 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 05268 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 05269 05270 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ 05271 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 05272 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 05273 05274 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */ 05275 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 05276 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 05277 05278 /* Register: RADIO_PREFIX0 */ 05279 /* Description: Prefixes bytes for logical addresses 0 to 3. */ 05280 05281 /* Bits 31..24 : Address prefix 3. Decision point: START task. */ 05282 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 05283 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 05284 05285 /* Bits 23..16 : Address prefix 2. Decision point: START task. */ 05286 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 05287 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 05288 05289 /* Bits 15..8 : Address prefix 1. Decision point: START task. */ 05290 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 05291 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 05292 05293 /* Bits 7..0 : Address prefix 0. Decision point: START task. */ 05294 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 05295 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 05296 05297 /* Register: RADIO_PREFIX1 */ 05298 /* Description: Prefixes bytes for logical addresses 4 to 7. */ 05299 05300 /* Bits 31..24 : Address prefix 7. Decision point: START task. */ 05301 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 05302 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 05303 05304 /* Bits 23..16 : Address prefix 6. Decision point: START task. */ 05305 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 05306 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 05307 05308 /* Bits 15..8 : Address prefix 5. Decision point: START task. */ 05309 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 05310 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 05311 05312 /* Bits 7..0 : Address prefix 4. Decision point: START task. */ 05313 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 05314 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 05315 05316 /* Register: RADIO_TXADDRESS */ 05317 /* Description: Transmit address select. */ 05318 05319 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ 05320 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 05321 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 05322 05323 /* Register: RADIO_RXADDRESSES */ 05324 /* Description: Receive address select. */ 05325 05326 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ 05327 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 05328 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 05329 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ 05330 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ 05331 05332 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ 05333 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 05334 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 05335 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ 05336 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ 05337 05338 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ 05339 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 05340 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 05341 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ 05342 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ 05343 05344 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ 05345 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 05346 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 05347 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ 05348 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ 05349 05350 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ 05351 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 05352 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 05353 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ 05354 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ 05355 05356 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ 05357 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 05358 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 05359 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ 05360 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ 05361 05362 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ 05363 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 05364 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 05365 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ 05366 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ 05367 05368 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ 05369 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 05370 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 05371 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ 05372 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ 05373 05374 /* Register: RADIO_CRCCNF */ 05375 /* Description: CRC configuration. */ 05376 05377 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ 05378 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 05379 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 05380 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ 05381 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ 05382 05383 /* Bits 1..0 : CRC length. Decision point: START task. */ 05384 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 05385 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 05386 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ 05387 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ 05388 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ 05389 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ 05390 05391 /* Register: RADIO_CRCPOLY */ 05392 /* Description: CRC polynomial. */ 05393 05394 /* Bits 23..0 : CRC polynomial. Decision point: START task. */ 05395 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 05396 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 05397 05398 /* Register: RADIO_CRCINIT */ 05399 /* Description: CRC initial value. */ 05400 05401 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ 05402 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 05403 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 05404 05405 /* Register: RADIO_TEST */ 05406 /* Description: Test features enable register. */ 05407 05408 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ 05409 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ 05410 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ 05411 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ 05412 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ 05413 05414 /* Bit 0 : Constant carrier. Decision point: TXEN task. */ 05415 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ 05416 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ 05417 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ 05418 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ 05419 05420 /* Register: RADIO_TIFS */ 05421 /* Description: Inter Frame Spacing in microseconds. */ 05422 05423 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ 05424 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 05425 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 05426 05427 /* Register: RADIO_RSSISAMPLE */ 05428 /* Description: RSSI sample. */ 05429 05430 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ 05431 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 05432 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 05433 05434 /* Register: RADIO_STATE */ 05435 /* Description: Current radio state. */ 05436 05437 /* Bits 3..0 : Current radio state. */ 05438 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 05439 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 05440 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ 05441 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ 05442 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ 05443 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ 05444 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ 05445 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ 05446 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ 05447 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ 05448 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ 05449 05450 /* Register: RADIO_DATAWHITEIV */ 05451 /* Description: Data whitening initial value. */ 05452 05453 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ 05454 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 05455 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 05456 05457 /* Register: RADIO_DAP */ 05458 /* Description: Device address prefix. */ 05459 05460 /* Bits 15..0 : Device address prefix. */ 05461 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 05462 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 05463 05464 /* Register: RADIO_DACNF */ 05465 /* Description: Device address match configuration. */ 05466 05467 /* Bit 15 : TxAdd for device address 7. */ 05468 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 05469 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 05470 05471 /* Bit 14 : TxAdd for device address 6. */ 05472 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 05473 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 05474 05475 /* Bit 13 : TxAdd for device address 5. */ 05476 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 05477 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 05478 05479 /* Bit 12 : TxAdd for device address 4. */ 05480 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 05481 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 05482 05483 /* Bit 11 : TxAdd for device address 3. */ 05484 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 05485 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 05486 05487 /* Bit 10 : TxAdd for device address 2. */ 05488 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 05489 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 05490 05491 /* Bit 9 : TxAdd for device address 1. */ 05492 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 05493 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 05494 05495 /* Bit 8 : TxAdd for device address 0. */ 05496 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 05497 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 05498 05499 /* Bit 7 : Enable or disable device address matching using device address 7. */ 05500 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 05501 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 05502 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ 05503 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ 05504 05505 /* Bit 6 : Enable or disable device address matching using device address 6. */ 05506 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 05507 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 05508 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ 05509 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ 05510 05511 /* Bit 5 : Enable or disable device address matching using device address 5. */ 05512 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 05513 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 05514 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ 05515 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ 05516 05517 /* Bit 4 : Enable or disable device address matching using device address 4. */ 05518 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 05519 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 05520 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ 05521 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ 05522 05523 /* Bit 3 : Enable or disable device address matching using device address 3. */ 05524 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 05525 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 05526 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ 05527 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ 05528 05529 /* Bit 2 : Enable or disable device address matching using device address 2. */ 05530 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 05531 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 05532 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ 05533 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ 05534 05535 /* Bit 1 : Enable or disable device address matching using device address 1. */ 05536 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 05537 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 05538 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ 05539 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ 05540 05541 /* Bit 0 : Enable or disable device address matching using device address 0. */ 05542 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 05543 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 05544 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ 05545 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ 05546 05547 /* Register: RADIO_OVERRIDE0 */ 05548 /* Description: Trim value override register 0. */ 05549 05550 /* Bits 31..0 : Trim value override 0. */ 05551 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ 05552 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ 05553 05554 /* Register: RADIO_OVERRIDE1 */ 05555 /* Description: Trim value override register 1. */ 05556 05557 /* Bits 31..0 : Trim value override 1. */ 05558 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ 05559 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ 05560 05561 /* Register: RADIO_OVERRIDE2 */ 05562 /* Description: Trim value override register 2. */ 05563 05564 /* Bits 31..0 : Trim value override 2. */ 05565 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ 05566 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ 05567 05568 /* Register: RADIO_OVERRIDE3 */ 05569 /* Description: Trim value override register 3. */ 05570 05571 /* Bits 31..0 : Trim value override 3. */ 05572 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ 05573 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ 05574 05575 /* Register: RADIO_OVERRIDE4 */ 05576 /* Description: Trim value override register 4. */ 05577 05578 /* Bit 31 : Enable or disable override of default trim values. */ 05579 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ 05580 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 05581 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ 05582 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ 05583 05584 /* Bits 27..0 : Trim value override 4. */ 05585 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ 05586 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ 05587 05588 /* Register: RADIO_POWER */ 05589 /* Description: Peripheral power control. */ 05590 05591 /* Bit 0 : Peripheral power control. */ 05592 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 05593 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 05594 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 05595 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 05596 05597 05598 /* Peripheral: RNG */ 05599 /* Description: Random Number Generator. */ 05600 05601 /* Register: RNG_SHORTS */ 05602 /* Description: Shortcuts for the RNG. */ 05603 05604 /* Bit 0 : Shortcut between VALRDY event and STOP task. */ 05605 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 05606 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 05607 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 05608 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 05609 05610 /* Register: RNG_INTENSET */ 05611 /* Description: Interrupt enable set register */ 05612 05613 /* Bit 0 : Enable interrupt on VALRDY event. */ 05614 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 05615 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 05616 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ 05617 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ 05618 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ 05619 05620 /* Register: RNG_INTENCLR */ 05621 /* Description: Interrupt enable clear register */ 05622 05623 /* Bit 0 : Disable interrupt on VALRDY event. */ 05624 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 05625 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 05626 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ 05627 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ 05628 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ 05629 05630 /* Register: RNG_CONFIG */ 05631 /* Description: Configuration register. */ 05632 05633 /* Bit 0 : Digital error correction enable. */ 05634 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 05635 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 05636 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ 05637 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ 05638 05639 /* Register: RNG_VALUE */ 05640 /* Description: RNG random number. */ 05641 05642 /* Bits 7..0 : Generated random number. */ 05643 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 05644 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 05645 05646 /* Register: RNG_POWER */ 05647 /* Description: Peripheral power control. */ 05648 05649 /* Bit 0 : Peripheral power control. */ 05650 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 05651 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 05652 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 05653 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 05654 05655 05656 /* Peripheral: RTC */ 05657 /* Description: Real time counter 0. */ 05658 05659 /* Register: RTC_INTENSET */ 05660 /* Description: Interrupt enable set register. */ 05661 05662 /* Bit 19 : Enable interrupt on COMPARE[3] event. */ 05663 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 05664 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 05665 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 05666 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 05667 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ 05668 05669 /* Bit 18 : Enable interrupt on COMPARE[2] event. */ 05670 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 05671 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 05672 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 05673 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 05674 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ 05675 05676 /* Bit 17 : Enable interrupt on COMPARE[1] event. */ 05677 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 05678 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 05679 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 05680 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 05681 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ 05682 05683 /* Bit 16 : Enable interrupt on COMPARE[0] event. */ 05684 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 05685 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 05686 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 05687 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 05688 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ 05689 05690 /* Bit 1 : Enable interrupt on OVRFLW event. */ 05691 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 05692 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 05693 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ 05694 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ 05695 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ 05696 05697 /* Bit 0 : Enable interrupt on TICK event. */ 05698 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 05699 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 05700 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ 05701 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ 05702 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ 05703 05704 /* Register: RTC_INTENCLR */ 05705 /* Description: Interrupt enable clear register. */ 05706 05707 /* Bit 19 : Disable interrupt on COMPARE[3] event. */ 05708 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 05709 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 05710 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 05711 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 05712 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ 05713 05714 /* Bit 18 : Disable interrupt on COMPARE[2] event. */ 05715 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 05716 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 05717 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 05718 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 05719 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ 05720 05721 /* Bit 17 : Disable interrupt on COMPARE[1] event. */ 05722 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 05723 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 05724 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 05725 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 05726 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ 05727 05728 /* Bit 16 : Disable interrupt on COMPARE[0] event. */ 05729 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 05730 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 05731 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 05732 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 05733 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ 05734 05735 /* Bit 1 : Disable interrupt on OVRFLW event. */ 05736 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 05737 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 05738 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ 05739 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ 05740 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ 05741 05742 /* Bit 0 : Disable interrupt on TICK event. */ 05743 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 05744 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 05745 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ 05746 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ 05747 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ 05748 05749 /* Register: RTC_EVTEN */ 05750 /* Description: Configures event enable routing to PPI for each RTC event. */ 05751 05752 /* Bit 19 : COMPARE[3] event enable. */ 05753 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 05754 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 05755 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 05756 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 05757 05758 /* Bit 18 : COMPARE[2] event enable. */ 05759 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 05760 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 05761 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 05762 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 05763 05764 /* Bit 17 : COMPARE[1] event enable. */ 05765 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 05766 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 05767 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 05768 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 05769 05770 /* Bit 16 : COMPARE[0] event enable. */ 05771 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 05772 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 05773 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 05774 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 05775 05776 /* Bit 1 : OVRFLW event enable. */ 05777 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 05778 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 05779 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 05780 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 05781 05782 /* Bit 0 : TICK event enable. */ 05783 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 05784 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 05785 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ 05786 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ 05787 05788 /* Register: RTC_EVTENSET */ 05789 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ 05790 05791 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ 05792 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 05793 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 05794 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 05795 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 05796 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ 05797 05798 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ 05799 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 05800 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 05801 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 05802 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 05803 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ 05804 05805 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ 05806 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 05807 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 05808 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 05809 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 05810 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ 05811 05812 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ 05813 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 05814 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 05815 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 05816 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 05817 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ 05818 05819 /* Bit 1 : Enable routing to PPI of OVRFLW event. */ 05820 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 05821 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 05822 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 05823 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 05824 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ 05825 05826 /* Bit 0 : Enable routing to PPI of TICK event. */ 05827 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 05828 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 05829 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ 05830 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ 05831 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ 05832 05833 /* Register: RTC_EVTENCLR */ 05834 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ 05835 05836 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ 05837 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 05838 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 05839 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 05840 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 05841 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ 05842 05843 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ 05844 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 05845 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 05846 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 05847 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 05848 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ 05849 05850 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ 05851 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 05852 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 05853 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 05854 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 05855 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ 05856 05857 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ 05858 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 05859 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 05860 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 05861 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 05862 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ 05863 05864 /* Bit 1 : Disable routing to PPI of OVRFLW event. */ 05865 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 05866 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 05867 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 05868 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 05869 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ 05870 05871 /* Bit 0 : Disable routing to PPI of TICK event. */ 05872 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 05873 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 05874 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ 05875 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ 05876 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ 05877 05878 /* Register: RTC_COUNTER */ 05879 /* Description: Current COUNTER value. */ 05880 05881 /* Bits 23..0 : Counter value. */ 05882 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 05883 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 05884 05885 /* Register: RTC_PRESCALER */ 05886 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ 05887 05888 /* Bits 11..0 : RTC PRESCALER value. */ 05889 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 05890 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 05891 05892 /* Register: RTC_CC */ 05893 /* Description: Capture/compare registers. */ 05894 05895 /* Bits 23..0 : Compare value. */ 05896 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 05897 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 05898 05899 /* Register: RTC_POWER */ 05900 /* Description: Peripheral power control. */ 05901 05902 /* Bit 0 : Peripheral power control. */ 05903 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 05904 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 05905 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 05906 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 05907 05908 05909 /* Peripheral: SPI */ 05910 /* Description: SPI master 0. */ 05911 05912 /* Register: SPI_INTENSET */ 05913 /* Description: Interrupt enable set register. */ 05914 05915 /* Bit 2 : Enable interrupt on READY event. */ 05916 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ 05917 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 05918 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 05919 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 05920 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 05921 05922 /* Register: SPI_INTENCLR */ 05923 /* Description: Interrupt enable clear register. */ 05924 05925 /* Bit 2 : Disable interrupt on READY event. */ 05926 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ 05927 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 05928 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 05929 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 05930 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 05931 05932 /* Register: SPI_ENABLE */ 05933 /* Description: Enable SPI. */ 05934 05935 /* Bits 2..0 : Enable or disable SPI. */ 05936 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 05937 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 05938 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ 05939 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ 05940 05941 /* Register: SPI_RXD */ 05942 /* Description: RX data. */ 05943 05944 /* Bits 7..0 : RX data from last transfer. */ 05945 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 05946 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 05947 05948 /* Register: SPI_TXD */ 05949 /* Description: TX data. */ 05950 05951 /* Bits 7..0 : TX data for next transfer. */ 05952 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 05953 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 05954 05955 /* Register: SPI_FREQUENCY */ 05956 /* Description: SPI frequency */ 05957 05958 /* Bits 31..0 : SPI data rate. */ 05959 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 05960 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 05961 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ 05962 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ 05963 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ 05964 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ 05965 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ 05966 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ 05967 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ 05968 05969 /* Register: SPI_CONFIG */ 05970 /* Description: Configuration register. */ 05971 05972 /* Bit 2 : Serial clock (SCK) polarity. */ 05973 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 05974 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 05975 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 05976 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 05977 05978 /* Bit 1 : Serial clock (SCK) phase. */ 05979 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 05980 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 05981 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 05982 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 05983 05984 /* Bit 0 : Bit order. */ 05985 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 05986 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 05987 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 05988 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 05989 05990 /* Register: SPI_POWER */ 05991 /* Description: Peripheral power control. */ 05992 05993 /* Bit 0 : Peripheral power control. */ 05994 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 05995 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 05996 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 05997 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 05998 05999 06000 /* Peripheral: SPIM */ 06001 /* Description: SPI master with easyDMA 1. */ 06002 06003 /* Register: SPIM_SHORTS */ 06004 /* Description: Shortcuts for SPIM. */ 06005 06006 /* Bit 17 : Shortcut between END event and START task. */ 06007 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 06008 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 06009 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ 06010 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ 06011 06012 /* Register: SPIM_INTENSET */ 06013 /* Description: Interrupt enable set register. */ 06014 06015 /* Bit 19 : Enable interrupt on STARTED event. */ 06016 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 06017 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 06018 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ 06019 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ 06020 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ 06021 06022 /* Bit 8 : Enable interrupt on ENDTX event. */ 06023 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 06024 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 06025 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ 06026 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ 06027 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ 06028 06029 /* Bit 6 : Enable interrupt on END event. */ 06030 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 06031 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 06032 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 06033 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 06034 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 06035 06036 /* Bit 4 : Enable interrupt on ENDRX event. */ 06037 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 06038 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 06039 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ 06040 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ 06041 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ 06042 06043 /* Bit 1 : Enable interrupt on STOPPED event. */ 06044 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 06045 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 06046 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 06047 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 06048 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ 06049 06050 /* Register: SPIM_INTENCLR */ 06051 /* Description: Interrupt enable clear register. */ 06052 06053 /* Bit 19 : Disable interrupt on STARTED event. */ 06054 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 06055 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 06056 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ 06057 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ 06058 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ 06059 06060 /* Bit 8 : Disable interrupt on ENDTX event. */ 06061 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 06062 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 06063 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ 06064 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ 06065 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ 06066 06067 /* Bit 6 : Disable interrupt on END event. */ 06068 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 06069 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 06070 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 06071 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 06072 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 06073 06074 /* Bit 4 : Disable interrupt on ENDRX event. */ 06075 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 06076 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 06077 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ 06078 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ 06079 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ 06080 06081 /* Bit 1 : Disable interrupt on STOPPED event. */ 06082 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 06083 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 06084 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 06085 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 06086 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ 06087 06088 /* Register: SPIM_ENABLE */ 06089 /* Description: Enable SPIM. */ 06090 06091 /* Bits 3..0 : Enable or disable SPIM. */ 06092 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 06093 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 06094 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ 06095 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ 06096 06097 /* Register: SPIM_RXDDATA */ 06098 /* Description: RXD register. */ 06099 06100 /* Bits 7..0 : RX data received. Double buffered. */ 06101 #define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */ 06102 #define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */ 06103 06104 /* Register: SPIM_TXDDATA */ 06105 /* Description: TXD register. */ 06106 06107 /* Bits 7..0 : TX data to send. Double buffered. */ 06108 #define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */ 06109 #define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */ 06110 06111 /* Register: SPIM_FREQUENCY */ 06112 /* Description: SPI frequency. */ 06113 06114 /* Bits 31..0 : SPI master data rate. */ 06115 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 06116 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 06117 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ 06118 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ 06119 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ 06120 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ 06121 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ 06122 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ 06123 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ 06124 06125 /* Register: SPIM_CONFIG */ 06126 /* Description: Configuration register. */ 06127 06128 /* Bit 2 : Serial clock (SCK) polarity. */ 06129 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 06130 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 06131 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 06132 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 06133 06134 /* Bit 1 : Serial clock (SCK) phase. */ 06135 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 06136 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 06137 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 06138 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 06139 06140 /* Bit 0 : Bit order. */ 06141 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 06142 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 06143 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 06144 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 06145 06146 /* Register: SPIM_ORC */ 06147 /* Description: Over-read character. */ 06148 06149 /* Bits 7..0 : Over-read character. */ 06150 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 06151 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 06152 06153 /* Register: SPIM_POWER */ 06154 /* Description: Peripheral power control. */ 06155 06156 /* Bit 0 : Peripheral power control. */ 06157 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 06158 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 06159 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 06160 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 06161 06162 /* Register: SPIM_RXD_PTR */ 06163 /* Description: Data pointer. */ 06164 06165 /* Bits 31..0 : Data pointer. */ 06166 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 06167 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 06168 06169 /* Register: SPIM_RXD_MAXCNT */ 06170 /* Description: Maximum number of buffer bytes to receive. */ 06171 06172 /* Bits 7..0 : Maximum number of buffer bytes to receive. */ 06173 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 06174 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 06175 06176 /* Register: SPIM_RXD_AMOUNT */ 06177 /* Description: Number of bytes received in the last transaction. */ 06178 06179 /* Bits 7..0 : Number of bytes received in the last transaction. */ 06180 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 06181 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 06182 06183 /* Register: SPIM_TXD_PTR */ 06184 /* Description: Data pointer. */ 06185 06186 /* Bits 31..0 : Data pointer. */ 06187 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 06188 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 06189 06190 /* Register: SPIM_TXD_MAXCNT */ 06191 /* Description: Maximum number of buffer bytes to send. */ 06192 06193 /* Bits 7..0 : Maximum number of buffer bytes to send. */ 06194 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 06195 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 06196 06197 /* Register: SPIM_TXD_AMOUNT */ 06198 /* Description: Number of bytes sent in the last transaction. */ 06199 06200 /* Bits 7..0 : Number of bytes sent in the last transaction. */ 06201 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 06202 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 06203 06204 06205 /* Peripheral: SPIS */ 06206 /* Description: SPI slave 1. */ 06207 06208 /* Register: SPIS_SHORTS */ 06209 /* Description: Shortcuts for SPIS. */ 06210 06211 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */ 06212 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 06213 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 06214 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ 06215 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ 06216 06217 /* Register: SPIS_INTENSET */ 06218 /* Description: Interrupt enable set register. */ 06219 06220 /* Bit 10 : Enable interrupt on ACQUIRED event. */ 06221 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 06222 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 06223 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ 06224 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ 06225 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ 06226 06227 /* Bit 1 : Enable interrupt on END event. */ 06228 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 06229 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 06230 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 06231 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 06232 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 06233 06234 /* Register: SPIS_INTENCLR */ 06235 /* Description: Interrupt enable clear register. */ 06236 06237 /* Bit 10 : Disable interrupt on ACQUIRED event. */ 06238 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 06239 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 06240 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ 06241 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ 06242 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ 06243 06244 /* Bit 1 : Disable interrupt on END event. */ 06245 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 06246 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 06247 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 06248 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 06249 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 06250 06251 /* Register: SPIS_SEMSTAT */ 06252 /* Description: Semaphore status. */ 06253 06254 /* Bits 1..0 : Semaphore status. */ 06255 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 06256 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 06257 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ 06258 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ 06259 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ 06260 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ 06261 06262 /* Register: SPIS_STATUS */ 06263 /* Description: Status from last transaction. */ 06264 06265 /* Bit 1 : RX buffer overflow detected, and prevented. */ 06266 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 06267 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 06268 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ 06269 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ 06270 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ 06271 06272 /* Bit 0 : TX buffer overread detected, and prevented. */ 06273 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 06274 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 06275 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ 06276 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ 06277 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ 06278 06279 /* Register: SPIS_ENABLE */ 06280 /* Description: Enable SPIS. */ 06281 06282 /* Bits 2..0 : Enable or disable SPIS. */ 06283 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 06284 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 06285 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ 06286 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ 06287 06288 /* Register: SPIS_MAXRX */ 06289 /* Description: Maximum number of bytes in the receive buffer. */ 06290 06291 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */ 06292 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ 06293 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ 06294 06295 /* Register: SPIS_AMOUNTRX */ 06296 /* Description: Number of bytes received in last granted transaction. */ 06297 06298 /* Bits 7..0 : Number of bytes received in last granted transaction. */ 06299 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ 06300 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ 06301 06302 /* Register: SPIS_MAXTX */ 06303 /* Description: Maximum number of bytes in the transmit buffer. */ 06304 06305 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ 06306 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ 06307 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ 06308 06309 /* Register: SPIS_AMOUNTTX */ 06310 /* Description: Number of bytes transmitted in last granted transaction. */ 06311 06312 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ 06313 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ 06314 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ 06315 06316 /* Register: SPIS_CONFIG */ 06317 /* Description: Configuration register. */ 06318 06319 /* Bit 2 : Serial clock (SCK) polarity. */ 06320 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 06321 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 06322 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 06323 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 06324 06325 /* Bit 1 : Serial clock (SCK) phase. */ 06326 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 06327 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 06328 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 06329 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 06330 06331 /* Bit 0 : Bit order. */ 06332 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 06333 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 06334 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 06335 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 06336 06337 /* Register: SPIS_DEF */ 06338 /* Description: Default character. */ 06339 06340 /* Bits 7..0 : Default character. */ 06341 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 06342 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 06343 06344 /* Register: SPIS_ORC */ 06345 /* Description: Over-read character. */ 06346 06347 /* Bits 7..0 : Over-read character. */ 06348 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 06349 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 06350 06351 /* Register: SPIS_POWER */ 06352 /* Description: Peripheral power control. */ 06353 06354 /* Bit 0 : Peripheral power control. */ 06355 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 06356 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 06357 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 06358 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 06359 06360 06361 /* Peripheral: TEMP */ 06362 /* Description: Temperature Sensor. */ 06363 06364 /* Register: TEMP_INTENSET */ 06365 /* Description: Interrupt enable set register. */ 06366 06367 /* Bit 0 : Enable interrupt on DATARDY event. */ 06368 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 06369 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 06370 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ 06371 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ 06372 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ 06373 06374 /* Register: TEMP_INTENCLR */ 06375 /* Description: Interrupt enable clear register. */ 06376 06377 /* Bit 0 : Disable interrupt on DATARDY event. */ 06378 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 06379 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 06380 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ 06381 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ 06382 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ 06383 06384 /* Register: TEMP_POWER */ 06385 /* Description: Peripheral power control. */ 06386 06387 /* Bit 0 : Peripheral power control. */ 06388 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 06389 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 06390 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 06391 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 06392 06393 06394 /* Peripheral: TIMER */ 06395 /* Description: Timer 0. */ 06396 06397 /* Register: TIMER_SHORTS */ 06398 /* Description: Shortcuts for Timer. */ 06399 06400 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */ 06401 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 06402 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 06403 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 06404 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 06405 06406 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */ 06407 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 06408 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 06409 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 06410 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 06411 06412 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */ 06413 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 06414 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 06415 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 06416 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 06417 06418 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */ 06419 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 06420 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 06421 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 06422 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 06423 06424 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ 06425 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 06426 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 06427 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 06428 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 06429 06430 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ 06431 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 06432 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 06433 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 06434 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 06435 06436 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ 06437 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 06438 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 06439 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 06440 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 06441 06442 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ 06443 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 06444 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 06445 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 06446 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 06447 06448 /* Register: TIMER_INTENSET */ 06449 /* Description: Interrupt enable set register. */ 06450 06451 /* Bit 19 : Enable interrupt on COMPARE[3] */ 06452 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 06453 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 06454 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 06455 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 06456 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ 06457 06458 /* Bit 18 : Enable interrupt on COMPARE[2] */ 06459 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 06460 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 06461 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 06462 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 06463 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ 06464 06465 /* Bit 17 : Enable interrupt on COMPARE[1] */ 06466 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 06467 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 06468 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 06469 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 06470 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ 06471 06472 /* Bit 16 : Enable interrupt on COMPARE[0] */ 06473 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 06474 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 06475 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 06476 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 06477 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ 06478 06479 /* Register: TIMER_INTENCLR */ 06480 /* Description: Interrupt enable clear register. */ 06481 06482 /* Bit 19 : Disable interrupt on COMPARE[3] */ 06483 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 06484 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 06485 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 06486 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 06487 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ 06488 06489 /* Bit 18 : Disable interrupt on COMPARE[2] */ 06490 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 06491 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 06492 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 06493 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 06494 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ 06495 06496 /* Bit 17 : Disable interrupt on COMPARE[1] */ 06497 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 06498 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 06499 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 06500 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 06501 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ 06502 06503 /* Bit 16 : Disable interrupt on COMPARE[0] */ 06504 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 06505 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 06506 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 06507 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 06508 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ 06509 06510 /* Register: TIMER_MODE */ 06511 /* Description: Timer Mode selection. */ 06512 06513 /* Bit 0 : Select Normal or Counter mode. */ 06514 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 06515 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 06516 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ 06517 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ 06518 06519 /* Register: TIMER_BITMODE */ 06520 /* Description: Sets timer behaviour. */ 06521 06522 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ 06523 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 06524 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 06525 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ 06526 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ 06527 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ 06528 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ 06529 06530 /* Register: TIMER_PRESCALER */ 06531 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ 06532 06533 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ 06534 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 06535 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 06536 06537 /* Register: TIMER_POWER */ 06538 /* Description: Peripheral power control. */ 06539 06540 /* Bit 0 : Peripheral power control. */ 06541 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 06542 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 06543 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 06544 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 06545 06546 06547 /* Peripheral: TWI */ 06548 /* Description: Two-wire interface master 0. */ 06549 06550 /* Register: TWI_SHORTS */ 06551 /* Description: Shortcuts for TWI. */ 06552 06553 /* Bit 1 : Shortcut between BB event and the STOP task. */ 06554 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ 06555 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ 06556 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 06557 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 06558 06559 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */ 06560 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ 06561 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ 06562 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ 06563 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ 06564 06565 /* Register: TWI_INTENSET */ 06566 /* Description: Interrupt enable set register. */ 06567 06568 /* Bit 18 : Enable interrupt on SUSPENDED event. */ 06569 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 06570 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 06571 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ 06572 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ 06573 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ 06574 06575 /* Bit 14 : Enable interrupt on BB event. */ 06576 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ 06577 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ 06578 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ 06579 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ 06580 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ 06581 06582 /* Bit 9 : Enable interrupt on ERROR event. */ 06583 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 06584 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06585 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 06586 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 06587 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 06588 06589 /* Bit 7 : Enable interrupt on TXDSENT event. */ 06590 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 06591 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 06592 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ 06593 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ 06594 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ 06595 06596 /* Bit 2 : Enable interrupt on READY event. */ 06597 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 06598 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 06599 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ 06600 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ 06601 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ 06602 06603 /* Bit 1 : Enable interrupt on STOPPED event. */ 06604 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 06605 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 06606 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 06607 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 06608 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ 06609 06610 /* Register: TWI_INTENCLR */ 06611 /* Description: Interrupt enable clear register. */ 06612 06613 /* Bit 18 : Disable interrupt on SUSPENDED event. */ 06614 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 06615 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 06616 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ 06617 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ 06618 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ 06619 06620 /* Bit 14 : Disable interrupt on BB event. */ 06621 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ 06622 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ 06623 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ 06624 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ 06625 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ 06626 06627 /* Bit 9 : Disable interrupt on ERROR event. */ 06628 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 06629 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06630 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 06631 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 06632 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 06633 06634 /* Bit 7 : Disable interrupt on TXDSENT event. */ 06635 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 06636 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 06637 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ 06638 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ 06639 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ 06640 06641 /* Bit 2 : Disable interrupt on RXDREADY event. */ 06642 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 06643 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 06644 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ 06645 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ 06646 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ 06647 06648 /* Bit 1 : Disable interrupt on STOPPED event. */ 06649 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 06650 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 06651 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 06652 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 06653 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ 06654 06655 /* Register: TWI_ERRORSRC */ 06656 /* Description: Two-wire error source. Write error field to 1 to clear error. */ 06657 06658 /* Bit 2 : NACK received after sending a data byte. */ 06659 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 06660 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 06661 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ 06662 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ 06663 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ 06664 06665 /* Bit 1 : NACK received after sending the address. */ 06666 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 06667 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 06668 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ 06669 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ 06670 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ 06671 06672 /* Register: TWI_ENABLE */ 06673 /* Description: Enable two-wire master. */ 06674 06675 /* Bits 2..0 : Enable or disable W2M */ 06676 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 06677 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 06678 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ 06679 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ 06680 06681 /* Register: TWI_RXD */ 06682 /* Description: RX data register. */ 06683 06684 /* Bits 7..0 : RX data from last transfer. */ 06685 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 06686 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 06687 06688 /* Register: TWI_TXD */ 06689 /* Description: TX data register. */ 06690 06691 /* Bits 7..0 : TX data for next transfer. */ 06692 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 06693 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 06694 06695 /* Register: TWI_FREQUENCY */ 06696 /* Description: Two-wire frequency. */ 06697 06698 /* Bits 31..0 : Two-wire master clock frequency. */ 06699 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 06700 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 06701 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ 06702 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ 06703 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ 06704 06705 /* Register: TWI_ADDRESS */ 06706 /* Description: Address used in the two-wire transfer. */ 06707 06708 /* Bits 6..0 : Two-wire address. */ 06709 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 06710 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 06711 06712 /* Register: TWI_POWER */ 06713 /* Description: Peripheral power control. */ 06714 06715 /* Bit 0 : Peripheral power control. */ 06716 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 06717 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 06718 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 06719 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 06720 06721 06722 /* Peripheral: UART */ 06723 /* Description: Universal Asynchronous Receiver/Transmitter. */ 06724 06725 /* Register: UART_SHORTS */ 06726 /* Description: Shortcuts for UART. */ 06727 06728 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ 06729 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ 06730 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ 06731 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ 06732 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ 06733 06734 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */ 06735 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ 06736 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ 06737 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ 06738 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ 06739 06740 /* Register: UART_INTENSET */ 06741 /* Description: Interrupt enable set register. */ 06742 06743 /* Bit 17 : Enable interrupt on RXTO event. */ 06744 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 06745 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 06746 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ 06747 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ 06748 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ 06749 06750 /* Bit 9 : Enable interrupt on ERROR event. */ 06751 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 06752 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06753 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 06754 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 06755 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 06756 06757 /* Bit 7 : Enable interrupt on TXRDY event. */ 06758 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 06759 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 06760 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 06761 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 06762 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ 06763 06764 /* Bit 2 : Enable interrupt on RXRDY event. */ 06765 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 06766 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 06767 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 06768 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 06769 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ 06770 06771 /* Bit 1 : Enable interrupt on NCTS event. */ 06772 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 06773 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 06774 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ 06775 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ 06776 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ 06777 06778 /* Bit 0 : Enable interrupt on CTS event. */ 06779 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 06780 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 06781 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ 06782 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ 06783 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ 06784 06785 /* Register: UART_INTENCLR */ 06786 /* Description: Interrupt enable clear register. */ 06787 06788 /* Bit 17 : Disable interrupt on RXTO event. */ 06789 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 06790 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 06791 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ 06792 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ 06793 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ 06794 06795 /* Bit 9 : Disable interrupt on ERROR event. */ 06796 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 06797 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06798 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 06799 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 06800 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 06801 06802 /* Bit 7 : Disable interrupt on TXRDY event. */ 06803 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 06804 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 06805 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 06806 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 06807 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ 06808 06809 /* Bit 2 : Disable interrupt on RXRDY event. */ 06810 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 06811 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 06812 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 06813 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 06814 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ 06815 06816 /* Bit 1 : Disable interrupt on NCTS event. */ 06817 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 06818 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 06819 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ 06820 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ 06821 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ 06822 06823 /* Bit 0 : Disable interrupt on CTS event. */ 06824 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 06825 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 06826 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ 06827 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ 06828 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ 06829 06830 /* Register: UART_ERRORSRC */ 06831 /* Description: Error source. Write error field to 1 to clear error. */ 06832 06833 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ 06834 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 06835 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 06836 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ 06837 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ 06838 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ 06839 06840 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ 06841 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 06842 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 06843 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ 06844 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ 06845 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ 06846 06847 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ 06848 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 06849 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 06850 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ 06851 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ 06852 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ 06853 06854 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ 06855 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 06856 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 06857 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ 06858 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ 06859 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ 06860 06861 /* Register: UART_ENABLE */ 06862 /* Description: Enable UART and acquire IOs. */ 06863 06864 /* Bits 2..0 : Enable or disable UART and acquire IOs. */ 06865 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 06866 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 06867 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ 06868 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ 06869 06870 /* Register: UART_RXD */ 06871 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ 06872 06873 /* Bits 7..0 : RX data from previous transfer. Double buffered. */ 06874 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 06875 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 06876 06877 /* Register: UART_TXD */ 06878 /* Description: TXD register. */ 06879 06880 /* Bits 7..0 : TX data for transfer. */ 06881 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 06882 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 06883 06884 /* Register: UART_BAUDRATE */ 06885 /* Description: UART Baudrate. */ 06886 06887 /* Bits 31..0 : UART baudrate. */ 06888 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 06889 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 06890 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ 06891 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ 06892 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ 06893 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ 06894 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ 06895 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ 06896 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ 06897 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ 06898 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ 06899 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ 06900 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ 06901 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ 06902 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ 06903 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ 06904 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */ 06905 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ 06906 06907 /* Register: UART_CONFIG */ 06908 /* Description: Configuration of parity and hardware flow control register. */ 06909 06910 /* Bits 3..1 : Include parity bit. */ 06911 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 06912 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 06913 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ 06914 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ 06915 06916 /* Bit 0 : Hardware flow control. */ 06917 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 06918 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 06919 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ 06920 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ 06921 06922 /* Register: UART_POWER */ 06923 /* Description: Peripheral power control. */ 06924 06925 /* Bit 0 : Peripheral power control. */ 06926 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 06927 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 06928 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 06929 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 06930 06931 06932 /* Peripheral: UICR */ 06933 /* Description: User Information Configuration. */ 06934 06935 /* Register: UICR_RBPCONF */ 06936 /* Description: Readback protection configuration. */ 06937 06938 /* Bits 15..8 : Readback protect all code in the device. */ 06939 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ 06940 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ 06941 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ 06942 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ 06943 06944 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ 06945 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ 06946 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ 06947 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ 06948 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ 06949 06950 /* Register: UICR_XTALFREQ */ 06951 /* Description: Reset value for CLOCK XTALFREQ register. */ 06952 06953 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ 06954 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ 06955 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ 06956 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ 06957 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ 06958 06959 /* Register: UICR_FWID */ 06960 /* Description: Firmware ID. */ 06961 06962 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */ 06963 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ 06964 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ 06965 06966 06967 /* Peripheral: WDT */ 06968 /* Description: Watchdog Timer. */ 06969 06970 /* Register: WDT_INTENSET */ 06971 /* Description: Interrupt enable set register. */ 06972 06973 /* Bit 0 : Enable interrupt on TIMEOUT event. */ 06974 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 06975 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 06976 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ 06977 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ 06978 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ 06979 06980 /* Register: WDT_INTENCLR */ 06981 /* Description: Interrupt enable clear register. */ 06982 06983 /* Bit 0 : Disable interrupt on TIMEOUT event. */ 06984 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 06985 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 06986 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ 06987 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ 06988 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ 06989 06990 /* Register: WDT_RUNSTATUS */ 06991 /* Description: Watchdog running status. */ 06992 06993 /* Bit 0 : Watchdog running status. */ 06994 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ 06995 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ 06996 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ 06997 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ 06998 06999 /* Register: WDT_REQSTATUS */ 07000 /* Description: Request status. */ 07001 07002 /* Bit 7 : Request status for RR[7]. */ 07003 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 07004 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 07005 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ 07006 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ 07007 07008 /* Bit 6 : Request status for RR[6]. */ 07009 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 07010 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 07011 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ 07012 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ 07013 07014 /* Bit 5 : Request status for RR[5]. */ 07015 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 07016 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 07017 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ 07018 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ 07019 07020 /* Bit 4 : Request status for RR[4]. */ 07021 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 07022 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 07023 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ 07024 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ 07025 07026 /* Bit 3 : Request status for RR[3]. */ 07027 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 07028 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 07029 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ 07030 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ 07031 07032 /* Bit 2 : Request status for RR[2]. */ 07033 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 07034 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 07035 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ 07036 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ 07037 07038 /* Bit 1 : Request status for RR[1]. */ 07039 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 07040 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 07041 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ 07042 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ 07043 07044 /* Bit 0 : Request status for RR[0]. */ 07045 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 07046 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 07047 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ 07048 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ 07049 07050 /* Register: WDT_RREN */ 07051 /* Description: Reload request enable. */ 07052 07053 /* Bit 7 : Enable or disable RR[7] register. */ 07054 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 07055 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 07056 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ 07057 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ 07058 07059 /* Bit 6 : Enable or disable RR[6] register. */ 07060 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 07061 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 07062 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ 07063 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ 07064 07065 /* Bit 5 : Enable or disable RR[5] register. */ 07066 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 07067 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 07068 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ 07069 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ 07070 07071 /* Bit 4 : Enable or disable RR[4] register. */ 07072 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 07073 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 07074 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ 07075 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ 07076 07077 /* Bit 3 : Enable or disable RR[3] register. */ 07078 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 07079 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 07080 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ 07081 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ 07082 07083 /* Bit 2 : Enable or disable RR[2] register. */ 07084 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 07085 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 07086 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ 07087 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ 07088 07089 /* Bit 1 : Enable or disable RR[1] register. */ 07090 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 07091 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 07092 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ 07093 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ 07094 07095 /* Bit 0 : Enable or disable RR[0] register. */ 07096 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 07097 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 07098 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ 07099 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ 07100 07101 /* Register: WDT_CONFIG */ 07102 /* Description: Configuration register. */ 07103 07104 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ 07105 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 07106 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 07107 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ 07108 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ 07109 07110 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ 07111 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 07112 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 07113 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ 07114 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ 07115 07116 /* Register: WDT_RR */ 07117 /* Description: Reload requests registers. */ 07118 07119 /* Bits 31..0 : Reload register. */ 07120 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 07121 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 07122 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ 07123 07124 /* Register: WDT_POWER */ 07125 /* Description: Peripheral power control. */ 07126 07127 /* Bit 0 : Peripheral power control. */ 07128 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 07129 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 07130 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 07131 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 07132 07133 07134 /*lint --flb "Leave library region" */ 07135 #endif
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