Freescale_Cachan / Mbed 2 deprecated Programme_course_vir_am_2

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Dependencies:   MMA8451Q mbed

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BP_MemMap Struct Reference
Data Fields

BP_MemMap Struct Reference
[BP]

BP - Peripheral register structure. More...

#include <MKL25Z4.h>

Data Fields

uint32_t CTRL
 FlashPatch Control Register, offset: 0x0.
uint32_t COMP [2]
 FlashPatch Comparator Register 0..FlashPatch Comparator Register 1, array offset: 0x8, array step: 0x4.
uint32_t PID4
 Peripheral Identification Register 4., offset: 0xFD0.
uint32_t PID5
 Peripheral Identification Register 5., offset: 0xFD4.
uint32_t PID6
 Peripheral Identification Register 6., offset: 0xFD8.
uint32_t PID7
 Peripheral Identification Register 7., offset: 0xFDC.
uint32_t PID0
 Peripheral Identification Register 0., offset: 0xFE0.
uint32_t PID1
 Peripheral Identification Register 1., offset: 0xFE4.
uint32_t PID2
 Peripheral Identification Register 2., offset: 0xFE8.
uint32_t PID3
 Peripheral Identification Register 3., offset: 0xFEC.
uint32_t CID0
 Component Identification Register 0., offset: 0xFF0.
uint32_t CID1
 Component Identification Register 1., offset: 0xFF4.
uint32_t CID2
 Component Identification Register 2., offset: 0xFF8.
uint32_t CID3
 Component Identification Register 3., offset: 0xFFC.

Detailed Description

BP - Peripheral register structure.

Definition at line 480 of file MKL25Z4.h.

Field Documentation

uint32_t CID0

Component Identification Register 0., offset: 0xFF0.

Definition at line 493 of file MKL25Z4.h.

uint32_t CID1

Component Identification Register 1., offset: 0xFF4.

Definition at line 494 of file MKL25Z4.h.

uint32_t CID2

Component Identification Register 2., offset: 0xFF8.

Definition at line 495 of file MKL25Z4.h.

uint32_t CID3

Component Identification Register 3., offset: 0xFFC.

Definition at line 496 of file MKL25Z4.h.

uint32_t COMP[2]

FlashPatch Comparator Register 0..FlashPatch Comparator Register 1, array offset: 0x8, array step: 0x4.

Definition at line 483 of file MKL25Z4.h.

uint32_t CTRL

FlashPatch Control Register, offset: 0x0.

Definition at line 481 of file MKL25Z4.h.

uint32_t PID0

Peripheral Identification Register 0., offset: 0xFE0.

Definition at line 489 of file MKL25Z4.h.

uint32_t PID1

Peripheral Identification Register 1., offset: 0xFE4.

Definition at line 490 of file MKL25Z4.h.

uint32_t PID2

Peripheral Identification Register 2., offset: 0xFE8.

Definition at line 491 of file MKL25Z4.h.

uint32_t PID3

Peripheral Identification Register 3., offset: 0xFEC.

Definition at line 492 of file MKL25Z4.h.

uint32_t PID4

Peripheral Identification Register 4., offset: 0xFD0.

Definition at line 485 of file MKL25Z4.h.

uint32_t PID5

Peripheral Identification Register 5., offset: 0xFD4.

Definition at line 486 of file MKL25Z4.h.

uint32_t PID6

Peripheral Identification Register 6., offset: 0xFD8.

Definition at line 487 of file MKL25Z4.h.

uint32_t PID7

Peripheral Identification Register 7., offset: 0xFDC.

Definition at line 488 of file MKL25Z4.h.

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