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Dependencies:   MMA8451Q mbed

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ADC_MemMap Struct Reference
Data Fields

ADC_MemMap Struct Reference
[ADC]

ADC - Peripheral register structure. More...

#include <MKL25Z4.h>

Data Fields

uint32_t SC1 [2]
 ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.
uint32_t CFG1
 ADC Configuration Register 1, offset: 0x8.
uint32_t CFG2
 ADC Configuration Register 2, offset: 0xC.
uint32_t R [2]
 ADC Data Result Register, array offset: 0x10, array step: 0x4.
uint32_t CV1
 Compare Value Registers, offset: 0x18.
uint32_t CV2
 Compare Value Registers, offset: 0x1C.
uint32_t SC2
 Status and Control Register 2, offset: 0x20.
uint32_t SC3
 Status and Control Register 3, offset: 0x24.
uint32_t OFS
 ADC Offset Correction Register, offset: 0x28.
uint32_t PG
 ADC Plus-Side Gain Register, offset: 0x2C.
uint32_t MG
 ADC Minus-Side Gain Register, offset: 0x30.
uint32_t CLPD
 ADC Plus-Side General Calibration Value Register, offset: 0x34.
uint32_t CLPS
 ADC Plus-Side General Calibration Value Register, offset: 0x38.
uint32_t CLP4
 ADC Plus-Side General Calibration Value Register, offset: 0x3C.
uint32_t CLP3
 ADC Plus-Side General Calibration Value Register, offset: 0x40.
uint32_t CLP2
 ADC Plus-Side General Calibration Value Register, offset: 0x44.
uint32_t CLP1
 ADC Plus-Side General Calibration Value Register, offset: 0x48.
uint32_t CLP0
 ADC Plus-Side General Calibration Value Register, offset: 0x4C.
uint32_t CLMD
 ADC Minus-Side General Calibration Value Register, offset: 0x54.
uint32_t CLMS
 ADC Minus-Side General Calibration Value Register, offset: 0x58.
uint32_t CLM4
 ADC Minus-Side General Calibration Value Register, offset: 0x5C.
uint32_t CLM3
 ADC Minus-Side General Calibration Value Register, offset: 0x60.
uint32_t CLM2
 ADC Minus-Side General Calibration Value Register, offset: 0x64.
uint32_t CLM1
 ADC Minus-Side General Calibration Value Register, offset: 0x68.
uint32_t CLM0
 ADC Minus-Side General Calibration Value Register, offset: 0x6C.

Detailed Description

ADC - Peripheral register structure.

Definition at line 182 of file MKL25Z4.h.

Field Documentation

uint32_t CFG1

ADC Configuration Register 1, offset: 0x8.

Definition at line 184 of file MKL25Z4.h.

uint32_t CFG2

ADC Configuration Register 2, offset: 0xC.

Definition at line 185 of file MKL25Z4.h.

uint32_t CLM0

ADC Minus-Side General Calibration Value Register, offset: 0x6C.

Definition at line 208 of file MKL25Z4.h.

uint32_t CLM1

ADC Minus-Side General Calibration Value Register, offset: 0x68.

Definition at line 207 of file MKL25Z4.h.

uint32_t CLM2

ADC Minus-Side General Calibration Value Register, offset: 0x64.

Definition at line 206 of file MKL25Z4.h.

uint32_t CLM3

ADC Minus-Side General Calibration Value Register, offset: 0x60.

Definition at line 205 of file MKL25Z4.h.

uint32_t CLM4

ADC Minus-Side General Calibration Value Register, offset: 0x5C.

Definition at line 204 of file MKL25Z4.h.

uint32_t CLMD

ADC Minus-Side General Calibration Value Register, offset: 0x54.

Definition at line 202 of file MKL25Z4.h.

uint32_t CLMS

ADC Minus-Side General Calibration Value Register, offset: 0x58.

Definition at line 203 of file MKL25Z4.h.

uint32_t CLP0

ADC Plus-Side General Calibration Value Register, offset: 0x4C.

Definition at line 200 of file MKL25Z4.h.

uint32_t CLP1

ADC Plus-Side General Calibration Value Register, offset: 0x48.

Definition at line 199 of file MKL25Z4.h.

uint32_t CLP2

ADC Plus-Side General Calibration Value Register, offset: 0x44.

Definition at line 198 of file MKL25Z4.h.

uint32_t CLP3

ADC Plus-Side General Calibration Value Register, offset: 0x40.

Definition at line 197 of file MKL25Z4.h.

uint32_t CLP4

ADC Plus-Side General Calibration Value Register, offset: 0x3C.

Definition at line 196 of file MKL25Z4.h.

uint32_t CLPD

ADC Plus-Side General Calibration Value Register, offset: 0x34.

Definition at line 194 of file MKL25Z4.h.

uint32_t CLPS

ADC Plus-Side General Calibration Value Register, offset: 0x38.

Definition at line 195 of file MKL25Z4.h.

uint32_t CV1

Compare Value Registers, offset: 0x18.

Definition at line 187 of file MKL25Z4.h.

uint32_t CV2

Compare Value Registers, offset: 0x1C.

Definition at line 188 of file MKL25Z4.h.

uint32_t MG

ADC Minus-Side Gain Register, offset: 0x30.

Definition at line 193 of file MKL25Z4.h.

uint32_t OFS

ADC Offset Correction Register, offset: 0x28.

Definition at line 191 of file MKL25Z4.h.

uint32_t PG

ADC Plus-Side Gain Register, offset: 0x2C.

Definition at line 192 of file MKL25Z4.h.

uint32_t R[2]

ADC Data Result Register, array offset: 0x10, array step: 0x4.

Definition at line 186 of file MKL25Z4.h.

uint32_t SC1[2]

ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.

Definition at line 183 of file MKL25Z4.h.

uint32_t SC2

Status and Control Register 2, offset: 0x20.

Definition at line 189 of file MKL25Z4.h.

uint32_t SC3

Status and Control Register 3, offset: 0x24.

Definition at line 190 of file MKL25Z4.h.

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