Freescale_Cachan / Mbed 2 deprecated Programme_course_30Tr

programme course avec menu amélioré

Dependencies:   MMA8451Q mbed

Fork of Programme_course_vir_am_2 by Freescale_Cachan

MKL25Z4.h@0:3ec7fc598e48, 2017-01-26 (annotated)

Committer:
Freescale_cup
Date:
Thu Jan 26 07:37:45 2017 +0000
Revision:
0:3ec7fc598e48
Programme de base

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Freescale_cup 0:3ec7fc598e48 1 /*
Freescale_cup 0:3ec7fc598e48 2 ** ###################################################################
Freescale_cup 0:3ec7fc598e48 3 ** Processors: MKL25Z128FM4
Freescale_cup 0:3ec7fc598e48 4 ** MKL25Z128FT4
Freescale_cup 0:3ec7fc598e48 5 ** MKL25Z128LH4
Freescale_cup 0:3ec7fc598e48 6 ** MKL25Z128VLK4
Freescale_cup 0:3ec7fc598e48 7 **
Freescale_cup 0:3ec7fc598e48 8 ** Compilers: ARM Compiler
Freescale_cup 0:3ec7fc598e48 9 ** Freescale C/C++ for Embedded ARM
Freescale_cup 0:3ec7fc598e48 10 ** GNU C Compiler
Freescale_cup 0:3ec7fc598e48 11 ** IAR ANSI C/C++ Compiler for ARM
Freescale_cup 0:3ec7fc598e48 12 **
Freescale_cup 0:3ec7fc598e48 13 ** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
Freescale_cup 0:3ec7fc598e48 14 ** Version: rev. 1.6, 2013-04-05
Freescale_cup 0:3ec7fc598e48 15 **
Freescale_cup 0:3ec7fc598e48 16 ** Abstract:
Freescale_cup 0:3ec7fc598e48 17 ** This header file implements peripheral memory map for MKL25Z4
Freescale_cup 0:3ec7fc598e48 18 ** processor.
Freescale_cup 0:3ec7fc598e48 19 **
Freescale_cup 0:3ec7fc598e48 20 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
Freescale_cup 0:3ec7fc598e48 21 **
Freescale_cup 0:3ec7fc598e48 22 ** http: www.freescale.com
Freescale_cup 0:3ec7fc598e48 23 ** mail: support@freescale.com
Freescale_cup 0:3ec7fc598e48 24 **
Freescale_cup 0:3ec7fc598e48 25 ** Revisions:
Freescale_cup 0:3ec7fc598e48 26 ** - rev. 1.0 (2012-05-17)
Freescale_cup 0:3ec7fc598e48 27 ** Initial version.
Freescale_cup 0:3ec7fc598e48 28 ** - rev. 1.1 (2012-06-08)
Freescale_cup 0:3ec7fc598e48 29 ** Update according to reference manual rev. 0, draft B.
Freescale_cup 0:3ec7fc598e48 30 ** - rev. 1.2 (2012-06-21)
Freescale_cup 0:3ec7fc598e48 31 ** Update according to reference manual rev. 1.
Freescale_cup 0:3ec7fc598e48 32 ** - rev. 1.3 (2012-08-01)
Freescale_cup 0:3ec7fc598e48 33 ** Device type UARTLP changed to UART0.
Freescale_cup 0:3ec7fc598e48 34 ** - rev. 1.4 (2012-10-04)
Freescale_cup 0:3ec7fc598e48 35 ** Update according to reference manual rev. 3.
Freescale_cup 0:3ec7fc598e48 36 ** - rev. 1.5 (2012-11-22)
Freescale_cup 0:3ec7fc598e48 37 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
Freescale_cup 0:3ec7fc598e48 38 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
Freescale_cup 0:3ec7fc598e48 39 ** - rev. 1.6 (2013-04-05)
Freescale_cup 0:3ec7fc598e48 40 ** Changed start of doxygen comment.
Freescale_cup 0:3ec7fc598e48 41 **
Freescale_cup 0:3ec7fc598e48 42 ** ###################################################################
Freescale_cup 0:3ec7fc598e48 43 */
Freescale_cup 0:3ec7fc598e48 44
Freescale_cup 0:3ec7fc598e48 45 /*!
Freescale_cup 0:3ec7fc598e48 46 * @file MKL25Z4.h
Freescale_cup 0:3ec7fc598e48 47 * @version 1.6
Freescale_cup 0:3ec7fc598e48 48 * @date 2013-04-05
Freescale_cup 0:3ec7fc598e48 49 * @brief Peripheral memory map for MKL25Z4
Freescale_cup 0:3ec7fc598e48 50 *
Freescale_cup 0:3ec7fc598e48 51 * This header file implements peripheral memory map for MKL25Z4 processor.
Freescale_cup 0:3ec7fc598e48 52 */
Freescale_cup 0:3ec7fc598e48 53
Freescale_cup 0:3ec7fc598e48 54
Freescale_cup 0:3ec7fc598e48 55 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 56 -- MCU activation
Freescale_cup 0:3ec7fc598e48 57 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 58
Freescale_cup 0:3ec7fc598e48 59 /* Prevention from multiple including the same memory map */
Freescale_cup 0:3ec7fc598e48 60 #if !defined(MCU_MKL25Z4) /* Check if memory map has not been already included */
Freescale_cup 0:3ec7fc598e48 61 #define MCU_MKL25Z4
Freescale_cup 0:3ec7fc598e48 62
Freescale_cup 0:3ec7fc598e48 63 /* Check if another memory map has not been also included */
Freescale_cup 0:3ec7fc598e48 64 #if (defined(MCU_ACTIVE))
Freescale_cup 0:3ec7fc598e48 65 #error MKL25Z4 memory map: There is already included another memory map. Only one memory map can be included.
Freescale_cup 0:3ec7fc598e48 66 #endif /* (defined(MCU_ACTIVE)) */
Freescale_cup 0:3ec7fc598e48 67 #define MCU_ACTIVE
Freescale_cup 0:3ec7fc598e48 68
Freescale_cup 0:3ec7fc598e48 69 #include <stdint.h>
Freescale_cup 0:3ec7fc598e48 70
Freescale_cup 0:3ec7fc598e48 71 /** Memory map major version (memory maps with equal major version number are
Freescale_cup 0:3ec7fc598e48 72 * compatible) */
Freescale_cup 0:3ec7fc598e48 73 #define MCU_MEM_MAP_VERSION 0x0100u
Freescale_cup 0:3ec7fc598e48 74 /** Memory map minor version */
Freescale_cup 0:3ec7fc598e48 75 //#define MCU_MEM_MAP_VERSION_MINOR 0x0006u
Freescale_cup 0:3ec7fc598e48 76
Freescale_cup 0:3ec7fc598e48 77
Freescale_cup 0:3ec7fc598e48 78 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 79 -- Interrupt vector numbers
Freescale_cup 0:3ec7fc598e48 80 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 81
Freescale_cup 0:3ec7fc598e48 82 /*!
Freescale_cup 0:3ec7fc598e48 83 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Freescale_cup 0:3ec7fc598e48 84 * @{
Freescale_cup 0:3ec7fc598e48 85 */
Freescale_cup 0:3ec7fc598e48 86
Freescale_cup 0:3ec7fc598e48 87 /** Interrupt Number Definitions */
Freescale_cup 0:3ec7fc598e48 88 typedef enum {
Freescale_cup 0:3ec7fc598e48 89 INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */
Freescale_cup 0:3ec7fc598e48 90 INT_Initial_Program_Counter = 1, /**< Initial program counter */
Freescale_cup 0:3ec7fc598e48 91 INT_NMI = 2, /**< Non-maskable interrupt */
Freescale_cup 0:3ec7fc598e48 92 INT_Hard_Fault = 3, /**< Hard fault exception */
Freescale_cup 0:3ec7fc598e48 93 INT_Reserved4 = 4, /**< Reserved interrupt 4 */
Freescale_cup 0:3ec7fc598e48 94 INT_Reserved5 = 5, /**< Reserved interrupt 5 */
Freescale_cup 0:3ec7fc598e48 95 INT_Reserved6 = 6, /**< Reserved interrupt 6 */
Freescale_cup 0:3ec7fc598e48 96 INT_Reserved7 = 7, /**< Reserved interrupt 7 */
Freescale_cup 0:3ec7fc598e48 97 INT_Reserved8 = 8, /**< Reserved interrupt 8 */
Freescale_cup 0:3ec7fc598e48 98 INT_Reserved9 = 9, /**< Reserved interrupt 9 */
Freescale_cup 0:3ec7fc598e48 99 INT_Reserved10 = 10, /**< Reserved interrupt 10 */
Freescale_cup 0:3ec7fc598e48 100 INT_SVCall = 11, /**< A supervisor call exception */
Freescale_cup 0:3ec7fc598e48 101 INT_Reserved12 = 12, /**< Reserved interrupt 12 */
Freescale_cup 0:3ec7fc598e48 102 INT_Reserved13 = 13, /**< Reserved interrupt 13 */
Freescale_cup 0:3ec7fc598e48 103 INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */
Freescale_cup 0:3ec7fc598e48 104 INT_SysTick = 15, /**< SysTick interrupt */
Freescale_cup 0:3ec7fc598e48 105 INT_DMA0 = 16, /**< DMA channel 0 transfer complete/error interrupt */
Freescale_cup 0:3ec7fc598e48 106 INT_DMA1 = 17, /**< DMA channel 1 transfer complete/error interrupt */
Freescale_cup 0:3ec7fc598e48 107 INT_DMA2 = 18, /**< DMA channel 2 transfer complete/error interrupt */
Freescale_cup 0:3ec7fc598e48 108 INT_DMA3 = 19, /**< DMA channel 3 transfer complete/error interrupt */
Freescale_cup 0:3ec7fc598e48 109 INT_Reserved20 = 20, /**< Reserved interrupt 20 */
Freescale_cup 0:3ec7fc598e48 110 INT_FTFA = 21, /**< FTFA command complete/read collision interrupt */
Freescale_cup 0:3ec7fc598e48 111 INT_LVD_LVW = 22, /**< Low Voltage Detect, Low Voltage Warning */
Freescale_cup 0:3ec7fc598e48 112 INT_LLW = 23, /**< Low Leakage Wakeup */
Freescale_cup 0:3ec7fc598e48 113 INT_I2C0 = 24, /**< I2C0 interrupt */
Freescale_cup 0:3ec7fc598e48 114 INT_I2C1 = 25, /**< I2C0 interrupt 25 */
Freescale_cup 0:3ec7fc598e48 115 INT_SPI0 = 26, /**< SPI0 interrupt */
Freescale_cup 0:3ec7fc598e48 116 INT_SPI1 = 27, /**< SPI1 interrupt */
Freescale_cup 0:3ec7fc598e48 117 INT_UART0 = 28, /**< UART0 status/error interrupt */
Freescale_cup 0:3ec7fc598e48 118 INT_UART1 = 29, /**< UART1 status/error interrupt */
Freescale_cup 0:3ec7fc598e48 119 INT_UART2 = 30, /**< UART2 status/error interrupt */
Freescale_cup 0:3ec7fc598e48 120 INT_ADC0 = 31, /**< ADC0 interrupt */
Freescale_cup 0:3ec7fc598e48 121 INT_CMP0 = 32, /**< CMP0 interrupt */
Freescale_cup 0:3ec7fc598e48 122 INT_TPM0 = 33, /**< TPM0 fault, overflow and channels interrupt */
Freescale_cup 0:3ec7fc598e48 123 INT_TPM1 = 34, /**< TPM1 fault, overflow and channels interrupt */
Freescale_cup 0:3ec7fc598e48 124 INT_TPM2 = 35, /**< TPM2 fault, overflow and channels interrupt */
Freescale_cup 0:3ec7fc598e48 125 INT_RTC = 36, /**< RTC interrupt */
Freescale_cup 0:3ec7fc598e48 126 INT_RTC_Seconds = 37, /**< RTC seconds interrupt */
Freescale_cup 0:3ec7fc598e48 127 INT_PIT = 38, /**< PIT timer interrupt */
Freescale_cup 0:3ec7fc598e48 128 INT_Reserved39 = 39, /**< Reserved interrupt 39 */
Freescale_cup 0:3ec7fc598e48 129 INT_USB0 = 40, /**< USB0 interrupt */
Freescale_cup 0:3ec7fc598e48 130 INT_DAC0 = 41, /**< DAC0 interrupt */
Freescale_cup 0:3ec7fc598e48 131 INT_TSI0 = 42, /**< TSI0 interrupt */
Freescale_cup 0:3ec7fc598e48 132 INT_MCG = 43, /**< MCG interrupt */
Freescale_cup 0:3ec7fc598e48 133 INT_LPTimer = 44, /**< LPTimer interrupt */
Freescale_cup 0:3ec7fc598e48 134 INT_Reserved45 = 45, /**< Reserved interrupt 45 */
Freescale_cup 0:3ec7fc598e48 135 INT_PORTA = 46, /**< Port A interrupt */
Freescale_cup 0:3ec7fc598e48 136 INT_PORTD = 47 /**< Port D interrupt */
Freescale_cup 0:3ec7fc598e48 137 } IRQInterruptIndex;
Freescale_cup 0:3ec7fc598e48 138
Freescale_cup 0:3ec7fc598e48 139 /*!
Freescale_cup 0:3ec7fc598e48 140 * @}
Freescale_cup 0:3ec7fc598e48 141 */ /* end of group Interrupt_vector_numbers */
Freescale_cup 0:3ec7fc598e48 142
Freescale_cup 0:3ec7fc598e48 143
Freescale_cup 0:3ec7fc598e48 144 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 145 -- Peripheral type defines
Freescale_cup 0:3ec7fc598e48 146 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 147
Freescale_cup 0:3ec7fc598e48 148 /*!
Freescale_cup 0:3ec7fc598e48 149 * @addtogroup Peripheral_defines Peripheral type defines
Freescale_cup 0:3ec7fc598e48 150 * @{
Freescale_cup 0:3ec7fc598e48 151 */
Freescale_cup 0:3ec7fc598e48 152
Freescale_cup 0:3ec7fc598e48 153
Freescale_cup 0:3ec7fc598e48 154 /*
Freescale_cup 0:3ec7fc598e48 155 ** Start of section using anonymous unions
Freescale_cup 0:3ec7fc598e48 156 */
Freescale_cup 0:3ec7fc598e48 157
Freescale_cup 0:3ec7fc598e48 158 #if defined(__ARMCC_VERSION)
Freescale_cup 0:3ec7fc598e48 159 #pragma push
Freescale_cup 0:3ec7fc598e48 160 #pragma anon_unions
Freescale_cup 0:3ec7fc598e48 161 #elif defined(__CWCC__)
Freescale_cup 0:3ec7fc598e48 162 #pragma push
Freescale_cup 0:3ec7fc598e48 163 #pragma cpp_extensions on
Freescale_cup 0:3ec7fc598e48 164 #elif defined(__GNUC__)
Freescale_cup 0:3ec7fc598e48 165 /* anonymous unions are enabled by default */
Freescale_cup 0:3ec7fc598e48 166 #elif defined(__IAR_SYSTEMS_ICC__)
Freescale_cup 0:3ec7fc598e48 167 #pragma language=extended
Freescale_cup 0:3ec7fc598e48 168 #else
Freescale_cup 0:3ec7fc598e48 169 #error Not supported compiler type
Freescale_cup 0:3ec7fc598e48 170 #endif
Freescale_cup 0:3ec7fc598e48 171
Freescale_cup 0:3ec7fc598e48 172 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 173 -- ADC
Freescale_cup 0:3ec7fc598e48 174 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 175
Freescale_cup 0:3ec7fc598e48 176 /*!
Freescale_cup 0:3ec7fc598e48 177 * @addtogroup ADC_Peripheral ADC
Freescale_cup 0:3ec7fc598e48 178 * @{
Freescale_cup 0:3ec7fc598e48 179 */
Freescale_cup 0:3ec7fc598e48 180
Freescale_cup 0:3ec7fc598e48 181 /** ADC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 182 typedef struct ADC_MemMap {
Freescale_cup 0:3ec7fc598e48 183 uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 184 uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 185 uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 186 uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 187 uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
Freescale_cup 0:3ec7fc598e48 188 uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
Freescale_cup 0:3ec7fc598e48 189 uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
Freescale_cup 0:3ec7fc598e48 190 uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
Freescale_cup 0:3ec7fc598e48 191 uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
Freescale_cup 0:3ec7fc598e48 192 uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
Freescale_cup 0:3ec7fc598e48 193 uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
Freescale_cup 0:3ec7fc598e48 194 uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
Freescale_cup 0:3ec7fc598e48 195 uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
Freescale_cup 0:3ec7fc598e48 196 uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
Freescale_cup 0:3ec7fc598e48 197 uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
Freescale_cup 0:3ec7fc598e48 198 uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
Freescale_cup 0:3ec7fc598e48 199 uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
Freescale_cup 0:3ec7fc598e48 200 uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
Freescale_cup 0:3ec7fc598e48 201 uint8_t RESERVED_0[4];
Freescale_cup 0:3ec7fc598e48 202 uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
Freescale_cup 0:3ec7fc598e48 203 uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
Freescale_cup 0:3ec7fc598e48 204 uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
Freescale_cup 0:3ec7fc598e48 205 uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
Freescale_cup 0:3ec7fc598e48 206 uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
Freescale_cup 0:3ec7fc598e48 207 uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
Freescale_cup 0:3ec7fc598e48 208 uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
Freescale_cup 0:3ec7fc598e48 209 } volatile *ADC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 210
Freescale_cup 0:3ec7fc598e48 211 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 212 -- ADC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 213 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 214
Freescale_cup 0:3ec7fc598e48 215 /*!
Freescale_cup 0:3ec7fc598e48 216 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 217 * @{
Freescale_cup 0:3ec7fc598e48 218 */
Freescale_cup 0:3ec7fc598e48 219
Freescale_cup 0:3ec7fc598e48 220
Freescale_cup 0:3ec7fc598e48 221 /* ADC - Register accessors */
Freescale_cup 0:3ec7fc598e48 222 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
Freescale_cup 0:3ec7fc598e48 223 #define ADC_CFG1_REG(base) ((base)->CFG1)
Freescale_cup 0:3ec7fc598e48 224 #define ADC_CFG2_REG(base) ((base)->CFG2)
Freescale_cup 0:3ec7fc598e48 225 #define ADC_R_REG(base,index) ((base)->R[index])
Freescale_cup 0:3ec7fc598e48 226 #define ADC_CV1_REG(base) ((base)->CV1)
Freescale_cup 0:3ec7fc598e48 227 #define ADC_CV2_REG(base) ((base)->CV2)
Freescale_cup 0:3ec7fc598e48 228 #define ADC_SC2_REG(base) ((base)->SC2)
Freescale_cup 0:3ec7fc598e48 229 #define ADC_SC3_REG(base) ((base)->SC3)
Freescale_cup 0:3ec7fc598e48 230 #define ADC_OFS_REG(base) ((base)->OFS)
Freescale_cup 0:3ec7fc598e48 231 #define ADC_PG_REG(base) ((base)->PG)
Freescale_cup 0:3ec7fc598e48 232 #define ADC_MG_REG(base) ((base)->MG)
Freescale_cup 0:3ec7fc598e48 233 #define ADC_CLPD_REG(base) ((base)->CLPD)
Freescale_cup 0:3ec7fc598e48 234 #define ADC_CLPS_REG(base) ((base)->CLPS)
Freescale_cup 0:3ec7fc598e48 235 #define ADC_CLP4_REG(base) ((base)->CLP4)
Freescale_cup 0:3ec7fc598e48 236 #define ADC_CLP3_REG(base) ((base)->CLP3)
Freescale_cup 0:3ec7fc598e48 237 #define ADC_CLP2_REG(base) ((base)->CLP2)
Freescale_cup 0:3ec7fc598e48 238 #define ADC_CLP1_REG(base) ((base)->CLP1)
Freescale_cup 0:3ec7fc598e48 239 #define ADC_CLP0_REG(base) ((base)->CLP0)
Freescale_cup 0:3ec7fc598e48 240 #define ADC_CLMD_REG(base) ((base)->CLMD)
Freescale_cup 0:3ec7fc598e48 241 #define ADC_CLMS_REG(base) ((base)->CLMS)
Freescale_cup 0:3ec7fc598e48 242 #define ADC_CLM4_REG(base) ((base)->CLM4)
Freescale_cup 0:3ec7fc598e48 243 #define ADC_CLM3_REG(base) ((base)->CLM3)
Freescale_cup 0:3ec7fc598e48 244 #define ADC_CLM2_REG(base) ((base)->CLM2)
Freescale_cup 0:3ec7fc598e48 245 #define ADC_CLM1_REG(base) ((base)->CLM1)
Freescale_cup 0:3ec7fc598e48 246 #define ADC_CLM0_REG(base) ((base)->CLM0)
Freescale_cup 0:3ec7fc598e48 247
Freescale_cup 0:3ec7fc598e48 248 /*!
Freescale_cup 0:3ec7fc598e48 249 * @}
Freescale_cup 0:3ec7fc598e48 250 */ /* end of group ADC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 251
Freescale_cup 0:3ec7fc598e48 252
Freescale_cup 0:3ec7fc598e48 253 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 254 -- ADC Register Masks
Freescale_cup 0:3ec7fc598e48 255 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 256
Freescale_cup 0:3ec7fc598e48 257 /*!
Freescale_cup 0:3ec7fc598e48 258 * @addtogroup ADC_Register_Masks ADC Register Masks
Freescale_cup 0:3ec7fc598e48 259 * @{
Freescale_cup 0:3ec7fc598e48 260 */
Freescale_cup 0:3ec7fc598e48 261
Freescale_cup 0:3ec7fc598e48 262 /* SC1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 263 #define ADC_SC1_ADCH_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 264 #define ADC_SC1_ADCH_SHIFT 0
Freescale_cup 0:3ec7fc598e48 265 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
Freescale_cup 0:3ec7fc598e48 266 #define ADC_SC1_DIFF_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 267 #define ADC_SC1_DIFF_SHIFT 5
Freescale_cup 0:3ec7fc598e48 268 #define ADC_SC1_AIEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 269 #define ADC_SC1_AIEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 270 #define ADC_SC1_COCO_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 271 #define ADC_SC1_COCO_SHIFT 7
Freescale_cup 0:3ec7fc598e48 272 /* CFG1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 273 #define ADC_CFG1_ADICLK_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 274 #define ADC_CFG1_ADICLK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 275 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
Freescale_cup 0:3ec7fc598e48 276 #define ADC_CFG1_MODE_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 277 #define ADC_CFG1_MODE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 278 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
Freescale_cup 0:3ec7fc598e48 279 #define ADC_CFG1_ADLSMP_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 280 #define ADC_CFG1_ADLSMP_SHIFT 4
Freescale_cup 0:3ec7fc598e48 281 #define ADC_CFG1_ADIV_MASK 0x60u
Freescale_cup 0:3ec7fc598e48 282 #define ADC_CFG1_ADIV_SHIFT 5
Freescale_cup 0:3ec7fc598e48 283 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
Freescale_cup 0:3ec7fc598e48 284 #define ADC_CFG1_ADLPC_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 285 #define ADC_CFG1_ADLPC_SHIFT 7
Freescale_cup 0:3ec7fc598e48 286 /* CFG2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 287 #define ADC_CFG2_ADLSTS_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 288 #define ADC_CFG2_ADLSTS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 289 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
Freescale_cup 0:3ec7fc598e48 290 #define ADC_CFG2_ADHSC_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 291 #define ADC_CFG2_ADHSC_SHIFT 2
Freescale_cup 0:3ec7fc598e48 292 #define ADC_CFG2_ADACKEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 293 #define ADC_CFG2_ADACKEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 294 #define ADC_CFG2_MUXSEL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 295 #define ADC_CFG2_MUXSEL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 296 /* R Bit Fields */
Freescale_cup 0:3ec7fc598e48 297 #define ADC_R_D_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 298 #define ADC_R_D_SHIFT 0
Freescale_cup 0:3ec7fc598e48 299 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
Freescale_cup 0:3ec7fc598e48 300 /* CV1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 301 #define ADC_CV1_CV_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 302 #define ADC_CV1_CV_SHIFT 0
Freescale_cup 0:3ec7fc598e48 303 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
Freescale_cup 0:3ec7fc598e48 304 /* CV2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 305 #define ADC_CV2_CV_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 306 #define ADC_CV2_CV_SHIFT 0
Freescale_cup 0:3ec7fc598e48 307 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
Freescale_cup 0:3ec7fc598e48 308 /* SC2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 309 #define ADC_SC2_REFSEL_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 310 #define ADC_SC2_REFSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 311 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
Freescale_cup 0:3ec7fc598e48 312 #define ADC_SC2_DMAEN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 313 #define ADC_SC2_DMAEN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 314 #define ADC_SC2_ACREN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 315 #define ADC_SC2_ACREN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 316 #define ADC_SC2_ACFGT_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 317 #define ADC_SC2_ACFGT_SHIFT 4
Freescale_cup 0:3ec7fc598e48 318 #define ADC_SC2_ACFE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 319 #define ADC_SC2_ACFE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 320 #define ADC_SC2_ADTRG_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 321 #define ADC_SC2_ADTRG_SHIFT 6
Freescale_cup 0:3ec7fc598e48 322 #define ADC_SC2_ADACT_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 323 #define ADC_SC2_ADACT_SHIFT 7
Freescale_cup 0:3ec7fc598e48 324 /* SC3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 325 #define ADC_SC3_AVGS_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 326 #define ADC_SC3_AVGS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 327 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
Freescale_cup 0:3ec7fc598e48 328 #define ADC_SC3_AVGE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 329 #define ADC_SC3_AVGE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 330 #define ADC_SC3_ADCO_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 331 #define ADC_SC3_ADCO_SHIFT 3
Freescale_cup 0:3ec7fc598e48 332 #define ADC_SC3_CALF_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 333 #define ADC_SC3_CALF_SHIFT 6
Freescale_cup 0:3ec7fc598e48 334 #define ADC_SC3_CAL_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 335 #define ADC_SC3_CAL_SHIFT 7
Freescale_cup 0:3ec7fc598e48 336 /* OFS Bit Fields */
Freescale_cup 0:3ec7fc598e48 337 #define ADC_OFS_OFS_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 338 #define ADC_OFS_OFS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 339 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
Freescale_cup 0:3ec7fc598e48 340 /* PG Bit Fields */
Freescale_cup 0:3ec7fc598e48 341 #define ADC_PG_PG_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 342 #define ADC_PG_PG_SHIFT 0
Freescale_cup 0:3ec7fc598e48 343 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
Freescale_cup 0:3ec7fc598e48 344 /* MG Bit Fields */
Freescale_cup 0:3ec7fc598e48 345 #define ADC_MG_MG_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 346 #define ADC_MG_MG_SHIFT 0
Freescale_cup 0:3ec7fc598e48 347 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
Freescale_cup 0:3ec7fc598e48 348 /* CLPD Bit Fields */
Freescale_cup 0:3ec7fc598e48 349 #define ADC_CLPD_CLPD_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 350 #define ADC_CLPD_CLPD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 351 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
Freescale_cup 0:3ec7fc598e48 352 /* CLPS Bit Fields */
Freescale_cup 0:3ec7fc598e48 353 #define ADC_CLPS_CLPS_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 354 #define ADC_CLPS_CLPS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 355 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
Freescale_cup 0:3ec7fc598e48 356 /* CLP4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 357 #define ADC_CLP4_CLP4_MASK 0x3FFu
Freescale_cup 0:3ec7fc598e48 358 #define ADC_CLP4_CLP4_SHIFT 0
Freescale_cup 0:3ec7fc598e48 359 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
Freescale_cup 0:3ec7fc598e48 360 /* CLP3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 361 #define ADC_CLP3_CLP3_MASK 0x1FFu
Freescale_cup 0:3ec7fc598e48 362 #define ADC_CLP3_CLP3_SHIFT 0
Freescale_cup 0:3ec7fc598e48 363 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
Freescale_cup 0:3ec7fc598e48 364 /* CLP2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 365 #define ADC_CLP2_CLP2_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 366 #define ADC_CLP2_CLP2_SHIFT 0
Freescale_cup 0:3ec7fc598e48 367 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
Freescale_cup 0:3ec7fc598e48 368 /* CLP1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 369 #define ADC_CLP1_CLP1_MASK 0x7Fu
Freescale_cup 0:3ec7fc598e48 370 #define ADC_CLP1_CLP1_SHIFT 0
Freescale_cup 0:3ec7fc598e48 371 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
Freescale_cup 0:3ec7fc598e48 372 /* CLP0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 373 #define ADC_CLP0_CLP0_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 374 #define ADC_CLP0_CLP0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 375 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
Freescale_cup 0:3ec7fc598e48 376 /* CLMD Bit Fields */
Freescale_cup 0:3ec7fc598e48 377 #define ADC_CLMD_CLMD_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 378 #define ADC_CLMD_CLMD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 379 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
Freescale_cup 0:3ec7fc598e48 380 /* CLMS Bit Fields */
Freescale_cup 0:3ec7fc598e48 381 #define ADC_CLMS_CLMS_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 382 #define ADC_CLMS_CLMS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 383 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
Freescale_cup 0:3ec7fc598e48 384 /* CLM4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 385 #define ADC_CLM4_CLM4_MASK 0x3FFu
Freescale_cup 0:3ec7fc598e48 386 #define ADC_CLM4_CLM4_SHIFT 0
Freescale_cup 0:3ec7fc598e48 387 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
Freescale_cup 0:3ec7fc598e48 388 /* CLM3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 389 #define ADC_CLM3_CLM3_MASK 0x1FFu
Freescale_cup 0:3ec7fc598e48 390 #define ADC_CLM3_CLM3_SHIFT 0
Freescale_cup 0:3ec7fc598e48 391 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
Freescale_cup 0:3ec7fc598e48 392 /* CLM2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 393 #define ADC_CLM2_CLM2_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 394 #define ADC_CLM2_CLM2_SHIFT 0
Freescale_cup 0:3ec7fc598e48 395 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
Freescale_cup 0:3ec7fc598e48 396 /* CLM1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 397 #define ADC_CLM1_CLM1_MASK 0x7Fu
Freescale_cup 0:3ec7fc598e48 398 #define ADC_CLM1_CLM1_SHIFT 0
Freescale_cup 0:3ec7fc598e48 399 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
Freescale_cup 0:3ec7fc598e48 400 /* CLM0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 401 #define ADC_CLM0_CLM0_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 402 #define ADC_CLM0_CLM0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 403 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
Freescale_cup 0:3ec7fc598e48 404
Freescale_cup 0:3ec7fc598e48 405 /*!
Freescale_cup 0:3ec7fc598e48 406 * @}
Freescale_cup 0:3ec7fc598e48 407 */ /* end of group ADC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 408
Freescale_cup 0:3ec7fc598e48 409
Freescale_cup 0:3ec7fc598e48 410 /* ADC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 411 /** Peripheral ADC0 base pointer */
Freescale_cup 0:3ec7fc598e48 412 #define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
Freescale_cup 0:3ec7fc598e48 413 /** Array initializer of ADC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 414 #define ADC_BASE_PTRS { ADC0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 415
Freescale_cup 0:3ec7fc598e48 416 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 417 -- ADC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 418 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 419
Freescale_cup 0:3ec7fc598e48 420 /*!
Freescale_cup 0:3ec7fc598e48 421 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 422 * @{
Freescale_cup 0:3ec7fc598e48 423 */
Freescale_cup 0:3ec7fc598e48 424
Freescale_cup 0:3ec7fc598e48 425
Freescale_cup 0:3ec7fc598e48 426 /* ADC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 427 /* ADC0 */
Freescale_cup 0:3ec7fc598e48 428 #define ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 429 #define ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 430 #define ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 431 #define ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 432 #define ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 433 #define ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 434 #define ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 435 #define ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 436 #define ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 437 #define ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 438 #define ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 439 #define ADC0_PG ADC_PG_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 440 #define ADC0_MG ADC_MG_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 441 #define ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 442 #define ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 443 #define ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 444 #define ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 445 #define ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 446 #define ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 447 #define ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 448 #define ADC0_CLMD ADC_CLMD_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 449 #define ADC0_CLMS ADC_CLMS_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 450 #define ADC0_CLM4 ADC_CLM4_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 451 #define ADC0_CLM3 ADC_CLM3_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 452 #define ADC0_CLM2 ADC_CLM2_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 453 #define ADC0_CLM1 ADC_CLM1_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 454 #define ADC0_CLM0 ADC_CLM0_REG(ADC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 455
Freescale_cup 0:3ec7fc598e48 456 /* ADC - Register array accessors */
Freescale_cup 0:3ec7fc598e48 457 #define ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 458 #define ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 459
Freescale_cup 0:3ec7fc598e48 460 /*!
Freescale_cup 0:3ec7fc598e48 461 * @}
Freescale_cup 0:3ec7fc598e48 462 */ /* end of group ADC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 463
Freescale_cup 0:3ec7fc598e48 464
Freescale_cup 0:3ec7fc598e48 465 /*!
Freescale_cup 0:3ec7fc598e48 466 * @}
Freescale_cup 0:3ec7fc598e48 467 */ /* end of group ADC_Peripheral */
Freescale_cup 0:3ec7fc598e48 468
Freescale_cup 0:3ec7fc598e48 469
Freescale_cup 0:3ec7fc598e48 470 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 471 -- BP
Freescale_cup 0:3ec7fc598e48 472 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 473
Freescale_cup 0:3ec7fc598e48 474 /*!
Freescale_cup 0:3ec7fc598e48 475 * @addtogroup BP_Peripheral BP
Freescale_cup 0:3ec7fc598e48 476 * @{
Freescale_cup 0:3ec7fc598e48 477 */
Freescale_cup 0:3ec7fc598e48 478
Freescale_cup 0:3ec7fc598e48 479 /** BP - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 480 typedef struct BP_MemMap {
Freescale_cup 0:3ec7fc598e48 481 uint32_t CTRL; /**< FlashPatch Control Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 482 uint8_t RESERVED_0[4];
Freescale_cup 0:3ec7fc598e48 483 uint32_t COMP[2]; /**< FlashPatch Comparator Register 0..FlashPatch Comparator Register 1, array offset: 0x8, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 484 uint8_t RESERVED_1[4032];
Freescale_cup 0:3ec7fc598e48 485 uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */
Freescale_cup 0:3ec7fc598e48 486 uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */
Freescale_cup 0:3ec7fc598e48 487 uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */
Freescale_cup 0:3ec7fc598e48 488 uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */
Freescale_cup 0:3ec7fc598e48 489 uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */
Freescale_cup 0:3ec7fc598e48 490 uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */
Freescale_cup 0:3ec7fc598e48 491 uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */
Freescale_cup 0:3ec7fc598e48 492 uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */
Freescale_cup 0:3ec7fc598e48 493 uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */
Freescale_cup 0:3ec7fc598e48 494 uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */
Freescale_cup 0:3ec7fc598e48 495 uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */
Freescale_cup 0:3ec7fc598e48 496 uint32_t CID3; /**< Component Identification Register 3., offset: 0xFFC */
Freescale_cup 0:3ec7fc598e48 497 } volatile *BP_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 498
Freescale_cup 0:3ec7fc598e48 499 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 500 -- BP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 501 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 502
Freescale_cup 0:3ec7fc598e48 503 /*!
Freescale_cup 0:3ec7fc598e48 504 * @addtogroup BP_Register_Accessor_Macros BP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 505 * @{
Freescale_cup 0:3ec7fc598e48 506 */
Freescale_cup 0:3ec7fc598e48 507
Freescale_cup 0:3ec7fc598e48 508
Freescale_cup 0:3ec7fc598e48 509 /* BP - Register accessors */
Freescale_cup 0:3ec7fc598e48 510 #define BP_CTRL_REG(base) ((base)->CTRL)
Freescale_cup 0:3ec7fc598e48 511 #define BP_COMP_REG(base,index) ((base)->COMP[index])
Freescale_cup 0:3ec7fc598e48 512 #define BP_PID4_REG(base) ((base)->PID4)
Freescale_cup 0:3ec7fc598e48 513 #define BP_PID5_REG(base) ((base)->PID5)
Freescale_cup 0:3ec7fc598e48 514 #define BP_PID6_REG(base) ((base)->PID6)
Freescale_cup 0:3ec7fc598e48 515 #define BP_PID7_REG(base) ((base)->PID7)
Freescale_cup 0:3ec7fc598e48 516 #define BP_PID0_REG(base) ((base)->PID0)
Freescale_cup 0:3ec7fc598e48 517 #define BP_PID1_REG(base) ((base)->PID1)
Freescale_cup 0:3ec7fc598e48 518 #define BP_PID2_REG(base) ((base)->PID2)
Freescale_cup 0:3ec7fc598e48 519 #define BP_PID3_REG(base) ((base)->PID3)
Freescale_cup 0:3ec7fc598e48 520 #define BP_CID0_REG(base) ((base)->CID0)
Freescale_cup 0:3ec7fc598e48 521 #define BP_CID1_REG(base) ((base)->CID1)
Freescale_cup 0:3ec7fc598e48 522 #define BP_CID2_REG(base) ((base)->CID2)
Freescale_cup 0:3ec7fc598e48 523 #define BP_CID3_REG(base) ((base)->CID3)
Freescale_cup 0:3ec7fc598e48 524
Freescale_cup 0:3ec7fc598e48 525 /*!
Freescale_cup 0:3ec7fc598e48 526 * @}
Freescale_cup 0:3ec7fc598e48 527 */ /* end of group BP_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 528
Freescale_cup 0:3ec7fc598e48 529
Freescale_cup 0:3ec7fc598e48 530 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 531 -- BP Register Masks
Freescale_cup 0:3ec7fc598e48 532 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 533
Freescale_cup 0:3ec7fc598e48 534 /*!
Freescale_cup 0:3ec7fc598e48 535 * @addtogroup BP_Register_Masks BP Register Masks
Freescale_cup 0:3ec7fc598e48 536 * @{
Freescale_cup 0:3ec7fc598e48 537 */
Freescale_cup 0:3ec7fc598e48 538
Freescale_cup 0:3ec7fc598e48 539
Freescale_cup 0:3ec7fc598e48 540 /*!
Freescale_cup 0:3ec7fc598e48 541 * @}
Freescale_cup 0:3ec7fc598e48 542 */ /* end of group BP_Register_Masks */
Freescale_cup 0:3ec7fc598e48 543
Freescale_cup 0:3ec7fc598e48 544
Freescale_cup 0:3ec7fc598e48 545 /* BP - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 546 /** Peripheral BP base pointer */
Freescale_cup 0:3ec7fc598e48 547 #define BP_BASE_PTR ((BP_MemMapPtr)0xE0002000u)
Freescale_cup 0:3ec7fc598e48 548 /** Array initializer of BP peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 549 #define BP_BASE_PTRS { BP_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 550
Freescale_cup 0:3ec7fc598e48 551 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 552 -- BP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 553 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 554
Freescale_cup 0:3ec7fc598e48 555 /*!
Freescale_cup 0:3ec7fc598e48 556 * @addtogroup BP_Register_Accessor_Macros BP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 557 * @{
Freescale_cup 0:3ec7fc598e48 558 */
Freescale_cup 0:3ec7fc598e48 559
Freescale_cup 0:3ec7fc598e48 560
Freescale_cup 0:3ec7fc598e48 561 /* BP - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 562 /* BP */
Freescale_cup 0:3ec7fc598e48 563 #define BP_CTRL BP_CTRL_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 564 #define BP_COMP0 BP_COMP_REG(BP_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 565 #define BP_COMP1 BP_COMP_REG(BP_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 566 #define BP_PID4 BP_PID4_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 567 #define BP_PID5 BP_PID5_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 568 #define BP_PID6 BP_PID6_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 569 #define BP_PID7 BP_PID7_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 570 #define BP_PID0 BP_PID0_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 571 #define BP_PID1 BP_PID1_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 572 #define BP_PID2 BP_PID2_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 573 #define BP_PID3 BP_PID3_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 574 #define BP_CID0 BP_CID0_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 575 #define BP_CID1 BP_CID1_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 576 #define BP_CID2 BP_CID2_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 577 #define BP_CID3 BP_CID3_REG(BP_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 578
Freescale_cup 0:3ec7fc598e48 579 /* BP - Register array accessors */
Freescale_cup 0:3ec7fc598e48 580 #define BP_COMP(index) BP_COMP_REG(BP_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 581
Freescale_cup 0:3ec7fc598e48 582 /*!
Freescale_cup 0:3ec7fc598e48 583 * @}
Freescale_cup 0:3ec7fc598e48 584 */ /* end of group BP_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 585
Freescale_cup 0:3ec7fc598e48 586
Freescale_cup 0:3ec7fc598e48 587 /*!
Freescale_cup 0:3ec7fc598e48 588 * @}
Freescale_cup 0:3ec7fc598e48 589 */ /* end of group BP_Peripheral */
Freescale_cup 0:3ec7fc598e48 590
Freescale_cup 0:3ec7fc598e48 591
Freescale_cup 0:3ec7fc598e48 592 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 593 -- CMP
Freescale_cup 0:3ec7fc598e48 594 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 595
Freescale_cup 0:3ec7fc598e48 596 /*!
Freescale_cup 0:3ec7fc598e48 597 * @addtogroup CMP_Peripheral CMP
Freescale_cup 0:3ec7fc598e48 598 * @{
Freescale_cup 0:3ec7fc598e48 599 */
Freescale_cup 0:3ec7fc598e48 600
Freescale_cup 0:3ec7fc598e48 601 /** CMP - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 602 typedef struct CMP_MemMap {
Freescale_cup 0:3ec7fc598e48 603 uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 604 uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 605 uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 606 uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 607 uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 608 uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 609 } volatile *CMP_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 610
Freescale_cup 0:3ec7fc598e48 611 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 612 -- CMP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 613 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 614
Freescale_cup 0:3ec7fc598e48 615 /*!
Freescale_cup 0:3ec7fc598e48 616 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 617 * @{
Freescale_cup 0:3ec7fc598e48 618 */
Freescale_cup 0:3ec7fc598e48 619
Freescale_cup 0:3ec7fc598e48 620
Freescale_cup 0:3ec7fc598e48 621 /* CMP - Register accessors */
Freescale_cup 0:3ec7fc598e48 622 #define CMP_CR0_REG(base) ((base)->CR0)
Freescale_cup 0:3ec7fc598e48 623 #define CMP_CR1_REG(base) ((base)->CR1)
Freescale_cup 0:3ec7fc598e48 624 #define CMP_FPR_REG(base) ((base)->FPR)
Freescale_cup 0:3ec7fc598e48 625 #define CMP_SCR_REG(base) ((base)->SCR)
Freescale_cup 0:3ec7fc598e48 626 #define CMP_DACCR_REG(base) ((base)->DACCR)
Freescale_cup 0:3ec7fc598e48 627 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
Freescale_cup 0:3ec7fc598e48 628
Freescale_cup 0:3ec7fc598e48 629 /*!
Freescale_cup 0:3ec7fc598e48 630 * @}
Freescale_cup 0:3ec7fc598e48 631 */ /* end of group CMP_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 632
Freescale_cup 0:3ec7fc598e48 633
Freescale_cup 0:3ec7fc598e48 634 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 635 -- CMP Register Masks
Freescale_cup 0:3ec7fc598e48 636 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 637
Freescale_cup 0:3ec7fc598e48 638 /*!
Freescale_cup 0:3ec7fc598e48 639 * @addtogroup CMP_Register_Masks CMP Register Masks
Freescale_cup 0:3ec7fc598e48 640 * @{
Freescale_cup 0:3ec7fc598e48 641 */
Freescale_cup 0:3ec7fc598e48 642
Freescale_cup 0:3ec7fc598e48 643 /* CR0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 644 #define CMP_CR0_HYSTCTR_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 645 #define CMP_CR0_HYSTCTR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 646 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
Freescale_cup 0:3ec7fc598e48 647 #define CMP_CR0_FILTER_CNT_MASK 0x70u
Freescale_cup 0:3ec7fc598e48 648 #define CMP_CR0_FILTER_CNT_SHIFT 4
Freescale_cup 0:3ec7fc598e48 649 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
Freescale_cup 0:3ec7fc598e48 650 /* CR1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 651 #define CMP_CR1_EN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 652 #define CMP_CR1_EN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 653 #define CMP_CR1_OPE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 654 #define CMP_CR1_OPE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 655 #define CMP_CR1_COS_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 656 #define CMP_CR1_COS_SHIFT 2
Freescale_cup 0:3ec7fc598e48 657 #define CMP_CR1_INV_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 658 #define CMP_CR1_INV_SHIFT 3
Freescale_cup 0:3ec7fc598e48 659 #define CMP_CR1_PMODE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 660 #define CMP_CR1_PMODE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 661 #define CMP_CR1_TRIGM_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 662 #define CMP_CR1_TRIGM_SHIFT 5
Freescale_cup 0:3ec7fc598e48 663 #define CMP_CR1_WE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 664 #define CMP_CR1_WE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 665 #define CMP_CR1_SE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 666 #define CMP_CR1_SE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 667 /* FPR Bit Fields */
Freescale_cup 0:3ec7fc598e48 668 #define CMP_FPR_FILT_PER_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 669 #define CMP_FPR_FILT_PER_SHIFT 0
Freescale_cup 0:3ec7fc598e48 670 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
Freescale_cup 0:3ec7fc598e48 671 /* SCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 672 #define CMP_SCR_COUT_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 673 #define CMP_SCR_COUT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 674 #define CMP_SCR_CFF_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 675 #define CMP_SCR_CFF_SHIFT 1
Freescale_cup 0:3ec7fc598e48 676 #define CMP_SCR_CFR_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 677 #define CMP_SCR_CFR_SHIFT 2
Freescale_cup 0:3ec7fc598e48 678 #define CMP_SCR_IEF_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 679 #define CMP_SCR_IEF_SHIFT 3
Freescale_cup 0:3ec7fc598e48 680 #define CMP_SCR_IER_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 681 #define CMP_SCR_IER_SHIFT 4
Freescale_cup 0:3ec7fc598e48 682 #define CMP_SCR_DMAEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 683 #define CMP_SCR_DMAEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 684 /* DACCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 685 #define CMP_DACCR_VOSEL_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 686 #define CMP_DACCR_VOSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 687 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
Freescale_cup 0:3ec7fc598e48 688 #define CMP_DACCR_VRSEL_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 689 #define CMP_DACCR_VRSEL_SHIFT 6
Freescale_cup 0:3ec7fc598e48 690 #define CMP_DACCR_DACEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 691 #define CMP_DACCR_DACEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 692 /* MUXCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 693 #define CMP_MUXCR_MSEL_MASK 0x7u
Freescale_cup 0:3ec7fc598e48 694 #define CMP_MUXCR_MSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 695 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
Freescale_cup 0:3ec7fc598e48 696 #define CMP_MUXCR_PSEL_MASK 0x38u
Freescale_cup 0:3ec7fc598e48 697 #define CMP_MUXCR_PSEL_SHIFT 3
Freescale_cup 0:3ec7fc598e48 698 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
Freescale_cup 0:3ec7fc598e48 699 //#define CMP_MUXCR_PSTM_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 700 //#define CMP_MUXCR_PSTM_SHIFT 7
Freescale_cup 0:3ec7fc598e48 701
Freescale_cup 0:3ec7fc598e48 702 /*!
Freescale_cup 0:3ec7fc598e48 703 * @}
Freescale_cup 0:3ec7fc598e48 704 */ /* end of group CMP_Register_Masks */
Freescale_cup 0:3ec7fc598e48 705
Freescale_cup 0:3ec7fc598e48 706
Freescale_cup 0:3ec7fc598e48 707 /* CMP - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 708 /** Peripheral CMP0 base pointer */
Freescale_cup 0:3ec7fc598e48 709 #define CMP0_BASE_PTR ((CMP_MemMapPtr)0x40073000u)
Freescale_cup 0:3ec7fc598e48 710 /** Array initializer of CMP peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 711 #define CMP_BASE_PTRS { CMP0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 712
Freescale_cup 0:3ec7fc598e48 713 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 714 -- CMP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 715 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 716
Freescale_cup 0:3ec7fc598e48 717 /*!
Freescale_cup 0:3ec7fc598e48 718 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Freescale_cup 0:3ec7fc598e48 719 * @{
Freescale_cup 0:3ec7fc598e48 720 */
Freescale_cup 0:3ec7fc598e48 721
Freescale_cup 0:3ec7fc598e48 722
Freescale_cup 0:3ec7fc598e48 723 /* CMP - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 724 /* CMP0 */
Freescale_cup 0:3ec7fc598e48 725 #define CMP0_CR0 CMP_CR0_REG(CMP0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 726 #define CMP0_CR1 CMP_CR1_REG(CMP0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 727 #define CMP0_FPR CMP_FPR_REG(CMP0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 728 #define CMP0_SCR CMP_SCR_REG(CMP0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 729 #define CMP0_DACCR CMP_DACCR_REG(CMP0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 730 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 731
Freescale_cup 0:3ec7fc598e48 732 /*!
Freescale_cup 0:3ec7fc598e48 733 * @}
Freescale_cup 0:3ec7fc598e48 734 */ /* end of group CMP_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 735
Freescale_cup 0:3ec7fc598e48 736
Freescale_cup 0:3ec7fc598e48 737 /*!
Freescale_cup 0:3ec7fc598e48 738 * @}
Freescale_cup 0:3ec7fc598e48 739 */ /* end of group CMP_Peripheral */
Freescale_cup 0:3ec7fc598e48 740
Freescale_cup 0:3ec7fc598e48 741
Freescale_cup 0:3ec7fc598e48 742 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 743 -- CoreDebug
Freescale_cup 0:3ec7fc598e48 744 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 745
Freescale_cup 0:3ec7fc598e48 746 /*!
Freescale_cup 0:3ec7fc598e48 747 * @addtogroup CoreDebug_Peripheral CoreDebug
Freescale_cup 0:3ec7fc598e48 748 * @{
Freescale_cup 0:3ec7fc598e48 749 */
Freescale_cup 0:3ec7fc598e48 750
Freescale_cup 0:3ec7fc598e48 751 /** CoreDebug - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 752 typedef struct CoreDebug_MemMap {
Freescale_cup 0:3ec7fc598e48 753 union { /* offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 754 uint32_t base_DHCSR_Read; /**< Debug Halting Control and Status Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 755 uint32_t base_DHCSR_Write; /**< Debug Halting Control and Status Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 756 };
Freescale_cup 0:3ec7fc598e48 757 uint32_t base_DCRSR; /**< Debug Core Register Selector Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 758 uint32_t base_DCRDR; /**< Debug Core Register Data Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 759 uint32_t base_DEMCR; /**< Debug Exception and Monitor Control Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 760 } volatile *CoreDebug_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 761
Freescale_cup 0:3ec7fc598e48 762 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 763 -- CoreDebug - Register accessor macros
Freescale_cup 0:3ec7fc598e48 764 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 765
Freescale_cup 0:3ec7fc598e48 766 /*!
Freescale_cup 0:3ec7fc598e48 767 * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
Freescale_cup 0:3ec7fc598e48 768 * @{
Freescale_cup 0:3ec7fc598e48 769 */
Freescale_cup 0:3ec7fc598e48 770
Freescale_cup 0:3ec7fc598e48 771
Freescale_cup 0:3ec7fc598e48 772 /* CoreDebug - Register accessors */
Freescale_cup 0:3ec7fc598e48 773 #define CoreDebug_base_DHCSR_Read_REG(base) ((base)->base_DHCSR_Read)
Freescale_cup 0:3ec7fc598e48 774 #define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write)
Freescale_cup 0:3ec7fc598e48 775 #define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR)
Freescale_cup 0:3ec7fc598e48 776 #define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR)
Freescale_cup 0:3ec7fc598e48 777 #define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR)
Freescale_cup 0:3ec7fc598e48 778
Freescale_cup 0:3ec7fc598e48 779 /*!
Freescale_cup 0:3ec7fc598e48 780 * @}
Freescale_cup 0:3ec7fc598e48 781 */ /* end of group CoreDebug_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 782
Freescale_cup 0:3ec7fc598e48 783
Freescale_cup 0:3ec7fc598e48 784 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 785 -- CoreDebug Register Masks
Freescale_cup 0:3ec7fc598e48 786 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 787
Freescale_cup 0:3ec7fc598e48 788 /*!
Freescale_cup 0:3ec7fc598e48 789 * @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks
Freescale_cup 0:3ec7fc598e48 790 * @{
Freescale_cup 0:3ec7fc598e48 791 */
Freescale_cup 0:3ec7fc598e48 792
Freescale_cup 0:3ec7fc598e48 793
Freescale_cup 0:3ec7fc598e48 794 /*!
Freescale_cup 0:3ec7fc598e48 795 * @}
Freescale_cup 0:3ec7fc598e48 796 */ /* end of group CoreDebug_Register_Masks */
Freescale_cup 0:3ec7fc598e48 797
Freescale_cup 0:3ec7fc598e48 798
Freescale_cup 0:3ec7fc598e48 799 /* CoreDebug - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 800 /** Peripheral CoreDebug base pointer */
Freescale_cup 0:3ec7fc598e48 801 #define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u)
Freescale_cup 0:3ec7fc598e48 802 /** Array initializer of CoreDebug peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 803 #define CoreDebug_BASE_PTRS { CoreDebug_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 804
Freescale_cup 0:3ec7fc598e48 805 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 806 -- CoreDebug - Register accessor macros
Freescale_cup 0:3ec7fc598e48 807 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 808
Freescale_cup 0:3ec7fc598e48 809 /*!
Freescale_cup 0:3ec7fc598e48 810 * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
Freescale_cup 0:3ec7fc598e48 811 * @{
Freescale_cup 0:3ec7fc598e48 812 */
Freescale_cup 0:3ec7fc598e48 813
Freescale_cup 0:3ec7fc598e48 814
Freescale_cup 0:3ec7fc598e48 815 /* CoreDebug - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 816 /* CoreDebug */
Freescale_cup 0:3ec7fc598e48 817 #define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 818 #define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 819 #define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 820 #define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 821 #define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 822
Freescale_cup 0:3ec7fc598e48 823 /*!
Freescale_cup 0:3ec7fc598e48 824 * @}
Freescale_cup 0:3ec7fc598e48 825 */ /* end of group CoreDebug_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 826
Freescale_cup 0:3ec7fc598e48 827
Freescale_cup 0:3ec7fc598e48 828 /*!
Freescale_cup 0:3ec7fc598e48 829 * @}
Freescale_cup 0:3ec7fc598e48 830 */ /* end of group CoreDebug_Peripheral */
Freescale_cup 0:3ec7fc598e48 831
Freescale_cup 0:3ec7fc598e48 832
Freescale_cup 0:3ec7fc598e48 833 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 834 -- DAC
Freescale_cup 0:3ec7fc598e48 835 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 836
Freescale_cup 0:3ec7fc598e48 837 /*!
Freescale_cup 0:3ec7fc598e48 838 * @addtogroup DAC_Peripheral DAC
Freescale_cup 0:3ec7fc598e48 839 * @{
Freescale_cup 0:3ec7fc598e48 840 */
Freescale_cup 0:3ec7fc598e48 841
Freescale_cup 0:3ec7fc598e48 842 /** DAC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 843 typedef struct DAC_MemMap {
Freescale_cup 0:3ec7fc598e48 844 struct { /* offset: 0x0, array step: 0x2 */
Freescale_cup 0:3ec7fc598e48 845 uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
Freescale_cup 0:3ec7fc598e48 846 uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
Freescale_cup 0:3ec7fc598e48 847 } DAT[2];
Freescale_cup 0:3ec7fc598e48 848 uint8_t RESERVED_0[28];
Freescale_cup 0:3ec7fc598e48 849 uint8_t SR; /**< DAC Status Register, offset: 0x20 */
Freescale_cup 0:3ec7fc598e48 850 uint8_t C0; /**< DAC Control Register, offset: 0x21 */
Freescale_cup 0:3ec7fc598e48 851 uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
Freescale_cup 0:3ec7fc598e48 852 uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
Freescale_cup 0:3ec7fc598e48 853 } volatile *DAC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 854
Freescale_cup 0:3ec7fc598e48 855 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 856 -- DAC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 857 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 858
Freescale_cup 0:3ec7fc598e48 859 /*!
Freescale_cup 0:3ec7fc598e48 860 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 861 * @{
Freescale_cup 0:3ec7fc598e48 862 */
Freescale_cup 0:3ec7fc598e48 863
Freescale_cup 0:3ec7fc598e48 864
Freescale_cup 0:3ec7fc598e48 865 /* DAC - Register accessors */
Freescale_cup 0:3ec7fc598e48 866 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
Freescale_cup 0:3ec7fc598e48 867 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
Freescale_cup 0:3ec7fc598e48 868 #define DAC_SR_REG(base) ((base)->SR)
Freescale_cup 0:3ec7fc598e48 869 #define DAC_C0_REG(base) ((base)->C0)
Freescale_cup 0:3ec7fc598e48 870 #define DAC_C1_REG(base) ((base)->C1)
Freescale_cup 0:3ec7fc598e48 871 #define DAC_C2_REG(base) ((base)->C2)
Freescale_cup 0:3ec7fc598e48 872
Freescale_cup 0:3ec7fc598e48 873 /*!
Freescale_cup 0:3ec7fc598e48 874 * @}
Freescale_cup 0:3ec7fc598e48 875 */ /* end of group DAC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 876
Freescale_cup 0:3ec7fc598e48 877
Freescale_cup 0:3ec7fc598e48 878 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 879 -- DAC Register Masks
Freescale_cup 0:3ec7fc598e48 880 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 881
Freescale_cup 0:3ec7fc598e48 882 /*!
Freescale_cup 0:3ec7fc598e48 883 * @addtogroup DAC_Register_Masks DAC Register Masks
Freescale_cup 0:3ec7fc598e48 884 * @{
Freescale_cup 0:3ec7fc598e48 885 */
Freescale_cup 0:3ec7fc598e48 886
Freescale_cup 0:3ec7fc598e48 887 /* DATL Bit Fields */
Freescale_cup 0:3ec7fc598e48 888 #define DAC_DATL_DATA0_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 889 #define DAC_DATL_DATA0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 890 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
Freescale_cup 0:3ec7fc598e48 891 /* DATH Bit Fields */
Freescale_cup 0:3ec7fc598e48 892 #define DAC_DATH_DATA1_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 893 #define DAC_DATH_DATA1_SHIFT 0
Freescale_cup 0:3ec7fc598e48 894 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
Freescale_cup 0:3ec7fc598e48 895 /* SR Bit Fields */
Freescale_cup 0:3ec7fc598e48 896 #define DAC_SR_DACBFRPBF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 897 #define DAC_SR_DACBFRPBF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 898 #define DAC_SR_DACBFRPTF_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 899 #define DAC_SR_DACBFRPTF_SHIFT 1
Freescale_cup 0:3ec7fc598e48 900 /* C0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 901 #define DAC_C0_DACBBIEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 902 #define DAC_C0_DACBBIEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 903 #define DAC_C0_DACBTIEN_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 904 #define DAC_C0_DACBTIEN_SHIFT 1
Freescale_cup 0:3ec7fc598e48 905 #define DAC_C0_LPEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 906 #define DAC_C0_LPEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 907 #define DAC_C0_DACSWTRG_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 908 #define DAC_C0_DACSWTRG_SHIFT 4
Freescale_cup 0:3ec7fc598e48 909 #define DAC_C0_DACTRGSEL_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 910 #define DAC_C0_DACTRGSEL_SHIFT 5
Freescale_cup 0:3ec7fc598e48 911 #define DAC_C0_DACRFS_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 912 #define DAC_C0_DACRFS_SHIFT 6
Freescale_cup 0:3ec7fc598e48 913 #define DAC_C0_DACEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 914 #define DAC_C0_DACEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 915 /* C1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 916 #define DAC_C1_DACBFEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 917 #define DAC_C1_DACBFEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 918 #define DAC_C1_DACBFMD_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 919 #define DAC_C1_DACBFMD_SHIFT 2
Freescale_cup 0:3ec7fc598e48 920 #define DAC_C1_DMAEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 921 #define DAC_C1_DMAEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 922 /* C2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 923 #define DAC_C2_DACBFUP_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 924 #define DAC_C2_DACBFUP_SHIFT 0
Freescale_cup 0:3ec7fc598e48 925 #define DAC_C2_DACBFRP_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 926 #define DAC_C2_DACBFRP_SHIFT 4
Freescale_cup 0:3ec7fc598e48 927
Freescale_cup 0:3ec7fc598e48 928 /*!
Freescale_cup 0:3ec7fc598e48 929 * @}
Freescale_cup 0:3ec7fc598e48 930 */ /* end of group DAC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 931
Freescale_cup 0:3ec7fc598e48 932
Freescale_cup 0:3ec7fc598e48 933 /* DAC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 934 /** Peripheral DAC0 base pointer */
Freescale_cup 0:3ec7fc598e48 935 #define DAC0_BASE_PTR ((DAC_MemMapPtr)0x4003F000u)
Freescale_cup 0:3ec7fc598e48 936 /** Array initializer of DAC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 937 #define DAC_BASE_PTRS { DAC0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 938
Freescale_cup 0:3ec7fc598e48 939 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 940 -- DAC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 941 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 942
Freescale_cup 0:3ec7fc598e48 943 /*!
Freescale_cup 0:3ec7fc598e48 944 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 945 * @{
Freescale_cup 0:3ec7fc598e48 946 */
Freescale_cup 0:3ec7fc598e48 947
Freescale_cup 0:3ec7fc598e48 948
Freescale_cup 0:3ec7fc598e48 949 /* DAC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 950 /* DAC0 */
Freescale_cup 0:3ec7fc598e48 951 #define DAC0_DAT0L DAC_DATL_REG(DAC0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 952 #define DAC0_DAT0H DAC_DATH_REG(DAC0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 953 #define DAC0_DAT1L DAC_DATL_REG(DAC0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 954 #define DAC0_DAT1H DAC_DATH_REG(DAC0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 955 #define DAC0_SR DAC_SR_REG(DAC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 956 #define DAC0_C0 DAC_C0_REG(DAC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 957 #define DAC0_C1 DAC_C1_REG(DAC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 958 #define DAC0_C2 DAC_C2_REG(DAC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 959
Freescale_cup 0:3ec7fc598e48 960 /* DAC - Register array accessors */
Freescale_cup 0:3ec7fc598e48 961 #define DAC0_DATL(index) DAC_DATL_REG(DAC0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 962 #define DAC0_DATH(index) DAC_DATH_REG(DAC0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 963
Freescale_cup 0:3ec7fc598e48 964 /*!
Freescale_cup 0:3ec7fc598e48 965 * @}
Freescale_cup 0:3ec7fc598e48 966 */ /* end of group DAC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 967
Freescale_cup 0:3ec7fc598e48 968
Freescale_cup 0:3ec7fc598e48 969 /*!
Freescale_cup 0:3ec7fc598e48 970 * @}
Freescale_cup 0:3ec7fc598e48 971 */ /* end of group DAC_Peripheral */
Freescale_cup 0:3ec7fc598e48 972
Freescale_cup 0:3ec7fc598e48 973
Freescale_cup 0:3ec7fc598e48 974 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 975 -- DMA
Freescale_cup 0:3ec7fc598e48 976 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 977
Freescale_cup 0:3ec7fc598e48 978 /*!
Freescale_cup 0:3ec7fc598e48 979 * @addtogroup DMA_Peripheral DMA
Freescale_cup 0:3ec7fc598e48 980 * @{
Freescale_cup 0:3ec7fc598e48 981 */
Freescale_cup 0:3ec7fc598e48 982
Freescale_cup 0:3ec7fc598e48 983 /** DMA - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 984 typedef struct DMA_MemMap {
Freescale_cup 0:3ec7fc598e48 985 uint8_t RESERVED_0[256];
Freescale_cup 0:3ec7fc598e48 986 struct { /* offset: 0x100, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 987 uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 988 uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 989 union { /* offset: 0x108, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 990 uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 991 struct { /* offset: 0x108, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 992 uint8_t RESERVED_0[3];
Freescale_cup 0:3ec7fc598e48 993 uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 994 } DMA_DSR_ACCESS8BIT;
Freescale_cup 0:3ec7fc598e48 995 };
Freescale_cup 0:3ec7fc598e48 996 uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 997 } DMA[4];
Freescale_cup 0:3ec7fc598e48 998 } volatile *DMA_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 999
Freescale_cup 0:3ec7fc598e48 1000 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1001 -- DMA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1002 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1003
Freescale_cup 0:3ec7fc598e48 1004 /*!
Freescale_cup 0:3ec7fc598e48 1005 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1006 * @{
Freescale_cup 0:3ec7fc598e48 1007 */
Freescale_cup 0:3ec7fc598e48 1008
Freescale_cup 0:3ec7fc598e48 1009
Freescale_cup 0:3ec7fc598e48 1010 /* DMA - Register accessors */
Freescale_cup 0:3ec7fc598e48 1011 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
Freescale_cup 0:3ec7fc598e48 1012 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
Freescale_cup 0:3ec7fc598e48 1013 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
Freescale_cup 0:3ec7fc598e48 1014 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
Freescale_cup 0:3ec7fc598e48 1015 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
Freescale_cup 0:3ec7fc598e48 1016
Freescale_cup 0:3ec7fc598e48 1017 /*!
Freescale_cup 0:3ec7fc598e48 1018 * @}
Freescale_cup 0:3ec7fc598e48 1019 */ /* end of group DMA_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1020
Freescale_cup 0:3ec7fc598e48 1021
Freescale_cup 0:3ec7fc598e48 1022 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1023 -- DMA Register Masks
Freescale_cup 0:3ec7fc598e48 1024 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1025
Freescale_cup 0:3ec7fc598e48 1026 /*!
Freescale_cup 0:3ec7fc598e48 1027 * @addtogroup DMA_Register_Masks DMA Register Masks
Freescale_cup 0:3ec7fc598e48 1028 * @{
Freescale_cup 0:3ec7fc598e48 1029 */
Freescale_cup 0:3ec7fc598e48 1030
Freescale_cup 0:3ec7fc598e48 1031 /* SAR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1032 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1033 #define DMA_SAR_SAR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1034 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
Freescale_cup 0:3ec7fc598e48 1035 /* DAR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1036 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1037 #define DMA_DAR_DAR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1038 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
Freescale_cup 0:3ec7fc598e48 1039 /* DSR_BCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1040 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
Freescale_cup 0:3ec7fc598e48 1041 #define DMA_DSR_BCR_BCR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1042 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
Freescale_cup 0:3ec7fc598e48 1043 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
Freescale_cup 0:3ec7fc598e48 1044 #define DMA_DSR_BCR_DONE_SHIFT 24
Freescale_cup 0:3ec7fc598e48 1045 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
Freescale_cup 0:3ec7fc598e48 1046 #define DMA_DSR_BCR_BSY_SHIFT 25
Freescale_cup 0:3ec7fc598e48 1047 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
Freescale_cup 0:3ec7fc598e48 1048 #define DMA_DSR_BCR_REQ_SHIFT 26
Freescale_cup 0:3ec7fc598e48 1049 #define DMA_DSR_BCR_BED_MASK 0x10000000u
Freescale_cup 0:3ec7fc598e48 1050 #define DMA_DSR_BCR_BED_SHIFT 28
Freescale_cup 0:3ec7fc598e48 1051 #define DMA_DSR_BCR_BES_MASK 0x20000000u
Freescale_cup 0:3ec7fc598e48 1052 #define DMA_DSR_BCR_BES_SHIFT 29
Freescale_cup 0:3ec7fc598e48 1053 #define DMA_DSR_BCR_CE_MASK 0x40000000u
Freescale_cup 0:3ec7fc598e48 1054 #define DMA_DSR_BCR_CE_SHIFT 30
Freescale_cup 0:3ec7fc598e48 1055 /* DCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1056 #define DMA_DCR_LCH2_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 1057 #define DMA_DCR_LCH2_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1058 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
Freescale_cup 0:3ec7fc598e48 1059 #define DMA_DCR_LCH1_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 1060 #define DMA_DCR_LCH1_SHIFT 2
Freescale_cup 0:3ec7fc598e48 1061 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
Freescale_cup 0:3ec7fc598e48 1062 #define DMA_DCR_LINKCC_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 1063 #define DMA_DCR_LINKCC_SHIFT 4
Freescale_cup 0:3ec7fc598e48 1064 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
Freescale_cup 0:3ec7fc598e48 1065 #define DMA_DCR_D_REQ_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 1066 #define DMA_DCR_D_REQ_SHIFT 7
Freescale_cup 0:3ec7fc598e48 1067 #define DMA_DCR_DMOD_MASK 0xF00u
Freescale_cup 0:3ec7fc598e48 1068 #define DMA_DCR_DMOD_SHIFT 8
Freescale_cup 0:3ec7fc598e48 1069 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
Freescale_cup 0:3ec7fc598e48 1070 #define DMA_DCR_SMOD_MASK 0xF000u
Freescale_cup 0:3ec7fc598e48 1071 #define DMA_DCR_SMOD_SHIFT 12
Freescale_cup 0:3ec7fc598e48 1072 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
Freescale_cup 0:3ec7fc598e48 1073 #define DMA_DCR_START_MASK 0x10000u
Freescale_cup 0:3ec7fc598e48 1074 #define DMA_DCR_START_SHIFT 16
Freescale_cup 0:3ec7fc598e48 1075 #define DMA_DCR_DSIZE_MASK 0x60000u
Freescale_cup 0:3ec7fc598e48 1076 #define DMA_DCR_DSIZE_SHIFT 17
Freescale_cup 0:3ec7fc598e48 1077 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
Freescale_cup 0:3ec7fc598e48 1078 #define DMA_DCR_DINC_MASK 0x80000u
Freescale_cup 0:3ec7fc598e48 1079 #define DMA_DCR_DINC_SHIFT 19
Freescale_cup 0:3ec7fc598e48 1080 #define DMA_DCR_SSIZE_MASK 0x300000u
Freescale_cup 0:3ec7fc598e48 1081 #define DMA_DCR_SSIZE_SHIFT 20
Freescale_cup 0:3ec7fc598e48 1082 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
Freescale_cup 0:3ec7fc598e48 1083 #define DMA_DCR_SINC_MASK 0x400000u
Freescale_cup 0:3ec7fc598e48 1084 #define DMA_DCR_SINC_SHIFT 22
Freescale_cup 0:3ec7fc598e48 1085 #define DMA_DCR_EADREQ_MASK 0x800000u
Freescale_cup 0:3ec7fc598e48 1086 #define DMA_DCR_EADREQ_SHIFT 23
Freescale_cup 0:3ec7fc598e48 1087 #define DMA_DCR_AA_MASK 0x10000000u
Freescale_cup 0:3ec7fc598e48 1088 #define DMA_DCR_AA_SHIFT 28
Freescale_cup 0:3ec7fc598e48 1089 #define DMA_DCR_CS_MASK 0x20000000u
Freescale_cup 0:3ec7fc598e48 1090 #define DMA_DCR_CS_SHIFT 29
Freescale_cup 0:3ec7fc598e48 1091 #define DMA_DCR_ERQ_MASK 0x40000000u
Freescale_cup 0:3ec7fc598e48 1092 #define DMA_DCR_ERQ_SHIFT 30
Freescale_cup 0:3ec7fc598e48 1093 #define DMA_DCR_EINT_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 1094 #define DMA_DCR_EINT_SHIFT 31
Freescale_cup 0:3ec7fc598e48 1095
Freescale_cup 0:3ec7fc598e48 1096 /*!
Freescale_cup 0:3ec7fc598e48 1097 * @}
Freescale_cup 0:3ec7fc598e48 1098 */ /* end of group DMA_Register_Masks */
Freescale_cup 0:3ec7fc598e48 1099
Freescale_cup 0:3ec7fc598e48 1100
Freescale_cup 0:3ec7fc598e48 1101 /* DMA - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 1102 /** Peripheral DMA base pointer */
Freescale_cup 0:3ec7fc598e48 1103 #define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u)
Freescale_cup 0:3ec7fc598e48 1104 /** Array initializer of DMA peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 1105 #define DMA_BASE_PTRS { DMA_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 1106
Freescale_cup 0:3ec7fc598e48 1107 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1108 -- DMA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1109 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1110
Freescale_cup 0:3ec7fc598e48 1111 /*!
Freescale_cup 0:3ec7fc598e48 1112 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1113 * @{
Freescale_cup 0:3ec7fc598e48 1114 */
Freescale_cup 0:3ec7fc598e48 1115
Freescale_cup 0:3ec7fc598e48 1116
Freescale_cup 0:3ec7fc598e48 1117 /* DMA - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 1118 /* DMA */
Freescale_cup 0:3ec7fc598e48 1119 #define DMA_SAR0 DMA_SAR_REG(DMA_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1120 #define DMA_DAR0 DMA_DAR_REG(DMA_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1121 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1122 #define DMA_DSR0 DMA_DSR_REG(DMA_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1123 #define DMA_DCR0 DMA_DCR_REG(DMA_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1124 #define DMA_SAR1 DMA_SAR_REG(DMA_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1125 #define DMA_DAR1 DMA_DAR_REG(DMA_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1126 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1127 #define DMA_DSR1 DMA_DSR_REG(DMA_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1128 #define DMA_DCR1 DMA_DCR_REG(DMA_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1129 #define DMA_SAR2 DMA_SAR_REG(DMA_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 1130 #define DMA_DAR2 DMA_DAR_REG(DMA_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 1131 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 1132 #define DMA_DSR2 DMA_DSR_REG(DMA_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 1133 #define DMA_DCR2 DMA_DCR_REG(DMA_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 1134 #define DMA_SAR3 DMA_SAR_REG(DMA_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 1135 #define DMA_DAR3 DMA_DAR_REG(DMA_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 1136 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 1137 #define DMA_DSR3 DMA_DSR_REG(DMA_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 1138 #define DMA_DCR3 DMA_DCR_REG(DMA_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 1139
Freescale_cup 0:3ec7fc598e48 1140 /* DMA - Register array accessors */
Freescale_cup 0:3ec7fc598e48 1141 #define DMA_SAR(index) DMA_SAR_REG(DMA_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1142 #define DMA_DAR(index) DMA_DAR_REG(DMA_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1143 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1144 #define DMA_DSR(index) DMA_DSR_REG(DMA_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1145 #define DMA_DCR(index) DMA_DCR_REG(DMA_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1146
Freescale_cup 0:3ec7fc598e48 1147 /*!
Freescale_cup 0:3ec7fc598e48 1148 * @}
Freescale_cup 0:3ec7fc598e48 1149 */ /* end of group DMA_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1150
Freescale_cup 0:3ec7fc598e48 1151
Freescale_cup 0:3ec7fc598e48 1152 /*!
Freescale_cup 0:3ec7fc598e48 1153 * @}
Freescale_cup 0:3ec7fc598e48 1154 */ /* end of group DMA_Peripheral */
Freescale_cup 0:3ec7fc598e48 1155
Freescale_cup 0:3ec7fc598e48 1156
Freescale_cup 0:3ec7fc598e48 1157 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1158 -- DMAMUX
Freescale_cup 0:3ec7fc598e48 1159 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1160
Freescale_cup 0:3ec7fc598e48 1161 /*!
Freescale_cup 0:3ec7fc598e48 1162 * @addtogroup DMAMUX_Peripheral DMAMUX
Freescale_cup 0:3ec7fc598e48 1163 * @{
Freescale_cup 0:3ec7fc598e48 1164 */
Freescale_cup 0:3ec7fc598e48 1165
Freescale_cup 0:3ec7fc598e48 1166 /** DMAMUX - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 1167 typedef struct DMAMUX_MemMap {
Freescale_cup 0:3ec7fc598e48 1168 uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
Freescale_cup 0:3ec7fc598e48 1169 } volatile *DMAMUX_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 1170
Freescale_cup 0:3ec7fc598e48 1171 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1172 -- DMAMUX - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1173 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1174
Freescale_cup 0:3ec7fc598e48 1175 /*!
Freescale_cup 0:3ec7fc598e48 1176 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1177 * @{
Freescale_cup 0:3ec7fc598e48 1178 */
Freescale_cup 0:3ec7fc598e48 1179
Freescale_cup 0:3ec7fc598e48 1180
Freescale_cup 0:3ec7fc598e48 1181 /* DMAMUX - Register accessors */
Freescale_cup 0:3ec7fc598e48 1182 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
Freescale_cup 0:3ec7fc598e48 1183
Freescale_cup 0:3ec7fc598e48 1184 /*!
Freescale_cup 0:3ec7fc598e48 1185 * @}
Freescale_cup 0:3ec7fc598e48 1186 */ /* end of group DMAMUX_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1187
Freescale_cup 0:3ec7fc598e48 1188
Freescale_cup 0:3ec7fc598e48 1189 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1190 -- DMAMUX Register Masks
Freescale_cup 0:3ec7fc598e48 1191 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1192
Freescale_cup 0:3ec7fc598e48 1193 /*!
Freescale_cup 0:3ec7fc598e48 1194 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Freescale_cup 0:3ec7fc598e48 1195 * @{
Freescale_cup 0:3ec7fc598e48 1196 */
Freescale_cup 0:3ec7fc598e48 1197
Freescale_cup 0:3ec7fc598e48 1198 /* CHCFG Bit Fields */
Freescale_cup 0:3ec7fc598e48 1199 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 1200 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1201 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
Freescale_cup 0:3ec7fc598e48 1202 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 1203 #define DMAMUX_CHCFG_TRIG_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1204 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 1205 #define DMAMUX_CHCFG_ENBL_SHIFT 7
Freescale_cup 0:3ec7fc598e48 1206
Freescale_cup 0:3ec7fc598e48 1207 /*!
Freescale_cup 0:3ec7fc598e48 1208 * @}
Freescale_cup 0:3ec7fc598e48 1209 */ /* end of group DMAMUX_Register_Masks */
Freescale_cup 0:3ec7fc598e48 1210
Freescale_cup 0:3ec7fc598e48 1211
Freescale_cup 0:3ec7fc598e48 1212 /* DMAMUX - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 1213 /** Peripheral DMAMUX0 base pointer */
Freescale_cup 0:3ec7fc598e48 1214 #define DMAMUX0_BASE_PTR ((DMAMUX_MemMapPtr)0x40021000u)
Freescale_cup 0:3ec7fc598e48 1215 /** Array initializer of DMAMUX peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 1216 #define DMAMUX_BASE_PTRS { DMAMUX0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 1217
Freescale_cup 0:3ec7fc598e48 1218 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1219 -- DMAMUX - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1220 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1221
Freescale_cup 0:3ec7fc598e48 1222 /*!
Freescale_cup 0:3ec7fc598e48 1223 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1224 * @{
Freescale_cup 0:3ec7fc598e48 1225 */
Freescale_cup 0:3ec7fc598e48 1226
Freescale_cup 0:3ec7fc598e48 1227
Freescale_cup 0:3ec7fc598e48 1228 /* DMAMUX - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 1229 /* DMAMUX0 */
Freescale_cup 0:3ec7fc598e48 1230 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1231 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1232 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 1233 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 1234
Freescale_cup 0:3ec7fc598e48 1235 /* DMAMUX - Register array accessors */
Freescale_cup 0:3ec7fc598e48 1236 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1237
Freescale_cup 0:3ec7fc598e48 1238 /*!
Freescale_cup 0:3ec7fc598e48 1239 * @}
Freescale_cup 0:3ec7fc598e48 1240 */ /* end of group DMAMUX_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1241
Freescale_cup 0:3ec7fc598e48 1242
Freescale_cup 0:3ec7fc598e48 1243 /*!
Freescale_cup 0:3ec7fc598e48 1244 * @}
Freescale_cup 0:3ec7fc598e48 1245 */ /* end of group DMAMUX_Peripheral */
Freescale_cup 0:3ec7fc598e48 1246
Freescale_cup 0:3ec7fc598e48 1247
Freescale_cup 0:3ec7fc598e48 1248 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1249 -- DWT
Freescale_cup 0:3ec7fc598e48 1250 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1251
Freescale_cup 0:3ec7fc598e48 1252 /*!
Freescale_cup 0:3ec7fc598e48 1253 * @addtogroup DWT_Peripheral DWT
Freescale_cup 0:3ec7fc598e48 1254 * @{
Freescale_cup 0:3ec7fc598e48 1255 */
Freescale_cup 0:3ec7fc598e48 1256
Freescale_cup 0:3ec7fc598e48 1257 /** DWT - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 1258 typedef struct DWT_MemMap {
Freescale_cup 0:3ec7fc598e48 1259 uint32_t CTRL; /**< Control Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 1260 uint8_t RESERVED_0[24];
Freescale_cup 0:3ec7fc598e48 1261 uint32_t PCSR; /**< Program Counter Sample Register, offset: 0x1C */
Freescale_cup 0:3ec7fc598e48 1262 struct { /* offset: 0x20, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 1263 uint32_t COMP; /**< Comparator Register 0..Comparator Register 1, array offset: 0x20, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 1264 uint32_t MASK; /**< Mask Register 0..Mask Register 1, array offset: 0x24, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 1265 uint32_t FUNCTION; /**< Function Register 0..Function Register 1, array offset: 0x28, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 1266 uint8_t RESERVED_0[4];
Freescale_cup 0:3ec7fc598e48 1267 } COMPARATOR[2];
Freescale_cup 0:3ec7fc598e48 1268 } volatile *DWT_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 1269
Freescale_cup 0:3ec7fc598e48 1270 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1271 -- DWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1272 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1273
Freescale_cup 0:3ec7fc598e48 1274 /*!
Freescale_cup 0:3ec7fc598e48 1275 * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1276 * @{
Freescale_cup 0:3ec7fc598e48 1277 */
Freescale_cup 0:3ec7fc598e48 1278
Freescale_cup 0:3ec7fc598e48 1279
Freescale_cup 0:3ec7fc598e48 1280 /* DWT - Register accessors */
Freescale_cup 0:3ec7fc598e48 1281 #define DWT_CTRL_REG(base) ((base)->CTRL)
Freescale_cup 0:3ec7fc598e48 1282 #define DWT_PCSR_REG(base) ((base)->PCSR)
Freescale_cup 0:3ec7fc598e48 1283 #define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
Freescale_cup 0:3ec7fc598e48 1284 #define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
Freescale_cup 0:3ec7fc598e48 1285 #define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION)
Freescale_cup 0:3ec7fc598e48 1286
Freescale_cup 0:3ec7fc598e48 1287 /*!
Freescale_cup 0:3ec7fc598e48 1288 * @}
Freescale_cup 0:3ec7fc598e48 1289 */ /* end of group DWT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1290
Freescale_cup 0:3ec7fc598e48 1291
Freescale_cup 0:3ec7fc598e48 1292 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1293 -- DWT Register Masks
Freescale_cup 0:3ec7fc598e48 1294 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1295
Freescale_cup 0:3ec7fc598e48 1296 /*!
Freescale_cup 0:3ec7fc598e48 1297 * @addtogroup DWT_Register_Masks DWT Register Masks
Freescale_cup 0:3ec7fc598e48 1298 * @{
Freescale_cup 0:3ec7fc598e48 1299 */
Freescale_cup 0:3ec7fc598e48 1300
Freescale_cup 0:3ec7fc598e48 1301
Freescale_cup 0:3ec7fc598e48 1302 /*!
Freescale_cup 0:3ec7fc598e48 1303 * @}
Freescale_cup 0:3ec7fc598e48 1304 */ /* end of group DWT_Register_Masks */
Freescale_cup 0:3ec7fc598e48 1305
Freescale_cup 0:3ec7fc598e48 1306
Freescale_cup 0:3ec7fc598e48 1307 /* DWT - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 1308 /** Peripheral DWT base pointer */
Freescale_cup 0:3ec7fc598e48 1309 #define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u)
Freescale_cup 0:3ec7fc598e48 1310 /** Array initializer of DWT peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 1311 #define DWT_BASE_PTRS { DWT_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 1312
Freescale_cup 0:3ec7fc598e48 1313 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1314 -- DWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1315 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1316
Freescale_cup 0:3ec7fc598e48 1317 /*!
Freescale_cup 0:3ec7fc598e48 1318 * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1319 * @{
Freescale_cup 0:3ec7fc598e48 1320 */
Freescale_cup 0:3ec7fc598e48 1321
Freescale_cup 0:3ec7fc598e48 1322
Freescale_cup 0:3ec7fc598e48 1323 /* DWT - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 1324 /* DWT */
Freescale_cup 0:3ec7fc598e48 1325 #define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1326 #define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1327 #define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1328 #define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1329 #define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 1330 #define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1331 #define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1332 #define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 1333
Freescale_cup 0:3ec7fc598e48 1334 /* DWT - Register array accessors */
Freescale_cup 0:3ec7fc598e48 1335 #define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1336 #define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1337 #define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 1338
Freescale_cup 0:3ec7fc598e48 1339 /*!
Freescale_cup 0:3ec7fc598e48 1340 * @}
Freescale_cup 0:3ec7fc598e48 1341 */ /* end of group DWT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1342
Freescale_cup 0:3ec7fc598e48 1343
Freescale_cup 0:3ec7fc598e48 1344 /*!
Freescale_cup 0:3ec7fc598e48 1345 * @}
Freescale_cup 0:3ec7fc598e48 1346 */ /* end of group DWT_Peripheral */
Freescale_cup 0:3ec7fc598e48 1347
Freescale_cup 0:3ec7fc598e48 1348
Freescale_cup 0:3ec7fc598e48 1349 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1350 -- FGPIO
Freescale_cup 0:3ec7fc598e48 1351 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1352
Freescale_cup 0:3ec7fc598e48 1353 /*!
Freescale_cup 0:3ec7fc598e48 1354 * @addtogroup FGPIO_Peripheral FGPIO
Freescale_cup 0:3ec7fc598e48 1355 * @{
Freescale_cup 0:3ec7fc598e48 1356 */
Freescale_cup 0:3ec7fc598e48 1357
Freescale_cup 0:3ec7fc598e48 1358 /** FGPIO - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 1359 typedef struct FGPIO_MemMap {
Freescale_cup 0:3ec7fc598e48 1360 uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 1361 uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 1362 uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 1363 uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 1364 uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
Freescale_cup 0:3ec7fc598e48 1365 uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
Freescale_cup 0:3ec7fc598e48 1366 } volatile *FGPIO_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 1367
Freescale_cup 0:3ec7fc598e48 1368 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1369 -- FGPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1370 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1371
Freescale_cup 0:3ec7fc598e48 1372 /*!
Freescale_cup 0:3ec7fc598e48 1373 * @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1374 * @{
Freescale_cup 0:3ec7fc598e48 1375 */
Freescale_cup 0:3ec7fc598e48 1376
Freescale_cup 0:3ec7fc598e48 1377
Freescale_cup 0:3ec7fc598e48 1378 /* FGPIO - Register accessors */
Freescale_cup 0:3ec7fc598e48 1379 #define FGPIO_PDOR_REG(base) ((base)->PDOR)
Freescale_cup 0:3ec7fc598e48 1380 #define FGPIO_PSOR_REG(base) ((base)->PSOR)
Freescale_cup 0:3ec7fc598e48 1381 #define FGPIO_PCOR_REG(base) ((base)->PCOR)
Freescale_cup 0:3ec7fc598e48 1382 #define FGPIO_PTOR_REG(base) ((base)->PTOR)
Freescale_cup 0:3ec7fc598e48 1383 #define FGPIO_PDIR_REG(base) ((base)->PDIR)
Freescale_cup 0:3ec7fc598e48 1384 #define FGPIO_PDDR_REG(base) ((base)->PDDR)
Freescale_cup 0:3ec7fc598e48 1385
Freescale_cup 0:3ec7fc598e48 1386 /*!
Freescale_cup 0:3ec7fc598e48 1387 * @}
Freescale_cup 0:3ec7fc598e48 1388 */ /* end of group FGPIO_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1389
Freescale_cup 0:3ec7fc598e48 1390
Freescale_cup 0:3ec7fc598e48 1391 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1392 -- FGPIO Register Masks
Freescale_cup 0:3ec7fc598e48 1393 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1394
Freescale_cup 0:3ec7fc598e48 1395 /*!
Freescale_cup 0:3ec7fc598e48 1396 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
Freescale_cup 0:3ec7fc598e48 1397 * @{
Freescale_cup 0:3ec7fc598e48 1398 */
Freescale_cup 0:3ec7fc598e48 1399
Freescale_cup 0:3ec7fc598e48 1400 /* PDOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1401 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1402 #define FGPIO_PDOR_PDO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1403 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
Freescale_cup 0:3ec7fc598e48 1404 /* PSOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1405 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1406 #define FGPIO_PSOR_PTSO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1407 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
Freescale_cup 0:3ec7fc598e48 1408 /* PCOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1409 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1410 #define FGPIO_PCOR_PTCO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1411 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
Freescale_cup 0:3ec7fc598e48 1412 /* PTOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1413 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1414 #define FGPIO_PTOR_PTTO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1415 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
Freescale_cup 0:3ec7fc598e48 1416 /* PDIR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1417 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1418 #define FGPIO_PDIR_PDI_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1419 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
Freescale_cup 0:3ec7fc598e48 1420 /* PDDR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1421 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1422 #define FGPIO_PDDR_PDD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1423 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
Freescale_cup 0:3ec7fc598e48 1424
Freescale_cup 0:3ec7fc598e48 1425 /*!
Freescale_cup 0:3ec7fc598e48 1426 * @}
Freescale_cup 0:3ec7fc598e48 1427 */ /* end of group FGPIO_Register_Masks */
Freescale_cup 0:3ec7fc598e48 1428
Freescale_cup 0:3ec7fc598e48 1429
Freescale_cup 0:3ec7fc598e48 1430 /* FGPIO - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 1431 /** Peripheral FPTA base pointer */
Freescale_cup 0:3ec7fc598e48 1432 #define FPTA_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF000u)
Freescale_cup 0:3ec7fc598e48 1433 /** Peripheral FPTB base pointer */
Freescale_cup 0:3ec7fc598e48 1434 #define FPTB_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF040u)
Freescale_cup 0:3ec7fc598e48 1435 /** Peripheral FPTC base pointer */
Freescale_cup 0:3ec7fc598e48 1436 #define FPTC_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF080u)
Freescale_cup 0:3ec7fc598e48 1437 /** Peripheral FPTD base pointer */
Freescale_cup 0:3ec7fc598e48 1438 #define FPTD_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF0C0u)
Freescale_cup 0:3ec7fc598e48 1439 /** Peripheral FPTE base pointer */
Freescale_cup 0:3ec7fc598e48 1440 #define FPTE_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF100u)
Freescale_cup 0:3ec7fc598e48 1441 /** Array initializer of FGPIO peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 1442 #define FGPIO_BASE_PTRS { FPTA_BASE_PTR, FPTB_BASE_PTR, FPTC_BASE_PTR, FPTD_BASE_PTR, FPTE_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 1443
Freescale_cup 0:3ec7fc598e48 1444 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1445 -- FGPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1446 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1447
Freescale_cup 0:3ec7fc598e48 1448 /*!
Freescale_cup 0:3ec7fc598e48 1449 * @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1450 * @{
Freescale_cup 0:3ec7fc598e48 1451 */
Freescale_cup 0:3ec7fc598e48 1452
Freescale_cup 0:3ec7fc598e48 1453
Freescale_cup 0:3ec7fc598e48 1454 /* FGPIO - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 1455 /* FPTA */
Freescale_cup 0:3ec7fc598e48 1456 #define FGPIOA_PDOR FGPIO_PDOR_REG(FPTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1457 #define FGPIOA_PSOR FGPIO_PSOR_REG(FPTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1458 #define FGPIOA_PCOR FGPIO_PCOR_REG(FPTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1459 #define FGPIOA_PTOR FGPIO_PTOR_REG(FPTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1460 #define FGPIOA_PDIR FGPIO_PDIR_REG(FPTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1461 #define FGPIOA_PDDR FGPIO_PDDR_REG(FPTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1462 /* FPTB */
Freescale_cup 0:3ec7fc598e48 1463 #define FGPIOB_PDOR FGPIO_PDOR_REG(FPTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1464 #define FGPIOB_PSOR FGPIO_PSOR_REG(FPTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1465 #define FGPIOB_PCOR FGPIO_PCOR_REG(FPTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1466 #define FGPIOB_PTOR FGPIO_PTOR_REG(FPTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1467 #define FGPIOB_PDIR FGPIO_PDIR_REG(FPTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1468 #define FGPIOB_PDDR FGPIO_PDDR_REG(FPTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1469 /* FPTC */
Freescale_cup 0:3ec7fc598e48 1470 #define FGPIOC_PDOR FGPIO_PDOR_REG(FPTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1471 #define FGPIOC_PSOR FGPIO_PSOR_REG(FPTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1472 #define FGPIOC_PCOR FGPIO_PCOR_REG(FPTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1473 #define FGPIOC_PTOR FGPIO_PTOR_REG(FPTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1474 #define FGPIOC_PDIR FGPIO_PDIR_REG(FPTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1475 #define FGPIOC_PDDR FGPIO_PDDR_REG(FPTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1476 /* FPTD */
Freescale_cup 0:3ec7fc598e48 1477 #define FGPIOD_PDOR FGPIO_PDOR_REG(FPTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1478 #define FGPIOD_PSOR FGPIO_PSOR_REG(FPTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1479 #define FGPIOD_PCOR FGPIO_PCOR_REG(FPTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1480 #define FGPIOD_PTOR FGPIO_PTOR_REG(FPTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1481 #define FGPIOD_PDIR FGPIO_PDIR_REG(FPTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1482 #define FGPIOD_PDDR FGPIO_PDDR_REG(FPTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1483 /* FPTE */
Freescale_cup 0:3ec7fc598e48 1484 #define FGPIOE_PDOR FGPIO_PDOR_REG(FPTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1485 #define FGPIOE_PSOR FGPIO_PSOR_REG(FPTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1486 #define FGPIOE_PCOR FGPIO_PCOR_REG(FPTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1487 #define FGPIOE_PTOR FGPIO_PTOR_REG(FPTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1488 #define FGPIOE_PDIR FGPIO_PDIR_REG(FPTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1489 #define FGPIOE_PDDR FGPIO_PDDR_REG(FPTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1490
Freescale_cup 0:3ec7fc598e48 1491 /*!
Freescale_cup 0:3ec7fc598e48 1492 * @}
Freescale_cup 0:3ec7fc598e48 1493 */ /* end of group FGPIO_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1494
Freescale_cup 0:3ec7fc598e48 1495
Freescale_cup 0:3ec7fc598e48 1496 /*!
Freescale_cup 0:3ec7fc598e48 1497 * @}
Freescale_cup 0:3ec7fc598e48 1498 */ /* end of group FGPIO_Peripheral */
Freescale_cup 0:3ec7fc598e48 1499
Freescale_cup 0:3ec7fc598e48 1500
Freescale_cup 0:3ec7fc598e48 1501 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1502 -- FTFA
Freescale_cup 0:3ec7fc598e48 1503 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1504
Freescale_cup 0:3ec7fc598e48 1505 /*!
Freescale_cup 0:3ec7fc598e48 1506 * @addtogroup FTFA_Peripheral FTFA
Freescale_cup 0:3ec7fc598e48 1507 * @{
Freescale_cup 0:3ec7fc598e48 1508 */
Freescale_cup 0:3ec7fc598e48 1509
Freescale_cup 0:3ec7fc598e48 1510 /** FTFA - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 1511 typedef struct FTFA_MemMap {
Freescale_cup 0:3ec7fc598e48 1512 uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 1513 uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 1514 uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 1515 uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 1516 uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 1517 uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 1518 uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 1519 uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 1520 uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 1521 uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
Freescale_cup 0:3ec7fc598e48 1522 uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
Freescale_cup 0:3ec7fc598e48 1523 uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
Freescale_cup 0:3ec7fc598e48 1524 uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 1525 uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
Freescale_cup 0:3ec7fc598e48 1526 uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
Freescale_cup 0:3ec7fc598e48 1527 uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
Freescale_cup 0:3ec7fc598e48 1528 uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
Freescale_cup 0:3ec7fc598e48 1529 uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
Freescale_cup 0:3ec7fc598e48 1530 uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
Freescale_cup 0:3ec7fc598e48 1531 uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
Freescale_cup 0:3ec7fc598e48 1532 } volatile *FTFA_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 1533
Freescale_cup 0:3ec7fc598e48 1534 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1535 -- FTFA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1536 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1537
Freescale_cup 0:3ec7fc598e48 1538 /*!
Freescale_cup 0:3ec7fc598e48 1539 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1540 * @{
Freescale_cup 0:3ec7fc598e48 1541 */
Freescale_cup 0:3ec7fc598e48 1542
Freescale_cup 0:3ec7fc598e48 1543
Freescale_cup 0:3ec7fc598e48 1544 /* FTFA - Register accessors */
Freescale_cup 0:3ec7fc598e48 1545 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
Freescale_cup 0:3ec7fc598e48 1546 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
Freescale_cup 0:3ec7fc598e48 1547 #define FTFA_FSEC_REG(base) ((base)->FSEC)
Freescale_cup 0:3ec7fc598e48 1548 #define FTFA_FOPT_REG(base) ((base)->FOPT)
Freescale_cup 0:3ec7fc598e48 1549 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
Freescale_cup 0:3ec7fc598e48 1550 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
Freescale_cup 0:3ec7fc598e48 1551 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
Freescale_cup 0:3ec7fc598e48 1552 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
Freescale_cup 0:3ec7fc598e48 1553 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
Freescale_cup 0:3ec7fc598e48 1554 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
Freescale_cup 0:3ec7fc598e48 1555 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
Freescale_cup 0:3ec7fc598e48 1556 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
Freescale_cup 0:3ec7fc598e48 1557 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
Freescale_cup 0:3ec7fc598e48 1558 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
Freescale_cup 0:3ec7fc598e48 1559 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
Freescale_cup 0:3ec7fc598e48 1560 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
Freescale_cup 0:3ec7fc598e48 1561 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
Freescale_cup 0:3ec7fc598e48 1562 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
Freescale_cup 0:3ec7fc598e48 1563 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
Freescale_cup 0:3ec7fc598e48 1564 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
Freescale_cup 0:3ec7fc598e48 1565
Freescale_cup 0:3ec7fc598e48 1566 /*!
Freescale_cup 0:3ec7fc598e48 1567 * @}
Freescale_cup 0:3ec7fc598e48 1568 */ /* end of group FTFA_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1569
Freescale_cup 0:3ec7fc598e48 1570
Freescale_cup 0:3ec7fc598e48 1571 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1572 -- FTFA Register Masks
Freescale_cup 0:3ec7fc598e48 1573 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1574
Freescale_cup 0:3ec7fc598e48 1575 /*!
Freescale_cup 0:3ec7fc598e48 1576 * @addtogroup FTFA_Register_Masks FTFA Register Masks
Freescale_cup 0:3ec7fc598e48 1577 * @{
Freescale_cup 0:3ec7fc598e48 1578 */
Freescale_cup 0:3ec7fc598e48 1579
Freescale_cup 0:3ec7fc598e48 1580 /* FSTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 1581 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 1582 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1583 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 1584 #define FTFA_FSTAT_FPVIOL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 1585 #define FTFA_FSTAT_ACCERR_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 1586 #define FTFA_FSTAT_ACCERR_SHIFT 5
Freescale_cup 0:3ec7fc598e48 1587 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 1588 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1589 #define FTFA_FSTAT_CCIF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 1590 #define FTFA_FSTAT_CCIF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 1591 /* FCNFG Bit Fields */
Freescale_cup 0:3ec7fc598e48 1592 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 1593 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
Freescale_cup 0:3ec7fc598e48 1594 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 1595 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
Freescale_cup 0:3ec7fc598e48 1596 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 1597 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1598 #define FTFA_FCNFG_CCIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 1599 #define FTFA_FCNFG_CCIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 1600 /* FSEC Bit Fields */
Freescale_cup 0:3ec7fc598e48 1601 #define FTFA_FSEC_SEC_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 1602 #define FTFA_FSEC_SEC_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1603 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
Freescale_cup 0:3ec7fc598e48 1604 #define FTFA_FSEC_FSLACC_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 1605 #define FTFA_FSEC_FSLACC_SHIFT 2
Freescale_cup 0:3ec7fc598e48 1606 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
Freescale_cup 0:3ec7fc598e48 1607 #define FTFA_FSEC_MEEN_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 1608 #define FTFA_FSEC_MEEN_SHIFT 4
Freescale_cup 0:3ec7fc598e48 1609 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
Freescale_cup 0:3ec7fc598e48 1610 #define FTFA_FSEC_KEYEN_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 1611 #define FTFA_FSEC_KEYEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1612 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
Freescale_cup 0:3ec7fc598e48 1613 /* FOPT Bit Fields */
Freescale_cup 0:3ec7fc598e48 1614 #define FTFA_FOPT_OPT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1615 #define FTFA_FOPT_OPT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1616 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
Freescale_cup 0:3ec7fc598e48 1617 /* FCCOB3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1618 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1619 #define FTFA_FCCOB3_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1620 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1621 /* FCCOB2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1622 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1623 #define FTFA_FCCOB2_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1624 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1625 /* FCCOB1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1626 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1627 #define FTFA_FCCOB1_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1628 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1629 /* FCCOB0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1630 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1631 #define FTFA_FCCOB0_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1632 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1633 /* FCCOB7 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1634 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1635 #define FTFA_FCCOB7_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1636 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1637 /* FCCOB6 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1638 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1639 #define FTFA_FCCOB6_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1640 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1641 /* FCCOB5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1642 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1643 #define FTFA_FCCOB5_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1644 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1645 /* FCCOB4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1646 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1647 #define FTFA_FCCOB4_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1648 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1649 /* FCCOBB Bit Fields */
Freescale_cup 0:3ec7fc598e48 1650 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1651 #define FTFA_FCCOBB_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1652 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1653 /* FCCOBA Bit Fields */
Freescale_cup 0:3ec7fc598e48 1654 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1655 #define FTFA_FCCOBA_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1656 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1657 /* FCCOB9 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1658 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1659 #define FTFA_FCCOB9_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1660 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1661 /* FCCOB8 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1662 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1663 #define FTFA_FCCOB8_CCOBn_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1664 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
Freescale_cup 0:3ec7fc598e48 1665 /* FPROT3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1666 #define FTFA_FPROT3_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1667 #define FTFA_FPROT3_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1668 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 1669 /* FPROT2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1670 #define FTFA_FPROT2_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1671 #define FTFA_FPROT2_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1672 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 1673 /* FPROT1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1674 #define FTFA_FPROT1_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1675 #define FTFA_FPROT1_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1676 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 1677 /* FPROT0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1678 #define FTFA_FPROT0_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1679 #define FTFA_FPROT0_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1680 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 1681
Freescale_cup 0:3ec7fc598e48 1682 /*!
Freescale_cup 0:3ec7fc598e48 1683 * @}
Freescale_cup 0:3ec7fc598e48 1684 */ /* end of group FTFA_Register_Masks */
Freescale_cup 0:3ec7fc598e48 1685
Freescale_cup 0:3ec7fc598e48 1686
Freescale_cup 0:3ec7fc598e48 1687 /* FTFA - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 1688 /** Peripheral FTFA base pointer */
Freescale_cup 0:3ec7fc598e48 1689 #define FTFA_BASE_PTR ((FTFA_MemMapPtr)0x40020000u)
Freescale_cup 0:3ec7fc598e48 1690 /** Array initializer of FTFA peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 1691 #define FTFA_BASE_PTRS { FTFA_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 1692
Freescale_cup 0:3ec7fc598e48 1693 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1694 -- FTFA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1695 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1696
Freescale_cup 0:3ec7fc598e48 1697 /*!
Freescale_cup 0:3ec7fc598e48 1698 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1699 * @{
Freescale_cup 0:3ec7fc598e48 1700 */
Freescale_cup 0:3ec7fc598e48 1701
Freescale_cup 0:3ec7fc598e48 1702
Freescale_cup 0:3ec7fc598e48 1703 /* FTFA - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 1704 /* FTFA */
Freescale_cup 0:3ec7fc598e48 1705 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1706 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1707 #define FTFA_FSEC FTFA_FSEC_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1708 #define FTFA_FOPT FTFA_FOPT_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1709 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1710 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1711 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1712 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1713 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1714 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1715 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1716 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1717 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1718 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1719 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1720 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1721 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1722 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1723 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1724 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1725
Freescale_cup 0:3ec7fc598e48 1726 /*!
Freescale_cup 0:3ec7fc598e48 1727 * @}
Freescale_cup 0:3ec7fc598e48 1728 */ /* end of group FTFA_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1729
Freescale_cup 0:3ec7fc598e48 1730
Freescale_cup 0:3ec7fc598e48 1731 /*!
Freescale_cup 0:3ec7fc598e48 1732 * @}
Freescale_cup 0:3ec7fc598e48 1733 */ /* end of group FTFA_Peripheral */
Freescale_cup 0:3ec7fc598e48 1734
Freescale_cup 0:3ec7fc598e48 1735
Freescale_cup 0:3ec7fc598e48 1736 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1737 -- GPIO
Freescale_cup 0:3ec7fc598e48 1738 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1739
Freescale_cup 0:3ec7fc598e48 1740 /*!
Freescale_cup 0:3ec7fc598e48 1741 * @addtogroup GPIO_Peripheral GPIO
Freescale_cup 0:3ec7fc598e48 1742 * @{
Freescale_cup 0:3ec7fc598e48 1743 */
Freescale_cup 0:3ec7fc598e48 1744
Freescale_cup 0:3ec7fc598e48 1745 /** GPIO - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 1746 typedef struct GPIO_MemMap {
Freescale_cup 0:3ec7fc598e48 1747 uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 1748 uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 1749 uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 1750 uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 1751 uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
Freescale_cup 0:3ec7fc598e48 1752 uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
Freescale_cup 0:3ec7fc598e48 1753 } volatile *GPIO_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 1754
Freescale_cup 0:3ec7fc598e48 1755 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1756 -- GPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1757 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1758
Freescale_cup 0:3ec7fc598e48 1759 /*!
Freescale_cup 0:3ec7fc598e48 1760 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1761 * @{
Freescale_cup 0:3ec7fc598e48 1762 */
Freescale_cup 0:3ec7fc598e48 1763
Freescale_cup 0:3ec7fc598e48 1764
Freescale_cup 0:3ec7fc598e48 1765 /* GPIO - Register accessors */
Freescale_cup 0:3ec7fc598e48 1766 #define GPIO_PDOR_REG(base) ((base)->PDOR)
Freescale_cup 0:3ec7fc598e48 1767 #define GPIO_PSOR_REG(base) ((base)->PSOR)
Freescale_cup 0:3ec7fc598e48 1768 #define GPIO_PCOR_REG(base) ((base)->PCOR)
Freescale_cup 0:3ec7fc598e48 1769 #define GPIO_PTOR_REG(base) ((base)->PTOR)
Freescale_cup 0:3ec7fc598e48 1770 #define GPIO_PDIR_REG(base) ((base)->PDIR)
Freescale_cup 0:3ec7fc598e48 1771 #define GPIO_PDDR_REG(base) ((base)->PDDR)
Freescale_cup 0:3ec7fc598e48 1772
Freescale_cup 0:3ec7fc598e48 1773 /*!
Freescale_cup 0:3ec7fc598e48 1774 * @}
Freescale_cup 0:3ec7fc598e48 1775 */ /* end of group GPIO_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1776
Freescale_cup 0:3ec7fc598e48 1777
Freescale_cup 0:3ec7fc598e48 1778 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1779 -- GPIO Register Masks
Freescale_cup 0:3ec7fc598e48 1780 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1781
Freescale_cup 0:3ec7fc598e48 1782 /*!
Freescale_cup 0:3ec7fc598e48 1783 * @addtogroup GPIO_Register_Masks GPIO Register Masks
Freescale_cup 0:3ec7fc598e48 1784 * @{
Freescale_cup 0:3ec7fc598e48 1785 */
Freescale_cup 0:3ec7fc598e48 1786
Freescale_cup 0:3ec7fc598e48 1787 /* PDOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1788 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1789 #define GPIO_PDOR_PDO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1790 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
Freescale_cup 0:3ec7fc598e48 1791 /* PSOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1792 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1793 #define GPIO_PSOR_PTSO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1794 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
Freescale_cup 0:3ec7fc598e48 1795 /* PCOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1796 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1797 #define GPIO_PCOR_PTCO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1798 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
Freescale_cup 0:3ec7fc598e48 1799 /* PTOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1800 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1801 #define GPIO_PTOR_PTTO_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1802 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
Freescale_cup 0:3ec7fc598e48 1803 /* PDIR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1804 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1805 #define GPIO_PDIR_PDI_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1806 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
Freescale_cup 0:3ec7fc598e48 1807 /* PDDR Bit Fields */
Freescale_cup 0:3ec7fc598e48 1808 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 1809 #define GPIO_PDDR_PDD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1810 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
Freescale_cup 0:3ec7fc598e48 1811
Freescale_cup 0:3ec7fc598e48 1812 /*!
Freescale_cup 0:3ec7fc598e48 1813 * @}
Freescale_cup 0:3ec7fc598e48 1814 */ /* end of group GPIO_Register_Masks */
Freescale_cup 0:3ec7fc598e48 1815
Freescale_cup 0:3ec7fc598e48 1816
Freescale_cup 0:3ec7fc598e48 1817 /* GPIO - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 1818 /** Peripheral PTA base pointer */
Freescale_cup 0:3ec7fc598e48 1819 #define PTA_BASE_PTR ((GPIO_MemMapPtr)0x400FF000u)
Freescale_cup 0:3ec7fc598e48 1820 /** Peripheral PTB base pointer */
Freescale_cup 0:3ec7fc598e48 1821 #define PTB_BASE_PTR ((GPIO_MemMapPtr)0x400FF040u)
Freescale_cup 0:3ec7fc598e48 1822 /** Peripheral PTC base pointer */
Freescale_cup 0:3ec7fc598e48 1823 #define PTC_BASE_PTR ((GPIO_MemMapPtr)0x400FF080u)
Freescale_cup 0:3ec7fc598e48 1824 /** Peripheral PTD base pointer */
Freescale_cup 0:3ec7fc598e48 1825 #define PTD_BASE_PTR ((GPIO_MemMapPtr)0x400FF0C0u)
Freescale_cup 0:3ec7fc598e48 1826 /** Peripheral PTE base pointer */
Freescale_cup 0:3ec7fc598e48 1827 #define PTE_BASE_PTR ((GPIO_MemMapPtr)0x400FF100u)
Freescale_cup 0:3ec7fc598e48 1828 /** Array initializer of GPIO peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 1829 #define GPIO_BASE_PTRS { PTA_BASE_PTR, PTB_BASE_PTR, PTC_BASE_PTR, PTD_BASE_PTR, PTE_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 1830
Freescale_cup 0:3ec7fc598e48 1831 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1832 -- GPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1833 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1834
Freescale_cup 0:3ec7fc598e48 1835 /*!
Freescale_cup 0:3ec7fc598e48 1836 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1837 * @{
Freescale_cup 0:3ec7fc598e48 1838 */
Freescale_cup 0:3ec7fc598e48 1839
Freescale_cup 0:3ec7fc598e48 1840
Freescale_cup 0:3ec7fc598e48 1841 /* GPIO - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 1842 /* PTA */
Freescale_cup 0:3ec7fc598e48 1843 #define GPIOA_PDOR GPIO_PDOR_REG(PTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1844 #define GPIOA_PSOR GPIO_PSOR_REG(PTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1845 #define GPIOA_PCOR GPIO_PCOR_REG(PTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1846 #define GPIOA_PTOR GPIO_PTOR_REG(PTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1847 #define GPIOA_PDIR GPIO_PDIR_REG(PTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1848 #define GPIOA_PDDR GPIO_PDDR_REG(PTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1849 /* PTB */
Freescale_cup 0:3ec7fc598e48 1850 #define GPIOB_PDOR GPIO_PDOR_REG(PTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1851 #define GPIOB_PSOR GPIO_PSOR_REG(PTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1852 #define GPIOB_PCOR GPIO_PCOR_REG(PTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1853 #define GPIOB_PTOR GPIO_PTOR_REG(PTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1854 #define GPIOB_PDIR GPIO_PDIR_REG(PTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1855 #define GPIOB_PDDR GPIO_PDDR_REG(PTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1856 /* PTC */
Freescale_cup 0:3ec7fc598e48 1857 #define GPIOC_PDOR GPIO_PDOR_REG(PTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1858 #define GPIOC_PSOR GPIO_PSOR_REG(PTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1859 #define GPIOC_PCOR GPIO_PCOR_REG(PTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1860 #define GPIOC_PTOR GPIO_PTOR_REG(PTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1861 #define GPIOC_PDIR GPIO_PDIR_REG(PTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1862 #define GPIOC_PDDR GPIO_PDDR_REG(PTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1863 /* PTD */
Freescale_cup 0:3ec7fc598e48 1864 #define GPIOD_PDOR GPIO_PDOR_REG(PTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1865 #define GPIOD_PSOR GPIO_PSOR_REG(PTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1866 #define GPIOD_PCOR GPIO_PCOR_REG(PTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1867 #define GPIOD_PTOR GPIO_PTOR_REG(PTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1868 #define GPIOD_PDIR GPIO_PDIR_REG(PTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1869 #define GPIOD_PDDR GPIO_PDDR_REG(PTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1870 /* PTE */
Freescale_cup 0:3ec7fc598e48 1871 #define GPIOE_PDOR GPIO_PDOR_REG(PTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1872 #define GPIOE_PSOR GPIO_PSOR_REG(PTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1873 #define GPIOE_PCOR GPIO_PCOR_REG(PTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1874 #define GPIOE_PTOR GPIO_PTOR_REG(PTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1875 #define GPIOE_PDIR GPIO_PDIR_REG(PTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1876 #define GPIOE_PDDR GPIO_PDDR_REG(PTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 1877
Freescale_cup 0:3ec7fc598e48 1878 /*!
Freescale_cup 0:3ec7fc598e48 1879 * @}
Freescale_cup 0:3ec7fc598e48 1880 */ /* end of group GPIO_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1881
Freescale_cup 0:3ec7fc598e48 1882
Freescale_cup 0:3ec7fc598e48 1883 /*!
Freescale_cup 0:3ec7fc598e48 1884 * @}
Freescale_cup 0:3ec7fc598e48 1885 */ /* end of group GPIO_Peripheral */
Freescale_cup 0:3ec7fc598e48 1886
Freescale_cup 0:3ec7fc598e48 1887
Freescale_cup 0:3ec7fc598e48 1888 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1889 -- I2C
Freescale_cup 0:3ec7fc598e48 1890 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1891
Freescale_cup 0:3ec7fc598e48 1892 /*!
Freescale_cup 0:3ec7fc598e48 1893 * @addtogroup I2C_Peripheral I2C
Freescale_cup 0:3ec7fc598e48 1894 * @{
Freescale_cup 0:3ec7fc598e48 1895 */
Freescale_cup 0:3ec7fc598e48 1896
Freescale_cup 0:3ec7fc598e48 1897 /** I2C - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 1898 typedef struct I2C_MemMap {
Freescale_cup 0:3ec7fc598e48 1899 uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 1900 uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 1901 uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 1902 uint8_t S; /**< I2C Status register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 1903 uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 1904 uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 1905 uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 1906 uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 1907 uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 1908 uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
Freescale_cup 0:3ec7fc598e48 1909 uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
Freescale_cup 0:3ec7fc598e48 1910 uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
Freescale_cup 0:3ec7fc598e48 1911 } volatile *I2C_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 1912
Freescale_cup 0:3ec7fc598e48 1913 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1914 -- I2C - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1915 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1916
Freescale_cup 0:3ec7fc598e48 1917 /*!
Freescale_cup 0:3ec7fc598e48 1918 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Freescale_cup 0:3ec7fc598e48 1919 * @{
Freescale_cup 0:3ec7fc598e48 1920 */
Freescale_cup 0:3ec7fc598e48 1921
Freescale_cup 0:3ec7fc598e48 1922
Freescale_cup 0:3ec7fc598e48 1923 /* I2C - Register accessors */
Freescale_cup 0:3ec7fc598e48 1924 #define I2C_A1_REG(base) ((base)->A1)
Freescale_cup 0:3ec7fc598e48 1925 #define I2C_F_REG(base) ((base)->F)
Freescale_cup 0:3ec7fc598e48 1926 #define I2C_C1_REG(base) ((base)->C1)
Freescale_cup 0:3ec7fc598e48 1927 #define I2C_S_REG(base) ((base)->S)
Freescale_cup 0:3ec7fc598e48 1928 #define I2C_D_REG(base) ((base)->D)
Freescale_cup 0:3ec7fc598e48 1929 #define I2C_C2_REG(base) ((base)->C2)
Freescale_cup 0:3ec7fc598e48 1930 #define I2C_FLT_REG(base) ((base)->FLT)
Freescale_cup 0:3ec7fc598e48 1931 #define I2C_RA_REG(base) ((base)->RA)
Freescale_cup 0:3ec7fc598e48 1932 #define I2C_SMB_REG(base) ((base)->SMB)
Freescale_cup 0:3ec7fc598e48 1933 #define I2C_A2_REG(base) ((base)->A2)
Freescale_cup 0:3ec7fc598e48 1934 #define I2C_SLTH_REG(base) ((base)->SLTH)
Freescale_cup 0:3ec7fc598e48 1935 #define I2C_SLTL_REG(base) ((base)->SLTL)
Freescale_cup 0:3ec7fc598e48 1936
Freescale_cup 0:3ec7fc598e48 1937 /*!
Freescale_cup 0:3ec7fc598e48 1938 * @}
Freescale_cup 0:3ec7fc598e48 1939 */ /* end of group I2C_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 1940
Freescale_cup 0:3ec7fc598e48 1941
Freescale_cup 0:3ec7fc598e48 1942 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 1943 -- I2C Register Masks
Freescale_cup 0:3ec7fc598e48 1944 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 1945
Freescale_cup 0:3ec7fc598e48 1946 /*!
Freescale_cup 0:3ec7fc598e48 1947 * @addtogroup I2C_Register_Masks I2C Register Masks
Freescale_cup 0:3ec7fc598e48 1948 * @{
Freescale_cup 0:3ec7fc598e48 1949 */
Freescale_cup 0:3ec7fc598e48 1950
Freescale_cup 0:3ec7fc598e48 1951 /* A1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1952 #define I2C_A1_AD_MASK 0xFEu
Freescale_cup 0:3ec7fc598e48 1953 #define I2C_A1_AD_SHIFT 1
Freescale_cup 0:3ec7fc598e48 1954 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
Freescale_cup 0:3ec7fc598e48 1955 /* F Bit Fields */
Freescale_cup 0:3ec7fc598e48 1956 #define I2C_F_ICR_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 1957 #define I2C_F_ICR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1958 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
Freescale_cup 0:3ec7fc598e48 1959 #define I2C_F_MULT_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 1960 #define I2C_F_MULT_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1961 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
Freescale_cup 0:3ec7fc598e48 1962 /* C1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 1963 #define I2C_C1_DMAEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 1964 #define I2C_C1_DMAEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1965 #define I2C_C1_WUEN_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 1966 #define I2C_C1_WUEN_SHIFT 1
Freescale_cup 0:3ec7fc598e48 1967 #define I2C_C1_RSTA_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 1968 #define I2C_C1_RSTA_SHIFT 2
Freescale_cup 0:3ec7fc598e48 1969 #define I2C_C1_TXAK_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 1970 #define I2C_C1_TXAK_SHIFT 3
Freescale_cup 0:3ec7fc598e48 1971 #define I2C_C1_TX_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 1972 #define I2C_C1_TX_SHIFT 4
Freescale_cup 0:3ec7fc598e48 1973 #define I2C_C1_MST_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 1974 #define I2C_C1_MST_SHIFT 5
Freescale_cup 0:3ec7fc598e48 1975 #define I2C_C1_IICIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 1976 #define I2C_C1_IICIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1977 #define I2C_C1_IICEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 1978 #define I2C_C1_IICEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 1979 /* S Bit Fields */
Freescale_cup 0:3ec7fc598e48 1980 #define I2C_S_RXAK_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 1981 #define I2C_S_RXAK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1982 #define I2C_S_IICIF_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 1983 #define I2C_S_IICIF_SHIFT 1
Freescale_cup 0:3ec7fc598e48 1984 #define I2C_S_SRW_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 1985 #define I2C_S_SRW_SHIFT 2
Freescale_cup 0:3ec7fc598e48 1986 #define I2C_S_RAM_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 1987 #define I2C_S_RAM_SHIFT 3
Freescale_cup 0:3ec7fc598e48 1988 #define I2C_S_ARBL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 1989 #define I2C_S_ARBL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 1990 #define I2C_S_BUSY_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 1991 #define I2C_S_BUSY_SHIFT 5
Freescale_cup 0:3ec7fc598e48 1992 #define I2C_S_IAAS_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 1993 #define I2C_S_IAAS_SHIFT 6
Freescale_cup 0:3ec7fc598e48 1994 #define I2C_S_TCF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 1995 #define I2C_S_TCF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 1996 /* D Bit Fields */
Freescale_cup 0:3ec7fc598e48 1997 #define I2C_D_DATA_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 1998 #define I2C_D_DATA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 1999 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
Freescale_cup 0:3ec7fc598e48 2000 /* C2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2001 #define I2C_C2_AD_MASK 0x7u
Freescale_cup 0:3ec7fc598e48 2002 #define I2C_C2_AD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2003 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
Freescale_cup 0:3ec7fc598e48 2004 #define I2C_C2_RMEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2005 #define I2C_C2_RMEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2006 #define I2C_C2_SBRC_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2007 #define I2C_C2_SBRC_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2008 #define I2C_C2_HDRS_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2009 #define I2C_C2_HDRS_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2010 #define I2C_C2_ADEXT_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2011 #define I2C_C2_ADEXT_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2012 #define I2C_C2_GCAEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2013 #define I2C_C2_GCAEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2014 /* FLT Bit Fields */
Freescale_cup 0:3ec7fc598e48 2015 #define I2C_FLT_FLT_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 2016 #define I2C_FLT_FLT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2017 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
Freescale_cup 0:3ec7fc598e48 2018 #define I2C_FLT_STOPIE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2019 #define I2C_FLT_STOPIE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2020 #define I2C_FLT_STOPF_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2021 #define I2C_FLT_STOPF_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2022 #define I2C_FLT_SHEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2023 #define I2C_FLT_SHEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2024 /* RA Bit Fields */
Freescale_cup 0:3ec7fc598e48 2025 #define I2C_RA_RAD_MASK 0xFEu
Freescale_cup 0:3ec7fc598e48 2026 #define I2C_RA_RAD_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2027 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
Freescale_cup 0:3ec7fc598e48 2028 /* SMB Bit Fields */
Freescale_cup 0:3ec7fc598e48 2029 #define I2C_SMB_SHTF2IE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2030 #define I2C_SMB_SHTF2IE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2031 #define I2C_SMB_SHTF2_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2032 #define I2C_SMB_SHTF2_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2033 #define I2C_SMB_SHTF1_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2034 #define I2C_SMB_SHTF1_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2035 #define I2C_SMB_SLTF_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2036 #define I2C_SMB_SLTF_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2037 #define I2C_SMB_TCKSEL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2038 #define I2C_SMB_TCKSEL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2039 #define I2C_SMB_SIICAEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2040 #define I2C_SMB_SIICAEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2041 #define I2C_SMB_ALERTEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2042 #define I2C_SMB_ALERTEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2043 #define I2C_SMB_FACK_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2044 #define I2C_SMB_FACK_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2045 /* A2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2046 #define I2C_A2_SAD_MASK 0xFEu
Freescale_cup 0:3ec7fc598e48 2047 #define I2C_A2_SAD_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2048 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
Freescale_cup 0:3ec7fc598e48 2049 /* SLTH Bit Fields */
Freescale_cup 0:3ec7fc598e48 2050 #define I2C_SLTH_SSLT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2051 #define I2C_SLTH_SSLT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2052 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
Freescale_cup 0:3ec7fc598e48 2053 /* SLTL Bit Fields */
Freescale_cup 0:3ec7fc598e48 2054 #define I2C_SLTL_SSLT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2055 #define I2C_SLTL_SSLT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2056 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
Freescale_cup 0:3ec7fc598e48 2057
Freescale_cup 0:3ec7fc598e48 2058 /*!
Freescale_cup 0:3ec7fc598e48 2059 * @}
Freescale_cup 0:3ec7fc598e48 2060 */ /* end of group I2C_Register_Masks */
Freescale_cup 0:3ec7fc598e48 2061
Freescale_cup 0:3ec7fc598e48 2062
Freescale_cup 0:3ec7fc598e48 2063 /* I2C - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 2064 /** Peripheral I2C0 base pointer */
Freescale_cup 0:3ec7fc598e48 2065 #define I2C0_BASE_PTR ((I2C_MemMapPtr)0x40066000u)
Freescale_cup 0:3ec7fc598e48 2066 /** Peripheral I2C1 base pointer */
Freescale_cup 0:3ec7fc598e48 2067 #define I2C1_BASE_PTR ((I2C_MemMapPtr)0x40067000u)
Freescale_cup 0:3ec7fc598e48 2068 /** Array initializer of I2C peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 2069 #define I2C_BASE_PTRS { I2C0_BASE_PTR, I2C1_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 2070
Freescale_cup 0:3ec7fc598e48 2071 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2072 -- I2C - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2073 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2074
Freescale_cup 0:3ec7fc598e48 2075 /*!
Freescale_cup 0:3ec7fc598e48 2076 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2077 * @{
Freescale_cup 0:3ec7fc598e48 2078 */
Freescale_cup 0:3ec7fc598e48 2079
Freescale_cup 0:3ec7fc598e48 2080
Freescale_cup 0:3ec7fc598e48 2081 /* I2C - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 2082 /* I2C0 */
Freescale_cup 0:3ec7fc598e48 2083 #define I2C0_A1 I2C_A1_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2084 #define I2C0_F I2C_F_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2085 #define I2C0_C1 I2C_C1_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2086 #define I2C0_S I2C_S_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2087 #define I2C0_D I2C_D_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2088 #define I2C0_C2 I2C_C2_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2089 #define I2C0_FLT I2C_FLT_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2090 #define I2C0_RA I2C_RA_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2091 #define I2C0_SMB I2C_SMB_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2092 #define I2C0_A2 I2C_A2_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2093 #define I2C0_SLTH I2C_SLTH_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2094 #define I2C0_SLTL I2C_SLTL_REG(I2C0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2095 /* I2C1 */
Freescale_cup 0:3ec7fc598e48 2096 #define I2C1_A1 I2C_A1_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2097 #define I2C1_F I2C_F_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2098 #define I2C1_C1 I2C_C1_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2099 #define I2C1_S I2C_S_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2100 #define I2C1_D I2C_D_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2101 #define I2C1_C2 I2C_C2_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2102 #define I2C1_FLT I2C_FLT_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2103 #define I2C1_RA I2C_RA_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2104 #define I2C1_SMB I2C_SMB_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2105 #define I2C1_A2 I2C_A2_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2106 #define I2C1_SLTH I2C_SLTH_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2107 #define I2C1_SLTL I2C_SLTL_REG(I2C1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2108
Freescale_cup 0:3ec7fc598e48 2109 /*!
Freescale_cup 0:3ec7fc598e48 2110 * @}
Freescale_cup 0:3ec7fc598e48 2111 */ /* end of group I2C_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2112
Freescale_cup 0:3ec7fc598e48 2113
Freescale_cup 0:3ec7fc598e48 2114 /*!
Freescale_cup 0:3ec7fc598e48 2115 * @}
Freescale_cup 0:3ec7fc598e48 2116 */ /* end of group I2C_Peripheral */
Freescale_cup 0:3ec7fc598e48 2117
Freescale_cup 0:3ec7fc598e48 2118
Freescale_cup 0:3ec7fc598e48 2119 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2120 -- LLWU
Freescale_cup 0:3ec7fc598e48 2121 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2122
Freescale_cup 0:3ec7fc598e48 2123 /*!
Freescale_cup 0:3ec7fc598e48 2124 * @addtogroup LLWU_Peripheral LLWU
Freescale_cup 0:3ec7fc598e48 2125 * @{
Freescale_cup 0:3ec7fc598e48 2126 */
Freescale_cup 0:3ec7fc598e48 2127
Freescale_cup 0:3ec7fc598e48 2128 /** LLWU - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 2129 typedef struct LLWU_MemMap {
Freescale_cup 0:3ec7fc598e48 2130 uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 2131 uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 2132 uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 2133 uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 2134 uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 2135 uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 2136 uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 2137 uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 2138 uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 2139 uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
Freescale_cup 0:3ec7fc598e48 2140 } volatile *LLWU_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 2141
Freescale_cup 0:3ec7fc598e48 2142 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2143 -- LLWU - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2144 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2145
Freescale_cup 0:3ec7fc598e48 2146 /*!
Freescale_cup 0:3ec7fc598e48 2147 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2148 * @{
Freescale_cup 0:3ec7fc598e48 2149 */
Freescale_cup 0:3ec7fc598e48 2150
Freescale_cup 0:3ec7fc598e48 2151
Freescale_cup 0:3ec7fc598e48 2152 /* LLWU - Register accessors */
Freescale_cup 0:3ec7fc598e48 2153 #define LLWU_PE1_REG(base) ((base)->PE1)
Freescale_cup 0:3ec7fc598e48 2154 #define LLWU_PE2_REG(base) ((base)->PE2)
Freescale_cup 0:3ec7fc598e48 2155 #define LLWU_PE3_REG(base) ((base)->PE3)
Freescale_cup 0:3ec7fc598e48 2156 #define LLWU_PE4_REG(base) ((base)->PE4)
Freescale_cup 0:3ec7fc598e48 2157 #define LLWU_ME_REG(base) ((base)->ME)
Freescale_cup 0:3ec7fc598e48 2158 #define LLWU_F1_REG(base) ((base)->F1)
Freescale_cup 0:3ec7fc598e48 2159 #define LLWU_F2_REG(base) ((base)->F2)
Freescale_cup 0:3ec7fc598e48 2160 #define LLWU_F3_REG(base) ((base)->F3)
Freescale_cup 0:3ec7fc598e48 2161 #define LLWU_FILT1_REG(base) ((base)->FILT1)
Freescale_cup 0:3ec7fc598e48 2162 #define LLWU_FILT2_REG(base) ((base)->FILT2)
Freescale_cup 0:3ec7fc598e48 2163
Freescale_cup 0:3ec7fc598e48 2164 /*!
Freescale_cup 0:3ec7fc598e48 2165 * @}
Freescale_cup 0:3ec7fc598e48 2166 */ /* end of group LLWU_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2167
Freescale_cup 0:3ec7fc598e48 2168
Freescale_cup 0:3ec7fc598e48 2169 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2170 -- LLWU Register Masks
Freescale_cup 0:3ec7fc598e48 2171 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2172
Freescale_cup 0:3ec7fc598e48 2173 /*!
Freescale_cup 0:3ec7fc598e48 2174 * @addtogroup LLWU_Register_Masks LLWU Register Masks
Freescale_cup 0:3ec7fc598e48 2175 * @{
Freescale_cup 0:3ec7fc598e48 2176 */
Freescale_cup 0:3ec7fc598e48 2177
Freescale_cup 0:3ec7fc598e48 2178 /* PE1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2179 #define LLWU_PE1_WUPE0_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 2180 #define LLWU_PE1_WUPE0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2181 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
Freescale_cup 0:3ec7fc598e48 2182 #define LLWU_PE1_WUPE1_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 2183 #define LLWU_PE1_WUPE1_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2184 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
Freescale_cup 0:3ec7fc598e48 2185 #define LLWU_PE1_WUPE2_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 2186 #define LLWU_PE1_WUPE2_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2187 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
Freescale_cup 0:3ec7fc598e48 2188 #define LLWU_PE1_WUPE3_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 2189 #define LLWU_PE1_WUPE3_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2190 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
Freescale_cup 0:3ec7fc598e48 2191 /* PE2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2192 #define LLWU_PE2_WUPE4_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 2193 #define LLWU_PE2_WUPE4_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2194 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
Freescale_cup 0:3ec7fc598e48 2195 #define LLWU_PE2_WUPE5_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 2196 #define LLWU_PE2_WUPE5_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2197 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
Freescale_cup 0:3ec7fc598e48 2198 #define LLWU_PE2_WUPE6_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 2199 #define LLWU_PE2_WUPE6_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2200 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
Freescale_cup 0:3ec7fc598e48 2201 #define LLWU_PE2_WUPE7_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 2202 #define LLWU_PE2_WUPE7_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2203 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
Freescale_cup 0:3ec7fc598e48 2204 /* PE3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2205 #define LLWU_PE3_WUPE8_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 2206 #define LLWU_PE3_WUPE8_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2207 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
Freescale_cup 0:3ec7fc598e48 2208 #define LLWU_PE3_WUPE9_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 2209 #define LLWU_PE3_WUPE9_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2210 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
Freescale_cup 0:3ec7fc598e48 2211 #define LLWU_PE3_WUPE10_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 2212 #define LLWU_PE3_WUPE10_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2213 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
Freescale_cup 0:3ec7fc598e48 2214 #define LLWU_PE3_WUPE11_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 2215 #define LLWU_PE3_WUPE11_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2216 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
Freescale_cup 0:3ec7fc598e48 2217 /* PE4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2218 #define LLWU_PE4_WUPE12_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 2219 #define LLWU_PE4_WUPE12_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2220 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
Freescale_cup 0:3ec7fc598e48 2221 #define LLWU_PE4_WUPE13_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 2222 #define LLWU_PE4_WUPE13_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2223 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
Freescale_cup 0:3ec7fc598e48 2224 #define LLWU_PE4_WUPE14_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 2225 #define LLWU_PE4_WUPE14_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2226 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
Freescale_cup 0:3ec7fc598e48 2227 #define LLWU_PE4_WUPE15_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 2228 #define LLWU_PE4_WUPE15_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2229 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
Freescale_cup 0:3ec7fc598e48 2230 /* ME Bit Fields */
Freescale_cup 0:3ec7fc598e48 2231 #define LLWU_ME_WUME0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2232 #define LLWU_ME_WUME0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2233 #define LLWU_ME_WUME1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2234 #define LLWU_ME_WUME1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2235 #define LLWU_ME_WUME2_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2236 #define LLWU_ME_WUME2_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2237 #define LLWU_ME_WUME3_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2238 #define LLWU_ME_WUME3_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2239 #define LLWU_ME_WUME4_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2240 #define LLWU_ME_WUME4_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2241 #define LLWU_ME_WUME5_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2242 #define LLWU_ME_WUME5_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2243 #define LLWU_ME_WUME6_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2244 #define LLWU_ME_WUME6_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2245 #define LLWU_ME_WUME7_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2246 #define LLWU_ME_WUME7_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2247 /* F1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2248 #define LLWU_F1_WUF0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2249 #define LLWU_F1_WUF0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2250 #define LLWU_F1_WUF1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2251 #define LLWU_F1_WUF1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2252 #define LLWU_F1_WUF2_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2253 #define LLWU_F1_WUF2_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2254 #define LLWU_F1_WUF3_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2255 #define LLWU_F1_WUF3_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2256 #define LLWU_F1_WUF4_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2257 #define LLWU_F1_WUF4_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2258 #define LLWU_F1_WUF5_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2259 #define LLWU_F1_WUF5_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2260 #define LLWU_F1_WUF6_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2261 #define LLWU_F1_WUF6_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2262 #define LLWU_F1_WUF7_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2263 #define LLWU_F1_WUF7_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2264 /* F2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2265 #define LLWU_F2_WUF8_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2266 #define LLWU_F2_WUF8_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2267 #define LLWU_F2_WUF9_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2268 #define LLWU_F2_WUF9_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2269 #define LLWU_F2_WUF10_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2270 #define LLWU_F2_WUF10_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2271 #define LLWU_F2_WUF11_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2272 #define LLWU_F2_WUF11_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2273 #define LLWU_F2_WUF12_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2274 #define LLWU_F2_WUF12_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2275 #define LLWU_F2_WUF13_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2276 #define LLWU_F2_WUF13_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2277 #define LLWU_F2_WUF14_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2278 #define LLWU_F2_WUF14_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2279 #define LLWU_F2_WUF15_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2280 #define LLWU_F2_WUF15_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2281 /* F3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2282 #define LLWU_F3_MWUF0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2283 #define LLWU_F3_MWUF0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2284 #define LLWU_F3_MWUF1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2285 #define LLWU_F3_MWUF1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2286 #define LLWU_F3_MWUF2_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2287 #define LLWU_F3_MWUF2_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2288 #define LLWU_F3_MWUF3_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2289 #define LLWU_F3_MWUF3_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2290 #define LLWU_F3_MWUF4_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2291 #define LLWU_F3_MWUF4_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2292 #define LLWU_F3_MWUF5_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2293 #define LLWU_F3_MWUF5_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2294 #define LLWU_F3_MWUF6_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2295 #define LLWU_F3_MWUF6_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2296 #define LLWU_F3_MWUF7_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2297 #define LLWU_F3_MWUF7_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2298 /* FILT1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2299 #define LLWU_FILT1_FILTSEL_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 2300 #define LLWU_FILT1_FILTSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2301 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
Freescale_cup 0:3ec7fc598e48 2302 #define LLWU_FILT1_FILTE_MASK 0x60u
Freescale_cup 0:3ec7fc598e48 2303 #define LLWU_FILT1_FILTE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2304 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
Freescale_cup 0:3ec7fc598e48 2305 #define LLWU_FILT1_FILTF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2306 #define LLWU_FILT1_FILTF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2307 /* FILT2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2308 #define LLWU_FILT2_FILTSEL_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 2309 #define LLWU_FILT2_FILTSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2310 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
Freescale_cup 0:3ec7fc598e48 2311 #define LLWU_FILT2_FILTE_MASK 0x60u
Freescale_cup 0:3ec7fc598e48 2312 #define LLWU_FILT2_FILTE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2313 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
Freescale_cup 0:3ec7fc598e48 2314 #define LLWU_FILT2_FILTF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2315 #define LLWU_FILT2_FILTF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2316
Freescale_cup 0:3ec7fc598e48 2317 /*!
Freescale_cup 0:3ec7fc598e48 2318 * @}
Freescale_cup 0:3ec7fc598e48 2319 */ /* end of group LLWU_Register_Masks */
Freescale_cup 0:3ec7fc598e48 2320
Freescale_cup 0:3ec7fc598e48 2321
Freescale_cup 0:3ec7fc598e48 2322 /* LLWU - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 2323 /** Peripheral LLWU base pointer */
Freescale_cup 0:3ec7fc598e48 2324 #define LLWU_BASE_PTR ((LLWU_MemMapPtr)0x4007C000u)
Freescale_cup 0:3ec7fc598e48 2325 /** Array initializer of LLWU peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 2326 #define LLWU_BASE_PTRS { LLWU_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 2327
Freescale_cup 0:3ec7fc598e48 2328 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2329 -- LLWU - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2330 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2331
Freescale_cup 0:3ec7fc598e48 2332 /*!
Freescale_cup 0:3ec7fc598e48 2333 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2334 * @{
Freescale_cup 0:3ec7fc598e48 2335 */
Freescale_cup 0:3ec7fc598e48 2336
Freescale_cup 0:3ec7fc598e48 2337
Freescale_cup 0:3ec7fc598e48 2338 /* LLWU - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 2339 /* LLWU */
Freescale_cup 0:3ec7fc598e48 2340 #define LLWU_PE1 LLWU_PE1_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2341 #define LLWU_PE2 LLWU_PE2_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2342 #define LLWU_PE3 LLWU_PE3_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2343 #define LLWU_PE4 LLWU_PE4_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2344 #define LLWU_ME LLWU_ME_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2345 #define LLWU_F1 LLWU_F1_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2346 #define LLWU_F2 LLWU_F2_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2347 #define LLWU_F3 LLWU_F3_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2348 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2349 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2350
Freescale_cup 0:3ec7fc598e48 2351 /*!
Freescale_cup 0:3ec7fc598e48 2352 * @}
Freescale_cup 0:3ec7fc598e48 2353 */ /* end of group LLWU_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2354
Freescale_cup 0:3ec7fc598e48 2355
Freescale_cup 0:3ec7fc598e48 2356 /*!
Freescale_cup 0:3ec7fc598e48 2357 * @}
Freescale_cup 0:3ec7fc598e48 2358 */ /* end of group LLWU_Peripheral */
Freescale_cup 0:3ec7fc598e48 2359
Freescale_cup 0:3ec7fc598e48 2360
Freescale_cup 0:3ec7fc598e48 2361 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2362 -- LPTMR
Freescale_cup 0:3ec7fc598e48 2363 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2364
Freescale_cup 0:3ec7fc598e48 2365 /*!
Freescale_cup 0:3ec7fc598e48 2366 * @addtogroup LPTMR_Peripheral LPTMR
Freescale_cup 0:3ec7fc598e48 2367 * @{
Freescale_cup 0:3ec7fc598e48 2368 */
Freescale_cup 0:3ec7fc598e48 2369
Freescale_cup 0:3ec7fc598e48 2370 /** LPTMR - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 2371 typedef struct LPTMR_MemMap {
Freescale_cup 0:3ec7fc598e48 2372 uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 2373 uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 2374 uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 2375 uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 2376 } volatile *LPTMR_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 2377
Freescale_cup 0:3ec7fc598e48 2378 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2379 -- LPTMR - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2380 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2381
Freescale_cup 0:3ec7fc598e48 2382 /*!
Freescale_cup 0:3ec7fc598e48 2383 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2384 * @{
Freescale_cup 0:3ec7fc598e48 2385 */
Freescale_cup 0:3ec7fc598e48 2386
Freescale_cup 0:3ec7fc598e48 2387
Freescale_cup 0:3ec7fc598e48 2388 /* LPTMR - Register accessors */
Freescale_cup 0:3ec7fc598e48 2389 #define LPTMR_CSR_REG(base) ((base)->CSR)
Freescale_cup 0:3ec7fc598e48 2390 #define LPTMR_PSR_REG(base) ((base)->PSR)
Freescale_cup 0:3ec7fc598e48 2391 #define LPTMR_CMR_REG(base) ((base)->CMR)
Freescale_cup 0:3ec7fc598e48 2392 #define LPTMR_CNR_REG(base) ((base)->CNR)
Freescale_cup 0:3ec7fc598e48 2393
Freescale_cup 0:3ec7fc598e48 2394 /*!
Freescale_cup 0:3ec7fc598e48 2395 * @}
Freescale_cup 0:3ec7fc598e48 2396 */ /* end of group LPTMR_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2397
Freescale_cup 0:3ec7fc598e48 2398
Freescale_cup 0:3ec7fc598e48 2399 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2400 -- LPTMR Register Masks
Freescale_cup 0:3ec7fc598e48 2401 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2402
Freescale_cup 0:3ec7fc598e48 2403 /*!
Freescale_cup 0:3ec7fc598e48 2404 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Freescale_cup 0:3ec7fc598e48 2405 * @{
Freescale_cup 0:3ec7fc598e48 2406 */
Freescale_cup 0:3ec7fc598e48 2407
Freescale_cup 0:3ec7fc598e48 2408 /* CSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 2409 #define LPTMR_CSR_TEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2410 #define LPTMR_CSR_TEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2411 #define LPTMR_CSR_TMS_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2412 #define LPTMR_CSR_TMS_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2413 #define LPTMR_CSR_TFC_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2414 #define LPTMR_CSR_TFC_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2415 #define LPTMR_CSR_TPP_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2416 #define LPTMR_CSR_TPP_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2417 #define LPTMR_CSR_TPS_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 2418 #define LPTMR_CSR_TPS_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2419 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
Freescale_cup 0:3ec7fc598e48 2420 #define LPTMR_CSR_TIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2421 #define LPTMR_CSR_TIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2422 #define LPTMR_CSR_TCF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2423 #define LPTMR_CSR_TCF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2424 /* PSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 2425 #define LPTMR_PSR_PCS_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 2426 #define LPTMR_PSR_PCS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2427 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
Freescale_cup 0:3ec7fc598e48 2428 #define LPTMR_PSR_PBYP_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2429 #define LPTMR_PSR_PBYP_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2430 #define LPTMR_PSR_PRESCALE_MASK 0x78u
Freescale_cup 0:3ec7fc598e48 2431 #define LPTMR_PSR_PRESCALE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2432 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
Freescale_cup 0:3ec7fc598e48 2433 /* CMR Bit Fields */
Freescale_cup 0:3ec7fc598e48 2434 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 2435 #define LPTMR_CMR_COMPARE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2436 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
Freescale_cup 0:3ec7fc598e48 2437 /* CNR Bit Fields */
Freescale_cup 0:3ec7fc598e48 2438 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 2439 #define LPTMR_CNR_COUNTER_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2440 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
Freescale_cup 0:3ec7fc598e48 2441
Freescale_cup 0:3ec7fc598e48 2442 /*!
Freescale_cup 0:3ec7fc598e48 2443 * @}
Freescale_cup 0:3ec7fc598e48 2444 */ /* end of group LPTMR_Register_Masks */
Freescale_cup 0:3ec7fc598e48 2445
Freescale_cup 0:3ec7fc598e48 2446
Freescale_cup 0:3ec7fc598e48 2447 /* LPTMR - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 2448 /** Peripheral LPTMR0 base pointer */
Freescale_cup 0:3ec7fc598e48 2449 #define LPTMR0_BASE_PTR ((LPTMR_MemMapPtr)0x40040000u)
Freescale_cup 0:3ec7fc598e48 2450 /** Array initializer of LPTMR peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 2451 #define LPTMR_BASE_PTRS { LPTMR0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 2452
Freescale_cup 0:3ec7fc598e48 2453 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2454 -- LPTMR - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2455 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2456
Freescale_cup 0:3ec7fc598e48 2457 /*!
Freescale_cup 0:3ec7fc598e48 2458 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2459 * @{
Freescale_cup 0:3ec7fc598e48 2460 */
Freescale_cup 0:3ec7fc598e48 2461
Freescale_cup 0:3ec7fc598e48 2462
Freescale_cup 0:3ec7fc598e48 2463 /* LPTMR - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 2464 /* LPTMR0 */
Freescale_cup 0:3ec7fc598e48 2465 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2466 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2467 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2468 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2469
Freescale_cup 0:3ec7fc598e48 2470 /*!
Freescale_cup 0:3ec7fc598e48 2471 * @}
Freescale_cup 0:3ec7fc598e48 2472 */ /* end of group LPTMR_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2473
Freescale_cup 0:3ec7fc598e48 2474
Freescale_cup 0:3ec7fc598e48 2475 /*!
Freescale_cup 0:3ec7fc598e48 2476 * @}
Freescale_cup 0:3ec7fc598e48 2477 */ /* end of group LPTMR_Peripheral */
Freescale_cup 0:3ec7fc598e48 2478
Freescale_cup 0:3ec7fc598e48 2479
Freescale_cup 0:3ec7fc598e48 2480 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2481 -- MCG
Freescale_cup 0:3ec7fc598e48 2482 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2483
Freescale_cup 0:3ec7fc598e48 2484 /*!
Freescale_cup 0:3ec7fc598e48 2485 * @addtogroup MCG_Peripheral MCG
Freescale_cup 0:3ec7fc598e48 2486 * @{
Freescale_cup 0:3ec7fc598e48 2487 */
Freescale_cup 0:3ec7fc598e48 2488
Freescale_cup 0:3ec7fc598e48 2489 /** MCG - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 2490 typedef struct MCG_MemMap {
Freescale_cup 0:3ec7fc598e48 2491 uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 2492 uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 2493 uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 2494 uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 2495 uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 2496 uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 2497 uint8_t S; /**< MCG Status Register, offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 2498 uint8_t RESERVED_0[1];
Freescale_cup 0:3ec7fc598e48 2499 uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 2500 uint8_t RESERVED_1[1];
Freescale_cup 0:3ec7fc598e48 2501 uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
Freescale_cup 0:3ec7fc598e48 2502 uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
Freescale_cup 0:3ec7fc598e48 2503 uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 2504 uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
Freescale_cup 0:3ec7fc598e48 2505 uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
Freescale_cup 0:3ec7fc598e48 2506 uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
Freescale_cup 0:3ec7fc598e48 2507 } volatile *MCG_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 2508
Freescale_cup 0:3ec7fc598e48 2509 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2510 -- MCG - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2511 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2512
Freescale_cup 0:3ec7fc598e48 2513 /*!
Freescale_cup 0:3ec7fc598e48 2514 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2515 * @{
Freescale_cup 0:3ec7fc598e48 2516 */
Freescale_cup 0:3ec7fc598e48 2517
Freescale_cup 0:3ec7fc598e48 2518
Freescale_cup 0:3ec7fc598e48 2519 /* MCG - Register accessors */
Freescale_cup 0:3ec7fc598e48 2520 #define MCG_C1_REG(base) ((base)->C1)
Freescale_cup 0:3ec7fc598e48 2521 #define MCG_C2_REG(base) ((base)->C2)
Freescale_cup 0:3ec7fc598e48 2522 #define MCG_C3_REG(base) ((base)->C3)
Freescale_cup 0:3ec7fc598e48 2523 #define MCG_C4_REG(base) ((base)->C4)
Freescale_cup 0:3ec7fc598e48 2524 #define MCG_C5_REG(base) ((base)->C5)
Freescale_cup 0:3ec7fc598e48 2525 #define MCG_C6_REG(base) ((base)->C6)
Freescale_cup 0:3ec7fc598e48 2526 #define MCG_S_REG(base) ((base)->S)
Freescale_cup 0:3ec7fc598e48 2527 #define MCG_SC_REG(base) ((base)->SC)
Freescale_cup 0:3ec7fc598e48 2528 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
Freescale_cup 0:3ec7fc598e48 2529 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
Freescale_cup 0:3ec7fc598e48 2530 #define MCG_C7_REG(base) ((base)->C7)
Freescale_cup 0:3ec7fc598e48 2531 #define MCG_C8_REG(base) ((base)->C8)
Freescale_cup 0:3ec7fc598e48 2532 #define MCG_C9_REG(base) ((base)->C9)
Freescale_cup 0:3ec7fc598e48 2533 #define MCG_C10_REG(base) ((base)->C10)
Freescale_cup 0:3ec7fc598e48 2534
Freescale_cup 0:3ec7fc598e48 2535 /*!
Freescale_cup 0:3ec7fc598e48 2536 * @}
Freescale_cup 0:3ec7fc598e48 2537 */ /* end of group MCG_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2538
Freescale_cup 0:3ec7fc598e48 2539
Freescale_cup 0:3ec7fc598e48 2540 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2541 -- MCG Register Masks
Freescale_cup 0:3ec7fc598e48 2542 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2543
Freescale_cup 0:3ec7fc598e48 2544 /*!
Freescale_cup 0:3ec7fc598e48 2545 * @addtogroup MCG_Register_Masks MCG Register Masks
Freescale_cup 0:3ec7fc598e48 2546 * @{
Freescale_cup 0:3ec7fc598e48 2547 */
Freescale_cup 0:3ec7fc598e48 2548
Freescale_cup 0:3ec7fc598e48 2549 /* C1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2550 #define MCG_C1_IREFSTEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2551 #define MCG_C1_IREFSTEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2552 #define MCG_C1_IRCLKEN_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2553 #define MCG_C1_IRCLKEN_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2554 #define MCG_C1_IREFS_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2555 #define MCG_C1_IREFS_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2556 #define MCG_C1_FRDIV_MASK 0x38u
Freescale_cup 0:3ec7fc598e48 2557 #define MCG_C1_FRDIV_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2558 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
Freescale_cup 0:3ec7fc598e48 2559 #define MCG_C1_CLKS_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 2560 #define MCG_C1_CLKS_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2561 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
Freescale_cup 0:3ec7fc598e48 2562 /* C2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2563 #define MCG_C2_IRCS_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2564 #define MCG_C2_IRCS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2565 #define MCG_C2_LP_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2566 #define MCG_C2_LP_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2567 #define MCG_C2_EREFS0_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2568 #define MCG_C2_EREFS0_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2569 #define MCG_C2_HGO0_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2570 #define MCG_C2_HGO0_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2571 #define MCG_C2_RANGE0_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 2572 #define MCG_C2_RANGE0_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2573 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
Freescale_cup 0:3ec7fc598e48 2574 #define MCG_C2_LOCRE0_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2575 #define MCG_C2_LOCRE0_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2576 /* C3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2577 #define MCG_C3_SCTRIM_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2578 #define MCG_C3_SCTRIM_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2579 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
Freescale_cup 0:3ec7fc598e48 2580 /* C4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2581 #define MCG_C4_SCFTRIM_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2582 #define MCG_C4_SCFTRIM_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2583 #define MCG_C4_FCTRIM_MASK 0x1Eu
Freescale_cup 0:3ec7fc598e48 2584 #define MCG_C4_FCTRIM_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2585 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
Freescale_cup 0:3ec7fc598e48 2586 #define MCG_C4_DRST_DRS_MASK 0x60u
Freescale_cup 0:3ec7fc598e48 2587 #define MCG_C4_DRST_DRS_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2588 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
Freescale_cup 0:3ec7fc598e48 2589 #define MCG_C4_DMX32_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2590 #define MCG_C4_DMX32_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2591 /* C5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2592 #define MCG_C5_PRDIV0_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 2593 #define MCG_C5_PRDIV0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2594 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
Freescale_cup 0:3ec7fc598e48 2595 #define MCG_C5_PLLSTEN0_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2596 #define MCG_C5_PLLSTEN0_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2597 #define MCG_C5_PLLCLKEN0_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2598 #define MCG_C5_PLLCLKEN0_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2599 /* C6 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2600 #define MCG_C6_VDIV0_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 2601 #define MCG_C6_VDIV0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2602 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
Freescale_cup 0:3ec7fc598e48 2603 #define MCG_C6_CME0_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2604 #define MCG_C6_CME0_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2605 #define MCG_C6_PLLS_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2606 #define MCG_C6_PLLS_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2607 #define MCG_C6_LOLIE0_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2608 #define MCG_C6_LOLIE0_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2609 /* S Bit Fields */
Freescale_cup 0:3ec7fc598e48 2610 #define MCG_S_IRCST_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2611 #define MCG_S_IRCST_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2612 #define MCG_S_OSCINIT0_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2613 #define MCG_S_OSCINIT0_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2614 #define MCG_S_CLKST_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 2615 #define MCG_S_CLKST_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2616 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
Freescale_cup 0:3ec7fc598e48 2617 #define MCG_S_IREFST_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2618 #define MCG_S_IREFST_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2619 #define MCG_S_PLLST_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2620 #define MCG_S_PLLST_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2621 #define MCG_S_LOCK0_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2622 #define MCG_S_LOCK0_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2623 #define MCG_S_LOLS0_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2624 #define MCG_S_LOLS0_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2625 /* SC Bit Fields */
Freescale_cup 0:3ec7fc598e48 2626 #define MCG_SC_LOCS0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2627 #define MCG_SC_LOCS0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2628 #define MCG_SC_FCRDIV_MASK 0xEu
Freescale_cup 0:3ec7fc598e48 2629 #define MCG_SC_FCRDIV_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2630 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
Freescale_cup 0:3ec7fc598e48 2631 #define MCG_SC_FLTPRSRV_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 2632 #define MCG_SC_FLTPRSRV_SHIFT 4
Freescale_cup 0:3ec7fc598e48 2633 #define MCG_SC_ATMF_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2634 #define MCG_SC_ATMF_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2635 #define MCG_SC_ATMS_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2636 #define MCG_SC_ATMS_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2637 #define MCG_SC_ATME_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2638 #define MCG_SC_ATME_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2639 /* ATCVH Bit Fields */
Freescale_cup 0:3ec7fc598e48 2640 #define MCG_ATCVH_ATCVH_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2641 #define MCG_ATCVH_ATCVH_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2642 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
Freescale_cup 0:3ec7fc598e48 2643 /* ATCVL Bit Fields */
Freescale_cup 0:3ec7fc598e48 2644 #define MCG_ATCVL_ATCVL_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2645 #define MCG_ATCVL_ATCVL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2646 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
Freescale_cup 0:3ec7fc598e48 2647 /* C8 Bit Fields */
Freescale_cup 0:3ec7fc598e48 2648 #define MCG_C8_LOLRE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2649 #define MCG_C8_LOLRE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2650
Freescale_cup 0:3ec7fc598e48 2651 /*!
Freescale_cup 0:3ec7fc598e48 2652 * @}
Freescale_cup 0:3ec7fc598e48 2653 */ /* end of group MCG_Register_Masks */
Freescale_cup 0:3ec7fc598e48 2654
Freescale_cup 0:3ec7fc598e48 2655
Freescale_cup 0:3ec7fc598e48 2656 /* MCG - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 2657 /** Peripheral MCG base pointer */
Freescale_cup 0:3ec7fc598e48 2658 #define MCG_BASE_PTR ((MCG_MemMapPtr)0x40064000u)
Freescale_cup 0:3ec7fc598e48 2659 /** Array initializer of MCG peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 2660 #define MCG_BASE_PTRS { MCG_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 2661
Freescale_cup 0:3ec7fc598e48 2662 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2663 -- MCG - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2664 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2665
Freescale_cup 0:3ec7fc598e48 2666 /*!
Freescale_cup 0:3ec7fc598e48 2667 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2668 * @{
Freescale_cup 0:3ec7fc598e48 2669 */
Freescale_cup 0:3ec7fc598e48 2670
Freescale_cup 0:3ec7fc598e48 2671
Freescale_cup 0:3ec7fc598e48 2672 /* MCG - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 2673 /* MCG */
Freescale_cup 0:3ec7fc598e48 2674 #define MCG_C1 MCG_C1_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2675 #define MCG_C2 MCG_C2_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2676 #define MCG_C3 MCG_C3_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2677 #define MCG_C4 MCG_C4_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2678 #define MCG_C5 MCG_C5_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2679 #define MCG_C6 MCG_C6_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2680 #define MCG_S MCG_S_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2681 #define MCG_SC MCG_SC_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2682 #define MCG_ATCVH MCG_ATCVH_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2683 #define MCG_ATCVL MCG_ATCVL_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2684 #define MCG_C7 MCG_C7_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2685 #define MCG_C8 MCG_C8_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2686 #define MCG_C9 MCG_C9_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2687 #define MCG_C10 MCG_C10_REG(MCG_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2688
Freescale_cup 0:3ec7fc598e48 2689 /*!
Freescale_cup 0:3ec7fc598e48 2690 * @}
Freescale_cup 0:3ec7fc598e48 2691 */ /* end of group MCG_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2692
Freescale_cup 0:3ec7fc598e48 2693
Freescale_cup 0:3ec7fc598e48 2694 /*!
Freescale_cup 0:3ec7fc598e48 2695 * @}
Freescale_cup 0:3ec7fc598e48 2696 */ /* end of group MCG_Peripheral */
Freescale_cup 0:3ec7fc598e48 2697
Freescale_cup 0:3ec7fc598e48 2698
Freescale_cup 0:3ec7fc598e48 2699 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2700 -- MCM
Freescale_cup 0:3ec7fc598e48 2701 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2702
Freescale_cup 0:3ec7fc598e48 2703 /*!
Freescale_cup 0:3ec7fc598e48 2704 * @addtogroup MCM_Peripheral MCM
Freescale_cup 0:3ec7fc598e48 2705 * @{
Freescale_cup 0:3ec7fc598e48 2706 */
Freescale_cup 0:3ec7fc598e48 2707
Freescale_cup 0:3ec7fc598e48 2708 /** MCM - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 2709 typedef struct MCM_MemMap {
Freescale_cup 0:3ec7fc598e48 2710 uint8_t RESERVED_0[8];
Freescale_cup 0:3ec7fc598e48 2711 uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 2712 uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
Freescale_cup 0:3ec7fc598e48 2713 uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 2714 uint8_t RESERVED_1[48];
Freescale_cup 0:3ec7fc598e48 2715 uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
Freescale_cup 0:3ec7fc598e48 2716 } volatile *MCM_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 2717
Freescale_cup 0:3ec7fc598e48 2718 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2719 -- MCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2720 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2721
Freescale_cup 0:3ec7fc598e48 2722 /*!
Freescale_cup 0:3ec7fc598e48 2723 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2724 * @{
Freescale_cup 0:3ec7fc598e48 2725 */
Freescale_cup 0:3ec7fc598e48 2726
Freescale_cup 0:3ec7fc598e48 2727
Freescale_cup 0:3ec7fc598e48 2728 /* MCM - Register accessors */
Freescale_cup 0:3ec7fc598e48 2729 #define MCM_PLASC_REG(base) ((base)->PLASC)
Freescale_cup 0:3ec7fc598e48 2730 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
Freescale_cup 0:3ec7fc598e48 2731 #define MCM_PLACR_REG(base) ((base)->PLACR)
Freescale_cup 0:3ec7fc598e48 2732 #define MCM_CPO_REG(base) ((base)->CPO)
Freescale_cup 0:3ec7fc598e48 2733
Freescale_cup 0:3ec7fc598e48 2734 /*!
Freescale_cup 0:3ec7fc598e48 2735 * @}
Freescale_cup 0:3ec7fc598e48 2736 */ /* end of group MCM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2737
Freescale_cup 0:3ec7fc598e48 2738
Freescale_cup 0:3ec7fc598e48 2739 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2740 -- MCM Register Masks
Freescale_cup 0:3ec7fc598e48 2741 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2742
Freescale_cup 0:3ec7fc598e48 2743 /*!
Freescale_cup 0:3ec7fc598e48 2744 * @addtogroup MCM_Register_Masks MCM Register Masks
Freescale_cup 0:3ec7fc598e48 2745 * @{
Freescale_cup 0:3ec7fc598e48 2746 */
Freescale_cup 0:3ec7fc598e48 2747
Freescale_cup 0:3ec7fc598e48 2748 /* PLASC Bit Fields */
Freescale_cup 0:3ec7fc598e48 2749 #define MCM_PLASC_ASC_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2750 #define MCM_PLASC_ASC_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2751 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
Freescale_cup 0:3ec7fc598e48 2752 /* PLAMC Bit Fields */
Freescale_cup 0:3ec7fc598e48 2753 #define MCM_PLAMC_AMC_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 2754 #define MCM_PLAMC_AMC_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2755 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
Freescale_cup 0:3ec7fc598e48 2756 /* PLACR Bit Fields */
Freescale_cup 0:3ec7fc598e48 2757 #define MCM_PLACR_ARB_MASK 0x200u
Freescale_cup 0:3ec7fc598e48 2758 #define MCM_PLACR_ARB_SHIFT 9
Freescale_cup 0:3ec7fc598e48 2759 #define MCM_PLACR_CFCC_MASK 0x400u
Freescale_cup 0:3ec7fc598e48 2760 #define MCM_PLACR_CFCC_SHIFT 10
Freescale_cup 0:3ec7fc598e48 2761 #define MCM_PLACR_DFCDA_MASK 0x800u
Freescale_cup 0:3ec7fc598e48 2762 #define MCM_PLACR_DFCDA_SHIFT 11
Freescale_cup 0:3ec7fc598e48 2763 #define MCM_PLACR_DFCIC_MASK 0x1000u
Freescale_cup 0:3ec7fc598e48 2764 #define MCM_PLACR_DFCIC_SHIFT 12
Freescale_cup 0:3ec7fc598e48 2765 #define MCM_PLACR_DFCC_MASK 0x2000u
Freescale_cup 0:3ec7fc598e48 2766 #define MCM_PLACR_DFCC_SHIFT 13
Freescale_cup 0:3ec7fc598e48 2767 #define MCM_PLACR_EFDS_MASK 0x4000u
Freescale_cup 0:3ec7fc598e48 2768 #define MCM_PLACR_EFDS_SHIFT 14
Freescale_cup 0:3ec7fc598e48 2769 #define MCM_PLACR_DFCS_MASK 0x8000u
Freescale_cup 0:3ec7fc598e48 2770 #define MCM_PLACR_DFCS_SHIFT 15
Freescale_cup 0:3ec7fc598e48 2771 #define MCM_PLACR_ESFC_MASK 0x10000u
Freescale_cup 0:3ec7fc598e48 2772 #define MCM_PLACR_ESFC_SHIFT 16
Freescale_cup 0:3ec7fc598e48 2773 /* CPO Bit Fields */
Freescale_cup 0:3ec7fc598e48 2774 #define MCM_CPO_CPOREQ_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2775 #define MCM_CPO_CPOREQ_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2776 #define MCM_CPO_CPOACK_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2777 #define MCM_CPO_CPOACK_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2778 #define MCM_CPO_CPOWOI_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2779 #define MCM_CPO_CPOWOI_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2780
Freescale_cup 0:3ec7fc598e48 2781 /*!
Freescale_cup 0:3ec7fc598e48 2782 * @}
Freescale_cup 0:3ec7fc598e48 2783 */ /* end of group MCM_Register_Masks */
Freescale_cup 0:3ec7fc598e48 2784
Freescale_cup 0:3ec7fc598e48 2785
Freescale_cup 0:3ec7fc598e48 2786 /* MCM - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 2787 /** Peripheral MCM base pointer */
Freescale_cup 0:3ec7fc598e48 2788 #define MCM_BASE_PTR ((MCM_MemMapPtr)0xF0003000u)
Freescale_cup 0:3ec7fc598e48 2789 /** Array initializer of MCM peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 2790 #define MCM_BASE_PTRS { MCM_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 2791
Freescale_cup 0:3ec7fc598e48 2792 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2793 -- MCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2794 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2795
Freescale_cup 0:3ec7fc598e48 2796 /*!
Freescale_cup 0:3ec7fc598e48 2797 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2798 * @{
Freescale_cup 0:3ec7fc598e48 2799 */
Freescale_cup 0:3ec7fc598e48 2800
Freescale_cup 0:3ec7fc598e48 2801
Freescale_cup 0:3ec7fc598e48 2802 /* MCM - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 2803 /* MCM */
Freescale_cup 0:3ec7fc598e48 2804 #define MCM_PLASC MCM_PLASC_REG(MCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2805 #define MCM_PLAMC MCM_PLAMC_REG(MCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2806 #define MCM_PLACR MCM_PLACR_REG(MCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2807 #define MCM_CPO MCM_CPO_REG(MCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 2808
Freescale_cup 0:3ec7fc598e48 2809 /*!
Freescale_cup 0:3ec7fc598e48 2810 * @}
Freescale_cup 0:3ec7fc598e48 2811 */ /* end of group MCM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2812
Freescale_cup 0:3ec7fc598e48 2813
Freescale_cup 0:3ec7fc598e48 2814 /*!
Freescale_cup 0:3ec7fc598e48 2815 * @}
Freescale_cup 0:3ec7fc598e48 2816 */ /* end of group MCM_Peripheral */
Freescale_cup 0:3ec7fc598e48 2817
Freescale_cup 0:3ec7fc598e48 2818
Freescale_cup 0:3ec7fc598e48 2819 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2820 -- MTB
Freescale_cup 0:3ec7fc598e48 2821 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2822
Freescale_cup 0:3ec7fc598e48 2823 /*!
Freescale_cup 0:3ec7fc598e48 2824 * @addtogroup MTB_Peripheral MTB
Freescale_cup 0:3ec7fc598e48 2825 * @{
Freescale_cup 0:3ec7fc598e48 2826 */
Freescale_cup 0:3ec7fc598e48 2827
Freescale_cup 0:3ec7fc598e48 2828 /** MTB - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 2829 typedef struct MTB_MemMap {
Freescale_cup 0:3ec7fc598e48 2830 uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 2831 uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 2832 uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 2833 uint32_t BASE; /**< MTB Base Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 2834 uint8_t RESERVED_0[3824];
Freescale_cup 0:3ec7fc598e48 2835 uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
Freescale_cup 0:3ec7fc598e48 2836 uint8_t RESERVED_1[156];
Freescale_cup 0:3ec7fc598e48 2837 uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
Freescale_cup 0:3ec7fc598e48 2838 uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
Freescale_cup 0:3ec7fc598e48 2839 uint8_t RESERVED_2[8];
Freescale_cup 0:3ec7fc598e48 2840 uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
Freescale_cup 0:3ec7fc598e48 2841 uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
Freescale_cup 0:3ec7fc598e48 2842 uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
Freescale_cup 0:3ec7fc598e48 2843 uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
Freescale_cup 0:3ec7fc598e48 2844 uint8_t RESERVED_3[8];
Freescale_cup 0:3ec7fc598e48 2845 uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
Freescale_cup 0:3ec7fc598e48 2846 uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
Freescale_cup 0:3ec7fc598e48 2847 uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 2848 uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 2849 } volatile *MTB_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 2850
Freescale_cup 0:3ec7fc598e48 2851 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2852 -- MTB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2853 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2854
Freescale_cup 0:3ec7fc598e48 2855 /*!
Freescale_cup 0:3ec7fc598e48 2856 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2857 * @{
Freescale_cup 0:3ec7fc598e48 2858 */
Freescale_cup 0:3ec7fc598e48 2859
Freescale_cup 0:3ec7fc598e48 2860
Freescale_cup 0:3ec7fc598e48 2861 /* MTB - Register accessors */
Freescale_cup 0:3ec7fc598e48 2862 #define MTB_POSITION_REG(base) ((base)->POSITION)
Freescale_cup 0:3ec7fc598e48 2863 #define MTB_MASTER_REG(base) ((base)->MASTER)
Freescale_cup 0:3ec7fc598e48 2864 #define MTB_FLOW_REG(base) ((base)->FLOW)
Freescale_cup 0:3ec7fc598e48 2865 #define MTB_BASE_REG(base) ((base)->BASE)
Freescale_cup 0:3ec7fc598e48 2866 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
Freescale_cup 0:3ec7fc598e48 2867 #define MTB_TAGSET_REG(base) ((base)->TAGSET)
Freescale_cup 0:3ec7fc598e48 2868 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
Freescale_cup 0:3ec7fc598e48 2869 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
Freescale_cup 0:3ec7fc598e48 2870 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
Freescale_cup 0:3ec7fc598e48 2871 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
Freescale_cup 0:3ec7fc598e48 2872 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
Freescale_cup 0:3ec7fc598e48 2873 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
Freescale_cup 0:3ec7fc598e48 2874 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
Freescale_cup 0:3ec7fc598e48 2875 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
Freescale_cup 0:3ec7fc598e48 2876 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
Freescale_cup 0:3ec7fc598e48 2877
Freescale_cup 0:3ec7fc598e48 2878 /*!
Freescale_cup 0:3ec7fc598e48 2879 * @}
Freescale_cup 0:3ec7fc598e48 2880 */ /* end of group MTB_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 2881
Freescale_cup 0:3ec7fc598e48 2882
Freescale_cup 0:3ec7fc598e48 2883 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2884 -- MTB Register Masks
Freescale_cup 0:3ec7fc598e48 2885 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2886
Freescale_cup 0:3ec7fc598e48 2887 /*!
Freescale_cup 0:3ec7fc598e48 2888 * @addtogroup MTB_Register_Masks MTB Register Masks
Freescale_cup 0:3ec7fc598e48 2889 * @{
Freescale_cup 0:3ec7fc598e48 2890 */
Freescale_cup 0:3ec7fc598e48 2891
Freescale_cup 0:3ec7fc598e48 2892 /* POSITION Bit Fields */
Freescale_cup 0:3ec7fc598e48 2893 #define MTB_POSITION_WRAP_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2894 #define MTB_POSITION_WRAP_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2895 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
Freescale_cup 0:3ec7fc598e48 2896 #define MTB_POSITION_POINTER_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2897 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
Freescale_cup 0:3ec7fc598e48 2898 /* MASTER Bit Fields */
Freescale_cup 0:3ec7fc598e48 2899 #define MTB_MASTER_MASK_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 2900 #define MTB_MASTER_MASK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2901 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
Freescale_cup 0:3ec7fc598e48 2902 #define MTB_MASTER_TSTARTEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 2903 #define MTB_MASTER_TSTARTEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 2904 #define MTB_MASTER_TSTOPEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 2905 #define MTB_MASTER_TSTOPEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 2906 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 2907 #define MTB_MASTER_SFRWPRIV_SHIFT 7
Freescale_cup 0:3ec7fc598e48 2908 #define MTB_MASTER_RAMPRIV_MASK 0x100u
Freescale_cup 0:3ec7fc598e48 2909 #define MTB_MASTER_RAMPRIV_SHIFT 8
Freescale_cup 0:3ec7fc598e48 2910 #define MTB_MASTER_HALTREQ_MASK 0x200u
Freescale_cup 0:3ec7fc598e48 2911 #define MTB_MASTER_HALTREQ_SHIFT 9
Freescale_cup 0:3ec7fc598e48 2912 #define MTB_MASTER_EN_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 2913 #define MTB_MASTER_EN_SHIFT 31
Freescale_cup 0:3ec7fc598e48 2914 /* FLOW Bit Fields */
Freescale_cup 0:3ec7fc598e48 2915 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2916 #define MTB_FLOW_AUTOSTOP_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2917 #define MTB_FLOW_AUTOHALT_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2918 #define MTB_FLOW_AUTOHALT_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2919 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
Freescale_cup 0:3ec7fc598e48 2920 #define MTB_FLOW_WATERMARK_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2921 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
Freescale_cup 0:3ec7fc598e48 2922 /* BASE Bit Fields */
Freescale_cup 0:3ec7fc598e48 2923 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2924 #define MTB_BASE_BASEADDR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2925 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
Freescale_cup 0:3ec7fc598e48 2926 /* MODECTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 2927 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2928 #define MTB_MODECTRL_MODECTRL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2929 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
Freescale_cup 0:3ec7fc598e48 2930 /* TAGSET Bit Fields */
Freescale_cup 0:3ec7fc598e48 2931 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2932 #define MTB_TAGSET_TAGSET_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2933 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
Freescale_cup 0:3ec7fc598e48 2934 /* TAGCLEAR Bit Fields */
Freescale_cup 0:3ec7fc598e48 2935 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2936 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2937 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
Freescale_cup 0:3ec7fc598e48 2938 /* LOCKACCESS Bit Fields */
Freescale_cup 0:3ec7fc598e48 2939 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2940 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2941 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
Freescale_cup 0:3ec7fc598e48 2942 /* LOCKSTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 2943 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2944 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2945 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
Freescale_cup 0:3ec7fc598e48 2946 /* AUTHSTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 2947 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 2948 #define MTB_AUTHSTAT_BIT0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2949 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 2950 #define MTB_AUTHSTAT_BIT1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 2951 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 2952 #define MTB_AUTHSTAT_BIT2_SHIFT 2
Freescale_cup 0:3ec7fc598e48 2953 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 2954 #define MTB_AUTHSTAT_BIT3_SHIFT 3
Freescale_cup 0:3ec7fc598e48 2955 /* DEVICEARCH Bit Fields */
Freescale_cup 0:3ec7fc598e48 2956 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2957 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2958 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
Freescale_cup 0:3ec7fc598e48 2959 /* DEVICECFG Bit Fields */
Freescale_cup 0:3ec7fc598e48 2960 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2961 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2962 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
Freescale_cup 0:3ec7fc598e48 2963 /* DEVICETYPID Bit Fields */
Freescale_cup 0:3ec7fc598e48 2964 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2965 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2966 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
Freescale_cup 0:3ec7fc598e48 2967 /* PERIPHID Bit Fields */
Freescale_cup 0:3ec7fc598e48 2968 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2969 #define MTB_PERIPHID_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2970 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 2971 /* COMPID Bit Fields */
Freescale_cup 0:3ec7fc598e48 2972 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 2973 #define MTB_COMPID_COMPID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 2974 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
Freescale_cup 0:3ec7fc598e48 2975
Freescale_cup 0:3ec7fc598e48 2976 /*!
Freescale_cup 0:3ec7fc598e48 2977 * @}
Freescale_cup 0:3ec7fc598e48 2978 */ /* end of group MTB_Register_Masks */
Freescale_cup 0:3ec7fc598e48 2979
Freescale_cup 0:3ec7fc598e48 2980
Freescale_cup 0:3ec7fc598e48 2981 /* MTB - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 2982 /** Peripheral MTB base pointer */
Freescale_cup 0:3ec7fc598e48 2983 #define MTB_BASE_PTR ((MTB_MemMapPtr)0xF0000000u)
Freescale_cup 0:3ec7fc598e48 2984 /** Array initializer of MTB peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 2985 #define MTB_BASE_PTRS { MTB_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 2986
Freescale_cup 0:3ec7fc598e48 2987 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 2988 -- MTB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2989 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 2990
Freescale_cup 0:3ec7fc598e48 2991 /*!
Freescale_cup 0:3ec7fc598e48 2992 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 2993 * @{
Freescale_cup 0:3ec7fc598e48 2994 */
Freescale_cup 0:3ec7fc598e48 2995
Freescale_cup 0:3ec7fc598e48 2996
Freescale_cup 0:3ec7fc598e48 2997 /* MTB - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 2998 /* MTB */
Freescale_cup 0:3ec7fc598e48 2999 #define MTB_POSITION MTB_POSITION_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3000 #define MTB_MASTER MTB_MASTER_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3001 #define MTB_FLOW MTB_FLOW_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3002 //#define MTB_BASE MTB_BASE_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3003 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3004 #define MTB_TAGSET MTB_TAGSET_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3005 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3006 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3007 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3008 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3009 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3010 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3011 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3012 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3013 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3014 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 3015 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 3016 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 3017 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 3018 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 3019 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 3020 #define MTB_COMPID0 MTB_COMPID_REG(MTB_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3021 #define MTB_COMPID1 MTB_COMPID_REG(MTB_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3022 #define MTB_COMPID2 MTB_COMPID_REG(MTB_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 3023 #define MTB_COMPID3 MTB_COMPID_REG(MTB_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 3024
Freescale_cup 0:3ec7fc598e48 3025 /* MTB - Register array accessors */
Freescale_cup 0:3ec7fc598e48 3026 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3027 #define MTB_COMPID(index) MTB_COMPID_REG(MTB_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3028
Freescale_cup 0:3ec7fc598e48 3029 /*!
Freescale_cup 0:3ec7fc598e48 3030 * @}
Freescale_cup 0:3ec7fc598e48 3031 */ /* end of group MTB_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3032
Freescale_cup 0:3ec7fc598e48 3033
Freescale_cup 0:3ec7fc598e48 3034 /*!
Freescale_cup 0:3ec7fc598e48 3035 * @}
Freescale_cup 0:3ec7fc598e48 3036 */ /* end of group MTB_Peripheral */
Freescale_cup 0:3ec7fc598e48 3037
Freescale_cup 0:3ec7fc598e48 3038
Freescale_cup 0:3ec7fc598e48 3039 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3040 -- MTBDWT
Freescale_cup 0:3ec7fc598e48 3041 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3042
Freescale_cup 0:3ec7fc598e48 3043 /*!
Freescale_cup 0:3ec7fc598e48 3044 * @addtogroup MTBDWT_Peripheral MTBDWT
Freescale_cup 0:3ec7fc598e48 3045 * @{
Freescale_cup 0:3ec7fc598e48 3046 */
Freescale_cup 0:3ec7fc598e48 3047
Freescale_cup 0:3ec7fc598e48 3048 /** MTBDWT - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3049 typedef struct MTBDWT_MemMap {
Freescale_cup 0:3ec7fc598e48 3050 uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 3051 uint8_t RESERVED_0[28];
Freescale_cup 0:3ec7fc598e48 3052 struct { /* offset: 0x20, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3053 uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3054 uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3055 uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3056 uint8_t RESERVED_0[4];
Freescale_cup 0:3ec7fc598e48 3057 } COMPARATOR[2];
Freescale_cup 0:3ec7fc598e48 3058 uint8_t RESERVED_1[448];
Freescale_cup 0:3ec7fc598e48 3059 uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
Freescale_cup 0:3ec7fc598e48 3060 uint8_t RESERVED_2[3524];
Freescale_cup 0:3ec7fc598e48 3061 uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
Freescale_cup 0:3ec7fc598e48 3062 uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
Freescale_cup 0:3ec7fc598e48 3063 uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 3064 uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 3065 } volatile *MTBDWT_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3066
Freescale_cup 0:3ec7fc598e48 3067 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3068 -- MTBDWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3069 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3070
Freescale_cup 0:3ec7fc598e48 3071 /*!
Freescale_cup 0:3ec7fc598e48 3072 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3073 * @{
Freescale_cup 0:3ec7fc598e48 3074 */
Freescale_cup 0:3ec7fc598e48 3075
Freescale_cup 0:3ec7fc598e48 3076
Freescale_cup 0:3ec7fc598e48 3077 /* MTBDWT - Register accessors */
Freescale_cup 0:3ec7fc598e48 3078 #define MTBDWT_CTRL_REG(base) ((base)->CTRL)
Freescale_cup 0:3ec7fc598e48 3079 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
Freescale_cup 0:3ec7fc598e48 3080 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
Freescale_cup 0:3ec7fc598e48 3081 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
Freescale_cup 0:3ec7fc598e48 3082 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
Freescale_cup 0:3ec7fc598e48 3083 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
Freescale_cup 0:3ec7fc598e48 3084 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
Freescale_cup 0:3ec7fc598e48 3085 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
Freescale_cup 0:3ec7fc598e48 3086 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
Freescale_cup 0:3ec7fc598e48 3087
Freescale_cup 0:3ec7fc598e48 3088 /*!
Freescale_cup 0:3ec7fc598e48 3089 * @}
Freescale_cup 0:3ec7fc598e48 3090 */ /* end of group MTBDWT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3091
Freescale_cup 0:3ec7fc598e48 3092
Freescale_cup 0:3ec7fc598e48 3093 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3094 -- MTBDWT Register Masks
Freescale_cup 0:3ec7fc598e48 3095 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3096
Freescale_cup 0:3ec7fc598e48 3097 /*!
Freescale_cup 0:3ec7fc598e48 3098 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
Freescale_cup 0:3ec7fc598e48 3099 * @{
Freescale_cup 0:3ec7fc598e48 3100 */
Freescale_cup 0:3ec7fc598e48 3101
Freescale_cup 0:3ec7fc598e48 3102 /* CTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 3103 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3104 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3105 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
Freescale_cup 0:3ec7fc598e48 3106 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
Freescale_cup 0:3ec7fc598e48 3107 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
Freescale_cup 0:3ec7fc598e48 3108 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
Freescale_cup 0:3ec7fc598e48 3109 /* COMP Bit Fields */
Freescale_cup 0:3ec7fc598e48 3110 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3111 #define MTBDWT_COMP_COMP_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3112 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
Freescale_cup 0:3ec7fc598e48 3113 /* MASK Bit Fields */
Freescale_cup 0:3ec7fc598e48 3114 #define MTBDWT_MASK_MASK_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 3115 #define MTBDWT_MASK_MASK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3116 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
Freescale_cup 0:3ec7fc598e48 3117 /* FCT Bit Fields */
Freescale_cup 0:3ec7fc598e48 3118 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 3119 #define MTBDWT_FCT_FUNCTION_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3120 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
Freescale_cup 0:3ec7fc598e48 3121 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
Freescale_cup 0:3ec7fc598e48 3122 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3123 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
Freescale_cup 0:3ec7fc598e48 3124 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
Freescale_cup 0:3ec7fc598e48 3125 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
Freescale_cup 0:3ec7fc598e48 3126 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
Freescale_cup 0:3ec7fc598e48 3127 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
Freescale_cup 0:3ec7fc598e48 3128 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
Freescale_cup 0:3ec7fc598e48 3129 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
Freescale_cup 0:3ec7fc598e48 3130 #define MTBDWT_FCT_MATCHED_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3131 /* TBCTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 3132 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3133 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3134 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 3135 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 3136 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
Freescale_cup 0:3ec7fc598e48 3137 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
Freescale_cup 0:3ec7fc598e48 3138 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
Freescale_cup 0:3ec7fc598e48 3139 /* DEVICECFG Bit Fields */
Freescale_cup 0:3ec7fc598e48 3140 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3141 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3142 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
Freescale_cup 0:3ec7fc598e48 3143 /* DEVICETYPID Bit Fields */
Freescale_cup 0:3ec7fc598e48 3144 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3145 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3146 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
Freescale_cup 0:3ec7fc598e48 3147 /* PERIPHID Bit Fields */
Freescale_cup 0:3ec7fc598e48 3148 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3149 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3150 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 3151 /* COMPID Bit Fields */
Freescale_cup 0:3ec7fc598e48 3152 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3153 #define MTBDWT_COMPID_COMPID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3154 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
Freescale_cup 0:3ec7fc598e48 3155
Freescale_cup 0:3ec7fc598e48 3156 /*!
Freescale_cup 0:3ec7fc598e48 3157 * @}
Freescale_cup 0:3ec7fc598e48 3158 */ /* end of group MTBDWT_Register_Masks */
Freescale_cup 0:3ec7fc598e48 3159
Freescale_cup 0:3ec7fc598e48 3160
Freescale_cup 0:3ec7fc598e48 3161 /* MTBDWT - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 3162 /** Peripheral MTBDWT base pointer */
Freescale_cup 0:3ec7fc598e48 3163 #define MTBDWT_BASE_PTR ((MTBDWT_MemMapPtr)0xF0001000u)
Freescale_cup 0:3ec7fc598e48 3164 /** Array initializer of MTBDWT peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 3165 #define MTBDWT_BASE_PTRS { MTBDWT_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 3166
Freescale_cup 0:3ec7fc598e48 3167 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3168 -- MTBDWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3169 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3170
Freescale_cup 0:3ec7fc598e48 3171 /*!
Freescale_cup 0:3ec7fc598e48 3172 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3173 * @{
Freescale_cup 0:3ec7fc598e48 3174 */
Freescale_cup 0:3ec7fc598e48 3175
Freescale_cup 0:3ec7fc598e48 3176
Freescale_cup 0:3ec7fc598e48 3177 /* MTBDWT - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 3178 /* MTBDWT */
Freescale_cup 0:3ec7fc598e48 3179 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3180 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3181 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3182 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3183 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3184 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3185 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3186 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3187 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3188 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3189 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3190 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3191 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 3192 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 3193 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 3194 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 3195 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 3196 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 3197 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3198 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3199 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 3200 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 3201
Freescale_cup 0:3ec7fc598e48 3202 /* MTBDWT - Register array accessors */
Freescale_cup 0:3ec7fc598e48 3203 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3204 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3205 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3206 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3207 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3208
Freescale_cup 0:3ec7fc598e48 3209 /*!
Freescale_cup 0:3ec7fc598e48 3210 * @}
Freescale_cup 0:3ec7fc598e48 3211 */ /* end of group MTBDWT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3212
Freescale_cup 0:3ec7fc598e48 3213
Freescale_cup 0:3ec7fc598e48 3214 /*!
Freescale_cup 0:3ec7fc598e48 3215 * @}
Freescale_cup 0:3ec7fc598e48 3216 */ /* end of group MTBDWT_Peripheral */
Freescale_cup 0:3ec7fc598e48 3217
Freescale_cup 0:3ec7fc598e48 3218
Freescale_cup 0:3ec7fc598e48 3219 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3220 -- NV
Freescale_cup 0:3ec7fc598e48 3221 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3222
Freescale_cup 0:3ec7fc598e48 3223 /*!
Freescale_cup 0:3ec7fc598e48 3224 * @addtogroup NV_Peripheral NV
Freescale_cup 0:3ec7fc598e48 3225 * @{
Freescale_cup 0:3ec7fc598e48 3226 */
Freescale_cup 0:3ec7fc598e48 3227
Freescale_cup 0:3ec7fc598e48 3228 /** NV - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3229 typedef struct NV_MemMap {
Freescale_cup 0:3ec7fc598e48 3230 uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 3231 uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 3232 uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 3233 uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 3234 uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 3235 uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 3236 uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 3237 uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 3238 uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 3239 uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
Freescale_cup 0:3ec7fc598e48 3240 uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
Freescale_cup 0:3ec7fc598e48 3241 uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
Freescale_cup 0:3ec7fc598e48 3242 uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 3243 uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
Freescale_cup 0:3ec7fc598e48 3244 } volatile *NV_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3245
Freescale_cup 0:3ec7fc598e48 3246 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3247 -- NV - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3248 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3249
Freescale_cup 0:3ec7fc598e48 3250 /*!
Freescale_cup 0:3ec7fc598e48 3251 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3252 * @{
Freescale_cup 0:3ec7fc598e48 3253 */
Freescale_cup 0:3ec7fc598e48 3254
Freescale_cup 0:3ec7fc598e48 3255
Freescale_cup 0:3ec7fc598e48 3256 /* NV - Register accessors */
Freescale_cup 0:3ec7fc598e48 3257 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
Freescale_cup 0:3ec7fc598e48 3258 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
Freescale_cup 0:3ec7fc598e48 3259 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
Freescale_cup 0:3ec7fc598e48 3260 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
Freescale_cup 0:3ec7fc598e48 3261 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
Freescale_cup 0:3ec7fc598e48 3262 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
Freescale_cup 0:3ec7fc598e48 3263 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
Freescale_cup 0:3ec7fc598e48 3264 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
Freescale_cup 0:3ec7fc598e48 3265 #define NV_FPROT3_REG(base) ((base)->FPROT3)
Freescale_cup 0:3ec7fc598e48 3266 #define NV_FPROT2_REG(base) ((base)->FPROT2)
Freescale_cup 0:3ec7fc598e48 3267 #define NV_FPROT1_REG(base) ((base)->FPROT1)
Freescale_cup 0:3ec7fc598e48 3268 #define NV_FPROT0_REG(base) ((base)->FPROT0)
Freescale_cup 0:3ec7fc598e48 3269 #define NV_FSEC_REG(base) ((base)->FSEC)
Freescale_cup 0:3ec7fc598e48 3270 #define NV_FOPT_REG(base) ((base)->FOPT)
Freescale_cup 0:3ec7fc598e48 3271
Freescale_cup 0:3ec7fc598e48 3272 /*!
Freescale_cup 0:3ec7fc598e48 3273 * @}
Freescale_cup 0:3ec7fc598e48 3274 */ /* end of group NV_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3275
Freescale_cup 0:3ec7fc598e48 3276
Freescale_cup 0:3ec7fc598e48 3277 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3278 -- NV Register Masks
Freescale_cup 0:3ec7fc598e48 3279 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3280
Freescale_cup 0:3ec7fc598e48 3281 /*!
Freescale_cup 0:3ec7fc598e48 3282 * @addtogroup NV_Register_Masks NV Register Masks
Freescale_cup 0:3ec7fc598e48 3283 * @{
Freescale_cup 0:3ec7fc598e48 3284 */
Freescale_cup 0:3ec7fc598e48 3285
Freescale_cup 0:3ec7fc598e48 3286 /* BACKKEY3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3287 #define NV_BACKKEY3_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3288 #define NV_BACKKEY3_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3289 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3290 /* BACKKEY2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3291 #define NV_BACKKEY2_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3292 #define NV_BACKKEY2_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3293 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3294 /* BACKKEY1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3295 #define NV_BACKKEY1_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3296 #define NV_BACKKEY1_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3297 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3298 /* BACKKEY0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3299 #define NV_BACKKEY0_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3300 #define NV_BACKKEY0_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3301 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3302 /* BACKKEY7 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3303 #define NV_BACKKEY7_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3304 #define NV_BACKKEY7_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3305 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3306 /* BACKKEY6 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3307 #define NV_BACKKEY6_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3308 #define NV_BACKKEY6_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3309 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3310 /* BACKKEY5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3311 #define NV_BACKKEY5_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3312 #define NV_BACKKEY5_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3313 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3314 /* BACKKEY4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3315 #define NV_BACKKEY4_KEY_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3316 #define NV_BACKKEY4_KEY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3317 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
Freescale_cup 0:3ec7fc598e48 3318 /* FPROT3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3319 #define NV_FPROT3_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3320 #define NV_FPROT3_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3321 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 3322 /* FPROT2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3323 #define NV_FPROT2_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3324 #define NV_FPROT2_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3325 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 3326 /* FPROT1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3327 #define NV_FPROT1_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3328 #define NV_FPROT1_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3329 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 3330 /* FPROT0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3331 #define NV_FPROT0_PROT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3332 #define NV_FPROT0_PROT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3333 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
Freescale_cup 0:3ec7fc598e48 3334 /* FSEC Bit Fields */
Freescale_cup 0:3ec7fc598e48 3335 #define NV_FSEC_SEC_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 3336 #define NV_FSEC_SEC_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3337 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
Freescale_cup 0:3ec7fc598e48 3338 #define NV_FSEC_FSLACC_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 3339 #define NV_FSEC_FSLACC_SHIFT 2
Freescale_cup 0:3ec7fc598e48 3340 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
Freescale_cup 0:3ec7fc598e48 3341 #define NV_FSEC_MEEN_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 3342 #define NV_FSEC_MEEN_SHIFT 4
Freescale_cup 0:3ec7fc598e48 3343 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
Freescale_cup 0:3ec7fc598e48 3344 #define NV_FSEC_KEYEN_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 3345 #define NV_FSEC_KEYEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 3346 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
Freescale_cup 0:3ec7fc598e48 3347 /* FOPT Bit Fields */
Freescale_cup 0:3ec7fc598e48 3348 #define NV_FOPT_LPBOOT0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3349 #define NV_FOPT_LPBOOT0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3350 #define NV_FOPT_NMI_DIS_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 3351 #define NV_FOPT_NMI_DIS_SHIFT 2
Freescale_cup 0:3ec7fc598e48 3352 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 3353 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
Freescale_cup 0:3ec7fc598e48 3354 #define NV_FOPT_LPBOOT1_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 3355 #define NV_FOPT_LPBOOT1_SHIFT 4
Freescale_cup 0:3ec7fc598e48 3356 #define NV_FOPT_FAST_INIT_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 3357 #define NV_FOPT_FAST_INIT_SHIFT 5
Freescale_cup 0:3ec7fc598e48 3358
Freescale_cup 0:3ec7fc598e48 3359 /*!
Freescale_cup 0:3ec7fc598e48 3360 * @}
Freescale_cup 0:3ec7fc598e48 3361 */ /* end of group NV_Register_Masks */
Freescale_cup 0:3ec7fc598e48 3362
Freescale_cup 0:3ec7fc598e48 3363
Freescale_cup 0:3ec7fc598e48 3364 /* NV - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 3365 /** Peripheral FTFA_FlashConfig base pointer */
Freescale_cup 0:3ec7fc598e48 3366 #define FTFA_FlashConfig_BASE_PTR ((NV_MemMapPtr)0x400u)
Freescale_cup 0:3ec7fc598e48 3367 /** Array initializer of NV peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 3368 #define NV_BASE_PTRS { FTFA_FlashConfig_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 3369
Freescale_cup 0:3ec7fc598e48 3370 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3371 -- NV - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3372 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3373
Freescale_cup 0:3ec7fc598e48 3374 /*!
Freescale_cup 0:3ec7fc598e48 3375 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3376 * @{
Freescale_cup 0:3ec7fc598e48 3377 */
Freescale_cup 0:3ec7fc598e48 3378
Freescale_cup 0:3ec7fc598e48 3379
Freescale_cup 0:3ec7fc598e48 3380 /* NV - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 3381 /* FTFA_FlashConfig */
Freescale_cup 0:3ec7fc598e48 3382 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3383 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3384 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3385 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3386 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3387 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3388 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3389 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3390 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3391 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3392 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3393 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3394 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3395 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3396
Freescale_cup 0:3ec7fc598e48 3397 /*!
Freescale_cup 0:3ec7fc598e48 3398 * @}
Freescale_cup 0:3ec7fc598e48 3399 */ /* end of group NV_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3400
Freescale_cup 0:3ec7fc598e48 3401
Freescale_cup 0:3ec7fc598e48 3402 /*!
Freescale_cup 0:3ec7fc598e48 3403 * @}
Freescale_cup 0:3ec7fc598e48 3404 */ /* end of group NV_Peripheral */
Freescale_cup 0:3ec7fc598e48 3405
Freescale_cup 0:3ec7fc598e48 3406
Freescale_cup 0:3ec7fc598e48 3407 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3408 -- NVIC
Freescale_cup 0:3ec7fc598e48 3409 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3410
Freescale_cup 0:3ec7fc598e48 3411 /*!
Freescale_cup 0:3ec7fc598e48 3412 * @addtogroup NVIC_Peripheral NVIC
Freescale_cup 0:3ec7fc598e48 3413 * @{
Freescale_cup 0:3ec7fc598e48 3414 */
Freescale_cup 0:3ec7fc598e48 3415
Freescale_cup 0:3ec7fc598e48 3416 /** NVIC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3417 typedef struct NVIC_MemMap {
Freescale_cup 0:3ec7fc598e48 3418 uint32_t ISER; /**< Interrupt Set Enable Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 3419 uint8_t RESERVED_0[124];
Freescale_cup 0:3ec7fc598e48 3420 uint32_t ICER; /**< Interrupt Clear Enable Register, offset: 0x80 */
Freescale_cup 0:3ec7fc598e48 3421 uint8_t RESERVED_1[124];
Freescale_cup 0:3ec7fc598e48 3422 uint32_t ISPR; /**< Interrupt Set Pending Register, offset: 0x100 */
Freescale_cup 0:3ec7fc598e48 3423 uint8_t RESERVED_2[124];
Freescale_cup 0:3ec7fc598e48 3424 uint32_t ICPR; /**< Interrupt Clear Pending Register, offset: 0x180 */
Freescale_cup 0:3ec7fc598e48 3425 uint8_t RESERVED_3[380];
Freescale_cup 0:3ec7fc598e48 3426 uint32_t IP[8]; /**< Interrupt Priority Register n, array offset: 0x300, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 3427 } volatile *NVIC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3428
Freescale_cup 0:3ec7fc598e48 3429 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3430 -- NVIC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3431 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3432
Freescale_cup 0:3ec7fc598e48 3433 /*!
Freescale_cup 0:3ec7fc598e48 3434 * @addtogroup NVIC_Register_Accessor_Macros NVIC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3435 * @{
Freescale_cup 0:3ec7fc598e48 3436 */
Freescale_cup 0:3ec7fc598e48 3437
Freescale_cup 0:3ec7fc598e48 3438
Freescale_cup 0:3ec7fc598e48 3439 /* NVIC - Register accessors */
Freescale_cup 0:3ec7fc598e48 3440 #define NVIC_ISER_REG(base) ((base)->ISER)
Freescale_cup 0:3ec7fc598e48 3441 #define NVIC_ICER_REG(base) ((base)->ICER)
Freescale_cup 0:3ec7fc598e48 3442 #define NVIC_ISPR_REG(base) ((base)->ISPR)
Freescale_cup 0:3ec7fc598e48 3443 #define NVIC_ICPR_REG(base) ((base)->ICPR)
Freescale_cup 0:3ec7fc598e48 3444 #define NVIC_IP_REG(base,index) ((base)->IP[index])
Freescale_cup 0:3ec7fc598e48 3445
Freescale_cup 0:3ec7fc598e48 3446 /*!
Freescale_cup 0:3ec7fc598e48 3447 * @}
Freescale_cup 0:3ec7fc598e48 3448 */ /* end of group NVIC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3449
Freescale_cup 0:3ec7fc598e48 3450
Freescale_cup 0:3ec7fc598e48 3451 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3452 -- NVIC Register Masks
Freescale_cup 0:3ec7fc598e48 3453 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3454
Freescale_cup 0:3ec7fc598e48 3455 /*!
Freescale_cup 0:3ec7fc598e48 3456 * @addtogroup NVIC_Register_Masks NVIC Register Masks
Freescale_cup 0:3ec7fc598e48 3457 * @{
Freescale_cup 0:3ec7fc598e48 3458 */
Freescale_cup 0:3ec7fc598e48 3459
Freescale_cup 0:3ec7fc598e48 3460 /* ISER Bit Fields */
Freescale_cup 0:3ec7fc598e48 3461 #define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3462 #define NVIC_ISER_SETENA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3463 #define NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISER_SETENA_SHIFT))&NVIC_ISER_SETENA_MASK)
Freescale_cup 0:3ec7fc598e48 3464 /* ICER Bit Fields */
Freescale_cup 0:3ec7fc598e48 3465 #define NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3466 #define NVIC_ICER_CLRENA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3467 #define NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICER_CLRENA_SHIFT))&NVIC_ICER_CLRENA_MASK)
Freescale_cup 0:3ec7fc598e48 3468 /* ISPR Bit Fields */
Freescale_cup 0:3ec7fc598e48 3469 #define NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3470 #define NVIC_ISPR_SETPEND_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3471 #define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)
Freescale_cup 0:3ec7fc598e48 3472 /* ICPR Bit Fields */
Freescale_cup 0:3ec7fc598e48 3473 #define NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3474 #define NVIC_ICPR_CLRPEND_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3475 #define NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICPR_CLRPEND_SHIFT))&NVIC_ICPR_CLRPEND_MASK)
Freescale_cup 0:3ec7fc598e48 3476 /* IP Bit Fields */
Freescale_cup 0:3ec7fc598e48 3477 #define NVIC_IP_PRI_0_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3478 #define NVIC_IP_PRI_0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3479 #define NVIC_IP_PRI_0(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_0_SHIFT))&NVIC_IP_PRI_0_MASK)
Freescale_cup 0:3ec7fc598e48 3480 #define NVIC_IP_PRI_28_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3481 #define NVIC_IP_PRI_28_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3482 #define NVIC_IP_PRI_28(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_28_SHIFT))&NVIC_IP_PRI_28_MASK)
Freescale_cup 0:3ec7fc598e48 3483 #define NVIC_IP_PRI_24_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3484 #define NVIC_IP_PRI_24_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3485 #define NVIC_IP_PRI_24(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_24_SHIFT))&NVIC_IP_PRI_24_MASK)
Freescale_cup 0:3ec7fc598e48 3486 #define NVIC_IP_PRI_20_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3487 #define NVIC_IP_PRI_20_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3488 #define NVIC_IP_PRI_20(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_20_SHIFT))&NVIC_IP_PRI_20_MASK)
Freescale_cup 0:3ec7fc598e48 3489 #define NVIC_IP_PRI_4_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3490 #define NVIC_IP_PRI_4_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3491 #define NVIC_IP_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_4_SHIFT))&NVIC_IP_PRI_4_MASK)
Freescale_cup 0:3ec7fc598e48 3492 #define NVIC_IP_PRI_16_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3493 #define NVIC_IP_PRI_16_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3494 #define NVIC_IP_PRI_16(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_16_SHIFT))&NVIC_IP_PRI_16_MASK)
Freescale_cup 0:3ec7fc598e48 3495 #define NVIC_IP_PRI_12_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3496 #define NVIC_IP_PRI_12_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3497 #define NVIC_IP_PRI_12(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_12_SHIFT))&NVIC_IP_PRI_12_MASK)
Freescale_cup 0:3ec7fc598e48 3498 #define NVIC_IP_PRI_8_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 3499 #define NVIC_IP_PRI_8_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3500 #define NVIC_IP_PRI_8(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_8_SHIFT))&NVIC_IP_PRI_8_MASK)
Freescale_cup 0:3ec7fc598e48 3501 #define NVIC_IP_PRI_13_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3502 #define NVIC_IP_PRI_13_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3503 #define NVIC_IP_PRI_13(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_13_SHIFT))&NVIC_IP_PRI_13_MASK)
Freescale_cup 0:3ec7fc598e48 3504 #define NVIC_IP_PRI_21_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3505 #define NVIC_IP_PRI_21_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3506 #define NVIC_IP_PRI_21(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_21_SHIFT))&NVIC_IP_PRI_21_MASK)
Freescale_cup 0:3ec7fc598e48 3507 #define NVIC_IP_PRI_29_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3508 #define NVIC_IP_PRI_29_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3509 #define NVIC_IP_PRI_29(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_29_SHIFT))&NVIC_IP_PRI_29_MASK)
Freescale_cup 0:3ec7fc598e48 3510 #define NVIC_IP_PRI_1_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3511 #define NVIC_IP_PRI_1_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3512 #define NVIC_IP_PRI_1(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_1_SHIFT))&NVIC_IP_PRI_1_MASK)
Freescale_cup 0:3ec7fc598e48 3513 #define NVIC_IP_PRI_9_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3514 #define NVIC_IP_PRI_9_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3515 #define NVIC_IP_PRI_9(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_9_SHIFT))&NVIC_IP_PRI_9_MASK)
Freescale_cup 0:3ec7fc598e48 3516 #define NVIC_IP_PRI_17_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3517 #define NVIC_IP_PRI_17_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3518 #define NVIC_IP_PRI_17(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_17_SHIFT))&NVIC_IP_PRI_17_MASK)
Freescale_cup 0:3ec7fc598e48 3519 #define NVIC_IP_PRI_25_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3520 #define NVIC_IP_PRI_25_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3521 #define NVIC_IP_PRI_25(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_25_SHIFT))&NVIC_IP_PRI_25_MASK)
Freescale_cup 0:3ec7fc598e48 3522 #define NVIC_IP_PRI_5_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 3523 #define NVIC_IP_PRI_5_SHIFT 8
Freescale_cup 0:3ec7fc598e48 3524 #define NVIC_IP_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_5_SHIFT))&NVIC_IP_PRI_5_MASK)
Freescale_cup 0:3ec7fc598e48 3525 #define NVIC_IP_PRI_2_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3526 #define NVIC_IP_PRI_2_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3527 #define NVIC_IP_PRI_2(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_2_SHIFT))&NVIC_IP_PRI_2_MASK)
Freescale_cup 0:3ec7fc598e48 3528 #define NVIC_IP_PRI_26_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3529 #define NVIC_IP_PRI_26_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3530 #define NVIC_IP_PRI_26(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_26_SHIFT))&NVIC_IP_PRI_26_MASK)
Freescale_cup 0:3ec7fc598e48 3531 #define NVIC_IP_PRI_18_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3532 #define NVIC_IP_PRI_18_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3533 #define NVIC_IP_PRI_18(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_18_SHIFT))&NVIC_IP_PRI_18_MASK)
Freescale_cup 0:3ec7fc598e48 3534 #define NVIC_IP_PRI_14_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3535 #define NVIC_IP_PRI_14_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3536 #define NVIC_IP_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_14_SHIFT))&NVIC_IP_PRI_14_MASK)
Freescale_cup 0:3ec7fc598e48 3537 #define NVIC_IP_PRI_6_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3538 #define NVIC_IP_PRI_6_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3539 #define NVIC_IP_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_6_SHIFT))&NVIC_IP_PRI_6_MASK)
Freescale_cup 0:3ec7fc598e48 3540 #define NVIC_IP_PRI_30_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3541 #define NVIC_IP_PRI_30_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3542 #define NVIC_IP_PRI_30(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_30_SHIFT))&NVIC_IP_PRI_30_MASK)
Freescale_cup 0:3ec7fc598e48 3543 #define NVIC_IP_PRI_22_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3544 #define NVIC_IP_PRI_22_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3545 #define NVIC_IP_PRI_22(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_22_SHIFT))&NVIC_IP_PRI_22_MASK)
Freescale_cup 0:3ec7fc598e48 3546 #define NVIC_IP_PRI_10_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 3547 #define NVIC_IP_PRI_10_SHIFT 16
Freescale_cup 0:3ec7fc598e48 3548 #define NVIC_IP_PRI_10(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_10_SHIFT))&NVIC_IP_PRI_10_MASK)
Freescale_cup 0:3ec7fc598e48 3549 #define NVIC_IP_PRI_31_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3550 #define NVIC_IP_PRI_31_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3551 #define NVIC_IP_PRI_31(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_31_SHIFT))&NVIC_IP_PRI_31_MASK)
Freescale_cup 0:3ec7fc598e48 3552 #define NVIC_IP_PRI_27_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3553 #define NVIC_IP_PRI_27_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3554 #define NVIC_IP_PRI_27(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_27_SHIFT))&NVIC_IP_PRI_27_MASK)
Freescale_cup 0:3ec7fc598e48 3555 #define NVIC_IP_PRI_23_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3556 #define NVIC_IP_PRI_23_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3557 #define NVIC_IP_PRI_23(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_23_SHIFT))&NVIC_IP_PRI_23_MASK)
Freescale_cup 0:3ec7fc598e48 3558 #define NVIC_IP_PRI_3_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3559 #define NVIC_IP_PRI_3_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3560 #define NVIC_IP_PRI_3(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_3_SHIFT))&NVIC_IP_PRI_3_MASK)
Freescale_cup 0:3ec7fc598e48 3561 #define NVIC_IP_PRI_19_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3562 #define NVIC_IP_PRI_19_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3563 #define NVIC_IP_PRI_19(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_19_SHIFT))&NVIC_IP_PRI_19_MASK)
Freescale_cup 0:3ec7fc598e48 3564 #define NVIC_IP_PRI_15_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3565 #define NVIC_IP_PRI_15_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3566 #define NVIC_IP_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_15_SHIFT))&NVIC_IP_PRI_15_MASK)
Freescale_cup 0:3ec7fc598e48 3567 #define NVIC_IP_PRI_11_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3568 #define NVIC_IP_PRI_11_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3569 #define NVIC_IP_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_11_SHIFT))&NVIC_IP_PRI_11_MASK)
Freescale_cup 0:3ec7fc598e48 3570 #define NVIC_IP_PRI_7_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 3571 #define NVIC_IP_PRI_7_SHIFT 24
Freescale_cup 0:3ec7fc598e48 3572 #define NVIC_IP_PRI_7(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_7_SHIFT))&NVIC_IP_PRI_7_MASK)
Freescale_cup 0:3ec7fc598e48 3573
Freescale_cup 0:3ec7fc598e48 3574 /*!
Freescale_cup 0:3ec7fc598e48 3575 * @}
Freescale_cup 0:3ec7fc598e48 3576 */ /* end of group NVIC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 3577
Freescale_cup 0:3ec7fc598e48 3578
Freescale_cup 0:3ec7fc598e48 3579 /* NVIC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 3580 /** Peripheral NVIC base pointer */
Freescale_cup 0:3ec7fc598e48 3581 #define NVIC_BASE_PTR ((NVIC_MemMapPtr)0xE000E100u)
Freescale_cup 0:3ec7fc598e48 3582 /** Array initializer of NVIC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 3583 #define NVIC_BASE_PTRS { NVIC_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 3584
Freescale_cup 0:3ec7fc598e48 3585 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3586 -- NVIC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3587 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3588
Freescale_cup 0:3ec7fc598e48 3589 /*!
Freescale_cup 0:3ec7fc598e48 3590 * @addtogroup NVIC_Register_Accessor_Macros NVIC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3591 * @{
Freescale_cup 0:3ec7fc598e48 3592 */
Freescale_cup 0:3ec7fc598e48 3593
Freescale_cup 0:3ec7fc598e48 3594
Freescale_cup 0:3ec7fc598e48 3595 /* NVIC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 3596 /* NVIC */
Freescale_cup 0:3ec7fc598e48 3597 #define NVIC_ISER NVIC_ISER_REG(NVIC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3598 #define NVIC_ICER NVIC_ICER_REG(NVIC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3599 #define NVIC_ISPR NVIC_ISPR_REG(NVIC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3600 #define NVIC_ICPR NVIC_ICPR_REG(NVIC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3601 #define NVIC_IPR0 NVIC_IP_REG(NVIC_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3602 #define NVIC_IPR1 NVIC_IP_REG(NVIC_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3603 #define NVIC_IPR2 NVIC_IP_REG(NVIC_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 3604 #define NVIC_IPR3 NVIC_IP_REG(NVIC_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 3605 #define NVIC_IPR4 NVIC_IP_REG(NVIC_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 3606 #define NVIC_IPR5 NVIC_IP_REG(NVIC_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 3607 #define NVIC_IPR6 NVIC_IP_REG(NVIC_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 3608 #define NVIC_IPR7 NVIC_IP_REG(NVIC_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 3609
Freescale_cup 0:3ec7fc598e48 3610 /* NVIC - Register array accessors */
Freescale_cup 0:3ec7fc598e48 3611 #define NVIC_IP(index) NVIC_IP_REG(NVIC_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3612
Freescale_cup 0:3ec7fc598e48 3613 /*!
Freescale_cup 0:3ec7fc598e48 3614 * @}
Freescale_cup 0:3ec7fc598e48 3615 */ /* end of group NVIC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3616
Freescale_cup 0:3ec7fc598e48 3617
Freescale_cup 0:3ec7fc598e48 3618 /*!
Freescale_cup 0:3ec7fc598e48 3619 * @}
Freescale_cup 0:3ec7fc598e48 3620 */ /* end of group NVIC_Peripheral */
Freescale_cup 0:3ec7fc598e48 3621
Freescale_cup 0:3ec7fc598e48 3622
Freescale_cup 0:3ec7fc598e48 3623 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3624 -- OSC
Freescale_cup 0:3ec7fc598e48 3625 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3626
Freescale_cup 0:3ec7fc598e48 3627 /*!
Freescale_cup 0:3ec7fc598e48 3628 * @addtogroup OSC_Peripheral OSC
Freescale_cup 0:3ec7fc598e48 3629 * @{
Freescale_cup 0:3ec7fc598e48 3630 */
Freescale_cup 0:3ec7fc598e48 3631
Freescale_cup 0:3ec7fc598e48 3632 /** OSC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3633 typedef struct OSC_MemMap {
Freescale_cup 0:3ec7fc598e48 3634 uint8_t CR; /**< OSC Control Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 3635 } volatile *OSC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3636
Freescale_cup 0:3ec7fc598e48 3637 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3638 -- OSC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3639 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3640
Freescale_cup 0:3ec7fc598e48 3641 /*!
Freescale_cup 0:3ec7fc598e48 3642 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3643 * @{
Freescale_cup 0:3ec7fc598e48 3644 */
Freescale_cup 0:3ec7fc598e48 3645
Freescale_cup 0:3ec7fc598e48 3646
Freescale_cup 0:3ec7fc598e48 3647 /* OSC - Register accessors */
Freescale_cup 0:3ec7fc598e48 3648 #define OSC_CR_REG(base) ((base)->CR)
Freescale_cup 0:3ec7fc598e48 3649
Freescale_cup 0:3ec7fc598e48 3650 /*!
Freescale_cup 0:3ec7fc598e48 3651 * @}
Freescale_cup 0:3ec7fc598e48 3652 */ /* end of group OSC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3653
Freescale_cup 0:3ec7fc598e48 3654
Freescale_cup 0:3ec7fc598e48 3655 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3656 -- OSC Register Masks
Freescale_cup 0:3ec7fc598e48 3657 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3658
Freescale_cup 0:3ec7fc598e48 3659 /*!
Freescale_cup 0:3ec7fc598e48 3660 * @addtogroup OSC_Register_Masks OSC Register Masks
Freescale_cup 0:3ec7fc598e48 3661 * @{
Freescale_cup 0:3ec7fc598e48 3662 */
Freescale_cup 0:3ec7fc598e48 3663
Freescale_cup 0:3ec7fc598e48 3664 /* CR Bit Fields */
Freescale_cup 0:3ec7fc598e48 3665 #define OSC_CR_SC16P_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3666 #define OSC_CR_SC16P_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3667 #define OSC_CR_SC8P_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 3668 #define OSC_CR_SC8P_SHIFT 1
Freescale_cup 0:3ec7fc598e48 3669 #define OSC_CR_SC4P_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 3670 #define OSC_CR_SC4P_SHIFT 2
Freescale_cup 0:3ec7fc598e48 3671 #define OSC_CR_SC2P_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 3672 #define OSC_CR_SC2P_SHIFT 3
Freescale_cup 0:3ec7fc598e48 3673 #define OSC_CR_EREFSTEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 3674 #define OSC_CR_EREFSTEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 3675 #define OSC_CR_ERCLKEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 3676 #define OSC_CR_ERCLKEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 3677
Freescale_cup 0:3ec7fc598e48 3678 /*!
Freescale_cup 0:3ec7fc598e48 3679 * @}
Freescale_cup 0:3ec7fc598e48 3680 */ /* end of group OSC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 3681
Freescale_cup 0:3ec7fc598e48 3682
Freescale_cup 0:3ec7fc598e48 3683 /* OSC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 3684 /** Peripheral OSC0 base pointer */
Freescale_cup 0:3ec7fc598e48 3685 #define OSC0_BASE_PTR ((OSC_MemMapPtr)0x40065000u)
Freescale_cup 0:3ec7fc598e48 3686 /** Array initializer of OSC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 3687 #define OSC_BASE_PTRS { OSC0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 3688
Freescale_cup 0:3ec7fc598e48 3689 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3690 -- OSC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3691 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3692
Freescale_cup 0:3ec7fc598e48 3693 /*!
Freescale_cup 0:3ec7fc598e48 3694 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3695 * @{
Freescale_cup 0:3ec7fc598e48 3696 */
Freescale_cup 0:3ec7fc598e48 3697
Freescale_cup 0:3ec7fc598e48 3698
Freescale_cup 0:3ec7fc598e48 3699 /* OSC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 3700 /* OSC0 */
Freescale_cup 0:3ec7fc598e48 3701 #define OSC0_CR OSC_CR_REG(OSC0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3702
Freescale_cup 0:3ec7fc598e48 3703 /*!
Freescale_cup 0:3ec7fc598e48 3704 * @}
Freescale_cup 0:3ec7fc598e48 3705 */ /* end of group OSC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3706
Freescale_cup 0:3ec7fc598e48 3707
Freescale_cup 0:3ec7fc598e48 3708 /*!
Freescale_cup 0:3ec7fc598e48 3709 * @}
Freescale_cup 0:3ec7fc598e48 3710 */ /* end of group OSC_Peripheral */
Freescale_cup 0:3ec7fc598e48 3711
Freescale_cup 0:3ec7fc598e48 3712
Freescale_cup 0:3ec7fc598e48 3713 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3714 -- PIT
Freescale_cup 0:3ec7fc598e48 3715 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3716
Freescale_cup 0:3ec7fc598e48 3717 /*!
Freescale_cup 0:3ec7fc598e48 3718 * @addtogroup PIT_Peripheral PIT
Freescale_cup 0:3ec7fc598e48 3719 * @{
Freescale_cup 0:3ec7fc598e48 3720 */
Freescale_cup 0:3ec7fc598e48 3721
Freescale_cup 0:3ec7fc598e48 3722 /** PIT - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3723 typedef struct PIT_MemMap {
Freescale_cup 0:3ec7fc598e48 3724 uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 3725 uint8_t RESERVED_0[220];
Freescale_cup 0:3ec7fc598e48 3726 uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
Freescale_cup 0:3ec7fc598e48 3727 uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
Freescale_cup 0:3ec7fc598e48 3728 uint8_t RESERVED_1[24];
Freescale_cup 0:3ec7fc598e48 3729 struct { /* offset: 0x100, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3730 uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3731 uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3732 uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3733 uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
Freescale_cup 0:3ec7fc598e48 3734 } CHANNEL[2];
Freescale_cup 0:3ec7fc598e48 3735 } volatile *PIT_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3736
Freescale_cup 0:3ec7fc598e48 3737 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3738 -- PIT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3739 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3740
Freescale_cup 0:3ec7fc598e48 3741 /*!
Freescale_cup 0:3ec7fc598e48 3742 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3743 * @{
Freescale_cup 0:3ec7fc598e48 3744 */
Freescale_cup 0:3ec7fc598e48 3745
Freescale_cup 0:3ec7fc598e48 3746
Freescale_cup 0:3ec7fc598e48 3747 /* PIT - Register accessors */
Freescale_cup 0:3ec7fc598e48 3748 #define PIT_MCR_REG(base) ((base)->MCR)
Freescale_cup 0:3ec7fc598e48 3749 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
Freescale_cup 0:3ec7fc598e48 3750 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
Freescale_cup 0:3ec7fc598e48 3751 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
Freescale_cup 0:3ec7fc598e48 3752 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
Freescale_cup 0:3ec7fc598e48 3753 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
Freescale_cup 0:3ec7fc598e48 3754 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
Freescale_cup 0:3ec7fc598e48 3755
Freescale_cup 0:3ec7fc598e48 3756 /*!
Freescale_cup 0:3ec7fc598e48 3757 * @}
Freescale_cup 0:3ec7fc598e48 3758 */ /* end of group PIT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3759
Freescale_cup 0:3ec7fc598e48 3760
Freescale_cup 0:3ec7fc598e48 3761 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3762 -- PIT Register Masks
Freescale_cup 0:3ec7fc598e48 3763 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3764
Freescale_cup 0:3ec7fc598e48 3765 /*!
Freescale_cup 0:3ec7fc598e48 3766 * @addtogroup PIT_Register_Masks PIT Register Masks
Freescale_cup 0:3ec7fc598e48 3767 * @{
Freescale_cup 0:3ec7fc598e48 3768 */
Freescale_cup 0:3ec7fc598e48 3769
Freescale_cup 0:3ec7fc598e48 3770 /* MCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 3771 #define PIT_MCR_FRZ_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3772 #define PIT_MCR_FRZ_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3773 #define PIT_MCR_MDIS_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 3774 #define PIT_MCR_MDIS_SHIFT 1
Freescale_cup 0:3ec7fc598e48 3775 /* LTMR64H Bit Fields */
Freescale_cup 0:3ec7fc598e48 3776 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3777 #define PIT_LTMR64H_LTH_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3778 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
Freescale_cup 0:3ec7fc598e48 3779 /* LTMR64L Bit Fields */
Freescale_cup 0:3ec7fc598e48 3780 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3781 #define PIT_LTMR64L_LTL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3782 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
Freescale_cup 0:3ec7fc598e48 3783 /* LDVAL Bit Fields */
Freescale_cup 0:3ec7fc598e48 3784 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3785 #define PIT_LDVAL_TSV_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3786 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
Freescale_cup 0:3ec7fc598e48 3787 /* CVAL Bit Fields */
Freescale_cup 0:3ec7fc598e48 3788 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 3789 #define PIT_CVAL_TVL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3790 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
Freescale_cup 0:3ec7fc598e48 3791 /* TCTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 3792 #define PIT_TCTRL_TEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3793 #define PIT_TCTRL_TEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3794 #define PIT_TCTRL_TIE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 3795 #define PIT_TCTRL_TIE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 3796 #define PIT_TCTRL_CHN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 3797 #define PIT_TCTRL_CHN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 3798 /* TFLG Bit Fields */
Freescale_cup 0:3ec7fc598e48 3799 #define PIT_TFLG_TIF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3800 #define PIT_TFLG_TIF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3801
Freescale_cup 0:3ec7fc598e48 3802 /*!
Freescale_cup 0:3ec7fc598e48 3803 * @}
Freescale_cup 0:3ec7fc598e48 3804 */ /* end of group PIT_Register_Masks */
Freescale_cup 0:3ec7fc598e48 3805
Freescale_cup 0:3ec7fc598e48 3806
Freescale_cup 0:3ec7fc598e48 3807 /* PIT - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 3808 /** Peripheral PIT base pointer */
Freescale_cup 0:3ec7fc598e48 3809 #define PIT_BASE_PTR ((PIT_MemMapPtr)0x40037000u)
Freescale_cup 0:3ec7fc598e48 3810 /** Array initializer of PIT peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 3811 #define PIT_BASE_PTRS { PIT_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 3812
Freescale_cup 0:3ec7fc598e48 3813 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3814 -- PIT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3815 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3816
Freescale_cup 0:3ec7fc598e48 3817 /*!
Freescale_cup 0:3ec7fc598e48 3818 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3819 * @{
Freescale_cup 0:3ec7fc598e48 3820 */
Freescale_cup 0:3ec7fc598e48 3821
Freescale_cup 0:3ec7fc598e48 3822
Freescale_cup 0:3ec7fc598e48 3823 /* PIT - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 3824 /* PIT */
Freescale_cup 0:3ec7fc598e48 3825 #define PIT_MCR PIT_MCR_REG(PIT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3826 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3827 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3828 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3829 #define PIT_CVAL0 PIT_CVAL_REG(PIT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3830 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3831 #define PIT_TFLG0 PIT_TFLG_REG(PIT_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 3832 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3833 #define PIT_CVAL1 PIT_CVAL_REG(PIT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3834 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3835 #define PIT_TFLG1 PIT_TFLG_REG(PIT_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 3836
Freescale_cup 0:3ec7fc598e48 3837 /* PIT - Register array accessors */
Freescale_cup 0:3ec7fc598e48 3838 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3839 #define PIT_CVAL(index) PIT_CVAL_REG(PIT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3840 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3841 #define PIT_TFLG(index) PIT_TFLG_REG(PIT_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 3842
Freescale_cup 0:3ec7fc598e48 3843 /*!
Freescale_cup 0:3ec7fc598e48 3844 * @}
Freescale_cup 0:3ec7fc598e48 3845 */ /* end of group PIT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3846
Freescale_cup 0:3ec7fc598e48 3847
Freescale_cup 0:3ec7fc598e48 3848 /*!
Freescale_cup 0:3ec7fc598e48 3849 * @}
Freescale_cup 0:3ec7fc598e48 3850 */ /* end of group PIT_Peripheral */
Freescale_cup 0:3ec7fc598e48 3851
Freescale_cup 0:3ec7fc598e48 3852
Freescale_cup 0:3ec7fc598e48 3853 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3854 -- PMC
Freescale_cup 0:3ec7fc598e48 3855 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3856
Freescale_cup 0:3ec7fc598e48 3857 /*!
Freescale_cup 0:3ec7fc598e48 3858 * @addtogroup PMC_Peripheral PMC
Freescale_cup 0:3ec7fc598e48 3859 * @{
Freescale_cup 0:3ec7fc598e48 3860 */
Freescale_cup 0:3ec7fc598e48 3861
Freescale_cup 0:3ec7fc598e48 3862 /** PMC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3863 typedef struct PMC_MemMap {
Freescale_cup 0:3ec7fc598e48 3864 uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 3865 uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 3866 uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 3867 } volatile *PMC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3868
Freescale_cup 0:3ec7fc598e48 3869 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3870 -- PMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3871 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3872
Freescale_cup 0:3ec7fc598e48 3873 /*!
Freescale_cup 0:3ec7fc598e48 3874 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3875 * @{
Freescale_cup 0:3ec7fc598e48 3876 */
Freescale_cup 0:3ec7fc598e48 3877
Freescale_cup 0:3ec7fc598e48 3878
Freescale_cup 0:3ec7fc598e48 3879 /* PMC - Register accessors */
Freescale_cup 0:3ec7fc598e48 3880 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
Freescale_cup 0:3ec7fc598e48 3881 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
Freescale_cup 0:3ec7fc598e48 3882 #define PMC_REGSC_REG(base) ((base)->REGSC)
Freescale_cup 0:3ec7fc598e48 3883
Freescale_cup 0:3ec7fc598e48 3884 /*!
Freescale_cup 0:3ec7fc598e48 3885 * @}
Freescale_cup 0:3ec7fc598e48 3886 */ /* end of group PMC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3887
Freescale_cup 0:3ec7fc598e48 3888
Freescale_cup 0:3ec7fc598e48 3889 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3890 -- PMC Register Masks
Freescale_cup 0:3ec7fc598e48 3891 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3892
Freescale_cup 0:3ec7fc598e48 3893 /*!
Freescale_cup 0:3ec7fc598e48 3894 * @addtogroup PMC_Register_Masks PMC Register Masks
Freescale_cup 0:3ec7fc598e48 3895 * @{
Freescale_cup 0:3ec7fc598e48 3896 */
Freescale_cup 0:3ec7fc598e48 3897
Freescale_cup 0:3ec7fc598e48 3898 /* LVDSC1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3899 #define PMC_LVDSC1_LVDV_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 3900 #define PMC_LVDSC1_LVDV_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3901 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
Freescale_cup 0:3ec7fc598e48 3902 #define PMC_LVDSC1_LVDRE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 3903 #define PMC_LVDSC1_LVDRE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 3904 #define PMC_LVDSC1_LVDIE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 3905 #define PMC_LVDSC1_LVDIE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 3906 #define PMC_LVDSC1_LVDACK_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 3907 #define PMC_LVDSC1_LVDACK_SHIFT 6
Freescale_cup 0:3ec7fc598e48 3908 #define PMC_LVDSC1_LVDF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 3909 #define PMC_LVDSC1_LVDF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 3910 /* LVDSC2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 3911 #define PMC_LVDSC2_LVWV_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 3912 #define PMC_LVDSC2_LVWV_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3913 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
Freescale_cup 0:3ec7fc598e48 3914 #define PMC_LVDSC2_LVWIE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 3915 #define PMC_LVDSC2_LVWIE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 3916 #define PMC_LVDSC2_LVWACK_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 3917 #define PMC_LVDSC2_LVWACK_SHIFT 6
Freescale_cup 0:3ec7fc598e48 3918 #define PMC_LVDSC2_LVWF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 3919 #define PMC_LVDSC2_LVWF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 3920 /* REGSC Bit Fields */
Freescale_cup 0:3ec7fc598e48 3921 #define PMC_REGSC_BGBE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 3922 #define PMC_REGSC_BGBE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 3923 #define PMC_REGSC_REGONS_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 3924 #define PMC_REGSC_REGONS_SHIFT 2
Freescale_cup 0:3ec7fc598e48 3925 #define PMC_REGSC_ACKISO_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 3926 #define PMC_REGSC_ACKISO_SHIFT 3
Freescale_cup 0:3ec7fc598e48 3927 #define PMC_REGSC_BGEN_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 3928 #define PMC_REGSC_BGEN_SHIFT 4
Freescale_cup 0:3ec7fc598e48 3929
Freescale_cup 0:3ec7fc598e48 3930 /*!
Freescale_cup 0:3ec7fc598e48 3931 * @}
Freescale_cup 0:3ec7fc598e48 3932 */ /* end of group PMC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 3933
Freescale_cup 0:3ec7fc598e48 3934
Freescale_cup 0:3ec7fc598e48 3935 /* PMC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 3936 /** Peripheral PMC base pointer */
Freescale_cup 0:3ec7fc598e48 3937 #define PMC_BASE_PTR ((PMC_MemMapPtr)0x4007D000u)
Freescale_cup 0:3ec7fc598e48 3938 /** Array initializer of PMC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 3939 #define PMC_BASE_PTRS { PMC_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 3940
Freescale_cup 0:3ec7fc598e48 3941 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3942 -- PMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3943 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3944
Freescale_cup 0:3ec7fc598e48 3945 /*!
Freescale_cup 0:3ec7fc598e48 3946 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3947 * @{
Freescale_cup 0:3ec7fc598e48 3948 */
Freescale_cup 0:3ec7fc598e48 3949
Freescale_cup 0:3ec7fc598e48 3950
Freescale_cup 0:3ec7fc598e48 3951 /* PMC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 3952 /* PMC */
Freescale_cup 0:3ec7fc598e48 3953 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3954 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3955 #define PMC_REGSC PMC_REGSC_REG(PMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 3956
Freescale_cup 0:3ec7fc598e48 3957 /*!
Freescale_cup 0:3ec7fc598e48 3958 * @}
Freescale_cup 0:3ec7fc598e48 3959 */ /* end of group PMC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 3960
Freescale_cup 0:3ec7fc598e48 3961
Freescale_cup 0:3ec7fc598e48 3962 /*!
Freescale_cup 0:3ec7fc598e48 3963 * @}
Freescale_cup 0:3ec7fc598e48 3964 */ /* end of group PMC_Peripheral */
Freescale_cup 0:3ec7fc598e48 3965
Freescale_cup 0:3ec7fc598e48 3966
Freescale_cup 0:3ec7fc598e48 3967 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3968 -- PORT
Freescale_cup 0:3ec7fc598e48 3969 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3970
Freescale_cup 0:3ec7fc598e48 3971 /*!
Freescale_cup 0:3ec7fc598e48 3972 * @addtogroup PORT_Peripheral PORT
Freescale_cup 0:3ec7fc598e48 3973 * @{
Freescale_cup 0:3ec7fc598e48 3974 */
Freescale_cup 0:3ec7fc598e48 3975
Freescale_cup 0:3ec7fc598e48 3976 /** PORT - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 3977 typedef struct PORT_MemMap {
Freescale_cup 0:3ec7fc598e48 3978 uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 3979 uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
Freescale_cup 0:3ec7fc598e48 3980 uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
Freescale_cup 0:3ec7fc598e48 3981 uint8_t RESERVED_0[24];
Freescale_cup 0:3ec7fc598e48 3982 uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
Freescale_cup 0:3ec7fc598e48 3983 } volatile *PORT_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 3984
Freescale_cup 0:3ec7fc598e48 3985 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 3986 -- PORT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3987 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 3988
Freescale_cup 0:3ec7fc598e48 3989 /*!
Freescale_cup 0:3ec7fc598e48 3990 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 3991 * @{
Freescale_cup 0:3ec7fc598e48 3992 */
Freescale_cup 0:3ec7fc598e48 3993
Freescale_cup 0:3ec7fc598e48 3994
Freescale_cup 0:3ec7fc598e48 3995 /* PORT - Register accessors */
Freescale_cup 0:3ec7fc598e48 3996 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
Freescale_cup 0:3ec7fc598e48 3997 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
Freescale_cup 0:3ec7fc598e48 3998 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
Freescale_cup 0:3ec7fc598e48 3999 #define PORT_ISFR_REG(base) ((base)->ISFR)
Freescale_cup 0:3ec7fc598e48 4000
Freescale_cup 0:3ec7fc598e48 4001 /*!
Freescale_cup 0:3ec7fc598e48 4002 * @}
Freescale_cup 0:3ec7fc598e48 4003 */ /* end of group PORT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4004
Freescale_cup 0:3ec7fc598e48 4005
Freescale_cup 0:3ec7fc598e48 4006 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4007 -- PORT Register Masks
Freescale_cup 0:3ec7fc598e48 4008 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4009
Freescale_cup 0:3ec7fc598e48 4010 /*!
Freescale_cup 0:3ec7fc598e48 4011 * @addtogroup PORT_Register_Masks PORT Register Masks
Freescale_cup 0:3ec7fc598e48 4012 * @{
Freescale_cup 0:3ec7fc598e48 4013 */
Freescale_cup 0:3ec7fc598e48 4014
Freescale_cup 0:3ec7fc598e48 4015 /* PCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4016 #define PORT_PCR_PS_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 4017 #define PORT_PCR_PS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4018 #define PORT_PCR_PE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4019 #define PORT_PCR_PE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4020 #define PORT_PCR_SRE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4021 #define PORT_PCR_SRE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4022 #define PORT_PCR_PFE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 4023 #define PORT_PCR_PFE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4024 #define PORT_PCR_DSE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 4025 #define PORT_PCR_DSE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 4026 #define PORT_PCR_MUX_MASK 0x700u
Freescale_cup 0:3ec7fc598e48 4027 #define PORT_PCR_MUX_SHIFT 8
Freescale_cup 0:3ec7fc598e48 4028 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
Freescale_cup 0:3ec7fc598e48 4029 #define PORT_PCR_IRQC_MASK 0xF0000u
Freescale_cup 0:3ec7fc598e48 4030 #define PORT_PCR_IRQC_SHIFT 16
Freescale_cup 0:3ec7fc598e48 4031 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
Freescale_cup 0:3ec7fc598e48 4032 #define PORT_PCR_ISF_MASK 0x1000000u
Freescale_cup 0:3ec7fc598e48 4033 #define PORT_PCR_ISF_SHIFT 24
Freescale_cup 0:3ec7fc598e48 4034 /* GPCLR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4035 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 4036 #define PORT_GPCLR_GPWD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4037 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
Freescale_cup 0:3ec7fc598e48 4038 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
Freescale_cup 0:3ec7fc598e48 4039 #define PORT_GPCLR_GPWE_SHIFT 16
Freescale_cup 0:3ec7fc598e48 4040 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
Freescale_cup 0:3ec7fc598e48 4041 /* GPCHR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4042 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 4043 #define PORT_GPCHR_GPWD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4044 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
Freescale_cup 0:3ec7fc598e48 4045 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
Freescale_cup 0:3ec7fc598e48 4046 #define PORT_GPCHR_GPWE_SHIFT 16
Freescale_cup 0:3ec7fc598e48 4047 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
Freescale_cup 0:3ec7fc598e48 4048 /* ISFR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4049 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4050 #define PORT_ISFR_ISF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4051 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
Freescale_cup 0:3ec7fc598e48 4052
Freescale_cup 0:3ec7fc598e48 4053 /*!
Freescale_cup 0:3ec7fc598e48 4054 * @}
Freescale_cup 0:3ec7fc598e48 4055 */ /* end of group PORT_Register_Masks */
Freescale_cup 0:3ec7fc598e48 4056
Freescale_cup 0:3ec7fc598e48 4057
Freescale_cup 0:3ec7fc598e48 4058 /* PORT - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 4059 /** Peripheral PORTA base pointer */
Freescale_cup 0:3ec7fc598e48 4060 #define PORTA_BASE_PTR ((PORT_MemMapPtr)0x40049000u)
Freescale_cup 0:3ec7fc598e48 4061 /** Peripheral PORTB base pointer */
Freescale_cup 0:3ec7fc598e48 4062 #define PORTB_BASE_PTR ((PORT_MemMapPtr)0x4004A000u)
Freescale_cup 0:3ec7fc598e48 4063 /** Peripheral PORTC base pointer */
Freescale_cup 0:3ec7fc598e48 4064 #define PORTC_BASE_PTR ((PORT_MemMapPtr)0x4004B000u)
Freescale_cup 0:3ec7fc598e48 4065 /** Peripheral PORTD base pointer */
Freescale_cup 0:3ec7fc598e48 4066 #define PORTD_BASE_PTR ((PORT_MemMapPtr)0x4004C000u)
Freescale_cup 0:3ec7fc598e48 4067 /** Peripheral PORTE base pointer */
Freescale_cup 0:3ec7fc598e48 4068 #define PORTE_BASE_PTR ((PORT_MemMapPtr)0x4004D000u)
Freescale_cup 0:3ec7fc598e48 4069 /** Array initializer of PORT peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 4070 #define PORT_BASE_PTRS { PORTA_BASE_PTR, PORTB_BASE_PTR, PORTC_BASE_PTR, PORTD_BASE_PTR, PORTE_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 4071
Freescale_cup 0:3ec7fc598e48 4072 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4073 -- PORT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4074 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4075
Freescale_cup 0:3ec7fc598e48 4076 /*!
Freescale_cup 0:3ec7fc598e48 4077 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4078 * @{
Freescale_cup 0:3ec7fc598e48 4079 */
Freescale_cup 0:3ec7fc598e48 4080
Freescale_cup 0:3ec7fc598e48 4081
Freescale_cup 0:3ec7fc598e48 4082 /* PORT - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 4083 /* PORTA */
Freescale_cup 0:3ec7fc598e48 4084 #define PORTA_PCR0 PORT_PCR_REG(PORTA_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4085 #define PORTA_PCR1 PORT_PCR_REG(PORTA_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4086 #define PORTA_PCR2 PORT_PCR_REG(PORTA_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4087 #define PORTA_PCR3 PORT_PCR_REG(PORTA_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 4088 #define PORTA_PCR4 PORT_PCR_REG(PORTA_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 4089 #define PORTA_PCR5 PORT_PCR_REG(PORTA_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 4090 #define PORTA_PCR6 PORT_PCR_REG(PORTA_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 4091 #define PORTA_PCR7 PORT_PCR_REG(PORTA_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 4092 #define PORTA_PCR8 PORT_PCR_REG(PORTA_BASE_PTR,8)
Freescale_cup 0:3ec7fc598e48 4093 #define PORTA_PCR9 PORT_PCR_REG(PORTA_BASE_PTR,9)
Freescale_cup 0:3ec7fc598e48 4094 #define PORTA_PCR10 PORT_PCR_REG(PORTA_BASE_PTR,10)
Freescale_cup 0:3ec7fc598e48 4095 #define PORTA_PCR11 PORT_PCR_REG(PORTA_BASE_PTR,11)
Freescale_cup 0:3ec7fc598e48 4096 #define PORTA_PCR12 PORT_PCR_REG(PORTA_BASE_PTR,12)
Freescale_cup 0:3ec7fc598e48 4097 #define PORTA_PCR13 PORT_PCR_REG(PORTA_BASE_PTR,13)
Freescale_cup 0:3ec7fc598e48 4098 #define PORTA_PCR14 PORT_PCR_REG(PORTA_BASE_PTR,14)
Freescale_cup 0:3ec7fc598e48 4099 #define PORTA_PCR15 PORT_PCR_REG(PORTA_BASE_PTR,15)
Freescale_cup 0:3ec7fc598e48 4100 #define PORTA_PCR16 PORT_PCR_REG(PORTA_BASE_PTR,16)
Freescale_cup 0:3ec7fc598e48 4101 #define PORTA_PCR17 PORT_PCR_REG(PORTA_BASE_PTR,17)
Freescale_cup 0:3ec7fc598e48 4102 #define PORTA_PCR18 PORT_PCR_REG(PORTA_BASE_PTR,18)
Freescale_cup 0:3ec7fc598e48 4103 #define PORTA_PCR19 PORT_PCR_REG(PORTA_BASE_PTR,19)
Freescale_cup 0:3ec7fc598e48 4104 #define PORTA_PCR20 PORT_PCR_REG(PORTA_BASE_PTR,20)
Freescale_cup 0:3ec7fc598e48 4105 #define PORTA_PCR21 PORT_PCR_REG(PORTA_BASE_PTR,21)
Freescale_cup 0:3ec7fc598e48 4106 #define PORTA_PCR22 PORT_PCR_REG(PORTA_BASE_PTR,22)
Freescale_cup 0:3ec7fc598e48 4107 #define PORTA_PCR23 PORT_PCR_REG(PORTA_BASE_PTR,23)
Freescale_cup 0:3ec7fc598e48 4108 #define PORTA_PCR24 PORT_PCR_REG(PORTA_BASE_PTR,24)
Freescale_cup 0:3ec7fc598e48 4109 #define PORTA_PCR25 PORT_PCR_REG(PORTA_BASE_PTR,25)
Freescale_cup 0:3ec7fc598e48 4110 #define PORTA_PCR26 PORT_PCR_REG(PORTA_BASE_PTR,26)
Freescale_cup 0:3ec7fc598e48 4111 #define PORTA_PCR27 PORT_PCR_REG(PORTA_BASE_PTR,27)
Freescale_cup 0:3ec7fc598e48 4112 #define PORTA_PCR28 PORT_PCR_REG(PORTA_BASE_PTR,28)
Freescale_cup 0:3ec7fc598e48 4113 #define PORTA_PCR29 PORT_PCR_REG(PORTA_BASE_PTR,29)
Freescale_cup 0:3ec7fc598e48 4114 #define PORTA_PCR30 PORT_PCR_REG(PORTA_BASE_PTR,30)
Freescale_cup 0:3ec7fc598e48 4115 #define PORTA_PCR31 PORT_PCR_REG(PORTA_BASE_PTR,31)
Freescale_cup 0:3ec7fc598e48 4116 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4117 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4118 #define PORTA_ISFR PORT_ISFR_REG(PORTA_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4119 /* PORTB */
Freescale_cup 0:3ec7fc598e48 4120 #define PORTB_PCR0 PORT_PCR_REG(PORTB_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4121 #define PORTB_PCR1 PORT_PCR_REG(PORTB_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4122 #define PORTB_PCR2 PORT_PCR_REG(PORTB_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4123 #define PORTB_PCR3 PORT_PCR_REG(PORTB_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 4124 #define PORTB_PCR4 PORT_PCR_REG(PORTB_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 4125 #define PORTB_PCR5 PORT_PCR_REG(PORTB_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 4126 #define PORTB_PCR6 PORT_PCR_REG(PORTB_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 4127 #define PORTB_PCR7 PORT_PCR_REG(PORTB_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 4128 #define PORTB_PCR8 PORT_PCR_REG(PORTB_BASE_PTR,8)
Freescale_cup 0:3ec7fc598e48 4129 #define PORTB_PCR9 PORT_PCR_REG(PORTB_BASE_PTR,9)
Freescale_cup 0:3ec7fc598e48 4130 #define PORTB_PCR10 PORT_PCR_REG(PORTB_BASE_PTR,10)
Freescale_cup 0:3ec7fc598e48 4131 #define PORTB_PCR11 PORT_PCR_REG(PORTB_BASE_PTR,11)
Freescale_cup 0:3ec7fc598e48 4132 #define PORTB_PCR12 PORT_PCR_REG(PORTB_BASE_PTR,12)
Freescale_cup 0:3ec7fc598e48 4133 #define PORTB_PCR13 PORT_PCR_REG(PORTB_BASE_PTR,13)
Freescale_cup 0:3ec7fc598e48 4134 #define PORTB_PCR14 PORT_PCR_REG(PORTB_BASE_PTR,14)
Freescale_cup 0:3ec7fc598e48 4135 #define PORTB_PCR15 PORT_PCR_REG(PORTB_BASE_PTR,15)
Freescale_cup 0:3ec7fc598e48 4136 #define PORTB_PCR16 PORT_PCR_REG(PORTB_BASE_PTR,16)
Freescale_cup 0:3ec7fc598e48 4137 #define PORTB_PCR17 PORT_PCR_REG(PORTB_BASE_PTR,17)
Freescale_cup 0:3ec7fc598e48 4138 #define PORTB_PCR18 PORT_PCR_REG(PORTB_BASE_PTR,18)
Freescale_cup 0:3ec7fc598e48 4139 #define PORTB_PCR19 PORT_PCR_REG(PORTB_BASE_PTR,19)
Freescale_cup 0:3ec7fc598e48 4140 #define PORTB_PCR20 PORT_PCR_REG(PORTB_BASE_PTR,20)
Freescale_cup 0:3ec7fc598e48 4141 #define PORTB_PCR21 PORT_PCR_REG(PORTB_BASE_PTR,21)
Freescale_cup 0:3ec7fc598e48 4142 #define PORTB_PCR22 PORT_PCR_REG(PORTB_BASE_PTR,22)
Freescale_cup 0:3ec7fc598e48 4143 #define PORTB_PCR23 PORT_PCR_REG(PORTB_BASE_PTR,23)
Freescale_cup 0:3ec7fc598e48 4144 #define PORTB_PCR24 PORT_PCR_REG(PORTB_BASE_PTR,24)
Freescale_cup 0:3ec7fc598e48 4145 #define PORTB_PCR25 PORT_PCR_REG(PORTB_BASE_PTR,25)
Freescale_cup 0:3ec7fc598e48 4146 #define PORTB_PCR26 PORT_PCR_REG(PORTB_BASE_PTR,26)
Freescale_cup 0:3ec7fc598e48 4147 #define PORTB_PCR27 PORT_PCR_REG(PORTB_BASE_PTR,27)
Freescale_cup 0:3ec7fc598e48 4148 #define PORTB_PCR28 PORT_PCR_REG(PORTB_BASE_PTR,28)
Freescale_cup 0:3ec7fc598e48 4149 #define PORTB_PCR29 PORT_PCR_REG(PORTB_BASE_PTR,29)
Freescale_cup 0:3ec7fc598e48 4150 #define PORTB_PCR30 PORT_PCR_REG(PORTB_BASE_PTR,30)
Freescale_cup 0:3ec7fc598e48 4151 #define PORTB_PCR31 PORT_PCR_REG(PORTB_BASE_PTR,31)
Freescale_cup 0:3ec7fc598e48 4152 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4153 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4154 #define PORTB_ISFR PORT_ISFR_REG(PORTB_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4155 /* PORTC */
Freescale_cup 0:3ec7fc598e48 4156 #define PORTC_PCR0 PORT_PCR_REG(PORTC_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4157 #define PORTC_PCR1 PORT_PCR_REG(PORTC_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4158 #define PORTC_PCR2 PORT_PCR_REG(PORTC_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4159 #define PORTC_PCR3 PORT_PCR_REG(PORTC_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 4160 #define PORTC_PCR4 PORT_PCR_REG(PORTC_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 4161 #define PORTC_PCR5 PORT_PCR_REG(PORTC_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 4162 #define PORTC_PCR6 PORT_PCR_REG(PORTC_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 4163 #define PORTC_PCR7 PORT_PCR_REG(PORTC_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 4164 #define PORTC_PCR8 PORT_PCR_REG(PORTC_BASE_PTR,8)
Freescale_cup 0:3ec7fc598e48 4165 #define PORTC_PCR9 PORT_PCR_REG(PORTC_BASE_PTR,9)
Freescale_cup 0:3ec7fc598e48 4166 #define PORTC_PCR10 PORT_PCR_REG(PORTC_BASE_PTR,10)
Freescale_cup 0:3ec7fc598e48 4167 #define PORTC_PCR11 PORT_PCR_REG(PORTC_BASE_PTR,11)
Freescale_cup 0:3ec7fc598e48 4168 #define PORTC_PCR12 PORT_PCR_REG(PORTC_BASE_PTR,12)
Freescale_cup 0:3ec7fc598e48 4169 #define PORTC_PCR13 PORT_PCR_REG(PORTC_BASE_PTR,13)
Freescale_cup 0:3ec7fc598e48 4170 #define PORTC_PCR14 PORT_PCR_REG(PORTC_BASE_PTR,14)
Freescale_cup 0:3ec7fc598e48 4171 #define PORTC_PCR15 PORT_PCR_REG(PORTC_BASE_PTR,15)
Freescale_cup 0:3ec7fc598e48 4172 #define PORTC_PCR16 PORT_PCR_REG(PORTC_BASE_PTR,16)
Freescale_cup 0:3ec7fc598e48 4173 #define PORTC_PCR17 PORT_PCR_REG(PORTC_BASE_PTR,17)
Freescale_cup 0:3ec7fc598e48 4174 #define PORTC_PCR18 PORT_PCR_REG(PORTC_BASE_PTR,18)
Freescale_cup 0:3ec7fc598e48 4175 #define PORTC_PCR19 PORT_PCR_REG(PORTC_BASE_PTR,19)
Freescale_cup 0:3ec7fc598e48 4176 #define PORTC_PCR20 PORT_PCR_REG(PORTC_BASE_PTR,20)
Freescale_cup 0:3ec7fc598e48 4177 #define PORTC_PCR21 PORT_PCR_REG(PORTC_BASE_PTR,21)
Freescale_cup 0:3ec7fc598e48 4178 #define PORTC_PCR22 PORT_PCR_REG(PORTC_BASE_PTR,22)
Freescale_cup 0:3ec7fc598e48 4179 #define PORTC_PCR23 PORT_PCR_REG(PORTC_BASE_PTR,23)
Freescale_cup 0:3ec7fc598e48 4180 #define PORTC_PCR24 PORT_PCR_REG(PORTC_BASE_PTR,24)
Freescale_cup 0:3ec7fc598e48 4181 #define PORTC_PCR25 PORT_PCR_REG(PORTC_BASE_PTR,25)
Freescale_cup 0:3ec7fc598e48 4182 #define PORTC_PCR26 PORT_PCR_REG(PORTC_BASE_PTR,26)
Freescale_cup 0:3ec7fc598e48 4183 #define PORTC_PCR27 PORT_PCR_REG(PORTC_BASE_PTR,27)
Freescale_cup 0:3ec7fc598e48 4184 #define PORTC_PCR28 PORT_PCR_REG(PORTC_BASE_PTR,28)
Freescale_cup 0:3ec7fc598e48 4185 #define PORTC_PCR29 PORT_PCR_REG(PORTC_BASE_PTR,29)
Freescale_cup 0:3ec7fc598e48 4186 #define PORTC_PCR30 PORT_PCR_REG(PORTC_BASE_PTR,30)
Freescale_cup 0:3ec7fc598e48 4187 #define PORTC_PCR31 PORT_PCR_REG(PORTC_BASE_PTR,31)
Freescale_cup 0:3ec7fc598e48 4188 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4189 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4190 #define PORTC_ISFR PORT_ISFR_REG(PORTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4191 /* PORTD */
Freescale_cup 0:3ec7fc598e48 4192 #define PORTD_PCR0 PORT_PCR_REG(PORTD_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4193 #define PORTD_PCR1 PORT_PCR_REG(PORTD_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4194 #define PORTD_PCR2 PORT_PCR_REG(PORTD_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4195 #define PORTD_PCR3 PORT_PCR_REG(PORTD_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 4196 #define PORTD_PCR4 PORT_PCR_REG(PORTD_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 4197 #define PORTD_PCR5 PORT_PCR_REG(PORTD_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 4198 #define PORTD_PCR6 PORT_PCR_REG(PORTD_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 4199 #define PORTD_PCR7 PORT_PCR_REG(PORTD_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 4200 #define PORTD_PCR8 PORT_PCR_REG(PORTD_BASE_PTR,8)
Freescale_cup 0:3ec7fc598e48 4201 #define PORTD_PCR9 PORT_PCR_REG(PORTD_BASE_PTR,9)
Freescale_cup 0:3ec7fc598e48 4202 #define PORTD_PCR10 PORT_PCR_REG(PORTD_BASE_PTR,10)
Freescale_cup 0:3ec7fc598e48 4203 #define PORTD_PCR11 PORT_PCR_REG(PORTD_BASE_PTR,11)
Freescale_cup 0:3ec7fc598e48 4204 #define PORTD_PCR12 PORT_PCR_REG(PORTD_BASE_PTR,12)
Freescale_cup 0:3ec7fc598e48 4205 #define PORTD_PCR13 PORT_PCR_REG(PORTD_BASE_PTR,13)
Freescale_cup 0:3ec7fc598e48 4206 #define PORTD_PCR14 PORT_PCR_REG(PORTD_BASE_PTR,14)
Freescale_cup 0:3ec7fc598e48 4207 #define PORTD_PCR15 PORT_PCR_REG(PORTD_BASE_PTR,15)
Freescale_cup 0:3ec7fc598e48 4208 #define PORTD_PCR16 PORT_PCR_REG(PORTD_BASE_PTR,16)
Freescale_cup 0:3ec7fc598e48 4209 #define PORTD_PCR17 PORT_PCR_REG(PORTD_BASE_PTR,17)
Freescale_cup 0:3ec7fc598e48 4210 #define PORTD_PCR18 PORT_PCR_REG(PORTD_BASE_PTR,18)
Freescale_cup 0:3ec7fc598e48 4211 #define PORTD_PCR19 PORT_PCR_REG(PORTD_BASE_PTR,19)
Freescale_cup 0:3ec7fc598e48 4212 #define PORTD_PCR20 PORT_PCR_REG(PORTD_BASE_PTR,20)
Freescale_cup 0:3ec7fc598e48 4213 #define PORTD_PCR21 PORT_PCR_REG(PORTD_BASE_PTR,21)
Freescale_cup 0:3ec7fc598e48 4214 #define PORTD_PCR22 PORT_PCR_REG(PORTD_BASE_PTR,22)
Freescale_cup 0:3ec7fc598e48 4215 #define PORTD_PCR23 PORT_PCR_REG(PORTD_BASE_PTR,23)
Freescale_cup 0:3ec7fc598e48 4216 #define PORTD_PCR24 PORT_PCR_REG(PORTD_BASE_PTR,24)
Freescale_cup 0:3ec7fc598e48 4217 #define PORTD_PCR25 PORT_PCR_REG(PORTD_BASE_PTR,25)
Freescale_cup 0:3ec7fc598e48 4218 #define PORTD_PCR26 PORT_PCR_REG(PORTD_BASE_PTR,26)
Freescale_cup 0:3ec7fc598e48 4219 #define PORTD_PCR27 PORT_PCR_REG(PORTD_BASE_PTR,27)
Freescale_cup 0:3ec7fc598e48 4220 #define PORTD_PCR28 PORT_PCR_REG(PORTD_BASE_PTR,28)
Freescale_cup 0:3ec7fc598e48 4221 #define PORTD_PCR29 PORT_PCR_REG(PORTD_BASE_PTR,29)
Freescale_cup 0:3ec7fc598e48 4222 #define PORTD_PCR30 PORT_PCR_REG(PORTD_BASE_PTR,30)
Freescale_cup 0:3ec7fc598e48 4223 #define PORTD_PCR31 PORT_PCR_REG(PORTD_BASE_PTR,31)
Freescale_cup 0:3ec7fc598e48 4224 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4225 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4226 #define PORTD_ISFR PORT_ISFR_REG(PORTD_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4227 /* PORTE */
Freescale_cup 0:3ec7fc598e48 4228 #define PORTE_PCR0 PORT_PCR_REG(PORTE_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4229 #define PORTE_PCR1 PORT_PCR_REG(PORTE_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4230 #define PORTE_PCR2 PORT_PCR_REG(PORTE_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4231 #define PORTE_PCR3 PORT_PCR_REG(PORTE_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 4232 #define PORTE_PCR4 PORT_PCR_REG(PORTE_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 4233 #define PORTE_PCR5 PORT_PCR_REG(PORTE_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 4234 #define PORTE_PCR6 PORT_PCR_REG(PORTE_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 4235 #define PORTE_PCR7 PORT_PCR_REG(PORTE_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 4236 #define PORTE_PCR8 PORT_PCR_REG(PORTE_BASE_PTR,8)
Freescale_cup 0:3ec7fc598e48 4237 #define PORTE_PCR9 PORT_PCR_REG(PORTE_BASE_PTR,9)
Freescale_cup 0:3ec7fc598e48 4238 #define PORTE_PCR10 PORT_PCR_REG(PORTE_BASE_PTR,10)
Freescale_cup 0:3ec7fc598e48 4239 #define PORTE_PCR11 PORT_PCR_REG(PORTE_BASE_PTR,11)
Freescale_cup 0:3ec7fc598e48 4240 #define PORTE_PCR12 PORT_PCR_REG(PORTE_BASE_PTR,12)
Freescale_cup 0:3ec7fc598e48 4241 #define PORTE_PCR13 PORT_PCR_REG(PORTE_BASE_PTR,13)
Freescale_cup 0:3ec7fc598e48 4242 #define PORTE_PCR14 PORT_PCR_REG(PORTE_BASE_PTR,14)
Freescale_cup 0:3ec7fc598e48 4243 #define PORTE_PCR15 PORT_PCR_REG(PORTE_BASE_PTR,15)
Freescale_cup 0:3ec7fc598e48 4244 #define PORTE_PCR16 PORT_PCR_REG(PORTE_BASE_PTR,16)
Freescale_cup 0:3ec7fc598e48 4245 #define PORTE_PCR17 PORT_PCR_REG(PORTE_BASE_PTR,17)
Freescale_cup 0:3ec7fc598e48 4246 #define PORTE_PCR18 PORT_PCR_REG(PORTE_BASE_PTR,18)
Freescale_cup 0:3ec7fc598e48 4247 #define PORTE_PCR19 PORT_PCR_REG(PORTE_BASE_PTR,19)
Freescale_cup 0:3ec7fc598e48 4248 #define PORTE_PCR20 PORT_PCR_REG(PORTE_BASE_PTR,20)
Freescale_cup 0:3ec7fc598e48 4249 #define PORTE_PCR21 PORT_PCR_REG(PORTE_BASE_PTR,21)
Freescale_cup 0:3ec7fc598e48 4250 #define PORTE_PCR22 PORT_PCR_REG(PORTE_BASE_PTR,22)
Freescale_cup 0:3ec7fc598e48 4251 #define PORTE_PCR23 PORT_PCR_REG(PORTE_BASE_PTR,23)
Freescale_cup 0:3ec7fc598e48 4252 #define PORTE_PCR24 PORT_PCR_REG(PORTE_BASE_PTR,24)
Freescale_cup 0:3ec7fc598e48 4253 #define PORTE_PCR25 PORT_PCR_REG(PORTE_BASE_PTR,25)
Freescale_cup 0:3ec7fc598e48 4254 #define PORTE_PCR26 PORT_PCR_REG(PORTE_BASE_PTR,26)
Freescale_cup 0:3ec7fc598e48 4255 #define PORTE_PCR27 PORT_PCR_REG(PORTE_BASE_PTR,27)
Freescale_cup 0:3ec7fc598e48 4256 #define PORTE_PCR28 PORT_PCR_REG(PORTE_BASE_PTR,28)
Freescale_cup 0:3ec7fc598e48 4257 #define PORTE_PCR29 PORT_PCR_REG(PORTE_BASE_PTR,29)
Freescale_cup 0:3ec7fc598e48 4258 #define PORTE_PCR30 PORT_PCR_REG(PORTE_BASE_PTR,30)
Freescale_cup 0:3ec7fc598e48 4259 #define PORTE_PCR31 PORT_PCR_REG(PORTE_BASE_PTR,31)
Freescale_cup 0:3ec7fc598e48 4260 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4261 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4262 #define PORTE_ISFR PORT_ISFR_REG(PORTE_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4263
Freescale_cup 0:3ec7fc598e48 4264 /* PORT - Register array accessors */
Freescale_cup 0:3ec7fc598e48 4265 #define PORTA_PCR(index) PORT_PCR_REG(PORTA_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4266 #define PORTB_PCR(index) PORT_PCR_REG(PORTB_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4267 #define PORTC_PCR(index) PORT_PCR_REG(PORTC_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4268 #define PORTD_PCR(index) PORT_PCR_REG(PORTD_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4269 #define PORTE_PCR(index) PORT_PCR_REG(PORTE_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4270
Freescale_cup 0:3ec7fc598e48 4271 /*!
Freescale_cup 0:3ec7fc598e48 4272 * @}
Freescale_cup 0:3ec7fc598e48 4273 */ /* end of group PORT_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4274
Freescale_cup 0:3ec7fc598e48 4275
Freescale_cup 0:3ec7fc598e48 4276 /*!
Freescale_cup 0:3ec7fc598e48 4277 * @}
Freescale_cup 0:3ec7fc598e48 4278 */ /* end of group PORT_Peripheral */
Freescale_cup 0:3ec7fc598e48 4279
Freescale_cup 0:3ec7fc598e48 4280
Freescale_cup 0:3ec7fc598e48 4281 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4282 -- RCM
Freescale_cup 0:3ec7fc598e48 4283 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4284
Freescale_cup 0:3ec7fc598e48 4285 /*!
Freescale_cup 0:3ec7fc598e48 4286 * @addtogroup RCM_Peripheral RCM
Freescale_cup 0:3ec7fc598e48 4287 * @{
Freescale_cup 0:3ec7fc598e48 4288 */
Freescale_cup 0:3ec7fc598e48 4289
Freescale_cup 0:3ec7fc598e48 4290 /** RCM - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 4291 typedef struct RCM_MemMap {
Freescale_cup 0:3ec7fc598e48 4292 uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 4293 uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 4294 uint8_t RESERVED_0[2];
Freescale_cup 0:3ec7fc598e48 4295 uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 4296 uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 4297 } volatile *RCM_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 4298
Freescale_cup 0:3ec7fc598e48 4299 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4300 -- RCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4301 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4302
Freescale_cup 0:3ec7fc598e48 4303 /*!
Freescale_cup 0:3ec7fc598e48 4304 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4305 * @{
Freescale_cup 0:3ec7fc598e48 4306 */
Freescale_cup 0:3ec7fc598e48 4307
Freescale_cup 0:3ec7fc598e48 4308
Freescale_cup 0:3ec7fc598e48 4309 /* RCM - Register accessors */
Freescale_cup 0:3ec7fc598e48 4310 #define RCM_SRS0_REG(base) ((base)->SRS0)
Freescale_cup 0:3ec7fc598e48 4311 #define RCM_SRS1_REG(base) ((base)->SRS1)
Freescale_cup 0:3ec7fc598e48 4312 #define RCM_RPFC_REG(base) ((base)->RPFC)
Freescale_cup 0:3ec7fc598e48 4313 #define RCM_RPFW_REG(base) ((base)->RPFW)
Freescale_cup 0:3ec7fc598e48 4314
Freescale_cup 0:3ec7fc598e48 4315 /*!
Freescale_cup 0:3ec7fc598e48 4316 * @}
Freescale_cup 0:3ec7fc598e48 4317 */ /* end of group RCM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4318
Freescale_cup 0:3ec7fc598e48 4319
Freescale_cup 0:3ec7fc598e48 4320 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4321 -- RCM Register Masks
Freescale_cup 0:3ec7fc598e48 4322 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4323
Freescale_cup 0:3ec7fc598e48 4324 /*!
Freescale_cup 0:3ec7fc598e48 4325 * @addtogroup RCM_Register_Masks RCM Register Masks
Freescale_cup 0:3ec7fc598e48 4326 * @{
Freescale_cup 0:3ec7fc598e48 4327 */
Freescale_cup 0:3ec7fc598e48 4328
Freescale_cup 0:3ec7fc598e48 4329 /* SRS0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4330 #define RCM_SRS0_WAKEUP_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 4331 #define RCM_SRS0_WAKEUP_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4332 #define RCM_SRS0_LVD_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4333 #define RCM_SRS0_LVD_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4334 #define RCM_SRS0_LOC_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4335 #define RCM_SRS0_LOC_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4336 #define RCM_SRS0_LOL_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 4337 #define RCM_SRS0_LOL_SHIFT 3
Freescale_cup 0:3ec7fc598e48 4338 #define RCM_SRS0_WDOG_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 4339 #define RCM_SRS0_WDOG_SHIFT 5
Freescale_cup 0:3ec7fc598e48 4340 #define RCM_SRS0_PIN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 4341 #define RCM_SRS0_PIN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 4342 #define RCM_SRS0_POR_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 4343 #define RCM_SRS0_POR_SHIFT 7
Freescale_cup 0:3ec7fc598e48 4344 /* SRS1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4345 #define RCM_SRS1_LOCKUP_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4346 #define RCM_SRS1_LOCKUP_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4347 #define RCM_SRS1_SW_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4348 #define RCM_SRS1_SW_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4349 #define RCM_SRS1_MDM_AP_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 4350 #define RCM_SRS1_MDM_AP_SHIFT 3
Freescale_cup 0:3ec7fc598e48 4351 #define RCM_SRS1_SACKERR_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 4352 #define RCM_SRS1_SACKERR_SHIFT 5
Freescale_cup 0:3ec7fc598e48 4353 /* RPFC Bit Fields */
Freescale_cup 0:3ec7fc598e48 4354 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 4355 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4356 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
Freescale_cup 0:3ec7fc598e48 4357 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4358 #define RCM_RPFC_RSTFLTSS_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4359 /* RPFW Bit Fields */
Freescale_cup 0:3ec7fc598e48 4360 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 4361 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4362 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
Freescale_cup 0:3ec7fc598e48 4363
Freescale_cup 0:3ec7fc598e48 4364 /*!
Freescale_cup 0:3ec7fc598e48 4365 * @}
Freescale_cup 0:3ec7fc598e48 4366 */ /* end of group RCM_Register_Masks */
Freescale_cup 0:3ec7fc598e48 4367
Freescale_cup 0:3ec7fc598e48 4368
Freescale_cup 0:3ec7fc598e48 4369 /* RCM - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 4370 /** Peripheral RCM base pointer */
Freescale_cup 0:3ec7fc598e48 4371 #define RCM_BASE_PTR ((RCM_MemMapPtr)0x4007F000u)
Freescale_cup 0:3ec7fc598e48 4372 /** Array initializer of RCM peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 4373 #define RCM_BASE_PTRS { RCM_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 4374
Freescale_cup 0:3ec7fc598e48 4375 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4376 -- RCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4377 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4378
Freescale_cup 0:3ec7fc598e48 4379 /*!
Freescale_cup 0:3ec7fc598e48 4380 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4381 * @{
Freescale_cup 0:3ec7fc598e48 4382 */
Freescale_cup 0:3ec7fc598e48 4383
Freescale_cup 0:3ec7fc598e48 4384
Freescale_cup 0:3ec7fc598e48 4385 /* RCM - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 4386 /* RCM */
Freescale_cup 0:3ec7fc598e48 4387 #define RCM_SRS0 RCM_SRS0_REG(RCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4388 #define RCM_SRS1 RCM_SRS1_REG(RCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4389 #define RCM_RPFC RCM_RPFC_REG(RCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4390 #define RCM_RPFW RCM_RPFW_REG(RCM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4391
Freescale_cup 0:3ec7fc598e48 4392 /*!
Freescale_cup 0:3ec7fc598e48 4393 * @}
Freescale_cup 0:3ec7fc598e48 4394 */ /* end of group RCM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4395
Freescale_cup 0:3ec7fc598e48 4396
Freescale_cup 0:3ec7fc598e48 4397 /*!
Freescale_cup 0:3ec7fc598e48 4398 * @}
Freescale_cup 0:3ec7fc598e48 4399 */ /* end of group RCM_Peripheral */
Freescale_cup 0:3ec7fc598e48 4400
Freescale_cup 0:3ec7fc598e48 4401
Freescale_cup 0:3ec7fc598e48 4402 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4403 -- ROM
Freescale_cup 0:3ec7fc598e48 4404 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4405
Freescale_cup 0:3ec7fc598e48 4406 /*!
Freescale_cup 0:3ec7fc598e48 4407 * @addtogroup ROM_Peripheral ROM
Freescale_cup 0:3ec7fc598e48 4408 * @{
Freescale_cup 0:3ec7fc598e48 4409 */
Freescale_cup 0:3ec7fc598e48 4410
Freescale_cup 0:3ec7fc598e48 4411 /** ROM - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 4412 typedef struct ROM_MemMap {
Freescale_cup 0:3ec7fc598e48 4413 uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 4414 uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 4415 uint8_t RESERVED_0[4028];
Freescale_cup 0:3ec7fc598e48 4416 uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
Freescale_cup 0:3ec7fc598e48 4417 uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
Freescale_cup 0:3ec7fc598e48 4418 uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
Freescale_cup 0:3ec7fc598e48 4419 uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
Freescale_cup 0:3ec7fc598e48 4420 uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
Freescale_cup 0:3ec7fc598e48 4421 uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
Freescale_cup 0:3ec7fc598e48 4422 uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
Freescale_cup 0:3ec7fc598e48 4423 uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
Freescale_cup 0:3ec7fc598e48 4424 uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
Freescale_cup 0:3ec7fc598e48 4425 uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 4426 } volatile *ROM_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 4427
Freescale_cup 0:3ec7fc598e48 4428 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4429 -- ROM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4430 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4431
Freescale_cup 0:3ec7fc598e48 4432 /*!
Freescale_cup 0:3ec7fc598e48 4433 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4434 * @{
Freescale_cup 0:3ec7fc598e48 4435 */
Freescale_cup 0:3ec7fc598e48 4436
Freescale_cup 0:3ec7fc598e48 4437
Freescale_cup 0:3ec7fc598e48 4438 /* ROM - Register accessors */
Freescale_cup 0:3ec7fc598e48 4439 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
Freescale_cup 0:3ec7fc598e48 4440 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
Freescale_cup 0:3ec7fc598e48 4441 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
Freescale_cup 0:3ec7fc598e48 4442 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
Freescale_cup 0:3ec7fc598e48 4443 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
Freescale_cup 0:3ec7fc598e48 4444 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
Freescale_cup 0:3ec7fc598e48 4445 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
Freescale_cup 0:3ec7fc598e48 4446 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
Freescale_cup 0:3ec7fc598e48 4447 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
Freescale_cup 0:3ec7fc598e48 4448 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
Freescale_cup 0:3ec7fc598e48 4449 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
Freescale_cup 0:3ec7fc598e48 4450 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
Freescale_cup 0:3ec7fc598e48 4451
Freescale_cup 0:3ec7fc598e48 4452 /*!
Freescale_cup 0:3ec7fc598e48 4453 * @}
Freescale_cup 0:3ec7fc598e48 4454 */ /* end of group ROM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4455
Freescale_cup 0:3ec7fc598e48 4456
Freescale_cup 0:3ec7fc598e48 4457 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4458 -- ROM Register Masks
Freescale_cup 0:3ec7fc598e48 4459 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4460
Freescale_cup 0:3ec7fc598e48 4461 /*!
Freescale_cup 0:3ec7fc598e48 4462 * @addtogroup ROM_Register_Masks ROM Register Masks
Freescale_cup 0:3ec7fc598e48 4463 * @{
Freescale_cup 0:3ec7fc598e48 4464 */
Freescale_cup 0:3ec7fc598e48 4465
Freescale_cup 0:3ec7fc598e48 4466 /* ENTRY Bit Fields */
Freescale_cup 0:3ec7fc598e48 4467 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4468 #define ROM_ENTRY_ENTRY_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4469 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
Freescale_cup 0:3ec7fc598e48 4470 /* TABLEMARK Bit Fields */
Freescale_cup 0:3ec7fc598e48 4471 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4472 #define ROM_TABLEMARK_MARK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4473 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
Freescale_cup 0:3ec7fc598e48 4474 /* SYSACCESS Bit Fields */
Freescale_cup 0:3ec7fc598e48 4475 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4476 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4477 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
Freescale_cup 0:3ec7fc598e48 4478 /* PERIPHID4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4479 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4480 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4481 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4482 /* PERIPHID5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4483 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4484 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4485 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4486 /* PERIPHID6 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4487 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4488 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4489 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4490 /* PERIPHID7 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4491 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4492 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4493 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4494 /* PERIPHID0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4495 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4496 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4497 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4498 /* PERIPHID1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4499 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4500 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4501 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4502 /* PERIPHID2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4503 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4504 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4505 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4506 /* PERIPHID3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4507 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4508 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4509 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
Freescale_cup 0:3ec7fc598e48 4510 /* COMPID Bit Fields */
Freescale_cup 0:3ec7fc598e48 4511 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4512 #define ROM_COMPID_COMPID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4513 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
Freescale_cup 0:3ec7fc598e48 4514
Freescale_cup 0:3ec7fc598e48 4515 /*!
Freescale_cup 0:3ec7fc598e48 4516 * @}
Freescale_cup 0:3ec7fc598e48 4517 */ /* end of group ROM_Register_Masks */
Freescale_cup 0:3ec7fc598e48 4518
Freescale_cup 0:3ec7fc598e48 4519
Freescale_cup 0:3ec7fc598e48 4520 /* ROM - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 4521 /** Peripheral ROM base pointer */
Freescale_cup 0:3ec7fc598e48 4522 #define ROM_BASE_PTR ((ROM_MemMapPtr)0xF0002000u)
Freescale_cup 0:3ec7fc598e48 4523 /** Array initializer of ROM peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 4524 #define ROM_BASE_PTRS { ROM_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 4525
Freescale_cup 0:3ec7fc598e48 4526 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4527 -- ROM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4528 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4529
Freescale_cup 0:3ec7fc598e48 4530 /*!
Freescale_cup 0:3ec7fc598e48 4531 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4532 * @{
Freescale_cup 0:3ec7fc598e48 4533 */
Freescale_cup 0:3ec7fc598e48 4534
Freescale_cup 0:3ec7fc598e48 4535
Freescale_cup 0:3ec7fc598e48 4536 /* ROM - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 4537 /* ROM */
Freescale_cup 0:3ec7fc598e48 4538 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4539 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4540 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4541 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4542 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4543 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4544 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4545 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4546 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4547 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4548 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4549 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4550 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4551 #define ROM_COMPID0 ROM_COMPID_REG(ROM_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 4552 #define ROM_COMPID1 ROM_COMPID_REG(ROM_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 4553 #define ROM_COMPID2 ROM_COMPID_REG(ROM_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 4554 #define ROM_COMPID3 ROM_COMPID_REG(ROM_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 4555
Freescale_cup 0:3ec7fc598e48 4556 /* ROM - Register array accessors */
Freescale_cup 0:3ec7fc598e48 4557 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4558 #define ROM_COMPID(index) ROM_COMPID_REG(ROM_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 4559
Freescale_cup 0:3ec7fc598e48 4560 /*!
Freescale_cup 0:3ec7fc598e48 4561 * @}
Freescale_cup 0:3ec7fc598e48 4562 */ /* end of group ROM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4563
Freescale_cup 0:3ec7fc598e48 4564
Freescale_cup 0:3ec7fc598e48 4565 /*!
Freescale_cup 0:3ec7fc598e48 4566 * @}
Freescale_cup 0:3ec7fc598e48 4567 */ /* end of group ROM_Peripheral */
Freescale_cup 0:3ec7fc598e48 4568
Freescale_cup 0:3ec7fc598e48 4569
Freescale_cup 0:3ec7fc598e48 4570 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4571 -- RTC
Freescale_cup 0:3ec7fc598e48 4572 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4573
Freescale_cup 0:3ec7fc598e48 4574 /*!
Freescale_cup 0:3ec7fc598e48 4575 * @addtogroup RTC_Peripheral RTC
Freescale_cup 0:3ec7fc598e48 4576 * @{
Freescale_cup 0:3ec7fc598e48 4577 */
Freescale_cup 0:3ec7fc598e48 4578
Freescale_cup 0:3ec7fc598e48 4579 /** RTC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 4580 typedef struct RTC_MemMap {
Freescale_cup 0:3ec7fc598e48 4581 uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 4582 uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 4583 uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 4584 uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 4585 uint32_t CR; /**< RTC Control Register, offset: 0x10 */
Freescale_cup 0:3ec7fc598e48 4586 uint32_t SR; /**< RTC Status Register, offset: 0x14 */
Freescale_cup 0:3ec7fc598e48 4587 uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
Freescale_cup 0:3ec7fc598e48 4588 uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
Freescale_cup 0:3ec7fc598e48 4589 } volatile *RTC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 4590
Freescale_cup 0:3ec7fc598e48 4591 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4592 -- RTC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4593 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4594
Freescale_cup 0:3ec7fc598e48 4595 /*!
Freescale_cup 0:3ec7fc598e48 4596 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4597 * @{
Freescale_cup 0:3ec7fc598e48 4598 */
Freescale_cup 0:3ec7fc598e48 4599
Freescale_cup 0:3ec7fc598e48 4600
Freescale_cup 0:3ec7fc598e48 4601 /* RTC - Register accessors */
Freescale_cup 0:3ec7fc598e48 4602 #define RTC_TSR_REG(base) ((base)->TSR)
Freescale_cup 0:3ec7fc598e48 4603 #define RTC_TPR_REG(base) ((base)->TPR)
Freescale_cup 0:3ec7fc598e48 4604 #define RTC_TAR_REG(base) ((base)->TAR)
Freescale_cup 0:3ec7fc598e48 4605 #define RTC_TCR_REG(base) ((base)->TCR)
Freescale_cup 0:3ec7fc598e48 4606 #define RTC_CR_REG(base) ((base)->CR)
Freescale_cup 0:3ec7fc598e48 4607 #define RTC_SR_REG(base) ((base)->SR)
Freescale_cup 0:3ec7fc598e48 4608 #define RTC_LR_REG(base) ((base)->LR)
Freescale_cup 0:3ec7fc598e48 4609 #define RTC_IER_REG(base) ((base)->IER)
Freescale_cup 0:3ec7fc598e48 4610
Freescale_cup 0:3ec7fc598e48 4611 /*!
Freescale_cup 0:3ec7fc598e48 4612 * @}
Freescale_cup 0:3ec7fc598e48 4613 */ /* end of group RTC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4614
Freescale_cup 0:3ec7fc598e48 4615
Freescale_cup 0:3ec7fc598e48 4616 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4617 -- RTC Register Masks
Freescale_cup 0:3ec7fc598e48 4618 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4619
Freescale_cup 0:3ec7fc598e48 4620 /*!
Freescale_cup 0:3ec7fc598e48 4621 * @addtogroup RTC_Register_Masks RTC Register Masks
Freescale_cup 0:3ec7fc598e48 4622 * @{
Freescale_cup 0:3ec7fc598e48 4623 */
Freescale_cup 0:3ec7fc598e48 4624
Freescale_cup 0:3ec7fc598e48 4625 /* TSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4626 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4627 #define RTC_TSR_TSR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4628 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
Freescale_cup 0:3ec7fc598e48 4629 /* TPR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4630 #define RTC_TPR_TPR_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 4631 #define RTC_TPR_TPR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4632 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
Freescale_cup 0:3ec7fc598e48 4633 /* TAR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4634 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 4635 #define RTC_TAR_TAR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4636 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
Freescale_cup 0:3ec7fc598e48 4637 /* TCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4638 #define RTC_TCR_TCR_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 4639 #define RTC_TCR_TCR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4640 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
Freescale_cup 0:3ec7fc598e48 4641 #define RTC_TCR_CIR_MASK 0xFF00u
Freescale_cup 0:3ec7fc598e48 4642 #define RTC_TCR_CIR_SHIFT 8
Freescale_cup 0:3ec7fc598e48 4643 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
Freescale_cup 0:3ec7fc598e48 4644 #define RTC_TCR_TCV_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 4645 #define RTC_TCR_TCV_SHIFT 16
Freescale_cup 0:3ec7fc598e48 4646 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
Freescale_cup 0:3ec7fc598e48 4647 #define RTC_TCR_CIC_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 4648 #define RTC_TCR_CIC_SHIFT 24
Freescale_cup 0:3ec7fc598e48 4649 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
Freescale_cup 0:3ec7fc598e48 4650 /* CR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4651 #define RTC_CR_SWR_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 4652 #define RTC_CR_SWR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4653 #define RTC_CR_WPE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4654 #define RTC_CR_WPE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4655 #define RTC_CR_SUP_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4656 #define RTC_CR_SUP_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4657 #define RTC_CR_UM_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 4658 #define RTC_CR_UM_SHIFT 3
Freescale_cup 0:3ec7fc598e48 4659 #define RTC_CR_OSCE_MASK 0x100u
Freescale_cup 0:3ec7fc598e48 4660 #define RTC_CR_OSCE_SHIFT 8
Freescale_cup 0:3ec7fc598e48 4661 #define RTC_CR_CLKO_MASK 0x200u
Freescale_cup 0:3ec7fc598e48 4662 #define RTC_CR_CLKO_SHIFT 9
Freescale_cup 0:3ec7fc598e48 4663 #define RTC_CR_SC16P_MASK 0x400u
Freescale_cup 0:3ec7fc598e48 4664 #define RTC_CR_SC16P_SHIFT 10
Freescale_cup 0:3ec7fc598e48 4665 #define RTC_CR_SC8P_MASK 0x800u
Freescale_cup 0:3ec7fc598e48 4666 #define RTC_CR_SC8P_SHIFT 11
Freescale_cup 0:3ec7fc598e48 4667 #define RTC_CR_SC4P_MASK 0x1000u
Freescale_cup 0:3ec7fc598e48 4668 #define RTC_CR_SC4P_SHIFT 12
Freescale_cup 0:3ec7fc598e48 4669 #define RTC_CR_SC2P_MASK 0x2000u
Freescale_cup 0:3ec7fc598e48 4670 #define RTC_CR_SC2P_SHIFT 13
Freescale_cup 0:3ec7fc598e48 4671 /* SR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4672 #define RTC_SR_TIF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 4673 #define RTC_SR_TIF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4674 #define RTC_SR_TOF_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4675 #define RTC_SR_TOF_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4676 #define RTC_SR_TAF_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4677 #define RTC_SR_TAF_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4678 #define RTC_SR_TCE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 4679 #define RTC_SR_TCE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4680 /* LR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4681 #define RTC_LR_TCL_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 4682 #define RTC_LR_TCL_SHIFT 3
Freescale_cup 0:3ec7fc598e48 4683 #define RTC_LR_CRL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 4684 #define RTC_LR_CRL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4685 #define RTC_LR_SRL_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 4686 #define RTC_LR_SRL_SHIFT 5
Freescale_cup 0:3ec7fc598e48 4687 #define RTC_LR_LRL_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 4688 #define RTC_LR_LRL_SHIFT 6
Freescale_cup 0:3ec7fc598e48 4689 /* IER Bit Fields */
Freescale_cup 0:3ec7fc598e48 4690 #define RTC_IER_TIIE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 4691 #define RTC_IER_TIIE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4692 #define RTC_IER_TOIE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4693 #define RTC_IER_TOIE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4694 #define RTC_IER_TAIE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4695 #define RTC_IER_TAIE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4696 #define RTC_IER_TSIE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 4697 #define RTC_IER_TSIE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4698 #define RTC_IER_WPON_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 4699 #define RTC_IER_WPON_SHIFT 7
Freescale_cup 0:3ec7fc598e48 4700
Freescale_cup 0:3ec7fc598e48 4701 /*!
Freescale_cup 0:3ec7fc598e48 4702 * @}
Freescale_cup 0:3ec7fc598e48 4703 */ /* end of group RTC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 4704
Freescale_cup 0:3ec7fc598e48 4705
Freescale_cup 0:3ec7fc598e48 4706 /* RTC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 4707 /** Peripheral RTC base pointer */
Freescale_cup 0:3ec7fc598e48 4708 #define RTC_BASE_PTR ((RTC_MemMapPtr)0x4003D000u)
Freescale_cup 0:3ec7fc598e48 4709 /** Array initializer of RTC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 4710 #define RTC_BASE_PTRS { RTC_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 4711
Freescale_cup 0:3ec7fc598e48 4712 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4713 -- RTC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4714 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4715
Freescale_cup 0:3ec7fc598e48 4716 /*!
Freescale_cup 0:3ec7fc598e48 4717 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4718 * @{
Freescale_cup 0:3ec7fc598e48 4719 */
Freescale_cup 0:3ec7fc598e48 4720
Freescale_cup 0:3ec7fc598e48 4721
Freescale_cup 0:3ec7fc598e48 4722 /* RTC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 4723 /* RTC */
Freescale_cup 0:3ec7fc598e48 4724 #define RTC_TSR RTC_TSR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4725 #define RTC_TPR RTC_TPR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4726 #define RTC_TAR RTC_TAR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4727 #define RTC_TCR RTC_TCR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4728 #define RTC_CR RTC_CR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4729 #define RTC_SR RTC_SR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4730 #define RTC_LR RTC_LR_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4731 #define RTC_IER RTC_IER_REG(RTC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4732
Freescale_cup 0:3ec7fc598e48 4733 /*!
Freescale_cup 0:3ec7fc598e48 4734 * @}
Freescale_cup 0:3ec7fc598e48 4735 */ /* end of group RTC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4736
Freescale_cup 0:3ec7fc598e48 4737
Freescale_cup 0:3ec7fc598e48 4738 /*!
Freescale_cup 0:3ec7fc598e48 4739 * @}
Freescale_cup 0:3ec7fc598e48 4740 */ /* end of group RTC_Peripheral */
Freescale_cup 0:3ec7fc598e48 4741
Freescale_cup 0:3ec7fc598e48 4742
Freescale_cup 0:3ec7fc598e48 4743 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4744 -- SCB
Freescale_cup 0:3ec7fc598e48 4745 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4746
Freescale_cup 0:3ec7fc598e48 4747 /*!
Freescale_cup 0:3ec7fc598e48 4748 * @addtogroup SCB_Peripheral SCB
Freescale_cup 0:3ec7fc598e48 4749 * @{
Freescale_cup 0:3ec7fc598e48 4750 */
Freescale_cup 0:3ec7fc598e48 4751
Freescale_cup 0:3ec7fc598e48 4752 /** SCB - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 4753 typedef struct SCB_MemMap {
Freescale_cup 0:3ec7fc598e48 4754 uint8_t RESERVED_0[8];
Freescale_cup 0:3ec7fc598e48 4755 uint32_t ACTLR; /**< Auxiliary Control Register,, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 4756 uint8_t RESERVED_1[3316];
Freescale_cup 0:3ec7fc598e48 4757 uint32_t CPUID; /**< CPUID Base Register, offset: 0xD00 */
Freescale_cup 0:3ec7fc598e48 4758 uint32_t ICSR; /**< Interrupt Control and State Register, offset: 0xD04 */
Freescale_cup 0:3ec7fc598e48 4759 uint32_t VTOR; /**< Vector Table Offset Register, offset: 0xD08 */
Freescale_cup 0:3ec7fc598e48 4760 uint32_t AIRCR; /**< Application Interrupt and Reset Control Register, offset: 0xD0C */
Freescale_cup 0:3ec7fc598e48 4761 uint32_t SCR; /**< System Control Register, offset: 0xD10 */
Freescale_cup 0:3ec7fc598e48 4762 uint32_t CCR; /**< Configuration and Control Register, offset: 0xD14 */
Freescale_cup 0:3ec7fc598e48 4763 uint8_t RESERVED_2[4];
Freescale_cup 0:3ec7fc598e48 4764 uint32_t SHPR2; /**< System Handler Priority Register 2, offset: 0xD1C */
Freescale_cup 0:3ec7fc598e48 4765 uint32_t SHPR3; /**< System Handler Priority Register 3, offset: 0xD20 */
Freescale_cup 0:3ec7fc598e48 4766 uint32_t SHCSR; /**< System Handler Control and State Register, offset: 0xD24 */
Freescale_cup 0:3ec7fc598e48 4767 uint8_t RESERVED_3[8];
Freescale_cup 0:3ec7fc598e48 4768 uint32_t DFSR; /**< Debug Fault Status Register, offset: 0xD30 */
Freescale_cup 0:3ec7fc598e48 4769 } volatile *SCB_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 4770
Freescale_cup 0:3ec7fc598e48 4771 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4772 -- SCB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4773 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4774
Freescale_cup 0:3ec7fc598e48 4775 /*!
Freescale_cup 0:3ec7fc598e48 4776 * @addtogroup SCB_Register_Accessor_Macros SCB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4777 * @{
Freescale_cup 0:3ec7fc598e48 4778 */
Freescale_cup 0:3ec7fc598e48 4779
Freescale_cup 0:3ec7fc598e48 4780
Freescale_cup 0:3ec7fc598e48 4781 /* SCB - Register accessors */
Freescale_cup 0:3ec7fc598e48 4782 #define SCB_ACTLR_REG(base) ((base)->ACTLR)
Freescale_cup 0:3ec7fc598e48 4783 #define SCB_CPUID_REG(base) ((base)->CPUID)
Freescale_cup 0:3ec7fc598e48 4784 #define SCB_ICSR_REG(base) ((base)->ICSR)
Freescale_cup 0:3ec7fc598e48 4785 #define SCB_VTOR_REG(base) ((base)->VTOR)
Freescale_cup 0:3ec7fc598e48 4786 #define SCB_AIRCR_REG(base) ((base)->AIRCR)
Freescale_cup 0:3ec7fc598e48 4787 #define SCB_SCR_REG(base) ((base)->SCR)
Freescale_cup 0:3ec7fc598e48 4788 #define SCB_CCR_REG(base) ((base)->CCR)
Freescale_cup 0:3ec7fc598e48 4789 #define SCB_SHPR2_REG(base) ((base)->SHPR2)
Freescale_cup 0:3ec7fc598e48 4790 #define SCB_SHPR3_REG(base) ((base)->SHPR3)
Freescale_cup 0:3ec7fc598e48 4791 #define SCB_SHCSR_REG(base) ((base)->SHCSR)
Freescale_cup 0:3ec7fc598e48 4792 #define SCB_DFSR_REG(base) ((base)->DFSR)
Freescale_cup 0:3ec7fc598e48 4793
Freescale_cup 0:3ec7fc598e48 4794 /*!
Freescale_cup 0:3ec7fc598e48 4795 * @}
Freescale_cup 0:3ec7fc598e48 4796 */ /* end of group SCB_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4797
Freescale_cup 0:3ec7fc598e48 4798
Freescale_cup 0:3ec7fc598e48 4799 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4800 -- SCB Register Masks
Freescale_cup 0:3ec7fc598e48 4801 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4802
Freescale_cup 0:3ec7fc598e48 4803 /*!
Freescale_cup 0:3ec7fc598e48 4804 * @addtogroup SCB_Register_Masks SCB Register Masks
Freescale_cup 0:3ec7fc598e48 4805 * @{
Freescale_cup 0:3ec7fc598e48 4806 */
Freescale_cup 0:3ec7fc598e48 4807
Freescale_cup 0:3ec7fc598e48 4808 /* CPUID Bit Fields */
Freescale_cup 0:3ec7fc598e48 4809 #define SCB_CPUID_REVISION_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 4810 #define SCB_CPUID_REVISION_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4811 #define SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_REVISION_SHIFT))&SCB_CPUID_REVISION_MASK)
Freescale_cup 0:3ec7fc598e48 4812 #define SCB_CPUID_PARTNO_MASK 0xFFF0u
Freescale_cup 0:3ec7fc598e48 4813 #define SCB_CPUID_PARTNO_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4814 #define SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_PARTNO_SHIFT))&SCB_CPUID_PARTNO_MASK)
Freescale_cup 0:3ec7fc598e48 4815 #define SCB_CPUID_VARIANT_MASK 0xF00000u
Freescale_cup 0:3ec7fc598e48 4816 #define SCB_CPUID_VARIANT_SHIFT 20
Freescale_cup 0:3ec7fc598e48 4817 #define SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_VARIANT_SHIFT))&SCB_CPUID_VARIANT_MASK)
Freescale_cup 0:3ec7fc598e48 4818 #define SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 4819 #define SCB_CPUID_IMPLEMENTER_SHIFT 24
Freescale_cup 0:3ec7fc598e48 4820 #define SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_IMPLEMENTER_SHIFT))&SCB_CPUID_IMPLEMENTER_MASK)
Freescale_cup 0:3ec7fc598e48 4821 /* ICSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4822 #define SCB_ICSR_VECTACTIVE_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 4823 #define SCB_ICSR_VECTACTIVE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4824 #define SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTACTIVE_SHIFT))&SCB_ICSR_VECTACTIVE_MASK)
Freescale_cup 0:3ec7fc598e48 4825 #define SCB_ICSR_VECTPENDING_MASK 0x3F000u
Freescale_cup 0:3ec7fc598e48 4826 #define SCB_ICSR_VECTPENDING_SHIFT 12
Freescale_cup 0:3ec7fc598e48 4827 #define SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTPENDING_SHIFT))&SCB_ICSR_VECTPENDING_MASK)
Freescale_cup 0:3ec7fc598e48 4828 #define SCB_ICSR_ISRPENDING_MASK 0x400000u
Freescale_cup 0:3ec7fc598e48 4829 #define SCB_ICSR_ISRPENDING_SHIFT 22
Freescale_cup 0:3ec7fc598e48 4830 #define SCB_ICSR_PENDSTCLR_MASK 0x2000000u
Freescale_cup 0:3ec7fc598e48 4831 #define SCB_ICSR_PENDSTCLR_SHIFT 25
Freescale_cup 0:3ec7fc598e48 4832 #define SCB_ICSR_PENDSTSET_MASK 0x4000000u
Freescale_cup 0:3ec7fc598e48 4833 #define SCB_ICSR_PENDSTSET_SHIFT 26
Freescale_cup 0:3ec7fc598e48 4834 #define SCB_ICSR_PENDSVCLR_MASK 0x8000000u
Freescale_cup 0:3ec7fc598e48 4835 #define SCB_ICSR_PENDSVCLR_SHIFT 27
Freescale_cup 0:3ec7fc598e48 4836 #define SCB_ICSR_PENDSVSET_MASK 0x10000000u
Freescale_cup 0:3ec7fc598e48 4837 #define SCB_ICSR_PENDSVSET_SHIFT 28
Freescale_cup 0:3ec7fc598e48 4838 #define SCB_ICSR_NMIPENDSET_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 4839 #define SCB_ICSR_NMIPENDSET_SHIFT 31
Freescale_cup 0:3ec7fc598e48 4840 /* VTOR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4841 #define SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u
Freescale_cup 0:3ec7fc598e48 4842 #define SCB_VTOR_TBLOFF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 4843 #define SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<SCB_VTOR_TBLOFF_SHIFT))&SCB_VTOR_TBLOFF_MASK)
Freescale_cup 0:3ec7fc598e48 4844 /* AIRCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4845 #define SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4846 #define SCB_AIRCR_VECTCLRACTIVE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4847 #define SCB_AIRCR_SYSRESETREQ_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4848 #define SCB_AIRCR_SYSRESETREQ_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4849 #define SCB_AIRCR_ENDIANNESS_MASK 0x8000u
Freescale_cup 0:3ec7fc598e48 4850 #define SCB_AIRCR_ENDIANNESS_SHIFT 15
Freescale_cup 0:3ec7fc598e48 4851 #define SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u
Freescale_cup 0:3ec7fc598e48 4852 #define SCB_AIRCR_VECTKEY_SHIFT 16
Freescale_cup 0:3ec7fc598e48 4853 #define SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<SCB_AIRCR_VECTKEY_SHIFT))&SCB_AIRCR_VECTKEY_MASK)
Freescale_cup 0:3ec7fc598e48 4854 /* SCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4855 #define SCB_SCR_SLEEPONEXIT_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4856 #define SCB_SCR_SLEEPONEXIT_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4857 #define SCB_SCR_SLEEPDEEP_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4858 #define SCB_SCR_SLEEPDEEP_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4859 #define SCB_SCR_SEVONPEND_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 4860 #define SCB_SCR_SEVONPEND_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4861 /* CCR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4862 #define SCB_CCR_UNALIGN_TRP_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 4863 #define SCB_CCR_UNALIGN_TRP_SHIFT 3
Freescale_cup 0:3ec7fc598e48 4864 #define SCB_CCR_STKALIGN_MASK 0x200u
Freescale_cup 0:3ec7fc598e48 4865 #define SCB_CCR_STKALIGN_SHIFT 9
Freescale_cup 0:3ec7fc598e48 4866 /* SHPR2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4867 #define SCB_SHPR2_PRI_11_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 4868 #define SCB_SHPR2_PRI_11_SHIFT 24
Freescale_cup 0:3ec7fc598e48 4869 #define SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR2_PRI_11_SHIFT))&SCB_SHPR2_PRI_11_MASK)
Freescale_cup 0:3ec7fc598e48 4870 /* SHPR3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 4871 #define SCB_SHPR3_PRI_14_MASK 0xFF0000u
Freescale_cup 0:3ec7fc598e48 4872 #define SCB_SHPR3_PRI_14_SHIFT 16
Freescale_cup 0:3ec7fc598e48 4873 #define SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_14_SHIFT))&SCB_SHPR3_PRI_14_MASK)
Freescale_cup 0:3ec7fc598e48 4874 #define SCB_SHPR3_PRI_15_MASK 0xFF000000u
Freescale_cup 0:3ec7fc598e48 4875 #define SCB_SHPR3_PRI_15_SHIFT 24
Freescale_cup 0:3ec7fc598e48 4876 #define SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_15_SHIFT))&SCB_SHPR3_PRI_15_MASK)
Freescale_cup 0:3ec7fc598e48 4877 /* SHCSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4878 #define SCB_SHCSR_SVCALLPENDED_MASK 0x8000u
Freescale_cup 0:3ec7fc598e48 4879 #define SCB_SHCSR_SVCALLPENDED_SHIFT 15
Freescale_cup 0:3ec7fc598e48 4880 /* DFSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 4881 #define SCB_DFSR_HALTED_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 4882 #define SCB_DFSR_HALTED_SHIFT 0
Freescale_cup 0:3ec7fc598e48 4883 #define SCB_DFSR_BKPT_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 4884 #define SCB_DFSR_BKPT_SHIFT 1
Freescale_cup 0:3ec7fc598e48 4885 #define SCB_DFSR_DWTTRAP_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 4886 #define SCB_DFSR_DWTTRAP_SHIFT 2
Freescale_cup 0:3ec7fc598e48 4887 #define SCB_DFSR_VCATCH_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 4888 #define SCB_DFSR_VCATCH_SHIFT 3
Freescale_cup 0:3ec7fc598e48 4889 #define SCB_DFSR_EXTERNAL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 4890 #define SCB_DFSR_EXTERNAL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 4891
Freescale_cup 0:3ec7fc598e48 4892 /*!
Freescale_cup 0:3ec7fc598e48 4893 * @}
Freescale_cup 0:3ec7fc598e48 4894 */ /* end of group SCB_Register_Masks */
Freescale_cup 0:3ec7fc598e48 4895
Freescale_cup 0:3ec7fc598e48 4896
Freescale_cup 0:3ec7fc598e48 4897 /* SCB - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 4898 /** Peripheral SystemControl base pointer */
Freescale_cup 0:3ec7fc598e48 4899 #define SystemControl_BASE_PTR ((SCB_MemMapPtr)0xE000E000u)
Freescale_cup 0:3ec7fc598e48 4900 /** Array initializer of SCB peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 4901 #define SCB_BASE_PTRS { SystemControl_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 4902
Freescale_cup 0:3ec7fc598e48 4903 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4904 -- SCB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4905 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4906
Freescale_cup 0:3ec7fc598e48 4907 /*!
Freescale_cup 0:3ec7fc598e48 4908 * @addtogroup SCB_Register_Accessor_Macros SCB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4909 * @{
Freescale_cup 0:3ec7fc598e48 4910 */
Freescale_cup 0:3ec7fc598e48 4911
Freescale_cup 0:3ec7fc598e48 4912
Freescale_cup 0:3ec7fc598e48 4913 /* SCB - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 4914 /* SystemControl */
Freescale_cup 0:3ec7fc598e48 4915 #define SCB_ACTLR SCB_ACTLR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4916 #define SCB_CPUID SCB_CPUID_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4917 #define SCB_ICSR SCB_ICSR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4918 #define SCB_VTOR SCB_VTOR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4919 #define SCB_AIRCR SCB_AIRCR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4920 #define SCB_SCR SCB_SCR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4921 #define SCB_CCR SCB_CCR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4922 #define SCB_SHPR2 SCB_SHPR2_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4923 #define SCB_SHPR3 SCB_SHPR3_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4924 #define SCB_SHCSR SCB_SHCSR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4925 #define SCB_DFSR SCB_DFSR_REG(SystemControl_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 4926
Freescale_cup 0:3ec7fc598e48 4927 /*!
Freescale_cup 0:3ec7fc598e48 4928 * @}
Freescale_cup 0:3ec7fc598e48 4929 */ /* end of group SCB_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 4930
Freescale_cup 0:3ec7fc598e48 4931
Freescale_cup 0:3ec7fc598e48 4932 /*!
Freescale_cup 0:3ec7fc598e48 4933 * @}
Freescale_cup 0:3ec7fc598e48 4934 */ /* end of group SCB_Peripheral */
Freescale_cup 0:3ec7fc598e48 4935
Freescale_cup 0:3ec7fc598e48 4936
Freescale_cup 0:3ec7fc598e48 4937 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4938 -- SIM
Freescale_cup 0:3ec7fc598e48 4939 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4940
Freescale_cup 0:3ec7fc598e48 4941 /*!
Freescale_cup 0:3ec7fc598e48 4942 * @addtogroup SIM_Peripheral SIM
Freescale_cup 0:3ec7fc598e48 4943 * @{
Freescale_cup 0:3ec7fc598e48 4944 */
Freescale_cup 0:3ec7fc598e48 4945
Freescale_cup 0:3ec7fc598e48 4946 /** SIM - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 4947 typedef struct SIM_MemMap {
Freescale_cup 0:3ec7fc598e48 4948 uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 4949 uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 4950 uint8_t RESERVED_0[4092];
Freescale_cup 0:3ec7fc598e48 4951 uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
Freescale_cup 0:3ec7fc598e48 4952 uint8_t RESERVED_1[4];
Freescale_cup 0:3ec7fc598e48 4953 uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
Freescale_cup 0:3ec7fc598e48 4954 uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
Freescale_cup 0:3ec7fc598e48 4955 uint8_t RESERVED_2[4];
Freescale_cup 0:3ec7fc598e48 4956 uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
Freescale_cup 0:3ec7fc598e48 4957 uint8_t RESERVED_3[8];
Freescale_cup 0:3ec7fc598e48 4958 uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
Freescale_cup 0:3ec7fc598e48 4959 uint8_t RESERVED_4[12];
Freescale_cup 0:3ec7fc598e48 4960 uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
Freescale_cup 0:3ec7fc598e48 4961 uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
Freescale_cup 0:3ec7fc598e48 4962 uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
Freescale_cup 0:3ec7fc598e48 4963 uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
Freescale_cup 0:3ec7fc598e48 4964 uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
Freescale_cup 0:3ec7fc598e48 4965 uint8_t RESERVED_5[4];
Freescale_cup 0:3ec7fc598e48 4966 uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
Freescale_cup 0:3ec7fc598e48 4967 uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
Freescale_cup 0:3ec7fc598e48 4968 uint8_t RESERVED_6[4];
Freescale_cup 0:3ec7fc598e48 4969 uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
Freescale_cup 0:3ec7fc598e48 4970 uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
Freescale_cup 0:3ec7fc598e48 4971 uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
Freescale_cup 0:3ec7fc598e48 4972 uint8_t RESERVED_7[156];
Freescale_cup 0:3ec7fc598e48 4973 uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
Freescale_cup 0:3ec7fc598e48 4974 uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
Freescale_cup 0:3ec7fc598e48 4975 } volatile *SIM_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 4976
Freescale_cup 0:3ec7fc598e48 4977 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 4978 -- SIM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4979 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 4980
Freescale_cup 0:3ec7fc598e48 4981 /*!
Freescale_cup 0:3ec7fc598e48 4982 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 4983 * @{
Freescale_cup 0:3ec7fc598e48 4984 */
Freescale_cup 0:3ec7fc598e48 4985
Freescale_cup 0:3ec7fc598e48 4986
Freescale_cup 0:3ec7fc598e48 4987 /* SIM - Register accessors */
Freescale_cup 0:3ec7fc598e48 4988 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
Freescale_cup 0:3ec7fc598e48 4989 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
Freescale_cup 0:3ec7fc598e48 4990 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
Freescale_cup 0:3ec7fc598e48 4991 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
Freescale_cup 0:3ec7fc598e48 4992 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
Freescale_cup 0:3ec7fc598e48 4993 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
Freescale_cup 0:3ec7fc598e48 4994 #define SIM_SDID_REG(base) ((base)->SDID)
Freescale_cup 0:3ec7fc598e48 4995 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
Freescale_cup 0:3ec7fc598e48 4996 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
Freescale_cup 0:3ec7fc598e48 4997 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
Freescale_cup 0:3ec7fc598e48 4998 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
Freescale_cup 0:3ec7fc598e48 4999 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
Freescale_cup 0:3ec7fc598e48 5000 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
Freescale_cup 0:3ec7fc598e48 5001 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
Freescale_cup 0:3ec7fc598e48 5002 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
Freescale_cup 0:3ec7fc598e48 5003 #define SIM_UIDML_REG(base) ((base)->UIDML)
Freescale_cup 0:3ec7fc598e48 5004 #define SIM_UIDL_REG(base) ((base)->UIDL)
Freescale_cup 0:3ec7fc598e48 5005 #define SIM_COPC_REG(base) ((base)->COPC)
Freescale_cup 0:3ec7fc598e48 5006 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
Freescale_cup 0:3ec7fc598e48 5007
Freescale_cup 0:3ec7fc598e48 5008 /*!
Freescale_cup 0:3ec7fc598e48 5009 * @}
Freescale_cup 0:3ec7fc598e48 5010 */ /* end of group SIM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5011
Freescale_cup 0:3ec7fc598e48 5012
Freescale_cup 0:3ec7fc598e48 5013 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5014 -- SIM Register Masks
Freescale_cup 0:3ec7fc598e48 5015 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5016
Freescale_cup 0:3ec7fc598e48 5017 /*!
Freescale_cup 0:3ec7fc598e48 5018 * @addtogroup SIM_Register_Masks SIM Register Masks
Freescale_cup 0:3ec7fc598e48 5019 * @{
Freescale_cup 0:3ec7fc598e48 5020 */
Freescale_cup 0:3ec7fc598e48 5021
Freescale_cup 0:3ec7fc598e48 5022 /* SOPT1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5023 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
Freescale_cup 0:3ec7fc598e48 5024 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
Freescale_cup 0:3ec7fc598e48 5025 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
Freescale_cup 0:3ec7fc598e48 5026 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
Freescale_cup 0:3ec7fc598e48 5027 #define SIM_SOPT1_USBVSTBY_SHIFT 29
Freescale_cup 0:3ec7fc598e48 5028 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
Freescale_cup 0:3ec7fc598e48 5029 #define SIM_SOPT1_USBSSTBY_SHIFT 30
Freescale_cup 0:3ec7fc598e48 5030 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 5031 #define SIM_SOPT1_USBREGEN_SHIFT 31
Freescale_cup 0:3ec7fc598e48 5032 /* SOPT1CFG Bit Fields */
Freescale_cup 0:3ec7fc598e48 5033 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
Freescale_cup 0:3ec7fc598e48 5034 #define SIM_SOPT1CFG_URWE_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5035 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
Freescale_cup 0:3ec7fc598e48 5036 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
Freescale_cup 0:3ec7fc598e48 5037 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
Freescale_cup 0:3ec7fc598e48 5038 #define SIM_SOPT1CFG_USSWE_SHIFT 26
Freescale_cup 0:3ec7fc598e48 5039 /* SOPT2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5040 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5041 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5042 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
Freescale_cup 0:3ec7fc598e48 5043 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5044 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
Freescale_cup 0:3ec7fc598e48 5045 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
Freescale_cup 0:3ec7fc598e48 5046 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5047 #define SIM_SOPT2_USBSRC_MASK 0x40000u
Freescale_cup 0:3ec7fc598e48 5048 #define SIM_SOPT2_USBSRC_SHIFT 18
Freescale_cup 0:3ec7fc598e48 5049 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
Freescale_cup 0:3ec7fc598e48 5050 #define SIM_SOPT2_TPMSRC_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5051 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
Freescale_cup 0:3ec7fc598e48 5052 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
Freescale_cup 0:3ec7fc598e48 5053 #define SIM_SOPT2_UART0SRC_SHIFT 26
Freescale_cup 0:3ec7fc598e48 5054 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
Freescale_cup 0:3ec7fc598e48 5055 /* SOPT4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5056 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
Freescale_cup 0:3ec7fc598e48 5057 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
Freescale_cup 0:3ec7fc598e48 5058 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
Freescale_cup 0:3ec7fc598e48 5059 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
Freescale_cup 0:3ec7fc598e48 5060 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
Freescale_cup 0:3ec7fc598e48 5061 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5062 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
Freescale_cup 0:3ec7fc598e48 5063 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
Freescale_cup 0:3ec7fc598e48 5064 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
Freescale_cup 0:3ec7fc598e48 5065 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
Freescale_cup 0:3ec7fc598e48 5066 /* SOPT5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5067 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
Freescale_cup 0:3ec7fc598e48 5068 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5069 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
Freescale_cup 0:3ec7fc598e48 5070 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5071 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5072 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
Freescale_cup 0:3ec7fc598e48 5073 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5074 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
Freescale_cup 0:3ec7fc598e48 5075 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5076 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5077 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
Freescale_cup 0:3ec7fc598e48 5078 #define SIM_SOPT5_UART0ODE_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5079 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
Freescale_cup 0:3ec7fc598e48 5080 #define SIM_SOPT5_UART1ODE_SHIFT 17
Freescale_cup 0:3ec7fc598e48 5081 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
Freescale_cup 0:3ec7fc598e48 5082 #define SIM_SOPT5_UART2ODE_SHIFT 18
Freescale_cup 0:3ec7fc598e48 5083 /* SOPT7 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5084 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 5085 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5086 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
Freescale_cup 0:3ec7fc598e48 5087 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5088 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5089 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5090 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5091 /* SDID Bit Fields */
Freescale_cup 0:3ec7fc598e48 5092 #define SIM_SDID_PINID_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 5093 #define SIM_SDID_PINID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5094 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
Freescale_cup 0:3ec7fc598e48 5095 #define SIM_SDID_DIEID_MASK 0xF80u
Freescale_cup 0:3ec7fc598e48 5096 #define SIM_SDID_DIEID_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5097 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
Freescale_cup 0:3ec7fc598e48 5098 #define SIM_SDID_REVID_MASK 0xF000u
Freescale_cup 0:3ec7fc598e48 5099 #define SIM_SDID_REVID_SHIFT 12
Freescale_cup 0:3ec7fc598e48 5100 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
Freescale_cup 0:3ec7fc598e48 5101 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
Freescale_cup 0:3ec7fc598e48 5102 #define SIM_SDID_SRAMSIZE_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5103 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
Freescale_cup 0:3ec7fc598e48 5104 #define SIM_SDID_SERIESID_MASK 0xF00000u
Freescale_cup 0:3ec7fc598e48 5105 #define SIM_SDID_SERIESID_SHIFT 20
Freescale_cup 0:3ec7fc598e48 5106 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
Freescale_cup 0:3ec7fc598e48 5107 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
Freescale_cup 0:3ec7fc598e48 5108 #define SIM_SDID_SUBFAMID_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5109 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
Freescale_cup 0:3ec7fc598e48 5110 #define SIM_SDID_FAMID_MASK 0xF0000000u
Freescale_cup 0:3ec7fc598e48 5111 #define SIM_SDID_FAMID_SHIFT 28
Freescale_cup 0:3ec7fc598e48 5112 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
Freescale_cup 0:3ec7fc598e48 5113 /* SCGC4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5114 #define SIM_SCGC4_I2C0_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5115 #define SIM_SCGC4_I2C0_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5116 #define SIM_SCGC4_I2C1_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5117 #define SIM_SCGC4_I2C1_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5118 #define SIM_SCGC4_UART0_MASK 0x400u
Freescale_cup 0:3ec7fc598e48 5119 #define SIM_SCGC4_UART0_SHIFT 10
Freescale_cup 0:3ec7fc598e48 5120 #define SIM_SCGC4_UART1_MASK 0x800u
Freescale_cup 0:3ec7fc598e48 5121 #define SIM_SCGC4_UART1_SHIFT 11
Freescale_cup 0:3ec7fc598e48 5122 #define SIM_SCGC4_UART2_MASK 0x1000u
Freescale_cup 0:3ec7fc598e48 5123 #define SIM_SCGC4_UART2_SHIFT 12
Freescale_cup 0:3ec7fc598e48 5124 #define SIM_SCGC4_USBOTG_MASK 0x40000u
Freescale_cup 0:3ec7fc598e48 5125 #define SIM_SCGC4_USBOTG_SHIFT 18
Freescale_cup 0:3ec7fc598e48 5126 #define SIM_SCGC4_CMP_MASK 0x80000u
Freescale_cup 0:3ec7fc598e48 5127 #define SIM_SCGC4_CMP_SHIFT 19
Freescale_cup 0:3ec7fc598e48 5128 #define SIM_SCGC4_SPI0_MASK 0x400000u
Freescale_cup 0:3ec7fc598e48 5129 #define SIM_SCGC4_SPI0_SHIFT 22
Freescale_cup 0:3ec7fc598e48 5130 #define SIM_SCGC4_SPI1_MASK 0x800000u
Freescale_cup 0:3ec7fc598e48 5131 #define SIM_SCGC4_SPI1_SHIFT 23
Freescale_cup 0:3ec7fc598e48 5132 /* SCGC5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5133 #define SIM_SCGC5_LPTMR_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5134 #define SIM_SCGC5_LPTMR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5135 #define SIM_SCGC5_TSI_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5136 #define SIM_SCGC5_TSI_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5137 #define SIM_SCGC5_PORTA_MASK 0x200u
Freescale_cup 0:3ec7fc598e48 5138 #define SIM_SCGC5_PORTA_SHIFT 9
Freescale_cup 0:3ec7fc598e48 5139 #define SIM_SCGC5_PORTB_MASK 0x400u
Freescale_cup 0:3ec7fc598e48 5140 #define SIM_SCGC5_PORTB_SHIFT 10
Freescale_cup 0:3ec7fc598e48 5141 #define SIM_SCGC5_PORTC_MASK 0x800u
Freescale_cup 0:3ec7fc598e48 5142 #define SIM_SCGC5_PORTC_SHIFT 11
Freescale_cup 0:3ec7fc598e48 5143 #define SIM_SCGC5_PORTD_MASK 0x1000u
Freescale_cup 0:3ec7fc598e48 5144 #define SIM_SCGC5_PORTD_SHIFT 12
Freescale_cup 0:3ec7fc598e48 5145 #define SIM_SCGC5_PORTE_MASK 0x2000u
Freescale_cup 0:3ec7fc598e48 5146 #define SIM_SCGC5_PORTE_SHIFT 13
Freescale_cup 0:3ec7fc598e48 5147 /* SCGC6 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5148 #define SIM_SCGC6_FTF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5149 #define SIM_SCGC6_FTF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5150 #define SIM_SCGC6_DMAMUX_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5151 #define SIM_SCGC6_DMAMUX_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5152 #define SIM_SCGC6_PIT_MASK 0x800000u
Freescale_cup 0:3ec7fc598e48 5153 #define SIM_SCGC6_PIT_SHIFT 23
Freescale_cup 0:3ec7fc598e48 5154 #define SIM_SCGC6_TPM0_MASK 0x1000000u
Freescale_cup 0:3ec7fc598e48 5155 #define SIM_SCGC6_TPM0_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5156 #define SIM_SCGC6_TPM1_MASK 0x2000000u
Freescale_cup 0:3ec7fc598e48 5157 #define SIM_SCGC6_TPM1_SHIFT 25
Freescale_cup 0:3ec7fc598e48 5158 #define SIM_SCGC6_TPM2_MASK 0x4000000u
Freescale_cup 0:3ec7fc598e48 5159 #define SIM_SCGC6_TPM2_SHIFT 26
Freescale_cup 0:3ec7fc598e48 5160 #define SIM_SCGC6_ADC0_MASK 0x8000000u
Freescale_cup 0:3ec7fc598e48 5161 #define SIM_SCGC6_ADC0_SHIFT 27
Freescale_cup 0:3ec7fc598e48 5162 #define SIM_SCGC6_RTC_MASK 0x20000000u
Freescale_cup 0:3ec7fc598e48 5163 #define SIM_SCGC6_RTC_SHIFT 29
Freescale_cup 0:3ec7fc598e48 5164 #define SIM_SCGC6_DAC0_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 5165 #define SIM_SCGC6_DAC0_SHIFT 31
Freescale_cup 0:3ec7fc598e48 5166 /* SCGC7 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5167 #define SIM_SCGC7_DMA_MASK 0x100u
Freescale_cup 0:3ec7fc598e48 5168 #define SIM_SCGC7_DMA_SHIFT 8
Freescale_cup 0:3ec7fc598e48 5169 /* CLKDIV1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5170 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
Freescale_cup 0:3ec7fc598e48 5171 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5172 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
Freescale_cup 0:3ec7fc598e48 5173 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
Freescale_cup 0:3ec7fc598e48 5174 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
Freescale_cup 0:3ec7fc598e48 5175 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
Freescale_cup 0:3ec7fc598e48 5176 /* FCFG1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5177 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5178 #define SIM_FCFG1_FLASHDIS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5179 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5180 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5181 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
Freescale_cup 0:3ec7fc598e48 5182 #define SIM_FCFG1_PFSIZE_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5183 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
Freescale_cup 0:3ec7fc598e48 5184 /* FCFG2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5185 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
Freescale_cup 0:3ec7fc598e48 5186 #define SIM_FCFG2_MAXADDR0_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5187 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
Freescale_cup 0:3ec7fc598e48 5188 /* UIDMH Bit Fields */
Freescale_cup 0:3ec7fc598e48 5189 #define SIM_UIDMH_UID_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 5190 #define SIM_UIDMH_UID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5191 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
Freescale_cup 0:3ec7fc598e48 5192 /* UIDML Bit Fields */
Freescale_cup 0:3ec7fc598e48 5193 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 5194 #define SIM_UIDML_UID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5195 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
Freescale_cup 0:3ec7fc598e48 5196 /* UIDL Bit Fields */
Freescale_cup 0:3ec7fc598e48 5197 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
Freescale_cup 0:3ec7fc598e48 5198 #define SIM_UIDL_UID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5199 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
Freescale_cup 0:3ec7fc598e48 5200 /* COPC Bit Fields */
Freescale_cup 0:3ec7fc598e48 5201 #define SIM_COPC_COPW_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5202 #define SIM_COPC_COPW_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5203 #define SIM_COPC_COPCLKS_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5204 #define SIM_COPC_COPCLKS_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5205 #define SIM_COPC_COPT_MASK 0xCu
Freescale_cup 0:3ec7fc598e48 5206 #define SIM_COPC_COPT_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5207 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
Freescale_cup 0:3ec7fc598e48 5208 /* SRVCOP Bit Fields */
Freescale_cup 0:3ec7fc598e48 5209 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 5210 #define SIM_SRVCOP_SRVCOP_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5211 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
Freescale_cup 0:3ec7fc598e48 5212
Freescale_cup 0:3ec7fc598e48 5213 /*!
Freescale_cup 0:3ec7fc598e48 5214 * @}
Freescale_cup 0:3ec7fc598e48 5215 */ /* end of group SIM_Register_Masks */
Freescale_cup 0:3ec7fc598e48 5216
Freescale_cup 0:3ec7fc598e48 5217
Freescale_cup 0:3ec7fc598e48 5218 /* SIM - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 5219 /** Peripheral SIM base pointer */
Freescale_cup 0:3ec7fc598e48 5220 #define SIM_BASE_PTR ((SIM_MemMapPtr)0x40047000u)
Freescale_cup 0:3ec7fc598e48 5221 /** Array initializer of SIM peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 5222 #define SIM_BASE_PTRS { SIM_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 5223
Freescale_cup 0:3ec7fc598e48 5224 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5225 -- SIM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5226 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5227
Freescale_cup 0:3ec7fc598e48 5228 /*!
Freescale_cup 0:3ec7fc598e48 5229 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5230 * @{
Freescale_cup 0:3ec7fc598e48 5231 */
Freescale_cup 0:3ec7fc598e48 5232
Freescale_cup 0:3ec7fc598e48 5233
Freescale_cup 0:3ec7fc598e48 5234 /* SIM - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 5235 /* SIM */
Freescale_cup 0:3ec7fc598e48 5236 #define SIM_SOPT1 SIM_SOPT1_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5237 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5238 #define SIM_SOPT2 SIM_SOPT2_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5239 #define SIM_SOPT4 SIM_SOPT4_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5240 #define SIM_SOPT5 SIM_SOPT5_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5241 #define SIM_SOPT7 SIM_SOPT7_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5242 #define SIM_SDID SIM_SDID_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5243 #define SIM_SCGC4 SIM_SCGC4_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5244 #define SIM_SCGC5 SIM_SCGC5_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5245 #define SIM_SCGC6 SIM_SCGC6_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5246 #define SIM_SCGC7 SIM_SCGC7_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5247 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5248 #define SIM_FCFG1 SIM_FCFG1_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5249 #define SIM_FCFG2 SIM_FCFG2_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5250 #define SIM_UIDMH SIM_UIDMH_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5251 #define SIM_UIDML SIM_UIDML_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5252 #define SIM_UIDL SIM_UIDL_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5253 #define SIM_COPC SIM_COPC_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5254 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5255
Freescale_cup 0:3ec7fc598e48 5256 /*!
Freescale_cup 0:3ec7fc598e48 5257 * @}
Freescale_cup 0:3ec7fc598e48 5258 */ /* end of group SIM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5259
Freescale_cup 0:3ec7fc598e48 5260
Freescale_cup 0:3ec7fc598e48 5261 /*!
Freescale_cup 0:3ec7fc598e48 5262 * @}
Freescale_cup 0:3ec7fc598e48 5263 */ /* end of group SIM_Peripheral */
Freescale_cup 0:3ec7fc598e48 5264
Freescale_cup 0:3ec7fc598e48 5265
Freescale_cup 0:3ec7fc598e48 5266 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5267 -- SMC
Freescale_cup 0:3ec7fc598e48 5268 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5269
Freescale_cup 0:3ec7fc598e48 5270 /*!
Freescale_cup 0:3ec7fc598e48 5271 * @addtogroup SMC_Peripheral SMC
Freescale_cup 0:3ec7fc598e48 5272 * @{
Freescale_cup 0:3ec7fc598e48 5273 */
Freescale_cup 0:3ec7fc598e48 5274
Freescale_cup 0:3ec7fc598e48 5275 /** SMC - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 5276 typedef struct SMC_MemMap {
Freescale_cup 0:3ec7fc598e48 5277 uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 5278 uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 5279 uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 5280 uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 5281 } volatile *SMC_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 5282
Freescale_cup 0:3ec7fc598e48 5283 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5284 -- SMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5285 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5286
Freescale_cup 0:3ec7fc598e48 5287 /*!
Freescale_cup 0:3ec7fc598e48 5288 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5289 * @{
Freescale_cup 0:3ec7fc598e48 5290 */
Freescale_cup 0:3ec7fc598e48 5291
Freescale_cup 0:3ec7fc598e48 5292
Freescale_cup 0:3ec7fc598e48 5293 /* SMC - Register accessors */
Freescale_cup 0:3ec7fc598e48 5294 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
Freescale_cup 0:3ec7fc598e48 5295 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
Freescale_cup 0:3ec7fc598e48 5296 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
Freescale_cup 0:3ec7fc598e48 5297 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
Freescale_cup 0:3ec7fc598e48 5298
Freescale_cup 0:3ec7fc598e48 5299 /*!
Freescale_cup 0:3ec7fc598e48 5300 * @}
Freescale_cup 0:3ec7fc598e48 5301 */ /* end of group SMC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5302
Freescale_cup 0:3ec7fc598e48 5303
Freescale_cup 0:3ec7fc598e48 5304 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5305 -- SMC Register Masks
Freescale_cup 0:3ec7fc598e48 5306 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5307
Freescale_cup 0:3ec7fc598e48 5308 /*!
Freescale_cup 0:3ec7fc598e48 5309 * @addtogroup SMC_Register_Masks SMC Register Masks
Freescale_cup 0:3ec7fc598e48 5310 * @{
Freescale_cup 0:3ec7fc598e48 5311 */
Freescale_cup 0:3ec7fc598e48 5312
Freescale_cup 0:3ec7fc598e48 5313 /* PMPROT Bit Fields */
Freescale_cup 0:3ec7fc598e48 5314 #define SMC_PMPROT_AVLLS_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5315 #define SMC_PMPROT_AVLLS_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5316 #define SMC_PMPROT_ALLS_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5317 #define SMC_PMPROT_ALLS_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5318 #define SMC_PMPROT_AVLP_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5319 #define SMC_PMPROT_AVLP_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5320 /* PMCTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 5321 #define SMC_PMCTRL_STOPM_MASK 0x7u
Freescale_cup 0:3ec7fc598e48 5322 #define SMC_PMCTRL_STOPM_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5323 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
Freescale_cup 0:3ec7fc598e48 5324 #define SMC_PMCTRL_STOPA_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5325 #define SMC_PMCTRL_STOPA_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5326 #define SMC_PMCTRL_RUNM_MASK 0x60u
Freescale_cup 0:3ec7fc598e48 5327 #define SMC_PMCTRL_RUNM_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5328 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
Freescale_cup 0:3ec7fc598e48 5329 /* STOPCTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 5330 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
Freescale_cup 0:3ec7fc598e48 5331 #define SMC_STOPCTRL_VLLSM_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5332 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
Freescale_cup 0:3ec7fc598e48 5333 #define SMC_STOPCTRL_PORPO_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5334 #define SMC_STOPCTRL_PORPO_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5335 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 5336 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5337 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
Freescale_cup 0:3ec7fc598e48 5338 /* PMSTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 5339 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
Freescale_cup 0:3ec7fc598e48 5340 #define SMC_PMSTAT_PMSTAT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5341 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
Freescale_cup 0:3ec7fc598e48 5342
Freescale_cup 0:3ec7fc598e48 5343 /*!
Freescale_cup 0:3ec7fc598e48 5344 * @}
Freescale_cup 0:3ec7fc598e48 5345 */ /* end of group SMC_Register_Masks */
Freescale_cup 0:3ec7fc598e48 5346
Freescale_cup 0:3ec7fc598e48 5347
Freescale_cup 0:3ec7fc598e48 5348 /* SMC - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 5349 /** Peripheral SMC base pointer */
Freescale_cup 0:3ec7fc598e48 5350 #define SMC_BASE_PTR ((SMC_MemMapPtr)0x4007E000u)
Freescale_cup 0:3ec7fc598e48 5351 /** Array initializer of SMC peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 5352 #define SMC_BASE_PTRS { SMC_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 5353
Freescale_cup 0:3ec7fc598e48 5354 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5355 -- SMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5356 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5357
Freescale_cup 0:3ec7fc598e48 5358 /*!
Freescale_cup 0:3ec7fc598e48 5359 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5360 * @{
Freescale_cup 0:3ec7fc598e48 5361 */
Freescale_cup 0:3ec7fc598e48 5362
Freescale_cup 0:3ec7fc598e48 5363
Freescale_cup 0:3ec7fc598e48 5364 /* SMC - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 5365 /* SMC */
Freescale_cup 0:3ec7fc598e48 5366 #define SMC_PMPROT SMC_PMPROT_REG(SMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5367 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5368 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5369 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5370
Freescale_cup 0:3ec7fc598e48 5371 /*!
Freescale_cup 0:3ec7fc598e48 5372 * @}
Freescale_cup 0:3ec7fc598e48 5373 */ /* end of group SMC_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5374
Freescale_cup 0:3ec7fc598e48 5375
Freescale_cup 0:3ec7fc598e48 5376 /*!
Freescale_cup 0:3ec7fc598e48 5377 * @}
Freescale_cup 0:3ec7fc598e48 5378 */ /* end of group SMC_Peripheral */
Freescale_cup 0:3ec7fc598e48 5379
Freescale_cup 0:3ec7fc598e48 5380
Freescale_cup 0:3ec7fc598e48 5381 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5382 -- SPI
Freescale_cup 0:3ec7fc598e48 5383 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5384
Freescale_cup 0:3ec7fc598e48 5385 /*!
Freescale_cup 0:3ec7fc598e48 5386 * @addtogroup SPI_Peripheral SPI
Freescale_cup 0:3ec7fc598e48 5387 * @{
Freescale_cup 0:3ec7fc598e48 5388 */
Freescale_cup 0:3ec7fc598e48 5389
Freescale_cup 0:3ec7fc598e48 5390 /** SPI - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 5391 typedef struct SPI_MemMap {
Freescale_cup 0:3ec7fc598e48 5392 uint8_t C1; /**< SPI control register 1, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 5393 uint8_t C2; /**< SPI control register 2, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 5394 uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 5395 uint8_t S; /**< SPI status register, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 5396 uint8_t RESERVED_0[1];
Freescale_cup 0:3ec7fc598e48 5397 uint8_t D; /**< SPI data register, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 5398 uint8_t RESERVED_1[1];
Freescale_cup 0:3ec7fc598e48 5399 uint8_t M; /**< SPI match register, offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 5400 } volatile *SPI_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 5401
Freescale_cup 0:3ec7fc598e48 5402 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5403 -- SPI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5404 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5405
Freescale_cup 0:3ec7fc598e48 5406 /*!
Freescale_cup 0:3ec7fc598e48 5407 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5408 * @{
Freescale_cup 0:3ec7fc598e48 5409 */
Freescale_cup 0:3ec7fc598e48 5410
Freescale_cup 0:3ec7fc598e48 5411
Freescale_cup 0:3ec7fc598e48 5412 /* SPI - Register accessors */
Freescale_cup 0:3ec7fc598e48 5413 #define SPI_C1_REG(base) ((base)->C1)
Freescale_cup 0:3ec7fc598e48 5414 #define SPI_C2_REG(base) ((base)->C2)
Freescale_cup 0:3ec7fc598e48 5415 #define SPI_BR_REG(base) ((base)->BR)
Freescale_cup 0:3ec7fc598e48 5416 #define SPI_S_REG(base) ((base)->S)
Freescale_cup 0:3ec7fc598e48 5417 #define SPI_D_REG(base) ((base)->D)
Freescale_cup 0:3ec7fc598e48 5418 #define SPI_M_REG(base) ((base)->M)
Freescale_cup 0:3ec7fc598e48 5419
Freescale_cup 0:3ec7fc598e48 5420 /*!
Freescale_cup 0:3ec7fc598e48 5421 * @}
Freescale_cup 0:3ec7fc598e48 5422 */ /* end of group SPI_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5423
Freescale_cup 0:3ec7fc598e48 5424
Freescale_cup 0:3ec7fc598e48 5425 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5426 -- SPI Register Masks
Freescale_cup 0:3ec7fc598e48 5427 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5428
Freescale_cup 0:3ec7fc598e48 5429 /*!
Freescale_cup 0:3ec7fc598e48 5430 * @addtogroup SPI_Register_Masks SPI Register Masks
Freescale_cup 0:3ec7fc598e48 5431 * @{
Freescale_cup 0:3ec7fc598e48 5432 */
Freescale_cup 0:3ec7fc598e48 5433
Freescale_cup 0:3ec7fc598e48 5434 /* C1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5435 #define SPI_C1_LSBFE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5436 #define SPI_C1_LSBFE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5437 #define SPI_C1_SSOE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5438 #define SPI_C1_SSOE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5439 #define SPI_C1_CPHA_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5440 #define SPI_C1_CPHA_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5441 #define SPI_C1_CPOL_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5442 #define SPI_C1_CPOL_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5443 #define SPI_C1_MSTR_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5444 #define SPI_C1_MSTR_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5445 #define SPI_C1_SPTIE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5446 #define SPI_C1_SPTIE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5447 #define SPI_C1_SPE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5448 #define SPI_C1_SPE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5449 #define SPI_C1_SPIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5450 #define SPI_C1_SPIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5451 /* C2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 5452 #define SPI_C2_SPC0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5453 #define SPI_C2_SPC0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5454 #define SPI_C2_SPISWAI_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5455 #define SPI_C2_SPISWAI_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5456 #define SPI_C2_RXDMAE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5457 #define SPI_C2_RXDMAE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5458 #define SPI_C2_BIDIROE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5459 #define SPI_C2_BIDIROE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5460 #define SPI_C2_MODFEN_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5461 #define SPI_C2_MODFEN_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5462 #define SPI_C2_TXDMAE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5463 #define SPI_C2_TXDMAE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5464 #define SPI_C2_SPMIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5465 #define SPI_C2_SPMIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5466 /* BR Bit Fields */
Freescale_cup 0:3ec7fc598e48 5467 #define SPI_BR_SPR_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 5468 #define SPI_BR_SPR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5469 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
Freescale_cup 0:3ec7fc598e48 5470 #define SPI_BR_SPPR_MASK 0x70u
Freescale_cup 0:3ec7fc598e48 5471 #define SPI_BR_SPPR_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5472 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
Freescale_cup 0:3ec7fc598e48 5473 /* S Bit Fields */
Freescale_cup 0:3ec7fc598e48 5474 #define SPI_S_MODF_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5475 #define SPI_S_MODF_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5476 #define SPI_S_SPTEF_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5477 #define SPI_S_SPTEF_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5478 #define SPI_S_SPMF_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5479 #define SPI_S_SPMF_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5480 #define SPI_S_SPRF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5481 #define SPI_S_SPRF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5482 /* D Bit Fields */
Freescale_cup 0:3ec7fc598e48 5483 #define SPI_D_Bits_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 5484 #define SPI_D_Bits_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5485 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
Freescale_cup 0:3ec7fc598e48 5486 /* M Bit Fields */
Freescale_cup 0:3ec7fc598e48 5487 #define SPI_M_Bits_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 5488 #define SPI_M_Bits_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5489 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
Freescale_cup 0:3ec7fc598e48 5490
Freescale_cup 0:3ec7fc598e48 5491 /*!
Freescale_cup 0:3ec7fc598e48 5492 * @}
Freescale_cup 0:3ec7fc598e48 5493 */ /* end of group SPI_Register_Masks */
Freescale_cup 0:3ec7fc598e48 5494
Freescale_cup 0:3ec7fc598e48 5495
Freescale_cup 0:3ec7fc598e48 5496 /* SPI - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 5497 /** Peripheral SPI0 base pointer */
Freescale_cup 0:3ec7fc598e48 5498 #define SPI0_BASE_PTR ((SPI_MemMapPtr)0x40076000u)
Freescale_cup 0:3ec7fc598e48 5499 /** Peripheral SPI1 base pointer */
Freescale_cup 0:3ec7fc598e48 5500 #define SPI1_BASE_PTR ((SPI_MemMapPtr)0x40077000u)
Freescale_cup 0:3ec7fc598e48 5501 /** Array initializer of SPI peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 5502 #define SPI_BASE_PTRS { SPI0_BASE_PTR, SPI1_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 5503
Freescale_cup 0:3ec7fc598e48 5504 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5505 -- SPI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5506 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5507
Freescale_cup 0:3ec7fc598e48 5508 /*!
Freescale_cup 0:3ec7fc598e48 5509 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5510 * @{
Freescale_cup 0:3ec7fc598e48 5511 */
Freescale_cup 0:3ec7fc598e48 5512
Freescale_cup 0:3ec7fc598e48 5513
Freescale_cup 0:3ec7fc598e48 5514 /* SPI - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 5515 /* SPI0 */
Freescale_cup 0:3ec7fc598e48 5516 #define SPI0_C1 SPI_C1_REG(SPI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5517 #define SPI0_C2 SPI_C2_REG(SPI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5518 #define SPI0_BR SPI_BR_REG(SPI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5519 #define SPI0_S SPI_S_REG(SPI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5520 #define SPI0_D SPI_D_REG(SPI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5521 #define SPI0_M SPI_M_REG(SPI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5522 /* SPI1 */
Freescale_cup 0:3ec7fc598e48 5523 #define SPI1_C1 SPI_C1_REG(SPI1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5524 #define SPI1_C2 SPI_C2_REG(SPI1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5525 #define SPI1_BR SPI_BR_REG(SPI1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5526 #define SPI1_S SPI_S_REG(SPI1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5527 #define SPI1_D SPI_D_REG(SPI1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5528 #define SPI1_M SPI_M_REG(SPI1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5529
Freescale_cup 0:3ec7fc598e48 5530 /*!
Freescale_cup 0:3ec7fc598e48 5531 * @}
Freescale_cup 0:3ec7fc598e48 5532 */ /* end of group SPI_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5533
Freescale_cup 0:3ec7fc598e48 5534
Freescale_cup 0:3ec7fc598e48 5535 /*!
Freescale_cup 0:3ec7fc598e48 5536 * @}
Freescale_cup 0:3ec7fc598e48 5537 */ /* end of group SPI_Peripheral */
Freescale_cup 0:3ec7fc598e48 5538
Freescale_cup 0:3ec7fc598e48 5539
Freescale_cup 0:3ec7fc598e48 5540 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5541 -- SysTick
Freescale_cup 0:3ec7fc598e48 5542 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5543
Freescale_cup 0:3ec7fc598e48 5544 /*!
Freescale_cup 0:3ec7fc598e48 5545 * @addtogroup SysTick_Peripheral SysTick
Freescale_cup 0:3ec7fc598e48 5546 * @{
Freescale_cup 0:3ec7fc598e48 5547 */
Freescale_cup 0:3ec7fc598e48 5548
Freescale_cup 0:3ec7fc598e48 5549 /** SysTick - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 5550 typedef struct SysTick_MemMap {
Freescale_cup 0:3ec7fc598e48 5551 uint32_t CSR; /**< SysTick Control and Status Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 5552 uint32_t RVR; /**< SysTick Reload Value Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 5553 uint32_t CVR; /**< SysTick Current Value Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 5554 uint32_t CALIB; /**< SysTick Calibration Value Register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 5555 } volatile *SysTick_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 5556
Freescale_cup 0:3ec7fc598e48 5557 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5558 -- SysTick - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5559 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5560
Freescale_cup 0:3ec7fc598e48 5561 /*!
Freescale_cup 0:3ec7fc598e48 5562 * @addtogroup SysTick_Register_Accessor_Macros SysTick - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5563 * @{
Freescale_cup 0:3ec7fc598e48 5564 */
Freescale_cup 0:3ec7fc598e48 5565
Freescale_cup 0:3ec7fc598e48 5566
Freescale_cup 0:3ec7fc598e48 5567 /* SysTick - Register accessors */
Freescale_cup 0:3ec7fc598e48 5568 #define SysTick_CSR_REG(base) ((base)->CSR)
Freescale_cup 0:3ec7fc598e48 5569 #define SysTick_RVR_REG(base) ((base)->RVR)
Freescale_cup 0:3ec7fc598e48 5570 #define SysTick_CVR_REG(base) ((base)->CVR)
Freescale_cup 0:3ec7fc598e48 5571 #define SysTick_CALIB_REG(base) ((base)->CALIB)
Freescale_cup 0:3ec7fc598e48 5572
Freescale_cup 0:3ec7fc598e48 5573 /*!
Freescale_cup 0:3ec7fc598e48 5574 * @}
Freescale_cup 0:3ec7fc598e48 5575 */ /* end of group SysTick_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5576
Freescale_cup 0:3ec7fc598e48 5577
Freescale_cup 0:3ec7fc598e48 5578 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5579 -- SysTick Register Masks
Freescale_cup 0:3ec7fc598e48 5580 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5581
Freescale_cup 0:3ec7fc598e48 5582 /*!
Freescale_cup 0:3ec7fc598e48 5583 * @addtogroup SysTick_Register_Masks SysTick Register Masks
Freescale_cup 0:3ec7fc598e48 5584 * @{
Freescale_cup 0:3ec7fc598e48 5585 */
Freescale_cup 0:3ec7fc598e48 5586
Freescale_cup 0:3ec7fc598e48 5587 /* CSR Bit Fields */
Freescale_cup 0:3ec7fc598e48 5588 #define SysTick_CSR_ENABLE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5589 #define SysTick_CSR_ENABLE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5590 #define SysTick_CSR_TICKINT_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5591 #define SysTick_CSR_TICKINT_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5592 #define SysTick_CSR_CLKSOURCE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5593 #define SysTick_CSR_CLKSOURCE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5594 #define SysTick_CSR_COUNTFLAG_MASK 0x10000u
Freescale_cup 0:3ec7fc598e48 5595 #define SysTick_CSR_COUNTFLAG_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5596 /* RVR Bit Fields */
Freescale_cup 0:3ec7fc598e48 5597 #define SysTick_RVR_RELOAD_MASK 0xFFFFFFu
Freescale_cup 0:3ec7fc598e48 5598 #define SysTick_RVR_RELOAD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5599 #define SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<SysTick_RVR_RELOAD_SHIFT))&SysTick_RVR_RELOAD_MASK)
Freescale_cup 0:3ec7fc598e48 5600 /* CVR Bit Fields */
Freescale_cup 0:3ec7fc598e48 5601 #define SysTick_CVR_CURRENT_MASK 0xFFFFFFu
Freescale_cup 0:3ec7fc598e48 5602 #define SysTick_CVR_CURRENT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5603 #define SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CVR_CURRENT_SHIFT))&SysTick_CVR_CURRENT_MASK)
Freescale_cup 0:3ec7fc598e48 5604 /* CALIB Bit Fields */
Freescale_cup 0:3ec7fc598e48 5605 #define SysTick_CALIB_TENMS_MASK 0xFFFFFFu
Freescale_cup 0:3ec7fc598e48 5606 #define SysTick_CALIB_TENMS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5607 #define SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CALIB_TENMS_SHIFT))&SysTick_CALIB_TENMS_MASK)
Freescale_cup 0:3ec7fc598e48 5608 #define SysTick_CALIB_SKEW_MASK 0x40000000u
Freescale_cup 0:3ec7fc598e48 5609 #define SysTick_CALIB_SKEW_SHIFT 30
Freescale_cup 0:3ec7fc598e48 5610 #define SysTick_CALIB_NOREF_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 5611 #define SysTick_CALIB_NOREF_SHIFT 31
Freescale_cup 0:3ec7fc598e48 5612
Freescale_cup 0:3ec7fc598e48 5613 /*!
Freescale_cup 0:3ec7fc598e48 5614 * @}
Freescale_cup 0:3ec7fc598e48 5615 */ /* end of group SysTick_Register_Masks */
Freescale_cup 0:3ec7fc598e48 5616
Freescale_cup 0:3ec7fc598e48 5617
Freescale_cup 0:3ec7fc598e48 5618 /* SysTick - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 5619 /** Peripheral SysTick base pointer */
Freescale_cup 0:3ec7fc598e48 5620 #define SysTick_BASE_PTR ((SysTick_MemMapPtr)0xE000E010u)
Freescale_cup 0:3ec7fc598e48 5621 /** Array initializer of SysTick peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 5622 #define SysTick_BASE_PTRS { SysTick_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 5623
Freescale_cup 0:3ec7fc598e48 5624 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5625 -- SysTick - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5626 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5627
Freescale_cup 0:3ec7fc598e48 5628 /*!
Freescale_cup 0:3ec7fc598e48 5629 * @addtogroup SysTick_Register_Accessor_Macros SysTick - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5630 * @{
Freescale_cup 0:3ec7fc598e48 5631 */
Freescale_cup 0:3ec7fc598e48 5632
Freescale_cup 0:3ec7fc598e48 5633
Freescale_cup 0:3ec7fc598e48 5634 /* SysTick - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 5635 /* SysTick */
Freescale_cup 0:3ec7fc598e48 5636 #define SYST_CSR SysTick_CSR_REG(SysTick_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5637 #define SYST_RVR SysTick_RVR_REG(SysTick_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5638 #define SYST_CVR SysTick_CVR_REG(SysTick_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5639 #define SYST_CALIB SysTick_CALIB_REG(SysTick_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5640
Freescale_cup 0:3ec7fc598e48 5641 /*!
Freescale_cup 0:3ec7fc598e48 5642 * @}
Freescale_cup 0:3ec7fc598e48 5643 */ /* end of group SysTick_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5644
Freescale_cup 0:3ec7fc598e48 5645
Freescale_cup 0:3ec7fc598e48 5646 /*!
Freescale_cup 0:3ec7fc598e48 5647 * @}
Freescale_cup 0:3ec7fc598e48 5648 */ /* end of group SysTick_Peripheral */
Freescale_cup 0:3ec7fc598e48 5649
Freescale_cup 0:3ec7fc598e48 5650
Freescale_cup 0:3ec7fc598e48 5651 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5652 -- TPM
Freescale_cup 0:3ec7fc598e48 5653 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5654
Freescale_cup 0:3ec7fc598e48 5655 /*!
Freescale_cup 0:3ec7fc598e48 5656 * @addtogroup TPM_Peripheral TPM
Freescale_cup 0:3ec7fc598e48 5657 * @{
Freescale_cup 0:3ec7fc598e48 5658 */
Freescale_cup 0:3ec7fc598e48 5659
Freescale_cup 0:3ec7fc598e48 5660 /** TPM - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 5661 typedef struct TPM_MemMap {
Freescale_cup 0:3ec7fc598e48 5662 uint32_t SC; /**< Status and Control, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 5663 uint32_t CNT; /**< Counter, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 5664 uint32_t MOD; /**< Modulo, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 5665 struct { /* offset: 0xC, array step: 0x8 */
Freescale_cup 0:3ec7fc598e48 5666 uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
Freescale_cup 0:3ec7fc598e48 5667 uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
Freescale_cup 0:3ec7fc598e48 5668 } CONTROLS[6];
Freescale_cup 0:3ec7fc598e48 5669 uint8_t RESERVED_0[20];
Freescale_cup 0:3ec7fc598e48 5670 uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
Freescale_cup 0:3ec7fc598e48 5671 uint8_t RESERVED_1[48];
Freescale_cup 0:3ec7fc598e48 5672 uint32_t CONF; /**< Configuration, offset: 0x84 */
Freescale_cup 0:3ec7fc598e48 5673 } volatile *TPM_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 5674
Freescale_cup 0:3ec7fc598e48 5675 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5676 -- TPM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5677 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5678
Freescale_cup 0:3ec7fc598e48 5679 /*!
Freescale_cup 0:3ec7fc598e48 5680 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5681 * @{
Freescale_cup 0:3ec7fc598e48 5682 */
Freescale_cup 0:3ec7fc598e48 5683
Freescale_cup 0:3ec7fc598e48 5684
Freescale_cup 0:3ec7fc598e48 5685 /* TPM - Register accessors */
Freescale_cup 0:3ec7fc598e48 5686 #define TPM_SC_REG(base) ((base)->SC)
Freescale_cup 0:3ec7fc598e48 5687 #define TPM_CNT_REG(base) ((base)->CNT)
Freescale_cup 0:3ec7fc598e48 5688 #define TPM_MOD_REG(base) ((base)->MOD)
Freescale_cup 0:3ec7fc598e48 5689 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
Freescale_cup 0:3ec7fc598e48 5690 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
Freescale_cup 0:3ec7fc598e48 5691 #define TPM_STATUS_REG(base) ((base)->STATUS)
Freescale_cup 0:3ec7fc598e48 5692 #define TPM_CONF_REG(base) ((base)->CONF)
Freescale_cup 0:3ec7fc598e48 5693
Freescale_cup 0:3ec7fc598e48 5694 /*!
Freescale_cup 0:3ec7fc598e48 5695 * @}
Freescale_cup 0:3ec7fc598e48 5696 */ /* end of group TPM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5697
Freescale_cup 0:3ec7fc598e48 5698
Freescale_cup 0:3ec7fc598e48 5699 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5700 -- TPM Register Masks
Freescale_cup 0:3ec7fc598e48 5701 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5702
Freescale_cup 0:3ec7fc598e48 5703 /*!
Freescale_cup 0:3ec7fc598e48 5704 * @addtogroup TPM_Register_Masks TPM Register Masks
Freescale_cup 0:3ec7fc598e48 5705 * @{
Freescale_cup 0:3ec7fc598e48 5706 */
Freescale_cup 0:3ec7fc598e48 5707
Freescale_cup 0:3ec7fc598e48 5708 /* SC Bit Fields */
Freescale_cup 0:3ec7fc598e48 5709 #define TPM_SC_PS_MASK 0x7u
Freescale_cup 0:3ec7fc598e48 5710 #define TPM_SC_PS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5711 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
Freescale_cup 0:3ec7fc598e48 5712 #define TPM_SC_CMOD_MASK 0x18u
Freescale_cup 0:3ec7fc598e48 5713 #define TPM_SC_CMOD_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5714 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
Freescale_cup 0:3ec7fc598e48 5715 #define TPM_SC_CPWMS_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5716 #define TPM_SC_CPWMS_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5717 #define TPM_SC_TOIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5718 #define TPM_SC_TOIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5719 #define TPM_SC_TOF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5720 #define TPM_SC_TOF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5721 #define TPM_SC_DMA_MASK 0x100u
Freescale_cup 0:3ec7fc598e48 5722 #define TPM_SC_DMA_SHIFT 8
Freescale_cup 0:3ec7fc598e48 5723 /* CNT Bit Fields */
Freescale_cup 0:3ec7fc598e48 5724 #define TPM_CNT_COUNT_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 5725 #define TPM_CNT_COUNT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5726 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
Freescale_cup 0:3ec7fc598e48 5727 /* MOD Bit Fields */
Freescale_cup 0:3ec7fc598e48 5728 #define TPM_MOD_MOD_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 5729 #define TPM_MOD_MOD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5730 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
Freescale_cup 0:3ec7fc598e48 5731 /* CnSC Bit Fields */
Freescale_cup 0:3ec7fc598e48 5732 #define TPM_CnSC_DMA_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5733 #define TPM_CnSC_DMA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5734 #define TPM_CnSC_ELSA_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5735 #define TPM_CnSC_ELSA_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5736 #define TPM_CnSC_ELSB_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5737 #define TPM_CnSC_ELSB_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5738 #define TPM_CnSC_MSA_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5739 #define TPM_CnSC_MSA_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5740 #define TPM_CnSC_MSB_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5741 #define TPM_CnSC_MSB_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5742 #define TPM_CnSC_CHIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5743 #define TPM_CnSC_CHIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5744 #define TPM_CnSC_CHF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5745 #define TPM_CnSC_CHF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5746 /* CnV Bit Fields */
Freescale_cup 0:3ec7fc598e48 5747 #define TPM_CnV_VAL_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 5748 #define TPM_CnV_VAL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5749 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
Freescale_cup 0:3ec7fc598e48 5750 /* STATUS Bit Fields */
Freescale_cup 0:3ec7fc598e48 5751 #define TPM_STATUS_CH0F_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 5752 #define TPM_STATUS_CH0F_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5753 #define TPM_STATUS_CH1F_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5754 #define TPM_STATUS_CH1F_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5755 #define TPM_STATUS_CH2F_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5756 #define TPM_STATUS_CH2F_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5757 #define TPM_STATUS_CH3F_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5758 #define TPM_STATUS_CH3F_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5759 #define TPM_STATUS_CH4F_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5760 #define TPM_STATUS_CH4F_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5761 #define TPM_STATUS_CH5F_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5762 #define TPM_STATUS_CH5F_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5763 #define TPM_STATUS_TOF_MASK 0x100u
Freescale_cup 0:3ec7fc598e48 5764 #define TPM_STATUS_TOF_SHIFT 8
Freescale_cup 0:3ec7fc598e48 5765 /* CONF Bit Fields */
Freescale_cup 0:3ec7fc598e48 5766 #define TPM_CONF_DOZEEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5767 #define TPM_CONF_DOZEEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5768 #define TPM_CONF_DBGMODE_MASK 0xC0u
Freescale_cup 0:3ec7fc598e48 5769 #define TPM_CONF_DBGMODE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5770 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
Freescale_cup 0:3ec7fc598e48 5771 #define TPM_CONF_GTBEEN_MASK 0x200u
Freescale_cup 0:3ec7fc598e48 5772 #define TPM_CONF_GTBEEN_SHIFT 9
Freescale_cup 0:3ec7fc598e48 5773 #define TPM_CONF_CSOT_MASK 0x10000u
Freescale_cup 0:3ec7fc598e48 5774 #define TPM_CONF_CSOT_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5775 #define TPM_CONF_CSOO_MASK 0x20000u
Freescale_cup 0:3ec7fc598e48 5776 #define TPM_CONF_CSOO_SHIFT 17
Freescale_cup 0:3ec7fc598e48 5777 #define TPM_CONF_CROT_MASK 0x40000u
Freescale_cup 0:3ec7fc598e48 5778 #define TPM_CONF_CROT_SHIFT 18
Freescale_cup 0:3ec7fc598e48 5779 #define TPM_CONF_TRGSEL_MASK 0xF000000u
Freescale_cup 0:3ec7fc598e48 5780 #define TPM_CONF_TRGSEL_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5781 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
Freescale_cup 0:3ec7fc598e48 5782
Freescale_cup 0:3ec7fc598e48 5783 /*!
Freescale_cup 0:3ec7fc598e48 5784 * @}
Freescale_cup 0:3ec7fc598e48 5785 */ /* end of group TPM_Register_Masks */
Freescale_cup 0:3ec7fc598e48 5786
Freescale_cup 0:3ec7fc598e48 5787
Freescale_cup 0:3ec7fc598e48 5788 /* TPM - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 5789 /** Peripheral TPM0 base pointer */
Freescale_cup 0:3ec7fc598e48 5790 #define TPM0_BASE_PTR ((TPM_MemMapPtr)0x40038000u)
Freescale_cup 0:3ec7fc598e48 5791 /** Peripheral TPM1 base pointer */
Freescale_cup 0:3ec7fc598e48 5792 #define TPM1_BASE_PTR ((TPM_MemMapPtr)0x40039000u)
Freescale_cup 0:3ec7fc598e48 5793 /** Peripheral TPM2 base pointer */
Freescale_cup 0:3ec7fc598e48 5794 #define TPM2_BASE_PTR ((TPM_MemMapPtr)0x4003A000u)
Freescale_cup 0:3ec7fc598e48 5795 /** Array initializer of TPM peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 5796 #define TPM_BASE_PTRS { TPM0_BASE_PTR, TPM1_BASE_PTR, TPM2_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 5797
Freescale_cup 0:3ec7fc598e48 5798 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5799 -- TPM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5800 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5801
Freescale_cup 0:3ec7fc598e48 5802 /*!
Freescale_cup 0:3ec7fc598e48 5803 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5804 * @{
Freescale_cup 0:3ec7fc598e48 5805 */
Freescale_cup 0:3ec7fc598e48 5806
Freescale_cup 0:3ec7fc598e48 5807
Freescale_cup 0:3ec7fc598e48 5808 /* TPM - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 5809 /* TPM0 */
Freescale_cup 0:3ec7fc598e48 5810 #define TPM0_SC TPM_SC_REG(TPM0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5811 #define TPM0_CNT TPM_CNT_REG(TPM0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5812 #define TPM0_MOD TPM_MOD_REG(TPM0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5813 #define TPM0_C0SC TPM_CnSC_REG(TPM0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 5814 #define TPM0_C0V TPM_CnV_REG(TPM0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 5815 #define TPM0_C1SC TPM_CnSC_REG(TPM0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 5816 #define TPM0_C1V TPM_CnV_REG(TPM0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 5817 #define TPM0_C2SC TPM_CnSC_REG(TPM0_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 5818 #define TPM0_C2V TPM_CnV_REG(TPM0_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 5819 #define TPM0_C3SC TPM_CnSC_REG(TPM0_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 5820 #define TPM0_C3V TPM_CnV_REG(TPM0_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 5821 #define TPM0_C4SC TPM_CnSC_REG(TPM0_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 5822 #define TPM0_C4V TPM_CnV_REG(TPM0_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 5823 #define TPM0_C5SC TPM_CnSC_REG(TPM0_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 5824 #define TPM0_C5V TPM_CnV_REG(TPM0_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 5825 #define TPM0_STATUS TPM_STATUS_REG(TPM0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5826 #define TPM0_CONF TPM_CONF_REG(TPM0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5827 /* TPM1 */
Freescale_cup 0:3ec7fc598e48 5828 #define TPM1_SC TPM_SC_REG(TPM1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5829 #define TPM1_CNT TPM_CNT_REG(TPM1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5830 #define TPM1_MOD TPM_MOD_REG(TPM1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5831 #define TPM1_C0SC TPM_CnSC_REG(TPM1_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 5832 #define TPM1_C0V TPM_CnV_REG(TPM1_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 5833 #define TPM1_C1SC TPM_CnSC_REG(TPM1_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 5834 #define TPM1_C1V TPM_CnV_REG(TPM1_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 5835 #define TPM1_STATUS TPM_STATUS_REG(TPM1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5836 #define TPM1_CONF TPM_CONF_REG(TPM1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5837 /* TPM2 */
Freescale_cup 0:3ec7fc598e48 5838 #define TPM2_SC TPM_SC_REG(TPM2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5839 #define TPM2_CNT TPM_CNT_REG(TPM2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5840 #define TPM2_MOD TPM_MOD_REG(TPM2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5841 #define TPM2_C0SC TPM_CnSC_REG(TPM2_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 5842 #define TPM2_C0V TPM_CnV_REG(TPM2_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 5843 #define TPM2_C1SC TPM_CnSC_REG(TPM2_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 5844 #define TPM2_C1V TPM_CnV_REG(TPM2_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 5845 #define TPM2_STATUS TPM_STATUS_REG(TPM2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5846 #define TPM2_CONF TPM_CONF_REG(TPM2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5847
Freescale_cup 0:3ec7fc598e48 5848 /* TPM - Register array accessors */
Freescale_cup 0:3ec7fc598e48 5849 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 5850 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 5851 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 5852 #define TPM0_CnV(index) TPM_CnV_REG(TPM0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 5853 #define TPM1_CnV(index) TPM_CnV_REG(TPM1_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 5854 #define TPM2_CnV(index) TPM_CnV_REG(TPM2_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 5855
Freescale_cup 0:3ec7fc598e48 5856 /*!
Freescale_cup 0:3ec7fc598e48 5857 * @}
Freescale_cup 0:3ec7fc598e48 5858 */ /* end of group TPM_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5859
Freescale_cup 0:3ec7fc598e48 5860
Freescale_cup 0:3ec7fc598e48 5861 /*!
Freescale_cup 0:3ec7fc598e48 5862 * @}
Freescale_cup 0:3ec7fc598e48 5863 */ /* end of group TPM_Peripheral */
Freescale_cup 0:3ec7fc598e48 5864
Freescale_cup 0:3ec7fc598e48 5865
Freescale_cup 0:3ec7fc598e48 5866 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5867 -- TSI
Freescale_cup 0:3ec7fc598e48 5868 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5869
Freescale_cup 0:3ec7fc598e48 5870 /*!
Freescale_cup 0:3ec7fc598e48 5871 * @addtogroup TSI_Peripheral TSI
Freescale_cup 0:3ec7fc598e48 5872 * @{
Freescale_cup 0:3ec7fc598e48 5873 */
Freescale_cup 0:3ec7fc598e48 5874
Freescale_cup 0:3ec7fc598e48 5875 /** TSI - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 5876 typedef struct TSI_MemMap {
Freescale_cup 0:3ec7fc598e48 5877 uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 5878 uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 5879 uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 5880 } volatile *TSI_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 5881
Freescale_cup 0:3ec7fc598e48 5882 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5883 -- TSI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5884 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5885
Freescale_cup 0:3ec7fc598e48 5886 /*!
Freescale_cup 0:3ec7fc598e48 5887 * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5888 * @{
Freescale_cup 0:3ec7fc598e48 5889 */
Freescale_cup 0:3ec7fc598e48 5890
Freescale_cup 0:3ec7fc598e48 5891
Freescale_cup 0:3ec7fc598e48 5892 /* TSI - Register accessors */
Freescale_cup 0:3ec7fc598e48 5893 #define TSI_GENCS_REG(base) ((base)->GENCS)
Freescale_cup 0:3ec7fc598e48 5894 #define TSI_DATA_REG(base) ((base)->DATA)
Freescale_cup 0:3ec7fc598e48 5895 #define TSI_TSHD_REG(base) ((base)->TSHD)
Freescale_cup 0:3ec7fc598e48 5896
Freescale_cup 0:3ec7fc598e48 5897 /*!
Freescale_cup 0:3ec7fc598e48 5898 * @}
Freescale_cup 0:3ec7fc598e48 5899 */ /* end of group TSI_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5900
Freescale_cup 0:3ec7fc598e48 5901
Freescale_cup 0:3ec7fc598e48 5902 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5903 -- TSI Register Masks
Freescale_cup 0:3ec7fc598e48 5904 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5905
Freescale_cup 0:3ec7fc598e48 5906 /*!
Freescale_cup 0:3ec7fc598e48 5907 * @addtogroup TSI_Register_Masks TSI Register Masks
Freescale_cup 0:3ec7fc598e48 5908 * @{
Freescale_cup 0:3ec7fc598e48 5909 */
Freescale_cup 0:3ec7fc598e48 5910
Freescale_cup 0:3ec7fc598e48 5911 /* GENCS Bit Fields */
Freescale_cup 0:3ec7fc598e48 5912 #define TSI_GENCS_CURSW_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 5913 #define TSI_GENCS_CURSW_SHIFT 1
Freescale_cup 0:3ec7fc598e48 5914 #define TSI_GENCS_EOSF_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 5915 #define TSI_GENCS_EOSF_SHIFT 2
Freescale_cup 0:3ec7fc598e48 5916 #define TSI_GENCS_SCNIP_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 5917 #define TSI_GENCS_SCNIP_SHIFT 3
Freescale_cup 0:3ec7fc598e48 5918 #define TSI_GENCS_STM_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 5919 #define TSI_GENCS_STM_SHIFT 4
Freescale_cup 0:3ec7fc598e48 5920 #define TSI_GENCS_STPE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 5921 #define TSI_GENCS_STPE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 5922 #define TSI_GENCS_TSIIEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 5923 #define TSI_GENCS_TSIIEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 5924 #define TSI_GENCS_TSIEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 5925 #define TSI_GENCS_TSIEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 5926 #define TSI_GENCS_NSCN_MASK 0x1F00u
Freescale_cup 0:3ec7fc598e48 5927 #define TSI_GENCS_NSCN_SHIFT 8
Freescale_cup 0:3ec7fc598e48 5928 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
Freescale_cup 0:3ec7fc598e48 5929 #define TSI_GENCS_PS_MASK 0xE000u
Freescale_cup 0:3ec7fc598e48 5930 #define TSI_GENCS_PS_SHIFT 13
Freescale_cup 0:3ec7fc598e48 5931 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
Freescale_cup 0:3ec7fc598e48 5932 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
Freescale_cup 0:3ec7fc598e48 5933 #define TSI_GENCS_EXTCHRG_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5934 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
Freescale_cup 0:3ec7fc598e48 5935 #define TSI_GENCS_DVOLT_MASK 0x180000u
Freescale_cup 0:3ec7fc598e48 5936 #define TSI_GENCS_DVOLT_SHIFT 19
Freescale_cup 0:3ec7fc598e48 5937 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
Freescale_cup 0:3ec7fc598e48 5938 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
Freescale_cup 0:3ec7fc598e48 5939 #define TSI_GENCS_REFCHRG_SHIFT 21
Freescale_cup 0:3ec7fc598e48 5940 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
Freescale_cup 0:3ec7fc598e48 5941 #define TSI_GENCS_MODE_MASK 0xF000000u
Freescale_cup 0:3ec7fc598e48 5942 #define TSI_GENCS_MODE_SHIFT 24
Freescale_cup 0:3ec7fc598e48 5943 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
Freescale_cup 0:3ec7fc598e48 5944 #define TSI_GENCS_ESOR_MASK 0x10000000u
Freescale_cup 0:3ec7fc598e48 5945 #define TSI_GENCS_ESOR_SHIFT 28
Freescale_cup 0:3ec7fc598e48 5946 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
Freescale_cup 0:3ec7fc598e48 5947 #define TSI_GENCS_OUTRGF_SHIFT 31
Freescale_cup 0:3ec7fc598e48 5948 /* DATA Bit Fields */
Freescale_cup 0:3ec7fc598e48 5949 #define TSI_DATA_TSICNT_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 5950 #define TSI_DATA_TSICNT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5951 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
Freescale_cup 0:3ec7fc598e48 5952 #define TSI_DATA_SWTS_MASK 0x400000u
Freescale_cup 0:3ec7fc598e48 5953 #define TSI_DATA_SWTS_SHIFT 22
Freescale_cup 0:3ec7fc598e48 5954 #define TSI_DATA_DMAEN_MASK 0x800000u
Freescale_cup 0:3ec7fc598e48 5955 #define TSI_DATA_DMAEN_SHIFT 23
Freescale_cup 0:3ec7fc598e48 5956 #define TSI_DATA_TSICH_MASK 0xF0000000u
Freescale_cup 0:3ec7fc598e48 5957 #define TSI_DATA_TSICH_SHIFT 28
Freescale_cup 0:3ec7fc598e48 5958 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
Freescale_cup 0:3ec7fc598e48 5959 /* TSHD Bit Fields */
Freescale_cup 0:3ec7fc598e48 5960 #define TSI_TSHD_THRESL_MASK 0xFFFFu
Freescale_cup 0:3ec7fc598e48 5961 #define TSI_TSHD_THRESL_SHIFT 0
Freescale_cup 0:3ec7fc598e48 5962 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
Freescale_cup 0:3ec7fc598e48 5963 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
Freescale_cup 0:3ec7fc598e48 5964 #define TSI_TSHD_THRESH_SHIFT 16
Freescale_cup 0:3ec7fc598e48 5965 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
Freescale_cup 0:3ec7fc598e48 5966
Freescale_cup 0:3ec7fc598e48 5967 /*!
Freescale_cup 0:3ec7fc598e48 5968 * @}
Freescale_cup 0:3ec7fc598e48 5969 */ /* end of group TSI_Register_Masks */
Freescale_cup 0:3ec7fc598e48 5970
Freescale_cup 0:3ec7fc598e48 5971
Freescale_cup 0:3ec7fc598e48 5972 /* TSI - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 5973 /** Peripheral TSI0 base pointer */
Freescale_cup 0:3ec7fc598e48 5974 #define TSI0_BASE_PTR ((TSI_MemMapPtr)0x40045000u)
Freescale_cup 0:3ec7fc598e48 5975 /** Array initializer of TSI peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 5976 #define TSI_BASE_PTRS { TSI0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 5977
Freescale_cup 0:3ec7fc598e48 5978 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 5979 -- TSI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5980 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 5981
Freescale_cup 0:3ec7fc598e48 5982 /*!
Freescale_cup 0:3ec7fc598e48 5983 * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
Freescale_cup 0:3ec7fc598e48 5984 * @{
Freescale_cup 0:3ec7fc598e48 5985 */
Freescale_cup 0:3ec7fc598e48 5986
Freescale_cup 0:3ec7fc598e48 5987
Freescale_cup 0:3ec7fc598e48 5988 /* TSI - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 5989 /* TSI0 */
Freescale_cup 0:3ec7fc598e48 5990 #define TSI0_GENCS TSI_GENCS_REG(TSI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5991 #define TSI0_DATA TSI_DATA_REG(TSI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5992 #define TSI0_TSHD TSI_TSHD_REG(TSI0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 5993
Freescale_cup 0:3ec7fc598e48 5994 /*!
Freescale_cup 0:3ec7fc598e48 5995 * @}
Freescale_cup 0:3ec7fc598e48 5996 */ /* end of group TSI_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 5997
Freescale_cup 0:3ec7fc598e48 5998
Freescale_cup 0:3ec7fc598e48 5999 /*!
Freescale_cup 0:3ec7fc598e48 6000 * @}
Freescale_cup 0:3ec7fc598e48 6001 */ /* end of group TSI_Peripheral */
Freescale_cup 0:3ec7fc598e48 6002
Freescale_cup 0:3ec7fc598e48 6003
Freescale_cup 0:3ec7fc598e48 6004 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6005 -- UART
Freescale_cup 0:3ec7fc598e48 6006 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6007
Freescale_cup 0:3ec7fc598e48 6008 /*!
Freescale_cup 0:3ec7fc598e48 6009 * @addtogroup UART_Peripheral UART
Freescale_cup 0:3ec7fc598e48 6010 * @{
Freescale_cup 0:3ec7fc598e48 6011 */
Freescale_cup 0:3ec7fc598e48 6012
Freescale_cup 0:3ec7fc598e48 6013 /** UART - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 6014 typedef struct UART_MemMap {
Freescale_cup 0:3ec7fc598e48 6015 uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 6016 uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 6017 uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 6018 uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 6019 uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 6020 uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 6021 uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 6022 uint8_t D; /**< UART Data Register, offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 6023 uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 6024 } volatile *UART_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 6025
Freescale_cup 0:3ec7fc598e48 6026 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6027 -- UART - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6028 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6029
Freescale_cup 0:3ec7fc598e48 6030 /*!
Freescale_cup 0:3ec7fc598e48 6031 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6032 * @{
Freescale_cup 0:3ec7fc598e48 6033 */
Freescale_cup 0:3ec7fc598e48 6034
Freescale_cup 0:3ec7fc598e48 6035
Freescale_cup 0:3ec7fc598e48 6036 /* UART - Register accessors */
Freescale_cup 0:3ec7fc598e48 6037 #define UART_BDH_REG(base) ((base)->BDH)
Freescale_cup 0:3ec7fc598e48 6038 #define UART_BDL_REG(base) ((base)->BDL)
Freescale_cup 0:3ec7fc598e48 6039 #define UART_C1_REG(base) ((base)->C1)
Freescale_cup 0:3ec7fc598e48 6040 #define UART_C2_REG(base) ((base)->C2)
Freescale_cup 0:3ec7fc598e48 6041 #define UART_S1_REG(base) ((base)->S1)
Freescale_cup 0:3ec7fc598e48 6042 #define UART_S2_REG(base) ((base)->S2)
Freescale_cup 0:3ec7fc598e48 6043 #define UART_C3_REG(base) ((base)->C3)
Freescale_cup 0:3ec7fc598e48 6044 #define UART_D_REG(base) ((base)->D)
Freescale_cup 0:3ec7fc598e48 6045 #define UART_C4_REG(base) ((base)->C4)
Freescale_cup 0:3ec7fc598e48 6046
Freescale_cup 0:3ec7fc598e48 6047 /*!
Freescale_cup 0:3ec7fc598e48 6048 * @}
Freescale_cup 0:3ec7fc598e48 6049 */ /* end of group UART_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 6050
Freescale_cup 0:3ec7fc598e48 6051
Freescale_cup 0:3ec7fc598e48 6052 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6053 -- UART Register Masks
Freescale_cup 0:3ec7fc598e48 6054 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6055
Freescale_cup 0:3ec7fc598e48 6056 /*!
Freescale_cup 0:3ec7fc598e48 6057 * @addtogroup UART_Register_Masks UART Register Masks
Freescale_cup 0:3ec7fc598e48 6058 * @{
Freescale_cup 0:3ec7fc598e48 6059 */
Freescale_cup 0:3ec7fc598e48 6060
Freescale_cup 0:3ec7fc598e48 6061 /* BDH Bit Fields */
Freescale_cup 0:3ec7fc598e48 6062 #define UART_BDH_SBR_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 6063 #define UART_BDH_SBR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6064 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
Freescale_cup 0:3ec7fc598e48 6065 #define UART_BDH_SBNS_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6066 #define UART_BDH_SBNS_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6067 #define UART_BDH_RXEDGIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6068 #define UART_BDH_RXEDGIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6069 #define UART_BDH_LBKDIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6070 #define UART_BDH_LBKDIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6071 /* BDL Bit Fields */
Freescale_cup 0:3ec7fc598e48 6072 #define UART_BDL_SBR_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6073 #define UART_BDL_SBR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6074 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
Freescale_cup 0:3ec7fc598e48 6075 /* C1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6076 #define UART_C1_PT_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6077 #define UART_C1_PT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6078 #define UART_C1_PE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6079 #define UART_C1_PE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6080 #define UART_C1_ILT_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6081 #define UART_C1_ILT_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6082 #define UART_C1_WAKE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6083 #define UART_C1_WAKE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6084 #define UART_C1_M_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6085 #define UART_C1_M_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6086 #define UART_C1_RSRC_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6087 #define UART_C1_RSRC_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6088 #define UART_C1_UARTSWAI_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6089 #define UART_C1_UARTSWAI_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6090 #define UART_C1_LOOPS_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6091 #define UART_C1_LOOPS_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6092 /* C2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6093 #define UART_C2_SBK_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6094 #define UART_C2_SBK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6095 #define UART_C2_RWU_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6096 #define UART_C2_RWU_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6097 #define UART_C2_RE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6098 #define UART_C2_RE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6099 #define UART_C2_TE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6100 #define UART_C2_TE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6101 #define UART_C2_ILIE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6102 #define UART_C2_ILIE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6103 #define UART_C2_RIE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6104 #define UART_C2_RIE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6105 #define UART_C2_TCIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6106 #define UART_C2_TCIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6107 #define UART_C2_TIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6108 #define UART_C2_TIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6109 /* S1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6110 #define UART_S1_PF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6111 #define UART_S1_PF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6112 #define UART_S1_FE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6113 #define UART_S1_FE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6114 #define UART_S1_NF_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6115 #define UART_S1_NF_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6116 #define UART_S1_OR_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6117 #define UART_S1_OR_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6118 #define UART_S1_IDLE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6119 #define UART_S1_IDLE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6120 #define UART_S1_RDRF_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6121 #define UART_S1_RDRF_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6122 #define UART_S1_TC_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6123 #define UART_S1_TC_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6124 #define UART_S1_TDRE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6125 #define UART_S1_TDRE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6126 /* S2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6127 #define UART_S2_RAF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6128 #define UART_S2_RAF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6129 #define UART_S2_LBKDE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6130 #define UART_S2_LBKDE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6131 #define UART_S2_BRK13_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6132 #define UART_S2_BRK13_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6133 #define UART_S2_RWUID_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6134 #define UART_S2_RWUID_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6135 #define UART_S2_RXINV_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6136 #define UART_S2_RXINV_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6137 #define UART_S2_RXEDGIF_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6138 #define UART_S2_RXEDGIF_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6139 #define UART_S2_LBKDIF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6140 #define UART_S2_LBKDIF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6141 /* C3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6142 #define UART_C3_PEIE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6143 #define UART_C3_PEIE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6144 #define UART_C3_FEIE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6145 #define UART_C3_FEIE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6146 #define UART_C3_NEIE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6147 #define UART_C3_NEIE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6148 #define UART_C3_ORIE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6149 #define UART_C3_ORIE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6150 #define UART_C3_TXINV_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6151 #define UART_C3_TXINV_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6152 #define UART_C3_TXDIR_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6153 #define UART_C3_TXDIR_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6154 #define UART_C3_T8_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6155 #define UART_C3_T8_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6156 #define UART_C3_R8_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6157 #define UART_C3_R8_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6158 /* D Bit Fields */
Freescale_cup 0:3ec7fc598e48 6159 #define UART_D_R0T0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6160 #define UART_D_R0T0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6161 #define UART_D_R1T1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6162 #define UART_D_R1T1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6163 #define UART_D_R2T2_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6164 #define UART_D_R2T2_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6165 #define UART_D_R3T3_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6166 #define UART_D_R3T3_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6167 #define UART_D_R4T4_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6168 #define UART_D_R4T4_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6169 #define UART_D_R5T5_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6170 #define UART_D_R5T5_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6171 #define UART_D_R6T6_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6172 #define UART_D_R6T6_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6173 #define UART_D_R7T7_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6174 #define UART_D_R7T7_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6175 /* C4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6176 #define UART_C4_RDMAS_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6177 #define UART_C4_RDMAS_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6178 #define UART_C4_TDMAS_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6179 #define UART_C4_TDMAS_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6180
Freescale_cup 0:3ec7fc598e48 6181 /*!
Freescale_cup 0:3ec7fc598e48 6182 * @}
Freescale_cup 0:3ec7fc598e48 6183 */ /* end of group UART_Register_Masks */
Freescale_cup 0:3ec7fc598e48 6184
Freescale_cup 0:3ec7fc598e48 6185
Freescale_cup 0:3ec7fc598e48 6186 /* UART - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 6187 /** Peripheral UART1 base pointer */
Freescale_cup 0:3ec7fc598e48 6188 #define UART1_BASE_PTR ((UART_MemMapPtr)0x4006B000u)
Freescale_cup 0:3ec7fc598e48 6189 /** Peripheral UART2 base pointer */
Freescale_cup 0:3ec7fc598e48 6190 #define UART2_BASE_PTR ((UART_MemMapPtr)0x4006C000u)
Freescale_cup 0:3ec7fc598e48 6191 /** Array initializer of UART peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 6192 #define UART_BASE_PTRS { UART1_BASE_PTR, UART2_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 6193
Freescale_cup 0:3ec7fc598e48 6194 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6195 -- UART - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6196 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6197
Freescale_cup 0:3ec7fc598e48 6198 /*!
Freescale_cup 0:3ec7fc598e48 6199 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6200 * @{
Freescale_cup 0:3ec7fc598e48 6201 */
Freescale_cup 0:3ec7fc598e48 6202
Freescale_cup 0:3ec7fc598e48 6203
Freescale_cup 0:3ec7fc598e48 6204 /* UART - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 6205 /* UART1 */
Freescale_cup 0:3ec7fc598e48 6206 #define UART1_BDH UART_BDH_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6207 #define UART1_BDL UART_BDL_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6208 #define UART1_C1 UART_C1_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6209 #define UART1_C2 UART_C2_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6210 #define UART1_S1 UART_S1_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6211 #define UART1_S2 UART_S2_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6212 #define UART1_C3 UART_C3_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6213 #define UART1_D UART_D_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6214 #define UART1_C4 UART_C4_REG(UART1_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6215 /* UART2 */
Freescale_cup 0:3ec7fc598e48 6216 #define UART2_BDH UART_BDH_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6217 #define UART2_BDL UART_BDL_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6218 #define UART2_C1 UART_C1_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6219 #define UART2_C2 UART_C2_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6220 #define UART2_S1 UART_S1_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6221 #define UART2_S2 UART_S2_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6222 #define UART2_C3 UART_C3_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6223 #define UART2_D UART_D_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6224 #define UART2_C4 UART_C4_REG(UART2_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6225
Freescale_cup 0:3ec7fc598e48 6226 /*!
Freescale_cup 0:3ec7fc598e48 6227 * @}
Freescale_cup 0:3ec7fc598e48 6228 */ /* end of group UART_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 6229
Freescale_cup 0:3ec7fc598e48 6230
Freescale_cup 0:3ec7fc598e48 6231 /*!
Freescale_cup 0:3ec7fc598e48 6232 * @}
Freescale_cup 0:3ec7fc598e48 6233 */ /* end of group UART_Peripheral */
Freescale_cup 0:3ec7fc598e48 6234
Freescale_cup 0:3ec7fc598e48 6235
Freescale_cup 0:3ec7fc598e48 6236 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6237 -- UART0
Freescale_cup 0:3ec7fc598e48 6238 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6239
Freescale_cup 0:3ec7fc598e48 6240 /*!
Freescale_cup 0:3ec7fc598e48 6241 * @addtogroup UART0_Peripheral UART0
Freescale_cup 0:3ec7fc598e48 6242 * @{
Freescale_cup 0:3ec7fc598e48 6243 */
Freescale_cup 0:3ec7fc598e48 6244
Freescale_cup 0:3ec7fc598e48 6245 /** UART0 - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 6246 typedef struct UART0_MemMap {
Freescale_cup 0:3ec7fc598e48 6247 uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 6248 uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
Freescale_cup 0:3ec7fc598e48 6249 uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
Freescale_cup 0:3ec7fc598e48 6250 uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
Freescale_cup 0:3ec7fc598e48 6251 uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 6252 uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
Freescale_cup 0:3ec7fc598e48 6253 uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
Freescale_cup 0:3ec7fc598e48 6254 uint8_t D; /**< UART Data Register, offset: 0x7 */
Freescale_cup 0:3ec7fc598e48 6255 uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 6256 uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
Freescale_cup 0:3ec7fc598e48 6257 uint8_t C4; /**< UART Control Register 4, offset: 0xA */
Freescale_cup 0:3ec7fc598e48 6258 uint8_t C5; /**< UART Control Register 5, offset: 0xB */
Freescale_cup 0:3ec7fc598e48 6259 } volatile *UART0_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 6260
Freescale_cup 0:3ec7fc598e48 6261 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6262 -- UART0 - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6263 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6264
Freescale_cup 0:3ec7fc598e48 6265 /*!
Freescale_cup 0:3ec7fc598e48 6266 * @addtogroup UART0_Register_Accessor_Macros UART0 - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6267 * @{
Freescale_cup 0:3ec7fc598e48 6268 */
Freescale_cup 0:3ec7fc598e48 6269
Freescale_cup 0:3ec7fc598e48 6270
Freescale_cup 0:3ec7fc598e48 6271 /* UART0 - Register accessors */
Freescale_cup 0:3ec7fc598e48 6272 #define UART0_BDH_REG(base) ((base)->BDH)
Freescale_cup 0:3ec7fc598e48 6273 #define UART0_BDL_REG(base) ((base)->BDL)
Freescale_cup 0:3ec7fc598e48 6274 #define UART0_C1_REG(base) ((base)->C1)
Freescale_cup 0:3ec7fc598e48 6275 #define UART0_C2_REG(base) ((base)->C2)
Freescale_cup 0:3ec7fc598e48 6276 #define UART0_S1_REG(base) ((base)->S1)
Freescale_cup 0:3ec7fc598e48 6277 #define UART0_S2_REG(base) ((base)->S2)
Freescale_cup 0:3ec7fc598e48 6278 #define UART0_C3_REG(base) ((base)->C3)
Freescale_cup 0:3ec7fc598e48 6279 #define UART0_D_REG(base) ((base)->D)
Freescale_cup 0:3ec7fc598e48 6280 #define UART0_MA1_REG(base) ((base)->MA1)
Freescale_cup 0:3ec7fc598e48 6281 #define UART0_MA2_REG(base) ((base)->MA2)
Freescale_cup 0:3ec7fc598e48 6282 #define UART0_C4_REG(base) ((base)->C4)
Freescale_cup 0:3ec7fc598e48 6283 #define UART0_C5_REG(base) ((base)->C5)
Freescale_cup 0:3ec7fc598e48 6284
Freescale_cup 0:3ec7fc598e48 6285 /*!
Freescale_cup 0:3ec7fc598e48 6286 * @}
Freescale_cup 0:3ec7fc598e48 6287 */ /* end of group UART0_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 6288
Freescale_cup 0:3ec7fc598e48 6289
Freescale_cup 0:3ec7fc598e48 6290 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6291 -- UART0 Register Masks
Freescale_cup 0:3ec7fc598e48 6292 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6293
Freescale_cup 0:3ec7fc598e48 6294 /*!
Freescale_cup 0:3ec7fc598e48 6295 * @addtogroup UART0_Register_Masks UART0 Register Masks
Freescale_cup 0:3ec7fc598e48 6296 * @{
Freescale_cup 0:3ec7fc598e48 6297 */
Freescale_cup 0:3ec7fc598e48 6298
Freescale_cup 0:3ec7fc598e48 6299 /* BDH Bit Fields */
Freescale_cup 0:3ec7fc598e48 6300 #define UART0_BDH_SBR_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 6301 #define UART0_BDH_SBR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6302 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
Freescale_cup 0:3ec7fc598e48 6303 #define UART0_BDH_SBNS_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6304 #define UART0_BDH_SBNS_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6305 #define UART0_BDH_RXEDGIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6306 #define UART0_BDH_RXEDGIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6307 #define UART0_BDH_LBKDIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6308 #define UART0_BDH_LBKDIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6309 /* BDL Bit Fields */
Freescale_cup 0:3ec7fc598e48 6310 #define UART0_BDL_SBR_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6311 #define UART0_BDL_SBR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6312 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
Freescale_cup 0:3ec7fc598e48 6313 /* C1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6314 #define UART0_C1_PT_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6315 #define UART0_C1_PT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6316 #define UART0_C1_PE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6317 #define UART0_C1_PE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6318 #define UART0_C1_ILT_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6319 #define UART0_C1_ILT_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6320 #define UART0_C1_WAKE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6321 #define UART0_C1_WAKE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6322 #define UART0_C1_M_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6323 #define UART0_C1_M_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6324 #define UART0_C1_RSRC_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6325 #define UART0_C1_RSRC_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6326 #define UART0_C1_DOZEEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6327 #define UART0_C1_DOZEEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6328 #define UART0_C1_LOOPS_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6329 #define UART0_C1_LOOPS_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6330 /* C2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6331 #define UART0_C2_SBK_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6332 #define UART0_C2_SBK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6333 #define UART0_C2_RWU_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6334 #define UART0_C2_RWU_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6335 #define UART0_C2_RE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6336 #define UART0_C2_RE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6337 #define UART0_C2_TE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6338 #define UART0_C2_TE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6339 #define UART0_C2_ILIE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6340 #define UART0_C2_ILIE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6341 #define UART0_C2_RIE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6342 #define UART0_C2_RIE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6343 #define UART0_C2_TCIE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6344 #define UART0_C2_TCIE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6345 #define UART0_C2_TIE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6346 #define UART0_C2_TIE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6347 /* S1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6348 #define UART0_S1_PF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6349 #define UART0_S1_PF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6350 #define UART0_S1_FE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6351 #define UART0_S1_FE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6352 #define UART0_S1_NF_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6353 #define UART0_S1_NF_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6354 #define UART0_S1_OR_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6355 #define UART0_S1_OR_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6356 #define UART0_S1_IDLE_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6357 #define UART0_S1_IDLE_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6358 #define UART0_S1_RDRF_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6359 #define UART0_S1_RDRF_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6360 #define UART0_S1_TC_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6361 #define UART0_S1_TC_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6362 #define UART0_S1_TDRE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6363 #define UART0_S1_TDRE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6364 /* S2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6365 #define UART0_S2_RAF_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6366 #define UART0_S2_RAF_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6367 #define UART0_S2_LBKDE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6368 #define UART0_S2_LBKDE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6369 #define UART0_S2_BRK13_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6370 #define UART0_S2_BRK13_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6371 #define UART0_S2_RWUID_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6372 #define UART0_S2_RWUID_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6373 #define UART0_S2_RXINV_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6374 #define UART0_S2_RXINV_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6375 #define UART0_S2_MSBF_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6376 #define UART0_S2_MSBF_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6377 #define UART0_S2_RXEDGIF_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6378 #define UART0_S2_RXEDGIF_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6379 #define UART0_S2_LBKDIF_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6380 #define UART0_S2_LBKDIF_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6381 /* C3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6382 #define UART0_C3_PEIE_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6383 #define UART0_C3_PEIE_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6384 #define UART0_C3_FEIE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6385 #define UART0_C3_FEIE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6386 #define UART0_C3_NEIE_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6387 #define UART0_C3_NEIE_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6388 #define UART0_C3_ORIE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6389 #define UART0_C3_ORIE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6390 #define UART0_C3_TXINV_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6391 #define UART0_C3_TXINV_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6392 #define UART0_C3_TXDIR_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6393 #define UART0_C3_TXDIR_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6394 #define UART0_C3_R9T8_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6395 #define UART0_C3_R9T8_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6396 #define UART0_C3_R8T9_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6397 #define UART0_C3_R8T9_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6398 /* D Bit Fields */
Freescale_cup 0:3ec7fc598e48 6399 #define UART0_D_R0T0_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6400 #define UART0_D_R0T0_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6401 #define UART0_D_R1T1_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6402 #define UART0_D_R1T1_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6403 #define UART0_D_R2T2_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6404 #define UART0_D_R2T2_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6405 #define UART0_D_R3T3_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6406 #define UART0_D_R3T3_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6407 #define UART0_D_R4T4_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6408 #define UART0_D_R4T4_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6409 #define UART0_D_R5T5_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6410 #define UART0_D_R5T5_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6411 #define UART0_D_R6T6_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6412 #define UART0_D_R6T6_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6413 #define UART0_D_R7T7_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6414 #define UART0_D_R7T7_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6415 /* MA1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6416 #define UART0_MA1_MA_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6417 #define UART0_MA1_MA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6418 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
Freescale_cup 0:3ec7fc598e48 6419 /* MA2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6420 #define UART0_MA2_MA_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6421 #define UART0_MA2_MA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6422 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
Freescale_cup 0:3ec7fc598e48 6423 /* C4 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6424 #define UART0_C4_OSR_MASK 0x1Fu
Freescale_cup 0:3ec7fc598e48 6425 #define UART0_C4_OSR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6426 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
Freescale_cup 0:3ec7fc598e48 6427 #define UART0_C4_M10_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6428 #define UART0_C4_M10_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6429 #define UART0_C4_MAEN2_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6430 #define UART0_C4_MAEN2_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6431 #define UART0_C4_MAEN1_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6432 #define UART0_C4_MAEN1_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6433 /* C5 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6434 #define UART0_C5_RESYNCDIS_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6435 #define UART0_C5_RESYNCDIS_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6436 #define UART0_C5_BOTHEDGE_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6437 #define UART0_C5_BOTHEDGE_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6438 #define UART0_C5_RDMAE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6439 #define UART0_C5_RDMAE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6440 #define UART0_C5_TDMAE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6441 #define UART0_C5_TDMAE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6442
Freescale_cup 0:3ec7fc598e48 6443 /*!
Freescale_cup 0:3ec7fc598e48 6444 * @}
Freescale_cup 0:3ec7fc598e48 6445 */ /* end of group UART0_Register_Masks */
Freescale_cup 0:3ec7fc598e48 6446
Freescale_cup 0:3ec7fc598e48 6447
Freescale_cup 0:3ec7fc598e48 6448 /* UART0 - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 6449 /** Peripheral UART0 base pointer */
Freescale_cup 0:3ec7fc598e48 6450 #define UART0_BASE_PTR ((UART0_MemMapPtr)0x4006A000u)
Freescale_cup 0:3ec7fc598e48 6451 /** Array initializer of UART0 peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 6452 #define UART0_BASE_PTRS { UART0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 6453
Freescale_cup 0:3ec7fc598e48 6454 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6455 -- UART0 - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6456 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6457
Freescale_cup 0:3ec7fc598e48 6458 /*!
Freescale_cup 0:3ec7fc598e48 6459 * @addtogroup UART0_Register_Accessor_Macros UART0 - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6460 * @{
Freescale_cup 0:3ec7fc598e48 6461 */
Freescale_cup 0:3ec7fc598e48 6462
Freescale_cup 0:3ec7fc598e48 6463
Freescale_cup 0:3ec7fc598e48 6464 /* UART0 - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 6465 /* UART0 */
Freescale_cup 0:3ec7fc598e48 6466 #define UART0_BDH UART0_BDH_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6467 #define UART0_BDL UART0_BDL_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6468 #define UART0_C1 UART0_C1_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6469 #define UART0_C2 UART0_C2_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6470 #define UART0_S1 UART0_S1_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6471 #define UART0_S2 UART0_S2_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6472 #define UART0_C3 UART0_C3_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6473 #define UART0_D UART0_D_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6474 #define UART0_MA1 UART0_MA1_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6475 #define UART0_MA2 UART0_MA2_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6476 #define UART0_C4 UART0_C4_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6477 #define UART0_C5 UART0_C5_REG(UART0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6478
Freescale_cup 0:3ec7fc598e48 6479 /*!
Freescale_cup 0:3ec7fc598e48 6480 * @}
Freescale_cup 0:3ec7fc598e48 6481 */ /* end of group UART0_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 6482
Freescale_cup 0:3ec7fc598e48 6483
Freescale_cup 0:3ec7fc598e48 6484 /*!
Freescale_cup 0:3ec7fc598e48 6485 * @}
Freescale_cup 0:3ec7fc598e48 6486 */ /* end of group UART0_Peripheral */
Freescale_cup 0:3ec7fc598e48 6487
Freescale_cup 0:3ec7fc598e48 6488
Freescale_cup 0:3ec7fc598e48 6489 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6490 -- USB
Freescale_cup 0:3ec7fc598e48 6491 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6492
Freescale_cup 0:3ec7fc598e48 6493 /*!
Freescale_cup 0:3ec7fc598e48 6494 * @addtogroup USB_Peripheral USB
Freescale_cup 0:3ec7fc598e48 6495 * @{
Freescale_cup 0:3ec7fc598e48 6496 */
Freescale_cup 0:3ec7fc598e48 6497
Freescale_cup 0:3ec7fc598e48 6498 /** USB - Peripheral register structure */
Freescale_cup 0:3ec7fc598e48 6499 typedef struct USB_MemMap {
Freescale_cup 0:3ec7fc598e48 6500 uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
Freescale_cup 0:3ec7fc598e48 6501 uint8_t RESERVED_0[3];
Freescale_cup 0:3ec7fc598e48 6502 uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
Freescale_cup 0:3ec7fc598e48 6503 uint8_t RESERVED_1[3];
Freescale_cup 0:3ec7fc598e48 6504 uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
Freescale_cup 0:3ec7fc598e48 6505 uint8_t RESERVED_2[3];
Freescale_cup 0:3ec7fc598e48 6506 uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
Freescale_cup 0:3ec7fc598e48 6507 uint8_t RESERVED_3[3];
Freescale_cup 0:3ec7fc598e48 6508 uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
Freescale_cup 0:3ec7fc598e48 6509 uint8_t RESERVED_4[3];
Freescale_cup 0:3ec7fc598e48 6510 uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
Freescale_cup 0:3ec7fc598e48 6511 uint8_t RESERVED_5[3];
Freescale_cup 0:3ec7fc598e48 6512 uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
Freescale_cup 0:3ec7fc598e48 6513 uint8_t RESERVED_6[3];
Freescale_cup 0:3ec7fc598e48 6514 uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
Freescale_cup 0:3ec7fc598e48 6515 uint8_t RESERVED_7[99];
Freescale_cup 0:3ec7fc598e48 6516 uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
Freescale_cup 0:3ec7fc598e48 6517 uint8_t RESERVED_8[3];
Freescale_cup 0:3ec7fc598e48 6518 uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
Freescale_cup 0:3ec7fc598e48 6519 uint8_t RESERVED_9[3];
Freescale_cup 0:3ec7fc598e48 6520 uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
Freescale_cup 0:3ec7fc598e48 6521 uint8_t RESERVED_10[3];
Freescale_cup 0:3ec7fc598e48 6522 uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
Freescale_cup 0:3ec7fc598e48 6523 uint8_t RESERVED_11[3];
Freescale_cup 0:3ec7fc598e48 6524 uint8_t STAT; /**< Status register, offset: 0x90 */
Freescale_cup 0:3ec7fc598e48 6525 uint8_t RESERVED_12[3];
Freescale_cup 0:3ec7fc598e48 6526 uint8_t CTL; /**< Control register, offset: 0x94 */
Freescale_cup 0:3ec7fc598e48 6527 uint8_t RESERVED_13[3];
Freescale_cup 0:3ec7fc598e48 6528 uint8_t ADDR; /**< Address register, offset: 0x98 */
Freescale_cup 0:3ec7fc598e48 6529 uint8_t RESERVED_14[3];
Freescale_cup 0:3ec7fc598e48 6530 uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
Freescale_cup 0:3ec7fc598e48 6531 uint8_t RESERVED_15[3];
Freescale_cup 0:3ec7fc598e48 6532 uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
Freescale_cup 0:3ec7fc598e48 6533 uint8_t RESERVED_16[3];
Freescale_cup 0:3ec7fc598e48 6534 uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
Freescale_cup 0:3ec7fc598e48 6535 uint8_t RESERVED_17[3];
Freescale_cup 0:3ec7fc598e48 6536 uint8_t TOKEN; /**< Token register, offset: 0xA8 */
Freescale_cup 0:3ec7fc598e48 6537 uint8_t RESERVED_18[3];
Freescale_cup 0:3ec7fc598e48 6538 uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
Freescale_cup 0:3ec7fc598e48 6539 uint8_t RESERVED_19[3];
Freescale_cup 0:3ec7fc598e48 6540 uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
Freescale_cup 0:3ec7fc598e48 6541 uint8_t RESERVED_20[3];
Freescale_cup 0:3ec7fc598e48 6542 uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
Freescale_cup 0:3ec7fc598e48 6543 uint8_t RESERVED_21[11];
Freescale_cup 0:3ec7fc598e48 6544 struct { /* offset: 0xC0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 6545 uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
Freescale_cup 0:3ec7fc598e48 6546 uint8_t RESERVED_0[3];
Freescale_cup 0:3ec7fc598e48 6547 } ENDPOINT[16];
Freescale_cup 0:3ec7fc598e48 6548 uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
Freescale_cup 0:3ec7fc598e48 6549 uint8_t RESERVED_22[3];
Freescale_cup 0:3ec7fc598e48 6550 uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
Freescale_cup 0:3ec7fc598e48 6551 uint8_t RESERVED_23[3];
Freescale_cup 0:3ec7fc598e48 6552 uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
Freescale_cup 0:3ec7fc598e48 6553 uint8_t RESERVED_24[3];
Freescale_cup 0:3ec7fc598e48 6554 uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
Freescale_cup 0:3ec7fc598e48 6555 uint8_t RESERVED_25[7];
Freescale_cup 0:3ec7fc598e48 6556 uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
Freescale_cup 0:3ec7fc598e48 6557 } volatile *USB_MemMapPtr;
Freescale_cup 0:3ec7fc598e48 6558
Freescale_cup 0:3ec7fc598e48 6559 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6560 -- USB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6561 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6562
Freescale_cup 0:3ec7fc598e48 6563 /*!
Freescale_cup 0:3ec7fc598e48 6564 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6565 * @{
Freescale_cup 0:3ec7fc598e48 6566 */
Freescale_cup 0:3ec7fc598e48 6567
Freescale_cup 0:3ec7fc598e48 6568
Freescale_cup 0:3ec7fc598e48 6569 /* USB - Register accessors */
Freescale_cup 0:3ec7fc598e48 6570 #define USB_PERID_REG(base) ((base)->PERID)
Freescale_cup 0:3ec7fc598e48 6571 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
Freescale_cup 0:3ec7fc598e48 6572 #define USB_REV_REG(base) ((base)->REV)
Freescale_cup 0:3ec7fc598e48 6573 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
Freescale_cup 0:3ec7fc598e48 6574 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
Freescale_cup 0:3ec7fc598e48 6575 #define USB_OTGICR_REG(base) ((base)->OTGICR)
Freescale_cup 0:3ec7fc598e48 6576 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
Freescale_cup 0:3ec7fc598e48 6577 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
Freescale_cup 0:3ec7fc598e48 6578 #define USB_ISTAT_REG(base) ((base)->ISTAT)
Freescale_cup 0:3ec7fc598e48 6579 #define USB_INTEN_REG(base) ((base)->INTEN)
Freescale_cup 0:3ec7fc598e48 6580 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
Freescale_cup 0:3ec7fc598e48 6581 #define USB_ERREN_REG(base) ((base)->ERREN)
Freescale_cup 0:3ec7fc598e48 6582 #define USB_STAT_REG(base) ((base)->STAT)
Freescale_cup 0:3ec7fc598e48 6583 #define USB_CTL_REG(base) ((base)->CTL)
Freescale_cup 0:3ec7fc598e48 6584 #define USB_ADDR_REG(base) ((base)->ADDR)
Freescale_cup 0:3ec7fc598e48 6585 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
Freescale_cup 0:3ec7fc598e48 6586 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
Freescale_cup 0:3ec7fc598e48 6587 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
Freescale_cup 0:3ec7fc598e48 6588 #define USB_TOKEN_REG(base) ((base)->TOKEN)
Freescale_cup 0:3ec7fc598e48 6589 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
Freescale_cup 0:3ec7fc598e48 6590 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
Freescale_cup 0:3ec7fc598e48 6591 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
Freescale_cup 0:3ec7fc598e48 6592 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
Freescale_cup 0:3ec7fc598e48 6593 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
Freescale_cup 0:3ec7fc598e48 6594 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
Freescale_cup 0:3ec7fc598e48 6595 #define USB_CONTROL_REG(base) ((base)->CONTROL)
Freescale_cup 0:3ec7fc598e48 6596 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
Freescale_cup 0:3ec7fc598e48 6597 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
Freescale_cup 0:3ec7fc598e48 6598
Freescale_cup 0:3ec7fc598e48 6599 /*!
Freescale_cup 0:3ec7fc598e48 6600 * @}
Freescale_cup 0:3ec7fc598e48 6601 */ /* end of group USB_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 6602
Freescale_cup 0:3ec7fc598e48 6603
Freescale_cup 0:3ec7fc598e48 6604 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6605 -- USB Register Masks
Freescale_cup 0:3ec7fc598e48 6606 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6607
Freescale_cup 0:3ec7fc598e48 6608 /*!
Freescale_cup 0:3ec7fc598e48 6609 * @addtogroup USB_Register_Masks USB Register Masks
Freescale_cup 0:3ec7fc598e48 6610 * @{
Freescale_cup 0:3ec7fc598e48 6611 */
Freescale_cup 0:3ec7fc598e48 6612
Freescale_cup 0:3ec7fc598e48 6613 /* PERID Bit Fields */
Freescale_cup 0:3ec7fc598e48 6614 #define USB_PERID_ID_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 6615 #define USB_PERID_ID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6616 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
Freescale_cup 0:3ec7fc598e48 6617 /* IDCOMP Bit Fields */
Freescale_cup 0:3ec7fc598e48 6618 #define USB_IDCOMP_NID_MASK 0x3Fu
Freescale_cup 0:3ec7fc598e48 6619 #define USB_IDCOMP_NID_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6620 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
Freescale_cup 0:3ec7fc598e48 6621 /* REV Bit Fields */
Freescale_cup 0:3ec7fc598e48 6622 #define USB_REV_REV_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6623 #define USB_REV_REV_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6624 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
Freescale_cup 0:3ec7fc598e48 6625 /* ADDINFO Bit Fields */
Freescale_cup 0:3ec7fc598e48 6626 #define USB_ADDINFO_IEHOST_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6627 #define USB_ADDINFO_IEHOST_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6628 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
Freescale_cup 0:3ec7fc598e48 6629 #define USB_ADDINFO_IRQNUM_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6630 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
Freescale_cup 0:3ec7fc598e48 6631 /* OTGISTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 6632 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6633 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6634 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6635 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6636 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6637 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6638 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6639 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6640 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6641 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6642 #define USB_OTGISTAT_IDCHG_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6643 #define USB_OTGISTAT_IDCHG_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6644 /* OTGICR Bit Fields */
Freescale_cup 0:3ec7fc598e48 6645 #define USB_OTGICR_AVBUSEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6646 #define USB_OTGICR_AVBUSEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6647 #define USB_OTGICR_BSESSEN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6648 #define USB_OTGICR_BSESSEN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6649 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6650 #define USB_OTGICR_SESSVLDEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6651 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6652 #define USB_OTGICR_LINESTATEEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6653 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6654 #define USB_OTGICR_ONEMSECEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6655 #define USB_OTGICR_IDEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6656 #define USB_OTGICR_IDEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6657 /* OTGSTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 6658 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6659 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6660 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6661 #define USB_OTGSTAT_BSESSEND_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6662 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6663 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6664 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6665 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6666 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6667 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6668 #define USB_OTGSTAT_ID_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6669 #define USB_OTGSTAT_ID_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6670 /* OTGCTL Bit Fields */
Freescale_cup 0:3ec7fc598e48 6671 #define USB_OTGCTL_OTGEN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6672 #define USB_OTGCTL_OTGEN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6673 #define USB_OTGCTL_DMLOW_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6674 #define USB_OTGCTL_DMLOW_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6675 #define USB_OTGCTL_DPLOW_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6676 #define USB_OTGCTL_DPLOW_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6677 #define USB_OTGCTL_DPHIGH_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6678 #define USB_OTGCTL_DPHIGH_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6679 /* ISTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 6680 #define USB_ISTAT_USBRST_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6681 #define USB_ISTAT_USBRST_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6682 #define USB_ISTAT_ERROR_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6683 #define USB_ISTAT_ERROR_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6684 #define USB_ISTAT_SOFTOK_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6685 #define USB_ISTAT_SOFTOK_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6686 #define USB_ISTAT_TOKDNE_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6687 #define USB_ISTAT_TOKDNE_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6688 #define USB_ISTAT_SLEEP_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6689 #define USB_ISTAT_SLEEP_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6690 #define USB_ISTAT_RESUME_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6691 #define USB_ISTAT_RESUME_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6692 #define USB_ISTAT_ATTACH_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6693 #define USB_ISTAT_ATTACH_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6694 #define USB_ISTAT_STALL_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6695 #define USB_ISTAT_STALL_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6696 /* INTEN Bit Fields */
Freescale_cup 0:3ec7fc598e48 6697 #define USB_INTEN_USBRSTEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6698 #define USB_INTEN_USBRSTEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6699 #define USB_INTEN_ERROREN_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6700 #define USB_INTEN_ERROREN_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6701 #define USB_INTEN_SOFTOKEN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6702 #define USB_INTEN_SOFTOKEN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6703 #define USB_INTEN_TOKDNEEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6704 #define USB_INTEN_TOKDNEEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6705 #define USB_INTEN_SLEEPEN_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6706 #define USB_INTEN_SLEEPEN_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6707 #define USB_INTEN_RESUMEEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6708 #define USB_INTEN_RESUMEEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6709 #define USB_INTEN_ATTACHEN_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6710 #define USB_INTEN_ATTACHEN_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6711 #define USB_INTEN_STALLEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6712 #define USB_INTEN_STALLEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6713 /* ERRSTAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 6714 #define USB_ERRSTAT_PIDERR_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6715 #define USB_ERRSTAT_PIDERR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6716 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6717 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6718 #define USB_ERRSTAT_CRC16_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6719 #define USB_ERRSTAT_CRC16_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6720 #define USB_ERRSTAT_DFN8_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6721 #define USB_ERRSTAT_DFN8_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6722 #define USB_ERRSTAT_BTOERR_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6723 #define USB_ERRSTAT_BTOERR_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6724 #define USB_ERRSTAT_DMAERR_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6725 #define USB_ERRSTAT_DMAERR_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6726 #define USB_ERRSTAT_BTSERR_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6727 #define USB_ERRSTAT_BTSERR_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6728 /* ERREN Bit Fields */
Freescale_cup 0:3ec7fc598e48 6729 #define USB_ERREN_PIDERREN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6730 #define USB_ERREN_PIDERREN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6731 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6732 #define USB_ERREN_CRC5EOFEN_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6733 #define USB_ERREN_CRC16EN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6734 #define USB_ERREN_CRC16EN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6735 #define USB_ERREN_DFN8EN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6736 #define USB_ERREN_DFN8EN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6737 #define USB_ERREN_BTOERREN_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6738 #define USB_ERREN_BTOERREN_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6739 #define USB_ERREN_DMAERREN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6740 #define USB_ERREN_DMAERREN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6741 #define USB_ERREN_BTSERREN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6742 #define USB_ERREN_BTSERREN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6743 /* STAT Bit Fields */
Freescale_cup 0:3ec7fc598e48 6744 #define USB_STAT_ODD_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6745 #define USB_STAT_ODD_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6746 #define USB_STAT_TX_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6747 #define USB_STAT_TX_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6748 #define USB_STAT_ENDP_MASK 0xF0u
Freescale_cup 0:3ec7fc598e48 6749 #define USB_STAT_ENDP_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6750 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
Freescale_cup 0:3ec7fc598e48 6751 /* CTL Bit Fields */
Freescale_cup 0:3ec7fc598e48 6752 #define USB_CTL_USBENSOFEN_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6753 #define USB_CTL_USBENSOFEN_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6754 #define USB_CTL_ODDRST_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6755 #define USB_CTL_ODDRST_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6756 #define USB_CTL_RESUME_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6757 #define USB_CTL_RESUME_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6758 #define USB_CTL_HOSTMODEEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6759 #define USB_CTL_HOSTMODEEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6760 #define USB_CTL_RESET_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6761 #define USB_CTL_RESET_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6762 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6763 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6764 #define USB_CTL_SE0_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6765 #define USB_CTL_SE0_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6766 #define USB_CTL_JSTATE_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6767 #define USB_CTL_JSTATE_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6768 /* ADDR Bit Fields */
Freescale_cup 0:3ec7fc598e48 6769 #define USB_ADDR_ADDR_MASK 0x7Fu
Freescale_cup 0:3ec7fc598e48 6770 #define USB_ADDR_ADDR_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6771 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
Freescale_cup 0:3ec7fc598e48 6772 #define USB_ADDR_LSEN_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6773 #define USB_ADDR_LSEN_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6774 /* BDTPAGE1 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6775 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
Freescale_cup 0:3ec7fc598e48 6776 #define USB_BDTPAGE1_BDTBA_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6777 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
Freescale_cup 0:3ec7fc598e48 6778 /* FRMNUML Bit Fields */
Freescale_cup 0:3ec7fc598e48 6779 #define USB_FRMNUML_FRM_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6780 #define USB_FRMNUML_FRM_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6781 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
Freescale_cup 0:3ec7fc598e48 6782 /* FRMNUMH Bit Fields */
Freescale_cup 0:3ec7fc598e48 6783 #define USB_FRMNUMH_FRM_MASK 0x7u
Freescale_cup 0:3ec7fc598e48 6784 #define USB_FRMNUMH_FRM_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6785 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
Freescale_cup 0:3ec7fc598e48 6786 /* TOKEN Bit Fields */
Freescale_cup 0:3ec7fc598e48 6787 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
Freescale_cup 0:3ec7fc598e48 6788 #define USB_TOKEN_TOKENENDPT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6789 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
Freescale_cup 0:3ec7fc598e48 6790 #define USB_TOKEN_TOKENPID_MASK 0xF0u
Freescale_cup 0:3ec7fc598e48 6791 #define USB_TOKEN_TOKENPID_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6792 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
Freescale_cup 0:3ec7fc598e48 6793 /* SOFTHLD Bit Fields */
Freescale_cup 0:3ec7fc598e48 6794 #define USB_SOFTHLD_CNT_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6795 #define USB_SOFTHLD_CNT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6796 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
Freescale_cup 0:3ec7fc598e48 6797 /* BDTPAGE2 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6798 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6799 #define USB_BDTPAGE2_BDTBA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6800 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
Freescale_cup 0:3ec7fc598e48 6801 /* BDTPAGE3 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6802 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6803 #define USB_BDTPAGE3_BDTBA_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6804 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
Freescale_cup 0:3ec7fc598e48 6805 /* ENDPT Bit Fields */
Freescale_cup 0:3ec7fc598e48 6806 #define USB_ENDPT_EPHSHK_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6807 #define USB_ENDPT_EPHSHK_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6808 #define USB_ENDPT_EPSTALL_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6809 #define USB_ENDPT_EPSTALL_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6810 #define USB_ENDPT_EPTXEN_MASK 0x4u
Freescale_cup 0:3ec7fc598e48 6811 #define USB_ENDPT_EPTXEN_SHIFT 2
Freescale_cup 0:3ec7fc598e48 6812 #define USB_ENDPT_EPRXEN_MASK 0x8u
Freescale_cup 0:3ec7fc598e48 6813 #define USB_ENDPT_EPRXEN_SHIFT 3
Freescale_cup 0:3ec7fc598e48 6814 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6815 #define USB_ENDPT_EPCTLDIS_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6816 #define USB_ENDPT_RETRYDIS_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6817 #define USB_ENDPT_RETRYDIS_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6818 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6819 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6820 /* USBCTRL Bit Fields */
Freescale_cup 0:3ec7fc598e48 6821 #define USB_USBCTRL_PDE_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6822 #define USB_USBCTRL_PDE_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6823 #define USB_USBCTRL_SUSP_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6824 #define USB_USBCTRL_SUSP_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6825 /* OBSERVE Bit Fields */
Freescale_cup 0:3ec7fc598e48 6826 #define USB_OBSERVE_DMPD_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6827 #define USB_OBSERVE_DMPD_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6828 #define USB_OBSERVE_DPPD_MASK 0x40u
Freescale_cup 0:3ec7fc598e48 6829 #define USB_OBSERVE_DPPD_SHIFT 6
Freescale_cup 0:3ec7fc598e48 6830 #define USB_OBSERVE_DPPU_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6831 #define USB_OBSERVE_DPPU_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6832 /* CONTROL Bit Fields */
Freescale_cup 0:3ec7fc598e48 6833 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
Freescale_cup 0:3ec7fc598e48 6834 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
Freescale_cup 0:3ec7fc598e48 6835 /* USBTRC0 Bit Fields */
Freescale_cup 0:3ec7fc598e48 6836 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
Freescale_cup 0:3ec7fc598e48 6837 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6838 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
Freescale_cup 0:3ec7fc598e48 6839 #define USB_USBTRC0_SYNC_DET_SHIFT 1
Freescale_cup 0:3ec7fc598e48 6840 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
Freescale_cup 0:3ec7fc598e48 6841 #define USB_USBTRC0_USBRESMEN_SHIFT 5
Freescale_cup 0:3ec7fc598e48 6842 #define USB_USBTRC0_USBRESET_MASK 0x80u
Freescale_cup 0:3ec7fc598e48 6843 #define USB_USBTRC0_USBRESET_SHIFT 7
Freescale_cup 0:3ec7fc598e48 6844 /* USBFRMADJUST Bit Fields */
Freescale_cup 0:3ec7fc598e48 6845 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
Freescale_cup 0:3ec7fc598e48 6846 #define USB_USBFRMADJUST_ADJ_SHIFT 0
Freescale_cup 0:3ec7fc598e48 6847 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
Freescale_cup 0:3ec7fc598e48 6848
Freescale_cup 0:3ec7fc598e48 6849 /*!
Freescale_cup 0:3ec7fc598e48 6850 * @}
Freescale_cup 0:3ec7fc598e48 6851 */ /* end of group USB_Register_Masks */
Freescale_cup 0:3ec7fc598e48 6852
Freescale_cup 0:3ec7fc598e48 6853
Freescale_cup 0:3ec7fc598e48 6854 /* USB - Peripheral instance base addresses */
Freescale_cup 0:3ec7fc598e48 6855 /** Peripheral USB0 base pointer */
Freescale_cup 0:3ec7fc598e48 6856 #define USB0_BASE_PTR ((USB_MemMapPtr)0x40072000u)
Freescale_cup 0:3ec7fc598e48 6857 /** Array initializer of USB peripheral base pointers */
Freescale_cup 0:3ec7fc598e48 6858 #define USB_BASE_PTRS { USB0_BASE_PTR }
Freescale_cup 0:3ec7fc598e48 6859
Freescale_cup 0:3ec7fc598e48 6860 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6861 -- USB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6862 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6863
Freescale_cup 0:3ec7fc598e48 6864 /*!
Freescale_cup 0:3ec7fc598e48 6865 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Freescale_cup 0:3ec7fc598e48 6866 * @{
Freescale_cup 0:3ec7fc598e48 6867 */
Freescale_cup 0:3ec7fc598e48 6868
Freescale_cup 0:3ec7fc598e48 6869
Freescale_cup 0:3ec7fc598e48 6870 /* USB - Register instance definitions */
Freescale_cup 0:3ec7fc598e48 6871 /* USB0 */
Freescale_cup 0:3ec7fc598e48 6872 #define USB0_PERID USB_PERID_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6873 #define USB0_IDCOMP USB_IDCOMP_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6874 #define USB0_REV USB_REV_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6875 #define USB0_ADDINFO USB_ADDINFO_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6876 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6877 #define USB0_OTGICR USB_OTGICR_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6878 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6879 #define USB0_OTGCTL USB_OTGCTL_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6880 #define USB0_ISTAT USB_ISTAT_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6881 #define USB0_INTEN USB_INTEN_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6882 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6883 #define USB0_ERREN USB_ERREN_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6884 #define USB0_STAT USB_STAT_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6885 #define USB0_CTL USB_CTL_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6886 #define USB0_ADDR USB_ADDR_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6887 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6888 #define USB0_FRMNUML USB_FRMNUML_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6889 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6890 #define USB0_TOKEN USB_TOKEN_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6891 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6892 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6893 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6894 #define USB0_ENDPT0 USB_ENDPT_REG(USB0_BASE_PTR,0)
Freescale_cup 0:3ec7fc598e48 6895 #define USB0_ENDPT1 USB_ENDPT_REG(USB0_BASE_PTR,1)
Freescale_cup 0:3ec7fc598e48 6896 #define USB0_ENDPT2 USB_ENDPT_REG(USB0_BASE_PTR,2)
Freescale_cup 0:3ec7fc598e48 6897 #define USB0_ENDPT3 USB_ENDPT_REG(USB0_BASE_PTR,3)
Freescale_cup 0:3ec7fc598e48 6898 #define USB0_ENDPT4 USB_ENDPT_REG(USB0_BASE_PTR,4)
Freescale_cup 0:3ec7fc598e48 6899 #define USB0_ENDPT5 USB_ENDPT_REG(USB0_BASE_PTR,5)
Freescale_cup 0:3ec7fc598e48 6900 #define USB0_ENDPT6 USB_ENDPT_REG(USB0_BASE_PTR,6)
Freescale_cup 0:3ec7fc598e48 6901 #define USB0_ENDPT7 USB_ENDPT_REG(USB0_BASE_PTR,7)
Freescale_cup 0:3ec7fc598e48 6902 #define USB0_ENDPT8 USB_ENDPT_REG(USB0_BASE_PTR,8)
Freescale_cup 0:3ec7fc598e48 6903 #define USB0_ENDPT9 USB_ENDPT_REG(USB0_BASE_PTR,9)
Freescale_cup 0:3ec7fc598e48 6904 #define USB0_ENDPT10 USB_ENDPT_REG(USB0_BASE_PTR,10)
Freescale_cup 0:3ec7fc598e48 6905 #define USB0_ENDPT11 USB_ENDPT_REG(USB0_BASE_PTR,11)
Freescale_cup 0:3ec7fc598e48 6906 #define USB0_ENDPT12 USB_ENDPT_REG(USB0_BASE_PTR,12)
Freescale_cup 0:3ec7fc598e48 6907 #define USB0_ENDPT13 USB_ENDPT_REG(USB0_BASE_PTR,13)
Freescale_cup 0:3ec7fc598e48 6908 #define USB0_ENDPT14 USB_ENDPT_REG(USB0_BASE_PTR,14)
Freescale_cup 0:3ec7fc598e48 6909 #define USB0_ENDPT15 USB_ENDPT_REG(USB0_BASE_PTR,15)
Freescale_cup 0:3ec7fc598e48 6910 #define USB0_USBCTRL USB_USBCTRL_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6911 #define USB0_OBSERVE USB_OBSERVE_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6912 #define USB0_CONTROL USB_CONTROL_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6913 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6914 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0_BASE_PTR)
Freescale_cup 0:3ec7fc598e48 6915
Freescale_cup 0:3ec7fc598e48 6916 /* USB - Register array accessors */
Freescale_cup 0:3ec7fc598e48 6917 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0_BASE_PTR,index)
Freescale_cup 0:3ec7fc598e48 6918
Freescale_cup 0:3ec7fc598e48 6919 /*!
Freescale_cup 0:3ec7fc598e48 6920 * @}
Freescale_cup 0:3ec7fc598e48 6921 */ /* end of group USB_Register_Accessor_Macros */
Freescale_cup 0:3ec7fc598e48 6922
Freescale_cup 0:3ec7fc598e48 6923
Freescale_cup 0:3ec7fc598e48 6924 /*!
Freescale_cup 0:3ec7fc598e48 6925 * @}
Freescale_cup 0:3ec7fc598e48 6926 */ /* end of group USB_Peripheral */
Freescale_cup 0:3ec7fc598e48 6927
Freescale_cup 0:3ec7fc598e48 6928
Freescale_cup 0:3ec7fc598e48 6929 /*
Freescale_cup 0:3ec7fc598e48 6930 ** End of section using anonymous unions
Freescale_cup 0:3ec7fc598e48 6931 */
Freescale_cup 0:3ec7fc598e48 6932
Freescale_cup 0:3ec7fc598e48 6933 #if defined(__ARMCC_VERSION)
Freescale_cup 0:3ec7fc598e48 6934 #pragma pop
Freescale_cup 0:3ec7fc598e48 6935 #elif defined(__CWCC__)
Freescale_cup 0:3ec7fc598e48 6936 #pragma pop
Freescale_cup 0:3ec7fc598e48 6937 #elif defined(__GNUC__)
Freescale_cup 0:3ec7fc598e48 6938 /* leave anonymous unions enabled */
Freescale_cup 0:3ec7fc598e48 6939 #elif defined(__IAR_SYSTEMS_ICC__)
Freescale_cup 0:3ec7fc598e48 6940 #pragma language=default
Freescale_cup 0:3ec7fc598e48 6941 #else
Freescale_cup 0:3ec7fc598e48 6942 #error Not supported compiler type
Freescale_cup 0:3ec7fc598e48 6943 #endif
Freescale_cup 0:3ec7fc598e48 6944
Freescale_cup 0:3ec7fc598e48 6945 /*!
Freescale_cup 0:3ec7fc598e48 6946 * @}
Freescale_cup 0:3ec7fc598e48 6947 */ /* end of group Peripheral_defines */
Freescale_cup 0:3ec7fc598e48 6948
Freescale_cup 0:3ec7fc598e48 6949
Freescale_cup 0:3ec7fc598e48 6950 /* ----------------------------------------------------------------------------
Freescale_cup 0:3ec7fc598e48 6951 -- Backward Compatibility
Freescale_cup 0:3ec7fc598e48 6952 ---------------------------------------------------------------------------- */
Freescale_cup 0:3ec7fc598e48 6953
Freescale_cup 0:3ec7fc598e48 6954 /*!
Freescale_cup 0:3ec7fc598e48 6955 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
Freescale_cup 0:3ec7fc598e48 6956 * @{
Freescale_cup 0:3ec7fc598e48 6957 */
Freescale_cup 0:3ec7fc598e48 6958
Freescale_cup 0:3ec7fc598e48 6959 #define DMA_REQC_ARR_REG(base,index2) This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6960 //#define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6961 //#define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6962 //#define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6963 //#define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6964 //#define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6965 #define DMA_REQC0 This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6966 #define DMA_REQC1 This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6967 #define DMA_REQC2 This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6968 #define DMA_REQC3 This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6969 #define DMA_REQC_ARR(index2) This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6970 //#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
Freescale_cup 0:3ec7fc598e48 6971 //#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
Freescale_cup 0:3ec7fc598e48 6972 //#define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
Freescale_cup 0:3ec7fc598e48 6973 //#define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
Freescale_cup 0:3ec7fc598e48 6974 //#define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
Freescale_cup 0:3ec7fc598e48 6975 //#define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6976 //#define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6977 //#define UART_C4_LBKDDMAS_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6978 //#define UART_C4_LBKDDMAS_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6979 //#define UART_C4_ILDMAS_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6980 //#define UART_C4_ILDMAS_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6981 //#define UART_C4_TCDMAS_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6982 //#define UART_C4_TCDMAS_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 6983 #define UARTLP_MemMap UART0_MemMap
Freescale_cup 0:3ec7fc598e48 6984 #define UARTLP_MemMapPtr UART0_MemMapPtr
Freescale_cup 0:3ec7fc598e48 6985 #define UARTLP_BDH_REG UART0_BDH_REG
Freescale_cup 0:3ec7fc598e48 6986 #define UARTLP_BDL_REG UART0_BDL_REG
Freescale_cup 0:3ec7fc598e48 6987 #define UARTLP_C1_REG UART0_C1_REG
Freescale_cup 0:3ec7fc598e48 6988 #define UARTLP_C2_REG UART0_C2_REG
Freescale_cup 0:3ec7fc598e48 6989 #define UARTLP_S1_REG UART0_S1_REG
Freescale_cup 0:3ec7fc598e48 6990 #define UARTLP_S2_REG UART0_S2_REG
Freescale_cup 0:3ec7fc598e48 6991 #define UARTLP_C3_REG UART0_C3_REG
Freescale_cup 0:3ec7fc598e48 6992 #define UARTLP_D_REG UART0_D_REG
Freescale_cup 0:3ec7fc598e48 6993 #define UARTLP_MA1_REG UART0_MA1_REG
Freescale_cup 0:3ec7fc598e48 6994 #define UARTLP_MA2_REG UART0_MA2_REG
Freescale_cup 0:3ec7fc598e48 6995 #define UARTLP_C4_REG UART0_C4_REG
Freescale_cup 0:3ec7fc598e48 6996 #define UARTLP_C5_REG UART0_C5_REG
Freescale_cup 0:3ec7fc598e48 6997 //#define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
Freescale_cup 0:3ec7fc598e48 6998 //#define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
Freescale_cup 0:3ec7fc598e48 6999 //#define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
Freescale_cup 0:3ec7fc598e48 7000 //#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
Freescale_cup 0:3ec7fc598e48 7001 //#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
Freescale_cup 0:3ec7fc598e48 7002 //#define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
Freescale_cup 0:3ec7fc598e48 7003 //#define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7004 //#define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
Freescale_cup 0:3ec7fc598e48 7005 //#define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7006 //#define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
Freescale_cup 0:3ec7fc598e48 7007 //#define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
Freescale_cup 0:3ec7fc598e48 7008 //#define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
Freescale_cup 0:3ec7fc598e48 7009 /*#define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
Freescale_cup 0:3ec7fc598e48 7010 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
Freescale_cup 0:3ec7fc598e48 7011 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
Freescale_cup 0:3ec7fc598e48 7012 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
Freescale_cup 0:3ec7fc598e48 7013 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
Freescale_cup 0:3ec7fc598e48 7014 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
Freescale_cup 0:3ec7fc598e48 7015 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
Freescale_cup 0:3ec7fc598e48 7016 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
Freescale_cup 0:3ec7fc598e48 7017 #define UARTLP_C1_M_MASK UART0_C1_M_MASK
Freescale_cup 0:3ec7fc598e48 7018 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
Freescale_cup 0:3ec7fc598e48 7019 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
Freescale_cup 0:3ec7fc598e48 7020 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
Freescale_cup 0:3ec7fc598e48 7021 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
Freescale_cup 0:3ec7fc598e48 7022 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
Freescale_cup 0:3ec7fc598e48 7023 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
Freescale_cup 0:3ec7fc598e48 7024 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
Freescale_cup 0:3ec7fc598e48 7025 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
Freescale_cup 0:3ec7fc598e48 7026 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT*/
Freescale_cup 0:3ec7fc598e48 7027 /*#define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
Freescale_cup 0:3ec7fc598e48 7028 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
Freescale_cup 0:3ec7fc598e48 7029 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
Freescale_cup 0:3ec7fc598e48 7030 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
Freescale_cup 0:3ec7fc598e48 7031 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
Freescale_cup 0:3ec7fc598e48 7032 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
Freescale_cup 0:3ec7fc598e48 7033 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
Freescale_cup 0:3ec7fc598e48 7034 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7035 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
Freescale_cup 0:3ec7fc598e48 7036 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7037 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
Freescale_cup 0:3ec7fc598e48 7038 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7039 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
Freescale_cup 0:3ec7fc598e48 7040 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7041 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
Freescale_cup 0:3ec7fc598e48 7042 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
Freescale_cup 0:3ec7fc598e48 7043 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
Freescale_cup 0:3ec7fc598e48 7044 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
Freescale_cup 0:3ec7fc598e48 7045 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
Freescale_cup 0:3ec7fc598e48 7046 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
Freescale_cup 0:3ec7fc598e48 7047 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
Freescale_cup 0:3ec7fc598e48 7048 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
Freescale_cup 0:3ec7fc598e48 7049 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
Freescale_cup 0:3ec7fc598e48 7050 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
Freescale_cup 0:3ec7fc598e48 7051 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
Freescale_cup 0:3ec7fc598e48 7052 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
Freescale_cup 0:3ec7fc598e48 7053 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
Freescale_cup 0:3ec7fc598e48 7054 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
Freescale_cup 0:3ec7fc598e48 7055 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
Freescale_cup 0:3ec7fc598e48 7056 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
Freescale_cup 0:3ec7fc598e48 7057 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
Freescale_cup 0:3ec7fc598e48 7058 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
Freescale_cup 0:3ec7fc598e48 7059 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
Freescale_cup 0:3ec7fc598e48 7060 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
Freescale_cup 0:3ec7fc598e48 7061 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
Freescale_cup 0:3ec7fc598e48 7062 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
Freescale_cup 0:3ec7fc598e48 7063 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
Freescale_cup 0:3ec7fc598e48 7064 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
Freescale_cup 0:3ec7fc598e48 7065 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
Freescale_cup 0:3ec7fc598e48 7066 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
Freescale_cup 0:3ec7fc598e48 7067 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
Freescale_cup 0:3ec7fc598e48 7068 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
Freescale_cup 0:3ec7fc598e48 7069 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
Freescale_cup 0:3ec7fc598e48 7070 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
Freescale_cup 0:3ec7fc598e48 7071 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
Freescale_cup 0:3ec7fc598e48 7072 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
Freescale_cup 0:3ec7fc598e48 7073 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
Freescale_cup 0:3ec7fc598e48 7074 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7075 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
Freescale_cup 0:3ec7fc598e48 7076 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7077 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
Freescale_cup 0:3ec7fc598e48 7078 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7079 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
Freescale_cup 0:3ec7fc598e48 7080 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
Freescale_cup 0:3ec7fc598e48 7081 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
Freescale_cup 0:3ec7fc598e48 7082 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
Freescale_cup 0:3ec7fc598e48 7083 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
Freescale_cup 0:3ec7fc598e48 7084 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
Freescale_cup 0:3ec7fc598e48 7085 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
Freescale_cup 0:3ec7fc598e48 7086 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
Freescale_cup 0:3ec7fc598e48 7087 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
Freescale_cup 0:3ec7fc598e48 7088 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
Freescale_cup 0:3ec7fc598e48 7089 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
Freescale_cup 0:3ec7fc598e48 7090 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
Freescale_cup 0:3ec7fc598e48 7091 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
Freescale_cup 0:3ec7fc598e48 7092 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
Freescale_cup 0:3ec7fc598e48 7093 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
Freescale_cup 0:3ec7fc598e48 7094 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
Freescale_cup 0:3ec7fc598e48 7095 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
Freescale_cup 0:3ec7fc598e48 7096 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
Freescale_cup 0:3ec7fc598e48 7097 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
Freescale_cup 0:3ec7fc598e48 7098 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
Freescale_cup 0:3ec7fc598e48 7099 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
Freescale_cup 0:3ec7fc598e48 7100 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
Freescale_cup 0:3ec7fc598e48 7101 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
Freescale_cup 0:3ec7fc598e48 7102 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
Freescale_cup 0:3ec7fc598e48 7103 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
Freescale_cup 0:3ec7fc598e48 7104 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
Freescale_cup 0:3ec7fc598e48 7105 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
Freescale_cup 0:3ec7fc598e48 7106 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
Freescale_cup 0:3ec7fc598e48 7107 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
Freescale_cup 0:3ec7fc598e48 7108 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
Freescale_cup 0:3ec7fc598e48 7109 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
Freescale_cup 0:3ec7fc598e48 7110 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
Freescale_cup 0:3ec7fc598e48 7111 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
Freescale_cup 0:3ec7fc598e48 7112 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
Freescale_cup 0:3ec7fc598e48 7113 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
Freescale_cup 0:3ec7fc598e48 7114 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
Freescale_cup 0:3ec7fc598e48 7115 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
Freescale_cup 0:3ec7fc598e48 7116 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
Freescale_cup 0:3ec7fc598e48 7117 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
Freescale_cup 0:3ec7fc598e48 7118 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
Freescale_cup 0:3ec7fc598e48 7119 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
Freescale_cup 0:3ec7fc598e48 7120 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
Freescale_cup 0:3ec7fc598e48 7121 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
Freescale_cup 0:3ec7fc598e48 7122 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
Freescale_cup 0:3ec7fc598e48 7123 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
Freescale_cup 0:3ec7fc598e48 7124 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
Freescale_cup 0:3ec7fc598e48 7125 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
Freescale_cup 0:3ec7fc598e48 7126 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
Freescale_cup 0:3ec7fc598e48 7127 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT*/
Freescale_cup 0:3ec7fc598e48 7128 #define UARTLP_BASE_PTRS UART0_BASE_PTRS
Freescale_cup 0:3ec7fc598e48 7129 #define NV_FOPT_EZPORT_DIS_MASK This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 7130 #define NV_FOPT_EZPORT_DIS_SHIFT This_symbol_has_been_deprecated
Freescale_cup 0:3ec7fc598e48 7131
Freescale_cup 0:3ec7fc598e48 7132 /*!
Freescale_cup 0:3ec7fc598e48 7133 * @}
Freescale_cup 0:3ec7fc598e48 7134 */ /* end of group Backward_Compatibility_Symbols */
Freescale_cup 0:3ec7fc598e48 7135
Freescale_cup 0:3ec7fc598e48 7136
Freescale_cup 0:3ec7fc598e48 7137 #else /* #if !defined(MCU_MKL25Z4) */
Freescale_cup 0:3ec7fc598e48 7138 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
Freescale_cup 0:3ec7fc598e48 7139 #if (MCU_MEM_MAP_VERSION != 0x0100u)
Freescale_cup 0:3ec7fc598e48 7140 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
Freescale_cup 0:3ec7fc598e48 7141 #warning There are included two not compatible versions of memory maps. Please check possible differences.
Freescale_cup 0:3ec7fc598e48 7142 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
Freescale_cup 0:3ec7fc598e48 7143 #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
Freescale_cup 0:3ec7fc598e48 7144 #endif /* #if !defined(MCU_MKL25Z4) */
Freescale_cup 0:3ec7fc598e48 7145
Freescale_cup 0:3ec7fc598e48 7146 /* MKL25Z4.h, eof. */