Flotsam
/
mbed-modifed
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Dependents: EEPROMWrite Full-Project
Fork of
mbed-src
by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 324:406fd2029f23 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Compilers: Keil ARM C/C++ Compiler |
| mbed_official | 324:406fd2029f23 | 4 | ** Freescale C/C++ for Embedded ARM |
| mbed_official | 324:406fd2029f23 | 5 | ** GNU C Compiler |
| mbed_official | 324:406fd2029f23 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
| mbed_official | 324:406fd2029f23 | 7 | ** |
| mbed_official | 324:406fd2029f23 | 8 | ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 |
| mbed_official | 324:406fd2029f23 | 9 | ** Version: rev. 2.5, 2014-05-06 |
| mbed_official | 324:406fd2029f23 | 10 | ** Build: b140604 |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 13 | ** Extension to the CMSIS register access layer header. |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** Copyright (c) 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 16 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 19 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 20 | ** |
| mbed_official | 324:406fd2029f23 | 21 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 22 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 23 | ** |
| mbed_official | 324:406fd2029f23 | 24 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 26 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 27 | ** |
| mbed_official | 324:406fd2029f23 | 28 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 29 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 30 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 31 | ** |
| mbed_official | 324:406fd2029f23 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 42 | ** |
| mbed_official | 324:406fd2029f23 | 43 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 44 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 45 | ** |
| mbed_official | 324:406fd2029f23 | 46 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 47 | ** - rev. 1.0 (2013-07-23) |
| mbed_official | 324:406fd2029f23 | 48 | ** Initial version. |
| mbed_official | 324:406fd2029f23 | 49 | ** - rev. 1.1 (2013-09-17) |
| mbed_official | 324:406fd2029f23 | 50 | ** RM rev. 0.4 update. |
| mbed_official | 324:406fd2029f23 | 51 | ** - rev. 2.0 (2013-10-29) |
| mbed_official | 324:406fd2029f23 | 52 | ** Register accessor macros added to the memory map. |
| mbed_official | 324:406fd2029f23 | 53 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
| mbed_official | 324:406fd2029f23 | 54 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
| mbed_official | 324:406fd2029f23 | 55 | ** System initialization updated. |
| mbed_official | 324:406fd2029f23 | 56 | ** - rev. 2.1 (2013-10-30) |
| mbed_official | 324:406fd2029f23 | 57 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
| mbed_official | 324:406fd2029f23 | 58 | ** - rev. 2.2 (2013-12-20) |
| mbed_official | 324:406fd2029f23 | 59 | ** Update according to reference manual rev. 0.6, |
| mbed_official | 324:406fd2029f23 | 60 | ** - rev. 2.3 (2014-01-13) |
| mbed_official | 324:406fd2029f23 | 61 | ** Update according to reference manual rev. 0.61, |
| mbed_official | 324:406fd2029f23 | 62 | ** - rev. 2.4 (2014-02-10) |
| mbed_official | 324:406fd2029f23 | 63 | ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h |
| mbed_official | 324:406fd2029f23 | 64 | ** - rev. 2.5 (2014-05-06) |
| mbed_official | 324:406fd2029f23 | 65 | ** Update according to reference manual rev. 1.0, |
| mbed_official | 324:406fd2029f23 | 66 | ** Update of system and startup files. |
| mbed_official | 324:406fd2029f23 | 67 | ** Module access macro module_BASES replaced by module_BASE_PTRS. |
| mbed_official | 324:406fd2029f23 | 68 | ** |
| mbed_official | 324:406fd2029f23 | 69 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 70 | */ |
| mbed_official | 324:406fd2029f23 | 71 | |
| mbed_official | 324:406fd2029f23 | 72 | /* |
| mbed_official | 324:406fd2029f23 | 73 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
| mbed_official | 324:406fd2029f23 | 74 | * |
| mbed_official | 324:406fd2029f23 | 75 | * This file was generated automatically and any changes may be lost. |
| mbed_official | 324:406fd2029f23 | 76 | */ |
| mbed_official | 324:406fd2029f23 | 77 | #ifndef __HW_CMP_REGISTERS_H__ |
| mbed_official | 324:406fd2029f23 | 78 | #define __HW_CMP_REGISTERS_H__ |
| mbed_official | 324:406fd2029f23 | 79 | |
| mbed_official | 324:406fd2029f23 | 80 | #include "MK22F51212.h" |
| mbed_official | 324:406fd2029f23 | 81 | #include "fsl_bitaccess.h" |
| mbed_official | 324:406fd2029f23 | 82 | |
| mbed_official | 324:406fd2029f23 | 83 | /* |
| mbed_official | 324:406fd2029f23 | 84 | * MK22F51212 CMP |
| mbed_official | 324:406fd2029f23 | 85 | * |
| mbed_official | 324:406fd2029f23 | 86 | * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) |
| mbed_official | 324:406fd2029f23 | 87 | * |
| mbed_official | 324:406fd2029f23 | 88 | * Registers defined in this header file: |
| mbed_official | 324:406fd2029f23 | 89 | * - HW_CMP_CR0 - CMP Control Register 0 |
| mbed_official | 324:406fd2029f23 | 90 | * - HW_CMP_CR1 - CMP Control Register 1 |
| mbed_official | 324:406fd2029f23 | 91 | * - HW_CMP_FPR - CMP Filter Period Register |
| mbed_official | 324:406fd2029f23 | 92 | * - HW_CMP_SCR - CMP Status and Control Register |
| mbed_official | 324:406fd2029f23 | 93 | * - HW_CMP_DACCR - DAC Control Register |
| mbed_official | 324:406fd2029f23 | 94 | * - HW_CMP_MUXCR - MUX Control Register |
| mbed_official | 324:406fd2029f23 | 95 | * |
| mbed_official | 324:406fd2029f23 | 96 | * - hw_cmp_t - Struct containing all module registers. |
| mbed_official | 324:406fd2029f23 | 97 | */ |
| mbed_official | 324:406fd2029f23 | 98 | |
| mbed_official | 324:406fd2029f23 | 99 | #define HW_CMP_INSTANCE_COUNT (2U) /*!< Number of instances of the CMP module. */ |
| mbed_official | 324:406fd2029f23 | 100 | #define HW_CMP0 (0U) /*!< Instance number for CMP0. */ |
| mbed_official | 324:406fd2029f23 | 101 | #define HW_CMP1 (1U) /*!< Instance number for CMP1. */ |
| mbed_official | 324:406fd2029f23 | 102 | |
| mbed_official | 324:406fd2029f23 | 103 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 104 | * HW_CMP_CR0 - CMP Control Register 0 |
| mbed_official | 324:406fd2029f23 | 105 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 106 | |
| mbed_official | 324:406fd2029f23 | 107 | /*! |
| mbed_official | 324:406fd2029f23 | 108 | * @brief HW_CMP_CR0 - CMP Control Register 0 (RW) |
| mbed_official | 324:406fd2029f23 | 109 | * |
| mbed_official | 324:406fd2029f23 | 110 | * Reset value: 0x00U |
| mbed_official | 324:406fd2029f23 | 111 | */ |
| mbed_official | 324:406fd2029f23 | 112 | typedef union _hw_cmp_cr0 |
| mbed_official | 324:406fd2029f23 | 113 | { |
| mbed_official | 324:406fd2029f23 | 114 | uint8_t U; |
| mbed_official | 324:406fd2029f23 | 115 | struct _hw_cmp_cr0_bitfields |
| mbed_official | 324:406fd2029f23 | 116 | { |
| mbed_official | 324:406fd2029f23 | 117 | uint8_t HYSTCTR : 2; /*!< [1:0] Comparator hard block hysteresis |
| mbed_official | 324:406fd2029f23 | 118 | * control */ |
| mbed_official | 324:406fd2029f23 | 119 | uint8_t RESERVED0 : 2; /*!< [3:2] */ |
| mbed_official | 324:406fd2029f23 | 120 | uint8_t FILTER_CNT : 3; /*!< [6:4] Filter Sample Count */ |
| mbed_official | 324:406fd2029f23 | 121 | uint8_t RESERVED1 : 1; /*!< [7] */ |
| mbed_official | 324:406fd2029f23 | 122 | } B; |
| mbed_official | 324:406fd2029f23 | 123 | } hw_cmp_cr0_t; |
| mbed_official | 324:406fd2029f23 | 124 | |
| mbed_official | 324:406fd2029f23 | 125 | /*! |
| mbed_official | 324:406fd2029f23 | 126 | * @name Constants and macros for entire CMP_CR0 register |
| mbed_official | 324:406fd2029f23 | 127 | */ |
| mbed_official | 324:406fd2029f23 | 128 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 129 | #define HW_CMP_CR0_ADDR(x) ((x) + 0x0U) |
| mbed_official | 324:406fd2029f23 | 130 | |
| mbed_official | 324:406fd2029f23 | 131 | #define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 132 | #define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U) |
| mbed_official | 324:406fd2029f23 | 133 | #define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 134 | #define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 135 | #define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 136 | #define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 137 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 138 | |
| mbed_official | 324:406fd2029f23 | 139 | /* |
| mbed_official | 324:406fd2029f23 | 140 | * Constants & macros for individual CMP_CR0 bitfields |
| mbed_official | 324:406fd2029f23 | 141 | */ |
| mbed_official | 324:406fd2029f23 | 142 | |
| mbed_official | 324:406fd2029f23 | 143 | /*! |
| mbed_official | 324:406fd2029f23 | 144 | * @name Register CMP_CR0, field HYSTCTR[1:0] (RW) |
| mbed_official | 324:406fd2029f23 | 145 | * |
| mbed_official | 324:406fd2029f23 | 146 | * Defines the programmable hysteresis level. The hysteresis values associated |
| mbed_official | 324:406fd2029f23 | 147 | * with each level are device-specific. See the Data Sheet of the device for the |
| mbed_official | 324:406fd2029f23 | 148 | * exact values. |
| mbed_official | 324:406fd2029f23 | 149 | * |
| mbed_official | 324:406fd2029f23 | 150 | * Values: |
| mbed_official | 324:406fd2029f23 | 151 | * - 00 - Level 0 |
| mbed_official | 324:406fd2029f23 | 152 | * - 01 - Level 1 |
| mbed_official | 324:406fd2029f23 | 153 | * - 10 - Level 2 |
| mbed_official | 324:406fd2029f23 | 154 | * - 11 - Level 3 |
| mbed_official | 324:406fd2029f23 | 155 | */ |
| mbed_official | 324:406fd2029f23 | 156 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 157 | #define BP_CMP_CR0_HYSTCTR (0U) /*!< Bit position for CMP_CR0_HYSTCTR. */ |
| mbed_official | 324:406fd2029f23 | 158 | #define BM_CMP_CR0_HYSTCTR (0x03U) /*!< Bit mask for CMP_CR0_HYSTCTR. */ |
| mbed_official | 324:406fd2029f23 | 159 | #define BS_CMP_CR0_HYSTCTR (2U) /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */ |
| mbed_official | 324:406fd2029f23 | 160 | |
| mbed_official | 324:406fd2029f23 | 161 | /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */ |
| mbed_official | 324:406fd2029f23 | 162 | #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR) |
| mbed_official | 324:406fd2029f23 | 163 | |
| mbed_official | 324:406fd2029f23 | 164 | /*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */ |
| mbed_official | 324:406fd2029f23 | 165 | #define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR) |
| mbed_official | 324:406fd2029f23 | 166 | |
| mbed_official | 324:406fd2029f23 | 167 | /*! @brief Set the HYSTCTR field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 168 | #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v))) |
| mbed_official | 324:406fd2029f23 | 169 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 170 | |
| mbed_official | 324:406fd2029f23 | 171 | /*! |
| mbed_official | 324:406fd2029f23 | 172 | * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW) |
| mbed_official | 324:406fd2029f23 | 173 | * |
| mbed_official | 324:406fd2029f23 | 174 | * Represents the number of consecutive samples that must agree prior to the |
| mbed_official | 324:406fd2029f23 | 175 | * comparator ouput filter accepting a new output state. For information regarding |
| mbed_official | 324:406fd2029f23 | 176 | * filter programming and latency, see the Functional descriptionThe CMP module |
| mbed_official | 324:406fd2029f23 | 177 | * can be used to compare two analog input voltages applied to INP and INM. . |
| mbed_official | 324:406fd2029f23 | 178 | * |
| mbed_official | 324:406fd2029f23 | 179 | * Values: |
| mbed_official | 324:406fd2029f23 | 180 | * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a |
| mbed_official | 324:406fd2029f23 | 181 | * legal state, and is not recommended. If SE = 0, COUT = COUTA. |
| mbed_official | 324:406fd2029f23 | 182 | * - 001 - One sample must agree. The comparator output is simply sampled. |
| mbed_official | 324:406fd2029f23 | 183 | * - 010 - 2 consecutive samples must agree. |
| mbed_official | 324:406fd2029f23 | 184 | * - 011 - 3 consecutive samples must agree. |
| mbed_official | 324:406fd2029f23 | 185 | * - 100 - 4 consecutive samples must agree. |
| mbed_official | 324:406fd2029f23 | 186 | * - 101 - 5 consecutive samples must agree. |
| mbed_official | 324:406fd2029f23 | 187 | * - 110 - 6 consecutive samples must agree. |
| mbed_official | 324:406fd2029f23 | 188 | * - 111 - 7 consecutive samples must agree. |
| mbed_official | 324:406fd2029f23 | 189 | */ |
| mbed_official | 324:406fd2029f23 | 190 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 191 | #define BP_CMP_CR0_FILTER_CNT (4U) /*!< Bit position for CMP_CR0_FILTER_CNT. */ |
| mbed_official | 324:406fd2029f23 | 192 | #define BM_CMP_CR0_FILTER_CNT (0x70U) /*!< Bit mask for CMP_CR0_FILTER_CNT. */ |
| mbed_official | 324:406fd2029f23 | 193 | #define BS_CMP_CR0_FILTER_CNT (3U) /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */ |
| mbed_official | 324:406fd2029f23 | 194 | |
| mbed_official | 324:406fd2029f23 | 195 | /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */ |
| mbed_official | 324:406fd2029f23 | 196 | #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT) |
| mbed_official | 324:406fd2029f23 | 197 | |
| mbed_official | 324:406fd2029f23 | 198 | /*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */ |
| mbed_official | 324:406fd2029f23 | 199 | #define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT) |
| mbed_official | 324:406fd2029f23 | 200 | |
| mbed_official | 324:406fd2029f23 | 201 | /*! @brief Set the FILTER_CNT field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 202 | #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v))) |
| mbed_official | 324:406fd2029f23 | 203 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 204 | |
| mbed_official | 324:406fd2029f23 | 205 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 206 | * HW_CMP_CR1 - CMP Control Register 1 |
| mbed_official | 324:406fd2029f23 | 207 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 208 | |
| mbed_official | 324:406fd2029f23 | 209 | /*! |
| mbed_official | 324:406fd2029f23 | 210 | * @brief HW_CMP_CR1 - CMP Control Register 1 (RW) |
| mbed_official | 324:406fd2029f23 | 211 | * |
| mbed_official | 324:406fd2029f23 | 212 | * Reset value: 0x00U |
| mbed_official | 324:406fd2029f23 | 213 | */ |
| mbed_official | 324:406fd2029f23 | 214 | typedef union _hw_cmp_cr1 |
| mbed_official | 324:406fd2029f23 | 215 | { |
| mbed_official | 324:406fd2029f23 | 216 | uint8_t U; |
| mbed_official | 324:406fd2029f23 | 217 | struct _hw_cmp_cr1_bitfields |
| mbed_official | 324:406fd2029f23 | 218 | { |
| mbed_official | 324:406fd2029f23 | 219 | uint8_t EN : 1; /*!< [0] Comparator Module Enable */ |
| mbed_official | 324:406fd2029f23 | 220 | uint8_t OPE : 1; /*!< [1] Comparator Output Pin Enable */ |
| mbed_official | 324:406fd2029f23 | 221 | uint8_t COS : 1; /*!< [2] Comparator Output Select */ |
| mbed_official | 324:406fd2029f23 | 222 | uint8_t INV : 1; /*!< [3] Comparator INVERT */ |
| mbed_official | 324:406fd2029f23 | 223 | uint8_t PMODE : 1; /*!< [4] Power Mode Select */ |
| mbed_official | 324:406fd2029f23 | 224 | uint8_t TRIGM : 1; /*!< [5] Trigger Mode Enable */ |
| mbed_official | 324:406fd2029f23 | 225 | uint8_t WE : 1; /*!< [6] Windowing Enable */ |
| mbed_official | 324:406fd2029f23 | 226 | uint8_t SE : 1; /*!< [7] Sample Enable */ |
| mbed_official | 324:406fd2029f23 | 227 | } B; |
| mbed_official | 324:406fd2029f23 | 228 | } hw_cmp_cr1_t; |
| mbed_official | 324:406fd2029f23 | 229 | |
| mbed_official | 324:406fd2029f23 | 230 | /*! |
| mbed_official | 324:406fd2029f23 | 231 | * @name Constants and macros for entire CMP_CR1 register |
| mbed_official | 324:406fd2029f23 | 232 | */ |
| mbed_official | 324:406fd2029f23 | 233 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 234 | #define HW_CMP_CR1_ADDR(x) ((x) + 0x1U) |
| mbed_official | 324:406fd2029f23 | 235 | |
| mbed_official | 324:406fd2029f23 | 236 | #define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 237 | #define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U) |
| mbed_official | 324:406fd2029f23 | 238 | #define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 239 | #define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 240 | #define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 241 | #define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 242 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 243 | |
| mbed_official | 324:406fd2029f23 | 244 | /* |
| mbed_official | 324:406fd2029f23 | 245 | * Constants & macros for individual CMP_CR1 bitfields |
| mbed_official | 324:406fd2029f23 | 246 | */ |
| mbed_official | 324:406fd2029f23 | 247 | |
| mbed_official | 324:406fd2029f23 | 248 | /*! |
| mbed_official | 324:406fd2029f23 | 249 | * @name Register CMP_CR1, field EN[0] (RW) |
| mbed_official | 324:406fd2029f23 | 250 | * |
| mbed_official | 324:406fd2029f23 | 251 | * Enables the Analog Comparator module. When the module is not enabled, it |
| mbed_official | 324:406fd2029f23 | 252 | * remains in the off state, and consumes no power. When the user selects the same |
| mbed_official | 324:406fd2029f23 | 253 | * input from analog mux to the positive and negative port, the comparator is |
| mbed_official | 324:406fd2029f23 | 254 | * disabled automatically. |
| mbed_official | 324:406fd2029f23 | 255 | * |
| mbed_official | 324:406fd2029f23 | 256 | * Values: |
| mbed_official | 324:406fd2029f23 | 257 | * - 0 - Analog Comparator is disabled. |
| mbed_official | 324:406fd2029f23 | 258 | * - 1 - Analog Comparator is enabled. |
| mbed_official | 324:406fd2029f23 | 259 | */ |
| mbed_official | 324:406fd2029f23 | 260 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 261 | #define BP_CMP_CR1_EN (0U) /*!< Bit position for CMP_CR1_EN. */ |
| mbed_official | 324:406fd2029f23 | 262 | #define BM_CMP_CR1_EN (0x01U) /*!< Bit mask for CMP_CR1_EN. */ |
| mbed_official | 324:406fd2029f23 | 263 | #define BS_CMP_CR1_EN (1U) /*!< Bit field size in bits for CMP_CR1_EN. */ |
| mbed_official | 324:406fd2029f23 | 264 | |
| mbed_official | 324:406fd2029f23 | 265 | /*! @brief Read current value of the CMP_CR1_EN field. */ |
| mbed_official | 324:406fd2029f23 | 266 | #define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN)) |
| mbed_official | 324:406fd2029f23 | 267 | |
| mbed_official | 324:406fd2029f23 | 268 | /*! @brief Format value for bitfield CMP_CR1_EN. */ |
| mbed_official | 324:406fd2029f23 | 269 | #define BF_CMP_CR1_EN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN) |
| mbed_official | 324:406fd2029f23 | 270 | |
| mbed_official | 324:406fd2029f23 | 271 | /*! @brief Set the EN field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 272 | #define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v)) |
| mbed_official | 324:406fd2029f23 | 273 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 274 | |
| mbed_official | 324:406fd2029f23 | 275 | /*! |
| mbed_official | 324:406fd2029f23 | 276 | * @name Register CMP_CR1, field OPE[1] (RW) |
| mbed_official | 324:406fd2029f23 | 277 | * |
| mbed_official | 324:406fd2029f23 | 278 | * Values: |
| mbed_official | 324:406fd2029f23 | 279 | * - 0 - CMPO is not available on the associated CMPO output pin. If the |
| mbed_official | 324:406fd2029f23 | 280 | * comparator does not own the pin, this field has no effect. |
| mbed_official | 324:406fd2029f23 | 281 | * - 1 - CMPO is available on the associated CMPO output pin. The comparator |
| mbed_official | 324:406fd2029f23 | 282 | * output (CMPO) is driven out on the associated CMPO output pin if the |
| mbed_official | 324:406fd2029f23 | 283 | * comparator owns the pin. If the comparator does not own the field, this bit has no |
| mbed_official | 324:406fd2029f23 | 284 | * effect. |
| mbed_official | 324:406fd2029f23 | 285 | */ |
| mbed_official | 324:406fd2029f23 | 286 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 287 | #define BP_CMP_CR1_OPE (1U) /*!< Bit position for CMP_CR1_OPE. */ |
| mbed_official | 324:406fd2029f23 | 288 | #define BM_CMP_CR1_OPE (0x02U) /*!< Bit mask for CMP_CR1_OPE. */ |
| mbed_official | 324:406fd2029f23 | 289 | #define BS_CMP_CR1_OPE (1U) /*!< Bit field size in bits for CMP_CR1_OPE. */ |
| mbed_official | 324:406fd2029f23 | 290 | |
| mbed_official | 324:406fd2029f23 | 291 | /*! @brief Read current value of the CMP_CR1_OPE field. */ |
| mbed_official | 324:406fd2029f23 | 292 | #define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE)) |
| mbed_official | 324:406fd2029f23 | 293 | |
| mbed_official | 324:406fd2029f23 | 294 | /*! @brief Format value for bitfield CMP_CR1_OPE. */ |
| mbed_official | 324:406fd2029f23 | 295 | #define BF_CMP_CR1_OPE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE) |
| mbed_official | 324:406fd2029f23 | 296 | |
| mbed_official | 324:406fd2029f23 | 297 | /*! @brief Set the OPE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 298 | #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v)) |
| mbed_official | 324:406fd2029f23 | 299 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 300 | |
| mbed_official | 324:406fd2029f23 | 301 | /*! |
| mbed_official | 324:406fd2029f23 | 302 | * @name Register CMP_CR1, field COS[2] (RW) |
| mbed_official | 324:406fd2029f23 | 303 | * |
| mbed_official | 324:406fd2029f23 | 304 | * Values: |
| mbed_official | 324:406fd2029f23 | 305 | * - 0 - Set the filtered comparator output (CMPO) to equal COUT. |
| mbed_official | 324:406fd2029f23 | 306 | * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA. |
| mbed_official | 324:406fd2029f23 | 307 | */ |
| mbed_official | 324:406fd2029f23 | 308 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 309 | #define BP_CMP_CR1_COS (2U) /*!< Bit position for CMP_CR1_COS. */ |
| mbed_official | 324:406fd2029f23 | 310 | #define BM_CMP_CR1_COS (0x04U) /*!< Bit mask for CMP_CR1_COS. */ |
| mbed_official | 324:406fd2029f23 | 311 | #define BS_CMP_CR1_COS (1U) /*!< Bit field size in bits for CMP_CR1_COS. */ |
| mbed_official | 324:406fd2029f23 | 312 | |
| mbed_official | 324:406fd2029f23 | 313 | /*! @brief Read current value of the CMP_CR1_COS field. */ |
| mbed_official | 324:406fd2029f23 | 314 | #define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS)) |
| mbed_official | 324:406fd2029f23 | 315 | |
| mbed_official | 324:406fd2029f23 | 316 | /*! @brief Format value for bitfield CMP_CR1_COS. */ |
| mbed_official | 324:406fd2029f23 | 317 | #define BF_CMP_CR1_COS(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS) |
| mbed_official | 324:406fd2029f23 | 318 | |
| mbed_official | 324:406fd2029f23 | 319 | /*! @brief Set the COS field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 320 | #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v)) |
| mbed_official | 324:406fd2029f23 | 321 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 322 | |
| mbed_official | 324:406fd2029f23 | 323 | /*! |
| mbed_official | 324:406fd2029f23 | 324 | * @name Register CMP_CR1, field INV[3] (RW) |
| mbed_official | 324:406fd2029f23 | 325 | * |
| mbed_official | 324:406fd2029f23 | 326 | * Allows selection of the polarity of the analog comparator function. It is |
| mbed_official | 324:406fd2029f23 | 327 | * also driven to the COUT output, on both the device pin and as SCR[COUT], when |
| mbed_official | 324:406fd2029f23 | 328 | * OPE=0. |
| mbed_official | 324:406fd2029f23 | 329 | * |
| mbed_official | 324:406fd2029f23 | 330 | * Values: |
| mbed_official | 324:406fd2029f23 | 331 | * - 0 - Does not invert the comparator output. |
| mbed_official | 324:406fd2029f23 | 332 | * - 1 - Inverts the comparator output. |
| mbed_official | 324:406fd2029f23 | 333 | */ |
| mbed_official | 324:406fd2029f23 | 334 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 335 | #define BP_CMP_CR1_INV (3U) /*!< Bit position for CMP_CR1_INV. */ |
| mbed_official | 324:406fd2029f23 | 336 | #define BM_CMP_CR1_INV (0x08U) /*!< Bit mask for CMP_CR1_INV. */ |
| mbed_official | 324:406fd2029f23 | 337 | #define BS_CMP_CR1_INV (1U) /*!< Bit field size in bits for CMP_CR1_INV. */ |
| mbed_official | 324:406fd2029f23 | 338 | |
| mbed_official | 324:406fd2029f23 | 339 | /*! @brief Read current value of the CMP_CR1_INV field. */ |
| mbed_official | 324:406fd2029f23 | 340 | #define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV)) |
| mbed_official | 324:406fd2029f23 | 341 | |
| mbed_official | 324:406fd2029f23 | 342 | /*! @brief Format value for bitfield CMP_CR1_INV. */ |
| mbed_official | 324:406fd2029f23 | 343 | #define BF_CMP_CR1_INV(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV) |
| mbed_official | 324:406fd2029f23 | 344 | |
| mbed_official | 324:406fd2029f23 | 345 | /*! @brief Set the INV field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 346 | #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v)) |
| mbed_official | 324:406fd2029f23 | 347 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 348 | |
| mbed_official | 324:406fd2029f23 | 349 | /*! |
| mbed_official | 324:406fd2029f23 | 350 | * @name Register CMP_CR1, field PMODE[4] (RW) |
| mbed_official | 324:406fd2029f23 | 351 | * |
| mbed_official | 324:406fd2029f23 | 352 | * See the electrical specifications table in the device Data Sheet for details. |
| mbed_official | 324:406fd2029f23 | 353 | * |
| mbed_official | 324:406fd2029f23 | 354 | * Values: |
| mbed_official | 324:406fd2029f23 | 355 | * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower |
| mbed_official | 324:406fd2029f23 | 356 | * output propagation delay and lower current consumption. |
| mbed_official | 324:406fd2029f23 | 357 | * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster |
| mbed_official | 324:406fd2029f23 | 358 | * output propagation delay and higher current consumption. |
| mbed_official | 324:406fd2029f23 | 359 | */ |
| mbed_official | 324:406fd2029f23 | 360 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 361 | #define BP_CMP_CR1_PMODE (4U) /*!< Bit position for CMP_CR1_PMODE. */ |
| mbed_official | 324:406fd2029f23 | 362 | #define BM_CMP_CR1_PMODE (0x10U) /*!< Bit mask for CMP_CR1_PMODE. */ |
| mbed_official | 324:406fd2029f23 | 363 | #define BS_CMP_CR1_PMODE (1U) /*!< Bit field size in bits for CMP_CR1_PMODE. */ |
| mbed_official | 324:406fd2029f23 | 364 | |
| mbed_official | 324:406fd2029f23 | 365 | /*! @brief Read current value of the CMP_CR1_PMODE field. */ |
| mbed_official | 324:406fd2029f23 | 366 | #define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE)) |
| mbed_official | 324:406fd2029f23 | 367 | |
| mbed_official | 324:406fd2029f23 | 368 | /*! @brief Format value for bitfield CMP_CR1_PMODE. */ |
| mbed_official | 324:406fd2029f23 | 369 | #define BF_CMP_CR1_PMODE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE) |
| mbed_official | 324:406fd2029f23 | 370 | |
| mbed_official | 324:406fd2029f23 | 371 | /*! @brief Set the PMODE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 372 | #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v)) |
| mbed_official | 324:406fd2029f23 | 373 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 374 | |
| mbed_official | 324:406fd2029f23 | 375 | /*! |
| mbed_official | 324:406fd2029f23 | 376 | * @name Register CMP_CR1, field TRIGM[5] (RW) |
| mbed_official | 324:406fd2029f23 | 377 | * |
| mbed_official | 324:406fd2029f23 | 378 | * CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to |
| mbed_official | 324:406fd2029f23 | 379 | * 1. In addition, the CMP should be enabled. If the DAC is to be used as a |
| mbed_official | 324:406fd2029f23 | 380 | * reference to the CMP, it should also be enabled. CMP Trigger mode depends on an |
| mbed_official | 324:406fd2029f23 | 381 | * external timer resource to periodically enable the CMP and 6-bit DAC in order to |
| mbed_official | 324:406fd2029f23 | 382 | * generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed |
| mbed_official | 324:406fd2029f23 | 383 | * in a standby state until an external timer resource trigger is received. See |
| mbed_official | 324:406fd2029f23 | 384 | * the chip configuration for details about the external timer resource. |
| mbed_official | 324:406fd2029f23 | 385 | * |
| mbed_official | 324:406fd2029f23 | 386 | * Values: |
| mbed_official | 324:406fd2029f23 | 387 | * - 0 - Trigger mode is disabled. |
| mbed_official | 324:406fd2029f23 | 388 | * - 1 - Trigger mode is enabled. |
| mbed_official | 324:406fd2029f23 | 389 | */ |
| mbed_official | 324:406fd2029f23 | 390 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 391 | #define BP_CMP_CR1_TRIGM (5U) /*!< Bit position for CMP_CR1_TRIGM. */ |
| mbed_official | 324:406fd2029f23 | 392 | #define BM_CMP_CR1_TRIGM (0x20U) /*!< Bit mask for CMP_CR1_TRIGM. */ |
| mbed_official | 324:406fd2029f23 | 393 | #define BS_CMP_CR1_TRIGM (1U) /*!< Bit field size in bits for CMP_CR1_TRIGM. */ |
| mbed_official | 324:406fd2029f23 | 394 | |
| mbed_official | 324:406fd2029f23 | 395 | /*! @brief Read current value of the CMP_CR1_TRIGM field. */ |
| mbed_official | 324:406fd2029f23 | 396 | #define BR_CMP_CR1_TRIGM(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM)) |
| mbed_official | 324:406fd2029f23 | 397 | |
| mbed_official | 324:406fd2029f23 | 398 | /*! @brief Format value for bitfield CMP_CR1_TRIGM. */ |
| mbed_official | 324:406fd2029f23 | 399 | #define BF_CMP_CR1_TRIGM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_TRIGM) & BM_CMP_CR1_TRIGM) |
| mbed_official | 324:406fd2029f23 | 400 | |
| mbed_official | 324:406fd2029f23 | 401 | /*! @brief Set the TRIGM field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 402 | #define BW_CMP_CR1_TRIGM(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM) = (v)) |
| mbed_official | 324:406fd2029f23 | 403 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 404 | |
| mbed_official | 324:406fd2029f23 | 405 | /*! |
| mbed_official | 324:406fd2029f23 | 406 | * @name Register CMP_CR1, field WE[6] (RW) |
| mbed_official | 324:406fd2029f23 | 407 | * |
| mbed_official | 324:406fd2029f23 | 408 | * At any given time, either SE or WE can be set. If a write to this register |
| mbed_official | 324:406fd2029f23 | 409 | * attempts to set both, then SE is set and WE is cleared. However, avoid writing |
| mbed_official | 324:406fd2029f23 | 410 | * 1s to both field locations because this "11" case is reserved and may change in |
| mbed_official | 324:406fd2029f23 | 411 | * future implementations. |
| mbed_official | 324:406fd2029f23 | 412 | * |
| mbed_official | 324:406fd2029f23 | 413 | * Values: |
| mbed_official | 324:406fd2029f23 | 414 | * - 0 - Windowing mode is not selected. |
| mbed_official | 324:406fd2029f23 | 415 | * - 1 - Windowing mode is selected. |
| mbed_official | 324:406fd2029f23 | 416 | */ |
| mbed_official | 324:406fd2029f23 | 417 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 418 | #define BP_CMP_CR1_WE (6U) /*!< Bit position for CMP_CR1_WE. */ |
| mbed_official | 324:406fd2029f23 | 419 | #define BM_CMP_CR1_WE (0x40U) /*!< Bit mask for CMP_CR1_WE. */ |
| mbed_official | 324:406fd2029f23 | 420 | #define BS_CMP_CR1_WE (1U) /*!< Bit field size in bits for CMP_CR1_WE. */ |
| mbed_official | 324:406fd2029f23 | 421 | |
| mbed_official | 324:406fd2029f23 | 422 | /*! @brief Read current value of the CMP_CR1_WE field. */ |
| mbed_official | 324:406fd2029f23 | 423 | #define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE)) |
| mbed_official | 324:406fd2029f23 | 424 | |
| mbed_official | 324:406fd2029f23 | 425 | /*! @brief Format value for bitfield CMP_CR1_WE. */ |
| mbed_official | 324:406fd2029f23 | 426 | #define BF_CMP_CR1_WE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE) |
| mbed_official | 324:406fd2029f23 | 427 | |
| mbed_official | 324:406fd2029f23 | 428 | /*! @brief Set the WE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 429 | #define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v)) |
| mbed_official | 324:406fd2029f23 | 430 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 431 | |
| mbed_official | 324:406fd2029f23 | 432 | /*! |
| mbed_official | 324:406fd2029f23 | 433 | * @name Register CMP_CR1, field SE[7] (RW) |
| mbed_official | 324:406fd2029f23 | 434 | * |
| mbed_official | 324:406fd2029f23 | 435 | * At any given time, either SE or WE can be set. If a write to this register |
| mbed_official | 324:406fd2029f23 | 436 | * attempts to set both, then SE is set and WE is cleared. However, avoid writing |
| mbed_official | 324:406fd2029f23 | 437 | * 1s to both field locations because this "11" case is reserved and may change in |
| mbed_official | 324:406fd2029f23 | 438 | * future implementations. |
| mbed_official | 324:406fd2029f23 | 439 | * |
| mbed_official | 324:406fd2029f23 | 440 | * Values: |
| mbed_official | 324:406fd2029f23 | 441 | * - 0 - Sampling mode is not selected. |
| mbed_official | 324:406fd2029f23 | 442 | * - 1 - Sampling mode is selected. |
| mbed_official | 324:406fd2029f23 | 443 | */ |
| mbed_official | 324:406fd2029f23 | 444 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 445 | #define BP_CMP_CR1_SE (7U) /*!< Bit position for CMP_CR1_SE. */ |
| mbed_official | 324:406fd2029f23 | 446 | #define BM_CMP_CR1_SE (0x80U) /*!< Bit mask for CMP_CR1_SE. */ |
| mbed_official | 324:406fd2029f23 | 447 | #define BS_CMP_CR1_SE (1U) /*!< Bit field size in bits for CMP_CR1_SE. */ |
| mbed_official | 324:406fd2029f23 | 448 | |
| mbed_official | 324:406fd2029f23 | 449 | /*! @brief Read current value of the CMP_CR1_SE field. */ |
| mbed_official | 324:406fd2029f23 | 450 | #define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE)) |
| mbed_official | 324:406fd2029f23 | 451 | |
| mbed_official | 324:406fd2029f23 | 452 | /*! @brief Format value for bitfield CMP_CR1_SE. */ |
| mbed_official | 324:406fd2029f23 | 453 | #define BF_CMP_CR1_SE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE) |
| mbed_official | 324:406fd2029f23 | 454 | |
| mbed_official | 324:406fd2029f23 | 455 | /*! @brief Set the SE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 456 | #define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v)) |
| mbed_official | 324:406fd2029f23 | 457 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 458 | |
| mbed_official | 324:406fd2029f23 | 459 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 460 | * HW_CMP_FPR - CMP Filter Period Register |
| mbed_official | 324:406fd2029f23 | 461 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 462 | |
| mbed_official | 324:406fd2029f23 | 463 | /*! |
| mbed_official | 324:406fd2029f23 | 464 | * @brief HW_CMP_FPR - CMP Filter Period Register (RW) |
| mbed_official | 324:406fd2029f23 | 465 | * |
| mbed_official | 324:406fd2029f23 | 466 | * Reset value: 0x00U |
| mbed_official | 324:406fd2029f23 | 467 | */ |
| mbed_official | 324:406fd2029f23 | 468 | typedef union _hw_cmp_fpr |
| mbed_official | 324:406fd2029f23 | 469 | { |
| mbed_official | 324:406fd2029f23 | 470 | uint8_t U; |
| mbed_official | 324:406fd2029f23 | 471 | struct _hw_cmp_fpr_bitfields |
| mbed_official | 324:406fd2029f23 | 472 | { |
| mbed_official | 324:406fd2029f23 | 473 | uint8_t FILT_PER : 8; /*!< [7:0] Filter Sample Period */ |
| mbed_official | 324:406fd2029f23 | 474 | } B; |
| mbed_official | 324:406fd2029f23 | 475 | } hw_cmp_fpr_t; |
| mbed_official | 324:406fd2029f23 | 476 | |
| mbed_official | 324:406fd2029f23 | 477 | /*! |
| mbed_official | 324:406fd2029f23 | 478 | * @name Constants and macros for entire CMP_FPR register |
| mbed_official | 324:406fd2029f23 | 479 | */ |
| mbed_official | 324:406fd2029f23 | 480 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 481 | #define HW_CMP_FPR_ADDR(x) ((x) + 0x2U) |
| mbed_official | 324:406fd2029f23 | 482 | |
| mbed_official | 324:406fd2029f23 | 483 | #define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 484 | #define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U) |
| mbed_official | 324:406fd2029f23 | 485 | #define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 486 | #define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 487 | #define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 488 | #define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 489 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 490 | |
| mbed_official | 324:406fd2029f23 | 491 | /* |
| mbed_official | 324:406fd2029f23 | 492 | * Constants & macros for individual CMP_FPR bitfields |
| mbed_official | 324:406fd2029f23 | 493 | */ |
| mbed_official | 324:406fd2029f23 | 494 | |
| mbed_official | 324:406fd2029f23 | 495 | /*! |
| mbed_official | 324:406fd2029f23 | 496 | * @name Register CMP_FPR, field FILT_PER[7:0] (RW) |
| mbed_official | 324:406fd2029f23 | 497 | * |
| mbed_official | 324:406fd2029f23 | 498 | * Specifies the sampling period, in bus clock cycles, of the comparator output |
| mbed_official | 324:406fd2029f23 | 499 | * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter |
| mbed_official | 324:406fd2029f23 | 500 | * programming and latency details appear in the Functional descriptionThe CMP |
| mbed_official | 324:406fd2029f23 | 501 | * module can be used to compare two analog input voltages applied to INP and INM. . |
| mbed_official | 324:406fd2029f23 | 502 | * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE |
| mbed_official | 324:406fd2029f23 | 503 | * signal is used to determine the sampling period. |
| mbed_official | 324:406fd2029f23 | 504 | */ |
| mbed_official | 324:406fd2029f23 | 505 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 506 | #define BP_CMP_FPR_FILT_PER (0U) /*!< Bit position for CMP_FPR_FILT_PER. */ |
| mbed_official | 324:406fd2029f23 | 507 | #define BM_CMP_FPR_FILT_PER (0xFFU) /*!< Bit mask for CMP_FPR_FILT_PER. */ |
| mbed_official | 324:406fd2029f23 | 508 | #define BS_CMP_FPR_FILT_PER (8U) /*!< Bit field size in bits for CMP_FPR_FILT_PER. */ |
| mbed_official | 324:406fd2029f23 | 509 | |
| mbed_official | 324:406fd2029f23 | 510 | /*! @brief Read current value of the CMP_FPR_FILT_PER field. */ |
| mbed_official | 324:406fd2029f23 | 511 | #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U) |
| mbed_official | 324:406fd2029f23 | 512 | |
| mbed_official | 324:406fd2029f23 | 513 | /*! @brief Format value for bitfield CMP_FPR_FILT_PER. */ |
| mbed_official | 324:406fd2029f23 | 514 | #define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER) |
| mbed_official | 324:406fd2029f23 | 515 | |
| mbed_official | 324:406fd2029f23 | 516 | /*! @brief Set the FILT_PER field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 517 | #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v)) |
| mbed_official | 324:406fd2029f23 | 518 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 519 | |
| mbed_official | 324:406fd2029f23 | 520 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 521 | * HW_CMP_SCR - CMP Status and Control Register |
| mbed_official | 324:406fd2029f23 | 522 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 523 | |
| mbed_official | 324:406fd2029f23 | 524 | /*! |
| mbed_official | 324:406fd2029f23 | 525 | * @brief HW_CMP_SCR - CMP Status and Control Register (RW) |
| mbed_official | 324:406fd2029f23 | 526 | * |
| mbed_official | 324:406fd2029f23 | 527 | * Reset value: 0x00U |
| mbed_official | 324:406fd2029f23 | 528 | */ |
| mbed_official | 324:406fd2029f23 | 529 | typedef union _hw_cmp_scr |
| mbed_official | 324:406fd2029f23 | 530 | { |
| mbed_official | 324:406fd2029f23 | 531 | uint8_t U; |
| mbed_official | 324:406fd2029f23 | 532 | struct _hw_cmp_scr_bitfields |
| mbed_official | 324:406fd2029f23 | 533 | { |
| mbed_official | 324:406fd2029f23 | 534 | uint8_t COUT : 1; /*!< [0] Analog Comparator Output */ |
| mbed_official | 324:406fd2029f23 | 535 | uint8_t CFF : 1; /*!< [1] Analog Comparator Flag Falling */ |
| mbed_official | 324:406fd2029f23 | 536 | uint8_t CFR : 1; /*!< [2] Analog Comparator Flag Rising */ |
| mbed_official | 324:406fd2029f23 | 537 | uint8_t IEF : 1; /*!< [3] Comparator Interrupt Enable Falling */ |
| mbed_official | 324:406fd2029f23 | 538 | uint8_t IER : 1; /*!< [4] Comparator Interrupt Enable Rising */ |
| mbed_official | 324:406fd2029f23 | 539 | uint8_t RESERVED0 : 1; /*!< [5] */ |
| mbed_official | 324:406fd2029f23 | 540 | uint8_t DMAEN : 1; /*!< [6] DMA Enable Control */ |
| mbed_official | 324:406fd2029f23 | 541 | uint8_t RESERVED1 : 1; /*!< [7] */ |
| mbed_official | 324:406fd2029f23 | 542 | } B; |
| mbed_official | 324:406fd2029f23 | 543 | } hw_cmp_scr_t; |
| mbed_official | 324:406fd2029f23 | 544 | |
| mbed_official | 324:406fd2029f23 | 545 | /*! |
| mbed_official | 324:406fd2029f23 | 546 | * @name Constants and macros for entire CMP_SCR register |
| mbed_official | 324:406fd2029f23 | 547 | */ |
| mbed_official | 324:406fd2029f23 | 548 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 549 | #define HW_CMP_SCR_ADDR(x) ((x) + 0x3U) |
| mbed_official | 324:406fd2029f23 | 550 | |
| mbed_official | 324:406fd2029f23 | 551 | #define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 552 | #define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U) |
| mbed_official | 324:406fd2029f23 | 553 | #define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 554 | #define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 555 | #define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 556 | #define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 557 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 558 | |
| mbed_official | 324:406fd2029f23 | 559 | /* |
| mbed_official | 324:406fd2029f23 | 560 | * Constants & macros for individual CMP_SCR bitfields |
| mbed_official | 324:406fd2029f23 | 561 | */ |
| mbed_official | 324:406fd2029f23 | 562 | |
| mbed_official | 324:406fd2029f23 | 563 | /*! |
| mbed_official | 324:406fd2029f23 | 564 | * @name Register CMP_SCR, field COUT[0] (RO) |
| mbed_official | 324:406fd2029f23 | 565 | * |
| mbed_official | 324:406fd2029f23 | 566 | * Returns the current value of the Analog Comparator output, when read. The |
| mbed_official | 324:406fd2029f23 | 567 | * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module |
| mbed_official | 324:406fd2029f23 | 568 | * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored. |
| mbed_official | 324:406fd2029f23 | 569 | */ |
| mbed_official | 324:406fd2029f23 | 570 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 571 | #define BP_CMP_SCR_COUT (0U) /*!< Bit position for CMP_SCR_COUT. */ |
| mbed_official | 324:406fd2029f23 | 572 | #define BM_CMP_SCR_COUT (0x01U) /*!< Bit mask for CMP_SCR_COUT. */ |
| mbed_official | 324:406fd2029f23 | 573 | #define BS_CMP_SCR_COUT (1U) /*!< Bit field size in bits for CMP_SCR_COUT. */ |
| mbed_official | 324:406fd2029f23 | 574 | |
| mbed_official | 324:406fd2029f23 | 575 | /*! @brief Read current value of the CMP_SCR_COUT field. */ |
| mbed_official | 324:406fd2029f23 | 576 | #define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT)) |
| mbed_official | 324:406fd2029f23 | 577 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 578 | |
| mbed_official | 324:406fd2029f23 | 579 | /*! |
| mbed_official | 324:406fd2029f23 | 580 | * @name Register CMP_SCR, field CFF[1] (W1C) |
| mbed_official | 324:406fd2029f23 | 581 | * |
| mbed_official | 324:406fd2029f23 | 582 | * Detects a falling-edge on COUT, when set, during normal operation. CFF is |
| mbed_official | 324:406fd2029f23 | 583 | * cleared by writing 1 to it. During Stop modes, CFF is level sensitive . |
| mbed_official | 324:406fd2029f23 | 584 | * |
| mbed_official | 324:406fd2029f23 | 585 | * Values: |
| mbed_official | 324:406fd2029f23 | 586 | * - 0 - Falling-edge on COUT has not been detected. |
| mbed_official | 324:406fd2029f23 | 587 | * - 1 - Falling-edge on COUT has occurred. |
| mbed_official | 324:406fd2029f23 | 588 | */ |
| mbed_official | 324:406fd2029f23 | 589 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 590 | #define BP_CMP_SCR_CFF (1U) /*!< Bit position for CMP_SCR_CFF. */ |
| mbed_official | 324:406fd2029f23 | 591 | #define BM_CMP_SCR_CFF (0x02U) /*!< Bit mask for CMP_SCR_CFF. */ |
| mbed_official | 324:406fd2029f23 | 592 | #define BS_CMP_SCR_CFF (1U) /*!< Bit field size in bits for CMP_SCR_CFF. */ |
| mbed_official | 324:406fd2029f23 | 593 | |
| mbed_official | 324:406fd2029f23 | 594 | /*! @brief Read current value of the CMP_SCR_CFF field. */ |
| mbed_official | 324:406fd2029f23 | 595 | #define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF)) |
| mbed_official | 324:406fd2029f23 | 596 | |
| mbed_official | 324:406fd2029f23 | 597 | /*! @brief Format value for bitfield CMP_SCR_CFF. */ |
| mbed_official | 324:406fd2029f23 | 598 | #define BF_CMP_SCR_CFF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF) |
| mbed_official | 324:406fd2029f23 | 599 | |
| mbed_official | 324:406fd2029f23 | 600 | /*! @brief Set the CFF field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 601 | #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v)) |
| mbed_official | 324:406fd2029f23 | 602 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 603 | |
| mbed_official | 324:406fd2029f23 | 604 | /*! |
| mbed_official | 324:406fd2029f23 | 605 | * @name Register CMP_SCR, field CFR[2] (W1C) |
| mbed_official | 324:406fd2029f23 | 606 | * |
| mbed_official | 324:406fd2029f23 | 607 | * Detects a rising-edge on COUT, when set, during normal operation. CFR is |
| mbed_official | 324:406fd2029f23 | 608 | * cleared by writing 1 to it. During Stop modes, CFR is level sensitive . |
| mbed_official | 324:406fd2029f23 | 609 | * |
| mbed_official | 324:406fd2029f23 | 610 | * Values: |
| mbed_official | 324:406fd2029f23 | 611 | * - 0 - Rising-edge on COUT has not been detected. |
| mbed_official | 324:406fd2029f23 | 612 | * - 1 - Rising-edge on COUT has occurred. |
| mbed_official | 324:406fd2029f23 | 613 | */ |
| mbed_official | 324:406fd2029f23 | 614 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 615 | #define BP_CMP_SCR_CFR (2U) /*!< Bit position for CMP_SCR_CFR. */ |
| mbed_official | 324:406fd2029f23 | 616 | #define BM_CMP_SCR_CFR (0x04U) /*!< Bit mask for CMP_SCR_CFR. */ |
| mbed_official | 324:406fd2029f23 | 617 | #define BS_CMP_SCR_CFR (1U) /*!< Bit field size in bits for CMP_SCR_CFR. */ |
| mbed_official | 324:406fd2029f23 | 618 | |
| mbed_official | 324:406fd2029f23 | 619 | /*! @brief Read current value of the CMP_SCR_CFR field. */ |
| mbed_official | 324:406fd2029f23 | 620 | #define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR)) |
| mbed_official | 324:406fd2029f23 | 621 | |
| mbed_official | 324:406fd2029f23 | 622 | /*! @brief Format value for bitfield CMP_SCR_CFR. */ |
| mbed_official | 324:406fd2029f23 | 623 | #define BF_CMP_SCR_CFR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR) |
| mbed_official | 324:406fd2029f23 | 624 | |
| mbed_official | 324:406fd2029f23 | 625 | /*! @brief Set the CFR field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 626 | #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v)) |
| mbed_official | 324:406fd2029f23 | 627 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 628 | |
| mbed_official | 324:406fd2029f23 | 629 | /*! |
| mbed_official | 324:406fd2029f23 | 630 | * @name Register CMP_SCR, field IEF[3] (RW) |
| mbed_official | 324:406fd2029f23 | 631 | * |
| mbed_official | 324:406fd2029f23 | 632 | * Enables the CFF interrupt from the CMP. When this field is set, an interrupt |
| mbed_official | 324:406fd2029f23 | 633 | * will be asserted when CFF is set. |
| mbed_official | 324:406fd2029f23 | 634 | * |
| mbed_official | 324:406fd2029f23 | 635 | * Values: |
| mbed_official | 324:406fd2029f23 | 636 | * - 0 - Interrupt is disabled. |
| mbed_official | 324:406fd2029f23 | 637 | * - 1 - Interrupt is enabled. |
| mbed_official | 324:406fd2029f23 | 638 | */ |
| mbed_official | 324:406fd2029f23 | 639 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 640 | #define BP_CMP_SCR_IEF (3U) /*!< Bit position for CMP_SCR_IEF. */ |
| mbed_official | 324:406fd2029f23 | 641 | #define BM_CMP_SCR_IEF (0x08U) /*!< Bit mask for CMP_SCR_IEF. */ |
| mbed_official | 324:406fd2029f23 | 642 | #define BS_CMP_SCR_IEF (1U) /*!< Bit field size in bits for CMP_SCR_IEF. */ |
| mbed_official | 324:406fd2029f23 | 643 | |
| mbed_official | 324:406fd2029f23 | 644 | /*! @brief Read current value of the CMP_SCR_IEF field. */ |
| mbed_official | 324:406fd2029f23 | 645 | #define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF)) |
| mbed_official | 324:406fd2029f23 | 646 | |
| mbed_official | 324:406fd2029f23 | 647 | /*! @brief Format value for bitfield CMP_SCR_IEF. */ |
| mbed_official | 324:406fd2029f23 | 648 | #define BF_CMP_SCR_IEF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF) |
| mbed_official | 324:406fd2029f23 | 649 | |
| mbed_official | 324:406fd2029f23 | 650 | /*! @brief Set the IEF field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 651 | #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v)) |
| mbed_official | 324:406fd2029f23 | 652 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 653 | |
| mbed_official | 324:406fd2029f23 | 654 | /*! |
| mbed_official | 324:406fd2029f23 | 655 | * @name Register CMP_SCR, field IER[4] (RW) |
| mbed_official | 324:406fd2029f23 | 656 | * |
| mbed_official | 324:406fd2029f23 | 657 | * Enables the CFR interrupt from the CMP. When this field is set, an interrupt |
| mbed_official | 324:406fd2029f23 | 658 | * will be asserted when CFR is set. |
| mbed_official | 324:406fd2029f23 | 659 | * |
| mbed_official | 324:406fd2029f23 | 660 | * Values: |
| mbed_official | 324:406fd2029f23 | 661 | * - 0 - Interrupt is disabled. |
| mbed_official | 324:406fd2029f23 | 662 | * - 1 - Interrupt is enabled. |
| mbed_official | 324:406fd2029f23 | 663 | */ |
| mbed_official | 324:406fd2029f23 | 664 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 665 | #define BP_CMP_SCR_IER (4U) /*!< Bit position for CMP_SCR_IER. */ |
| mbed_official | 324:406fd2029f23 | 666 | #define BM_CMP_SCR_IER (0x10U) /*!< Bit mask for CMP_SCR_IER. */ |
| mbed_official | 324:406fd2029f23 | 667 | #define BS_CMP_SCR_IER (1U) /*!< Bit field size in bits for CMP_SCR_IER. */ |
| mbed_official | 324:406fd2029f23 | 668 | |
| mbed_official | 324:406fd2029f23 | 669 | /*! @brief Read current value of the CMP_SCR_IER field. */ |
| mbed_official | 324:406fd2029f23 | 670 | #define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER)) |
| mbed_official | 324:406fd2029f23 | 671 | |
| mbed_official | 324:406fd2029f23 | 672 | /*! @brief Format value for bitfield CMP_SCR_IER. */ |
| mbed_official | 324:406fd2029f23 | 673 | #define BF_CMP_SCR_IER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER) |
| mbed_official | 324:406fd2029f23 | 674 | |
| mbed_official | 324:406fd2029f23 | 675 | /*! @brief Set the IER field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 676 | #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v)) |
| mbed_official | 324:406fd2029f23 | 677 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 678 | |
| mbed_official | 324:406fd2029f23 | 679 | /*! |
| mbed_official | 324:406fd2029f23 | 680 | * @name Register CMP_SCR, field DMAEN[6] (RW) |
| mbed_official | 324:406fd2029f23 | 681 | * |
| mbed_official | 324:406fd2029f23 | 682 | * Enables the DMA transfer triggered from the CMP module. When this field is |
| mbed_official | 324:406fd2029f23 | 683 | * set, a DMA request is asserted when CFR or CFF is set. |
| mbed_official | 324:406fd2029f23 | 684 | * |
| mbed_official | 324:406fd2029f23 | 685 | * Values: |
| mbed_official | 324:406fd2029f23 | 686 | * - 0 - DMA is disabled. |
| mbed_official | 324:406fd2029f23 | 687 | * - 1 - DMA is enabled. |
| mbed_official | 324:406fd2029f23 | 688 | */ |
| mbed_official | 324:406fd2029f23 | 689 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 690 | #define BP_CMP_SCR_DMAEN (6U) /*!< Bit position for CMP_SCR_DMAEN. */ |
| mbed_official | 324:406fd2029f23 | 691 | #define BM_CMP_SCR_DMAEN (0x40U) /*!< Bit mask for CMP_SCR_DMAEN. */ |
| mbed_official | 324:406fd2029f23 | 692 | #define BS_CMP_SCR_DMAEN (1U) /*!< Bit field size in bits for CMP_SCR_DMAEN. */ |
| mbed_official | 324:406fd2029f23 | 693 | |
| mbed_official | 324:406fd2029f23 | 694 | /*! @brief Read current value of the CMP_SCR_DMAEN field. */ |
| mbed_official | 324:406fd2029f23 | 695 | #define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN)) |
| mbed_official | 324:406fd2029f23 | 696 | |
| mbed_official | 324:406fd2029f23 | 697 | /*! @brief Format value for bitfield CMP_SCR_DMAEN. */ |
| mbed_official | 324:406fd2029f23 | 698 | #define BF_CMP_SCR_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN) |
| mbed_official | 324:406fd2029f23 | 699 | |
| mbed_official | 324:406fd2029f23 | 700 | /*! @brief Set the DMAEN field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 701 | #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v)) |
| mbed_official | 324:406fd2029f23 | 702 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 703 | |
| mbed_official | 324:406fd2029f23 | 704 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 705 | * HW_CMP_DACCR - DAC Control Register |
| mbed_official | 324:406fd2029f23 | 706 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 707 | |
| mbed_official | 324:406fd2029f23 | 708 | /*! |
| mbed_official | 324:406fd2029f23 | 709 | * @brief HW_CMP_DACCR - DAC Control Register (RW) |
| mbed_official | 324:406fd2029f23 | 710 | * |
| mbed_official | 324:406fd2029f23 | 711 | * Reset value: 0x00U |
| mbed_official | 324:406fd2029f23 | 712 | */ |
| mbed_official | 324:406fd2029f23 | 713 | typedef union _hw_cmp_daccr |
| mbed_official | 324:406fd2029f23 | 714 | { |
| mbed_official | 324:406fd2029f23 | 715 | uint8_t U; |
| mbed_official | 324:406fd2029f23 | 716 | struct _hw_cmp_daccr_bitfields |
| mbed_official | 324:406fd2029f23 | 717 | { |
| mbed_official | 324:406fd2029f23 | 718 | uint8_t VOSEL : 6; /*!< [5:0] DAC Output Voltage Select */ |
| mbed_official | 324:406fd2029f23 | 719 | uint8_t VRSEL : 1; /*!< [6] Supply Voltage Reference Source Select */ |
| mbed_official | 324:406fd2029f23 | 720 | uint8_t DACEN : 1; /*!< [7] DAC Enable */ |
| mbed_official | 324:406fd2029f23 | 721 | } B; |
| mbed_official | 324:406fd2029f23 | 722 | } hw_cmp_daccr_t; |
| mbed_official | 324:406fd2029f23 | 723 | |
| mbed_official | 324:406fd2029f23 | 724 | /*! |
| mbed_official | 324:406fd2029f23 | 725 | * @name Constants and macros for entire CMP_DACCR register |
| mbed_official | 324:406fd2029f23 | 726 | */ |
| mbed_official | 324:406fd2029f23 | 727 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 728 | #define HW_CMP_DACCR_ADDR(x) ((x) + 0x4U) |
| mbed_official | 324:406fd2029f23 | 729 | |
| mbed_official | 324:406fd2029f23 | 730 | #define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 731 | #define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U) |
| mbed_official | 324:406fd2029f23 | 732 | #define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 733 | #define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 734 | #define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 735 | #define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 736 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 737 | |
| mbed_official | 324:406fd2029f23 | 738 | /* |
| mbed_official | 324:406fd2029f23 | 739 | * Constants & macros for individual CMP_DACCR bitfields |
| mbed_official | 324:406fd2029f23 | 740 | */ |
| mbed_official | 324:406fd2029f23 | 741 | |
| mbed_official | 324:406fd2029f23 | 742 | /*! |
| mbed_official | 324:406fd2029f23 | 743 | * @name Register CMP_DACCR, field VOSEL[5:0] (RW) |
| mbed_official | 324:406fd2029f23 | 744 | * |
| mbed_official | 324:406fd2029f23 | 745 | * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) * |
| mbed_official | 324:406fd2029f23 | 746 | * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in . |
| mbed_official | 324:406fd2029f23 | 747 | */ |
| mbed_official | 324:406fd2029f23 | 748 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 749 | #define BP_CMP_DACCR_VOSEL (0U) /*!< Bit position for CMP_DACCR_VOSEL. */ |
| mbed_official | 324:406fd2029f23 | 750 | #define BM_CMP_DACCR_VOSEL (0x3FU) /*!< Bit mask for CMP_DACCR_VOSEL. */ |
| mbed_official | 324:406fd2029f23 | 751 | #define BS_CMP_DACCR_VOSEL (6U) /*!< Bit field size in bits for CMP_DACCR_VOSEL. */ |
| mbed_official | 324:406fd2029f23 | 752 | |
| mbed_official | 324:406fd2029f23 | 753 | /*! @brief Read current value of the CMP_DACCR_VOSEL field. */ |
| mbed_official | 324:406fd2029f23 | 754 | #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL) |
| mbed_official | 324:406fd2029f23 | 755 | |
| mbed_official | 324:406fd2029f23 | 756 | /*! @brief Format value for bitfield CMP_DACCR_VOSEL. */ |
| mbed_official | 324:406fd2029f23 | 757 | #define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL) |
| mbed_official | 324:406fd2029f23 | 758 | |
| mbed_official | 324:406fd2029f23 | 759 | /*! @brief Set the VOSEL field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 760 | #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v))) |
| mbed_official | 324:406fd2029f23 | 761 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 762 | |
| mbed_official | 324:406fd2029f23 | 763 | /*! |
| mbed_official | 324:406fd2029f23 | 764 | * @name Register CMP_DACCR, field VRSEL[6] (RW) |
| mbed_official | 324:406fd2029f23 | 765 | * |
| mbed_official | 324:406fd2029f23 | 766 | * Values: |
| mbed_official | 324:406fd2029f23 | 767 | * - 0 - V is selected as resistor ladder network supply reference V. in1 in |
| mbed_official | 324:406fd2029f23 | 768 | * - 1 - V is selected as resistor ladder network supply reference V. in2 in |
| mbed_official | 324:406fd2029f23 | 769 | */ |
| mbed_official | 324:406fd2029f23 | 770 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 771 | #define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */ |
| mbed_official | 324:406fd2029f23 | 772 | #define BM_CMP_DACCR_VRSEL (0x40U) /*!< Bit mask for CMP_DACCR_VRSEL. */ |
| mbed_official | 324:406fd2029f23 | 773 | #define BS_CMP_DACCR_VRSEL (1U) /*!< Bit field size in bits for CMP_DACCR_VRSEL. */ |
| mbed_official | 324:406fd2029f23 | 774 | |
| mbed_official | 324:406fd2029f23 | 775 | /*! @brief Read current value of the CMP_DACCR_VRSEL field. */ |
| mbed_official | 324:406fd2029f23 | 776 | #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL)) |
| mbed_official | 324:406fd2029f23 | 777 | |
| mbed_official | 324:406fd2029f23 | 778 | /*! @brief Format value for bitfield CMP_DACCR_VRSEL. */ |
| mbed_official | 324:406fd2029f23 | 779 | #define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL) |
| mbed_official | 324:406fd2029f23 | 780 | |
| mbed_official | 324:406fd2029f23 | 781 | /*! @brief Set the VRSEL field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 782 | #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v)) |
| mbed_official | 324:406fd2029f23 | 783 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 784 | |
| mbed_official | 324:406fd2029f23 | 785 | /*! |
| mbed_official | 324:406fd2029f23 | 786 | * @name Register CMP_DACCR, field DACEN[7] (RW) |
| mbed_official | 324:406fd2029f23 | 787 | * |
| mbed_official | 324:406fd2029f23 | 788 | * Enables the DAC. When the DAC is disabled, it is powered down to conserve |
| mbed_official | 324:406fd2029f23 | 789 | * power. |
| mbed_official | 324:406fd2029f23 | 790 | * |
| mbed_official | 324:406fd2029f23 | 791 | * Values: |
| mbed_official | 324:406fd2029f23 | 792 | * - 0 - DAC is disabled. |
| mbed_official | 324:406fd2029f23 | 793 | * - 1 - DAC is enabled. |
| mbed_official | 324:406fd2029f23 | 794 | */ |
| mbed_official | 324:406fd2029f23 | 795 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 796 | #define BP_CMP_DACCR_DACEN (7U) /*!< Bit position for CMP_DACCR_DACEN. */ |
| mbed_official | 324:406fd2029f23 | 797 | #define BM_CMP_DACCR_DACEN (0x80U) /*!< Bit mask for CMP_DACCR_DACEN. */ |
| mbed_official | 324:406fd2029f23 | 798 | #define BS_CMP_DACCR_DACEN (1U) /*!< Bit field size in bits for CMP_DACCR_DACEN. */ |
| mbed_official | 324:406fd2029f23 | 799 | |
| mbed_official | 324:406fd2029f23 | 800 | /*! @brief Read current value of the CMP_DACCR_DACEN field. */ |
| mbed_official | 324:406fd2029f23 | 801 | #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN)) |
| mbed_official | 324:406fd2029f23 | 802 | |
| mbed_official | 324:406fd2029f23 | 803 | /*! @brief Format value for bitfield CMP_DACCR_DACEN. */ |
| mbed_official | 324:406fd2029f23 | 804 | #define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN) |
| mbed_official | 324:406fd2029f23 | 805 | |
| mbed_official | 324:406fd2029f23 | 806 | /*! @brief Set the DACEN field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 807 | #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v)) |
| mbed_official | 324:406fd2029f23 | 808 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 809 | |
| mbed_official | 324:406fd2029f23 | 810 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 811 | * HW_CMP_MUXCR - MUX Control Register |
| mbed_official | 324:406fd2029f23 | 812 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 813 | |
| mbed_official | 324:406fd2029f23 | 814 | /*! |
| mbed_official | 324:406fd2029f23 | 815 | * @brief HW_CMP_MUXCR - MUX Control Register (RW) |
| mbed_official | 324:406fd2029f23 | 816 | * |
| mbed_official | 324:406fd2029f23 | 817 | * Reset value: 0x00U |
| mbed_official | 324:406fd2029f23 | 818 | */ |
| mbed_official | 324:406fd2029f23 | 819 | typedef union _hw_cmp_muxcr |
| mbed_official | 324:406fd2029f23 | 820 | { |
| mbed_official | 324:406fd2029f23 | 821 | uint8_t U; |
| mbed_official | 324:406fd2029f23 | 822 | struct _hw_cmp_muxcr_bitfields |
| mbed_official | 324:406fd2029f23 | 823 | { |
| mbed_official | 324:406fd2029f23 | 824 | uint8_t MSEL : 3; /*!< [2:0] Minus Input Mux Control */ |
| mbed_official | 324:406fd2029f23 | 825 | uint8_t PSEL : 3; /*!< [5:3] Plus Input Mux Control */ |
| mbed_official | 324:406fd2029f23 | 826 | uint8_t RESERVED0 : 2; /*!< [7:6] Bit can be programmed to zero only |
| mbed_official | 324:406fd2029f23 | 827 | * . */ |
| mbed_official | 324:406fd2029f23 | 828 | } B; |
| mbed_official | 324:406fd2029f23 | 829 | } hw_cmp_muxcr_t; |
| mbed_official | 324:406fd2029f23 | 830 | |
| mbed_official | 324:406fd2029f23 | 831 | /*! |
| mbed_official | 324:406fd2029f23 | 832 | * @name Constants and macros for entire CMP_MUXCR register |
| mbed_official | 324:406fd2029f23 | 833 | */ |
| mbed_official | 324:406fd2029f23 | 834 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 835 | #define HW_CMP_MUXCR_ADDR(x) ((x) + 0x5U) |
| mbed_official | 324:406fd2029f23 | 836 | |
| mbed_official | 324:406fd2029f23 | 837 | #define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 838 | #define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U) |
| mbed_official | 324:406fd2029f23 | 839 | #define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 840 | #define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 841 | #define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 842 | #define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 843 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 844 | |
| mbed_official | 324:406fd2029f23 | 845 | /* |
| mbed_official | 324:406fd2029f23 | 846 | * Constants & macros for individual CMP_MUXCR bitfields |
| mbed_official | 324:406fd2029f23 | 847 | */ |
| mbed_official | 324:406fd2029f23 | 848 | |
| mbed_official | 324:406fd2029f23 | 849 | /*! |
| mbed_official | 324:406fd2029f23 | 850 | * @name Register CMP_MUXCR, field MSEL[2:0] (RW) |
| mbed_official | 324:406fd2029f23 | 851 | * |
| mbed_official | 324:406fd2029f23 | 852 | * Determines which input is selected for the minus input of the comparator. For |
| mbed_official | 324:406fd2029f23 | 853 | * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate |
| mbed_official | 324:406fd2029f23 | 854 | * operation selects the same input for both muxes, the comparator automatically |
| mbed_official | 324:406fd2029f23 | 855 | * shuts down to prevent itself from becoming a noise generator. |
| mbed_official | 324:406fd2029f23 | 856 | * |
| mbed_official | 324:406fd2029f23 | 857 | * Values: |
| mbed_official | 324:406fd2029f23 | 858 | * - 000 - IN0 |
| mbed_official | 324:406fd2029f23 | 859 | * - 001 - IN1 |
| mbed_official | 324:406fd2029f23 | 860 | * - 010 - IN2 |
| mbed_official | 324:406fd2029f23 | 861 | * - 011 - IN3 |
| mbed_official | 324:406fd2029f23 | 862 | * - 100 - IN4 |
| mbed_official | 324:406fd2029f23 | 863 | * - 101 - IN5 |
| mbed_official | 324:406fd2029f23 | 864 | * - 110 - IN6 |
| mbed_official | 324:406fd2029f23 | 865 | * - 111 - IN7 |
| mbed_official | 324:406fd2029f23 | 866 | */ |
| mbed_official | 324:406fd2029f23 | 867 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 868 | #define BP_CMP_MUXCR_MSEL (0U) /*!< Bit position for CMP_MUXCR_MSEL. */ |
| mbed_official | 324:406fd2029f23 | 869 | #define BM_CMP_MUXCR_MSEL (0x07U) /*!< Bit mask for CMP_MUXCR_MSEL. */ |
| mbed_official | 324:406fd2029f23 | 870 | #define BS_CMP_MUXCR_MSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_MSEL. */ |
| mbed_official | 324:406fd2029f23 | 871 | |
| mbed_official | 324:406fd2029f23 | 872 | /*! @brief Read current value of the CMP_MUXCR_MSEL field. */ |
| mbed_official | 324:406fd2029f23 | 873 | #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL) |
| mbed_official | 324:406fd2029f23 | 874 | |
| mbed_official | 324:406fd2029f23 | 875 | /*! @brief Format value for bitfield CMP_MUXCR_MSEL. */ |
| mbed_official | 324:406fd2029f23 | 876 | #define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL) |
| mbed_official | 324:406fd2029f23 | 877 | |
| mbed_official | 324:406fd2029f23 | 878 | /*! @brief Set the MSEL field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 879 | #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v))) |
| mbed_official | 324:406fd2029f23 | 880 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 881 | |
| mbed_official | 324:406fd2029f23 | 882 | /*! |
| mbed_official | 324:406fd2029f23 | 883 | * @name Register CMP_MUXCR, field PSEL[5:3] (RW) |
| mbed_official | 324:406fd2029f23 | 884 | * |
| mbed_official | 324:406fd2029f23 | 885 | * Determines which input is selected for the plus input of the comparator. For |
| mbed_official | 324:406fd2029f23 | 886 | * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate |
| mbed_official | 324:406fd2029f23 | 887 | * operation selects the same input for both muxes, the comparator automatically |
| mbed_official | 324:406fd2029f23 | 888 | * shuts down to prevent itself from becoming a noise generator. |
| mbed_official | 324:406fd2029f23 | 889 | * |
| mbed_official | 324:406fd2029f23 | 890 | * Values: |
| mbed_official | 324:406fd2029f23 | 891 | * - 000 - IN0 |
| mbed_official | 324:406fd2029f23 | 892 | * - 001 - IN1 |
| mbed_official | 324:406fd2029f23 | 893 | * - 010 - IN2 |
| mbed_official | 324:406fd2029f23 | 894 | * - 011 - IN3 |
| mbed_official | 324:406fd2029f23 | 895 | * - 100 - IN4 |
| mbed_official | 324:406fd2029f23 | 896 | * - 101 - IN5 |
| mbed_official | 324:406fd2029f23 | 897 | * - 110 - IN6 |
| mbed_official | 324:406fd2029f23 | 898 | * - 111 - IN7 |
| mbed_official | 324:406fd2029f23 | 899 | */ |
| mbed_official | 324:406fd2029f23 | 900 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 901 | #define BP_CMP_MUXCR_PSEL (3U) /*!< Bit position for CMP_MUXCR_PSEL. */ |
| mbed_official | 324:406fd2029f23 | 902 | #define BM_CMP_MUXCR_PSEL (0x38U) /*!< Bit mask for CMP_MUXCR_PSEL. */ |
| mbed_official | 324:406fd2029f23 | 903 | #define BS_CMP_MUXCR_PSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_PSEL. */ |
| mbed_official | 324:406fd2029f23 | 904 | |
| mbed_official | 324:406fd2029f23 | 905 | /*! @brief Read current value of the CMP_MUXCR_PSEL field. */ |
| mbed_official | 324:406fd2029f23 | 906 | #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL) |
| mbed_official | 324:406fd2029f23 | 907 | |
| mbed_official | 324:406fd2029f23 | 908 | /*! @brief Format value for bitfield CMP_MUXCR_PSEL. */ |
| mbed_official | 324:406fd2029f23 | 909 | #define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL) |
| mbed_official | 324:406fd2029f23 | 910 | |
| mbed_official | 324:406fd2029f23 | 911 | /*! @brief Set the PSEL field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 912 | #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v))) |
| mbed_official | 324:406fd2029f23 | 913 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 914 | |
| mbed_official | 324:406fd2029f23 | 915 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 916 | * hw_cmp_t - module struct |
| mbed_official | 324:406fd2029f23 | 917 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 918 | /*! |
| mbed_official | 324:406fd2029f23 | 919 | * @brief All CMP module registers. |
| mbed_official | 324:406fd2029f23 | 920 | */ |
| mbed_official | 324:406fd2029f23 | 921 | #pragma pack(1) |
| mbed_official | 324:406fd2029f23 | 922 | typedef struct _hw_cmp |
| mbed_official | 324:406fd2029f23 | 923 | { |
| mbed_official | 324:406fd2029f23 | 924 | __IO hw_cmp_cr0_t CR0; /*!< [0x0] CMP Control Register 0 */ |
| mbed_official | 324:406fd2029f23 | 925 | __IO hw_cmp_cr1_t CR1; /*!< [0x1] CMP Control Register 1 */ |
| mbed_official | 324:406fd2029f23 | 926 | __IO hw_cmp_fpr_t FPR; /*!< [0x2] CMP Filter Period Register */ |
| mbed_official | 324:406fd2029f23 | 927 | __IO hw_cmp_scr_t SCR; /*!< [0x3] CMP Status and Control Register */ |
| mbed_official | 324:406fd2029f23 | 928 | __IO hw_cmp_daccr_t DACCR; /*!< [0x4] DAC Control Register */ |
| mbed_official | 324:406fd2029f23 | 929 | __IO hw_cmp_muxcr_t MUXCR; /*!< [0x5] MUX Control Register */ |
| mbed_official | 324:406fd2029f23 | 930 | } hw_cmp_t; |
| mbed_official | 324:406fd2029f23 | 931 | #pragma pack() |
| mbed_official | 324:406fd2029f23 | 932 | |
| mbed_official | 324:406fd2029f23 | 933 | /*! @brief Macro to access all CMP registers. */ |
| mbed_official | 324:406fd2029f23 | 934 | /*! @param x CMP module instance base address. */ |
| mbed_official | 324:406fd2029f23 | 935 | /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
| mbed_official | 324:406fd2029f23 | 936 | * use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */ |
| mbed_official | 324:406fd2029f23 | 937 | #define HW_CMP(x) (*(hw_cmp_t *)(x)) |
| mbed_official | 324:406fd2029f23 | 938 | |
| mbed_official | 324:406fd2029f23 | 939 | #endif /* __HW_CMP_REGISTERS_H__ */ |
| mbed_official | 324:406fd2029f23 | 940 | /* EOF */ |