FRA221:A / Mbed 2 deprecated RC522_LF

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Dependencies:   mbed

MFRC522.h@1:486ccde79dc6, 2015-11-14 (annotated)

Committer:
kantapon501
Date:
Sat Nov 14 08:28:43 2015 +0000
Revision:
1:486ccde79dc6
Parent:
0:3d4bd1fdeb2e 
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mustwillza 0:3d4bd1fdeb2e 1 /**
mustwillza 0:3d4bd1fdeb2e 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
mustwillza 0:3d4bd1fdeb2e 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
mustwillza 0:3d4bd1fdeb2e 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
mustwillza 0:3d4bd1fdeb2e 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
mustwillza 0:3d4bd1fdeb2e 6 * Ported to mbed by Martin Olejar, Dec, 2013
mustwillza 0:3d4bd1fdeb2e 7 *
mustwillza 0:3d4bd1fdeb2e 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
mustwillza 0:3d4bd1fdeb2e 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
mustwillza 0:3d4bd1fdeb2e 10 *
mustwillza 0:3d4bd1fdeb2e 11 * There are three hardware components involved:
mustwillza 0:3d4bd1fdeb2e 12 * 1) The micro controller: An Arduino
mustwillza 0:3d4bd1fdeb2e 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
mustwillza 0:3d4bd1fdeb2e 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
mustwillza 0:3d4bd1fdeb2e 15 *
mustwillza 0:3d4bd1fdeb2e 16 * The microcontroller and card reader uses SPI for communication.
mustwillza 0:3d4bd1fdeb2e 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
mustwillza 0:3d4bd1fdeb2e 18 *
mustwillza 0:3d4bd1fdeb2e 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
mustwillza 0:3d4bd1fdeb2e 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
mustwillza 0:3d4bd1fdeb2e 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
mustwillza 0:3d4bd1fdeb2e 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
mustwillza 0:3d4bd1fdeb2e 23 *
mustwillza 0:3d4bd1fdeb2e 24 * If only the PICC UID is wanted, the above documents has all the needed information.
mustwillza 0:3d4bd1fdeb2e 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
mustwillza 0:3d4bd1fdeb2e 26 * The MIFARE Classic chips and protocol is described in the datasheets:
mustwillza 0:3d4bd1fdeb2e 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
mustwillza 0:3d4bd1fdeb2e 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
mustwillza 0:3d4bd1fdeb2e 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
mustwillza 0:3d4bd1fdeb2e 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
mustwillza 0:3d4bd1fdeb2e 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
mustwillza 0:3d4bd1fdeb2e 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
mustwillza 0:3d4bd1fdeb2e 33 *
mustwillza 0:3d4bd1fdeb2e 34 * MIFARE Classic 1K (MF1S503x):
mustwillza 0:3d4bd1fdeb2e 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
mustwillza 0:3d4bd1fdeb2e 36 * The blocks are numbered 0-63.
mustwillza 0:3d4bd1fdeb2e 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
mustwillza 0:3d4bd1fdeb2e 38 * Bytes 0-5: Key A
mustwillza 0:3d4bd1fdeb2e 39 * Bytes 6-8: Access Bits
mustwillza 0:3d4bd1fdeb2e 40 * Bytes 9: User data
mustwillza 0:3d4bd1fdeb2e 41 * Bytes 10-15: Key B (or user data)
mustwillza 0:3d4bd1fdeb2e 42 * Block 0 is read only manufacturer data.
mustwillza 0:3d4bd1fdeb2e 43 * To access a block, an authentication using a key from the block's sector must be performed first.
mustwillza 0:3d4bd1fdeb2e 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
mustwillza 0:3d4bd1fdeb2e 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
mustwillza 0:3d4bd1fdeb2e 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
mustwillza 0:3d4bd1fdeb2e 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
mustwillza 0:3d4bd1fdeb2e 48 * MIFARE Classic 4K (MF1S703x):
mustwillza 0:3d4bd1fdeb2e 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
mustwillza 0:3d4bd1fdeb2e 50 * The blocks are numbered 0-255.
mustwillza 0:3d4bd1fdeb2e 51 * The last block in each sector is the Sector Trailer like above.
mustwillza 0:3d4bd1fdeb2e 52 * MIFARE Classic Mini (MF1 IC S20):
mustwillza 0:3d4bd1fdeb2e 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
mustwillza 0:3d4bd1fdeb2e 54 * The blocks are numbered 0-19.
mustwillza 0:3d4bd1fdeb2e 55 * The last block in each sector is the Sector Trailer like above.
mustwillza 0:3d4bd1fdeb2e 56 *
mustwillza 0:3d4bd1fdeb2e 57 * MIFARE Ultralight (MF0ICU1):
mustwillza 0:3d4bd1fdeb2e 58 * Has 16 pages of 4 bytes = 64 bytes.
mustwillza 0:3d4bd1fdeb2e 59 * Pages 0 + 1 is used for the 7-byte UID.
mustwillza 0:3d4bd1fdeb2e 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
mustwillza 0:3d4bd1fdeb2e 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
mustwillza 0:3d4bd1fdeb2e 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
mustwillza 0:3d4bd1fdeb2e 63 * MIFARE Ultralight C (MF0ICU2):
mustwillza 0:3d4bd1fdeb2e 64 * Has 48 pages of 4 bytes = 64 bytes.
mustwillza 0:3d4bd1fdeb2e 65 * Pages 0 + 1 is used for the 7-byte UID.
mustwillza 0:3d4bd1fdeb2e 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
mustwillza 0:3d4bd1fdeb2e 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
mustwillza 0:3d4bd1fdeb2e 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
mustwillza 0:3d4bd1fdeb2e 69 * Page 40 Lock bytes
mustwillza 0:3d4bd1fdeb2e 70 * Page 41 16 bit one way counter
mustwillza 0:3d4bd1fdeb2e 71 * Pages 42-43 Authentication configuration
mustwillza 0:3d4bd1fdeb2e 72 * Pages 44-47 Authentication key
mustwillza 0:3d4bd1fdeb2e 73 */
mustwillza 0:3d4bd1fdeb2e 74 #ifndef MFRC522_h
mustwillza 0:3d4bd1fdeb2e 75 #define MFRC522_h
mustwillza 0:3d4bd1fdeb2e 76
mustwillza 0:3d4bd1fdeb2e 77 #include "mbed.h"
mustwillza 0:3d4bd1fdeb2e 78
mustwillza 0:3d4bd1fdeb2e 79 /**
mustwillza 0:3d4bd1fdeb2e 80 * MFRC522 example
mustwillza 0:3d4bd1fdeb2e 81 *
mustwillza 0:3d4bd1fdeb2e 82 * @code
mustwillza 0:3d4bd1fdeb2e 83 * #include "mbed.h"
mustwillza 0:3d4bd1fdeb2e 84 * #include "MFRC522.h"
mustwillza 0:3d4bd1fdeb2e 85 *
mustwillza 0:3d4bd1fdeb2e 86 * //KL25Z Pins for MFRC522 SPI interface
mustwillza 0:3d4bd1fdeb2e 87 * #define SPI_MOSI PTC6
mustwillza 0:3d4bd1fdeb2e 88 * #define SPI_MISO PTC7
mustwillza 0:3d4bd1fdeb2e 89 * #define SPI_SCLK PTC5
mustwillza 0:3d4bd1fdeb2e 90 * #define SPI_CS PTC4
mustwillza 0:3d4bd1fdeb2e 91 * // KL25Z Pin for MFRC522 reset
mustwillza 0:3d4bd1fdeb2e 92 * #define MF_RESET PTC3
mustwillza 0:3d4bd1fdeb2e 93 * // KL25Z Pins for Debug UART port
mustwillza 0:3d4bd1fdeb2e 94 * #define UART_RX PTA1
mustwillza 0:3d4bd1fdeb2e 95 * #define UART_TX PTA2
mustwillza 0:3d4bd1fdeb2e 96 *
mustwillza 0:3d4bd1fdeb2e 97 * DigitalOut LedRed (LED_RED);
mustwillza 0:3d4bd1fdeb2e 98 * DigitalOut LedGreen (LED_GREEN);
mustwillza 0:3d4bd1fdeb2e 99 *
mustwillza 0:3d4bd1fdeb2e 100 * Serial DebugUART(UART_TX, UART_RX);
mustwillza 0:3d4bd1fdeb2e 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
mustwillza 0:3d4bd1fdeb2e 102 *
mustwillza 0:3d4bd1fdeb2e 103 * int main(void) {
mustwillza 0:3d4bd1fdeb2e 104 * // Set debug UART speed
mustwillza 0:3d4bd1fdeb2e 105 * DebugUART.baud(115200);
mustwillza 0:3d4bd1fdeb2e 106 *
mustwillza 0:3d4bd1fdeb2e 107 * // Init. RC522 Chip
mustwillza 0:3d4bd1fdeb2e 108 * RfChip.PCD_Init();
mustwillza 0:3d4bd1fdeb2e 109 *
mustwillza 0:3d4bd1fdeb2e 110 * while (true) {
mustwillza 0:3d4bd1fdeb2e 111 * LedRed = 1;
mustwillza 0:3d4bd1fdeb2e 112 * LedGreen = 1;
mustwillza 0:3d4bd1fdeb2e 113 *
mustwillza 0:3d4bd1fdeb2e 114 * // Look for new cards
mustwillza 0:3d4bd1fdeb2e 115 * if ( ! RfChip.PICC_IsNewCardPresent())
mustwillza 0:3d4bd1fdeb2e 116 * {
mustwillza 0:3d4bd1fdeb2e 117 * wait_ms(500);
mustwillza 0:3d4bd1fdeb2e 118 * continue;
mustwillza 0:3d4bd1fdeb2e 119 * }
mustwillza 0:3d4bd1fdeb2e 120 *
mustwillza 0:3d4bd1fdeb2e 121 * LedRed = 0;
mustwillza 0:3d4bd1fdeb2e 122 *
mustwillza 0:3d4bd1fdeb2e 123 * // Select one of the cards
mustwillza 0:3d4bd1fdeb2e 124 * if ( ! RfChip.PICC_ReadCardSerial())
mustwillza 0:3d4bd1fdeb2e 125 * {
mustwillza 0:3d4bd1fdeb2e 126 * wait_ms(500);
mustwillza 0:3d4bd1fdeb2e 127 * continue;
mustwillza 0:3d4bd1fdeb2e 128 * }
mustwillza 0:3d4bd1fdeb2e 129 *
mustwillza 0:3d4bd1fdeb2e 130 * LedRed = 1;
mustwillza 0:3d4bd1fdeb2e 131 * LedGreen = 0;
mustwillza 0:3d4bd1fdeb2e 132 *
mustwillza 0:3d4bd1fdeb2e 133 * // Print Card UID
mustwillza 0:3d4bd1fdeb2e 134 * printf("Card UID: ");
mustwillza 0:3d4bd1fdeb2e 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
mustwillza 0:3d4bd1fdeb2e 136 * {
mustwillza 0:3d4bd1fdeb2e 137 * printf(" %X02", RfChip.uid.uidByte[i]);
mustwillza 0:3d4bd1fdeb2e 138 * }
mustwillza 0:3d4bd1fdeb2e 139 * printf("\n\r");
mustwillza 0:3d4bd1fdeb2e 140 *
mustwillza 0:3d4bd1fdeb2e 141 * // Print Card type
mustwillza 0:3d4bd1fdeb2e 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
mustwillza 0:3d4bd1fdeb2e 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
mustwillza 0:3d4bd1fdeb2e 144 * wait_ms(1000);
mustwillza 0:3d4bd1fdeb2e 145 * }
mustwillza 0:3d4bd1fdeb2e 146 * }
mustwillza 0:3d4bd1fdeb2e 147 * @endcode
mustwillza 0:3d4bd1fdeb2e 148 */
mustwillza 0:3d4bd1fdeb2e 149
mustwillza 0:3d4bd1fdeb2e 150 class MFRC522 {
mustwillza 0:3d4bd1fdeb2e 151 public:
mustwillza 0:3d4bd1fdeb2e 152
mustwillza 0:3d4bd1fdeb2e 153 /**
mustwillza 0:3d4bd1fdeb2e 154 * MFRC522 registers (described in chapter 9 of the datasheet).
mustwillza 0:3d4bd1fdeb2e 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
mustwillza 0:3d4bd1fdeb2e 156 */
mustwillza 0:3d4bd1fdeb2e 157 enum PCD_Register {
mustwillza 0:3d4bd1fdeb2e 158 // Page 0: Command and status
mustwillza 0:3d4bd1fdeb2e 159 // 0x00 // reserved for future use
mustwillza 0:3d4bd1fdeb2e 160 CommandReg = 0x01 << 1, // starts and stops command execution
mustwillza 0:3d4bd1fdeb2e 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
mustwillza 0:3d4bd1fdeb2e 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
mustwillza 0:3d4bd1fdeb2e 163 ComIrqReg = 0x04 << 1, // interrupt request bits
mustwillza 0:3d4bd1fdeb2e 164 DivIrqReg = 0x05 << 1, // interrupt request bits
mustwillza 0:3d4bd1fdeb2e 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
mustwillza 0:3d4bd1fdeb2e 166 Status1Reg = 0x07 << 1, // communication status bits
mustwillza 0:3d4bd1fdeb2e 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
mustwillza 0:3d4bd1fdeb2e 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
mustwillza 0:3d4bd1fdeb2e 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
mustwillza 0:3d4bd1fdeb2e 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
mustwillza 0:3d4bd1fdeb2e 171 ControlReg = 0x0C << 1, // miscellaneous control registers
mustwillza 0:3d4bd1fdeb2e 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
mustwillza 0:3d4bd1fdeb2e 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
mustwillza 0:3d4bd1fdeb2e 174 // 0x0F // reserved for future use
mustwillza 0:3d4bd1fdeb2e 175
mustwillza 0:3d4bd1fdeb2e 176 // Page 1:Command
mustwillza 0:3d4bd1fdeb2e 177 // 0x10 // reserved for future use
mustwillza 0:3d4bd1fdeb2e 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
mustwillza 0:3d4bd1fdeb2e 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
mustwillza 0:3d4bd1fdeb2e 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
mustwillza 0:3d4bd1fdeb2e 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
mustwillza 0:3d4bd1fdeb2e 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
mustwillza 0:3d4bd1fdeb2e 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
mustwillza 0:3d4bd1fdeb2e 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
mustwillza 0:3d4bd1fdeb2e 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
mustwillza 0:3d4bd1fdeb2e 186 DemodReg = 0x19 << 1, // defines demodulator settings
mustwillza 0:3d4bd1fdeb2e 187 // 0x1A // reserved for future use
mustwillza 0:3d4bd1fdeb2e 188 // 0x1B // reserved for future use
mustwillza 0:3d4bd1fdeb2e 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
mustwillza 0:3d4bd1fdeb2e 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
mustwillza 0:3d4bd1fdeb2e 191 // 0x1E // reserved for future use
mustwillza 0:3d4bd1fdeb2e 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
mustwillza 0:3d4bd1fdeb2e 193
mustwillza 0:3d4bd1fdeb2e 194 // Page 2: Configuration
mustwillza 0:3d4bd1fdeb2e 195 // 0x20 // reserved for future use
mustwillza 0:3d4bd1fdeb2e 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
mustwillza 0:3d4bd1fdeb2e 197 CRCResultRegL = 0x22 << 1,
mustwillza 0:3d4bd1fdeb2e 198 // 0x23 // reserved for future use
mustwillza 0:3d4bd1fdeb2e 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
mustwillza 0:3d4bd1fdeb2e 200 // 0x25 // reserved for future use
mustwillza 0:3d4bd1fdeb2e 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
mustwillza 0:3d4bd1fdeb2e 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
mustwillza 0:3d4bd1fdeb2e 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
mustwillza 0:3d4bd1fdeb2e 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
mustwillza 0:3d4bd1fdeb2e 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
mustwillza 0:3d4bd1fdeb2e 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
mustwillza 0:3d4bd1fdeb2e 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
mustwillza 0:3d4bd1fdeb2e 208 TReloadRegL = 0x2D << 1,
mustwillza 0:3d4bd1fdeb2e 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
mustwillza 0:3d4bd1fdeb2e 210 TCntValueRegL = 0x2F << 1,
mustwillza 0:3d4bd1fdeb2e 211
mustwillza 0:3d4bd1fdeb2e 212 // Page 3:Test Registers
mustwillza 0:3d4bd1fdeb2e 213 // 0x30 // reserved for future use
mustwillza 0:3d4bd1fdeb2e 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
mustwillza 0:3d4bd1fdeb2e 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
mustwillza 0:3d4bd1fdeb2e 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
mustwillza 0:3d4bd1fdeb2e 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
mustwillza 0:3d4bd1fdeb2e 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
mustwillza 0:3d4bd1fdeb2e 219 AutoTestReg = 0x36 << 1, // controls the digital self test
mustwillza 0:3d4bd1fdeb2e 220 VersionReg = 0x37 << 1, // shows the software version
mustwillza 0:3d4bd1fdeb2e 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
mustwillza 0:3d4bd1fdeb2e 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
mustwillza 0:3d4bd1fdeb2e 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
mustwillza 0:3d4bd1fdeb2e 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
mustwillza 0:3d4bd1fdeb2e 225 // 0x3C // reserved for production tests
mustwillza 0:3d4bd1fdeb2e 226 // 0x3D // reserved for production tests
mustwillza 0:3d4bd1fdeb2e 227 // 0x3E // reserved for production tests
mustwillza 0:3d4bd1fdeb2e 228 // 0x3F // reserved for production tests
mustwillza 0:3d4bd1fdeb2e 229 };
mustwillza 0:3d4bd1fdeb2e 230
mustwillza 0:3d4bd1fdeb2e 231 // MFRC522 commands Described in chapter 10 of the datasheet.
mustwillza 0:3d4bd1fdeb2e 232 enum PCD_Command {
mustwillza 0:3d4bd1fdeb2e 233 PCD_Idle = 0x00, // no action, cancels current command execution
mustwillza 0:3d4bd1fdeb2e 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
mustwillza 0:3d4bd1fdeb2e 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
mustwillza 0:3d4bd1fdeb2e 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
mustwillza 0:3d4bd1fdeb2e 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
mustwillza 0:3d4bd1fdeb2e 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
mustwillza 0:3d4bd1fdeb2e 239 PCD_Receive = 0x08, // activates the receiver circuits
mustwillza 0:3d4bd1fdeb2e 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
mustwillza 0:3d4bd1fdeb2e 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
mustwillza 0:3d4bd1fdeb2e 242 PCD_SoftReset = 0x0F // resets the MFRC522
mustwillza 0:3d4bd1fdeb2e 243 };
mustwillza 0:3d4bd1fdeb2e 244
mustwillza 0:3d4bd1fdeb2e 245 // Commands sent to the PICC.
mustwillza 0:3d4bd1fdeb2e 246 enum PICC_Command {
mustwillza 0:3d4bd1fdeb2e 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
mustwillza 0:3d4bd1fdeb2e 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:3d4bd1fdeb2e 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:3d4bd1fdeb2e 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
mustwillza 0:3d4bd1fdeb2e 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
mustwillza 0:3d4bd1fdeb2e 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
mustwillza 0:3d4bd1fdeb2e 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
mustwillza 0:3d4bd1fdeb2e 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
mustwillza 0:3d4bd1fdeb2e 255
mustwillza 0:3d4bd1fdeb2e 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
mustwillza 0:3d4bd1fdeb2e 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
mustwillza 0:3d4bd1fdeb2e 258 // The read/write commands can also be used for MIFARE Ultralight.
mustwillza 0:3d4bd1fdeb2e 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
mustwillza 0:3d4bd1fdeb2e 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
mustwillza 0:3d4bd1fdeb2e 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
mustwillza 0:3d4bd1fdeb2e 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
mustwillza 0:3d4bd1fdeb2e 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
mustwillza 0:3d4bd1fdeb2e 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
mustwillza 0:3d4bd1fdeb2e 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
mustwillza 0:3d4bd1fdeb2e 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
mustwillza 0:3d4bd1fdeb2e 267
mustwillza 0:3d4bd1fdeb2e 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
mustwillza 0:3d4bd1fdeb2e 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
mustwillza 0:3d4bd1fdeb2e 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
mustwillza 0:3d4bd1fdeb2e 271 };
mustwillza 0:3d4bd1fdeb2e 272
mustwillza 0:3d4bd1fdeb2e 273 // MIFARE constants that does not fit anywhere else
mustwillza 0:3d4bd1fdeb2e 274 enum MIFARE_Misc {
mustwillza 0:3d4bd1fdeb2e 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
mustwillza 0:3d4bd1fdeb2e 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
mustwillza 0:3d4bd1fdeb2e 277 };
mustwillza 0:3d4bd1fdeb2e 278
mustwillza 0:3d4bd1fdeb2e 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
mustwillza 0:3d4bd1fdeb2e 280 enum PICC_Type {
mustwillza 0:3d4bd1fdeb2e 281 PICC_TYPE_UNKNOWN = 0,
mustwillza 0:3d4bd1fdeb2e 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
mustwillza 0:3d4bd1fdeb2e 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
mustwillza 0:3d4bd1fdeb2e 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
mustwillza 0:3d4bd1fdeb2e 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
mustwillza 0:3d4bd1fdeb2e 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
mustwillza 0:3d4bd1fdeb2e 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
mustwillza 0:3d4bd1fdeb2e 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
mustwillza 0:3d4bd1fdeb2e 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
mustwillza 0:3d4bd1fdeb2e 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
mustwillza 0:3d4bd1fdeb2e 291 };
mustwillza 0:3d4bd1fdeb2e 292
mustwillza 0:3d4bd1fdeb2e 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
mustwillza 0:3d4bd1fdeb2e 294 enum StatusCode {
mustwillza 0:3d4bd1fdeb2e 295 STATUS_OK = 1, // Success
mustwillza 0:3d4bd1fdeb2e 296 STATUS_ERROR = 2, // Error in communication
mustwillza 0:3d4bd1fdeb2e 297 STATUS_COLLISION = 3, // Collision detected
mustwillza 0:3d4bd1fdeb2e 298 STATUS_TIMEOUT = 4, // Timeout in communication.
mustwillza 0:3d4bd1fdeb2e 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
mustwillza 0:3d4bd1fdeb2e 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
mustwillza 0:3d4bd1fdeb2e 301 STATUS_INVALID = 7, // Invalid argument.
mustwillza 0:3d4bd1fdeb2e 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
mustwillza 0:3d4bd1fdeb2e 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
mustwillza 0:3d4bd1fdeb2e 304 };
mustwillza 0:3d4bd1fdeb2e 305
mustwillza 0:3d4bd1fdeb2e 306 // A struct used for passing the UID of a PICC.
mustwillza 0:3d4bd1fdeb2e 307 typedef struct {
mustwillza 0:3d4bd1fdeb2e 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
mustwillza 0:3d4bd1fdeb2e 309 uint8_t uidByte[10];
kantapon501 1:486ccde79dc6 310 char uidcheck[100];
mustwillza 0:3d4bd1fdeb2e 311 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
mustwillza 0:3d4bd1fdeb2e 312 } Uid;
mustwillza 0:3d4bd1fdeb2e 313
mustwillza 0:3d4bd1fdeb2e 314 // A struct used for passing a MIFARE Crypto1 key
mustwillza 0:3d4bd1fdeb2e 315 typedef struct {
mustwillza 0:3d4bd1fdeb2e 316 uint8_t keyByte[MF_KEY_SIZE];
mustwillza 0:3d4bd1fdeb2e 317 } MIFARE_Key;
mustwillza 0:3d4bd1fdeb2e 318
mustwillza 0:3d4bd1fdeb2e 319 // Member variables
mustwillza 0:3d4bd1fdeb2e 320 Uid uid; // Used by PICC_ReadCardSerial().
mustwillza 0:3d4bd1fdeb2e 321
mustwillza 0:3d4bd1fdeb2e 322 // Size of the MFRC522 FIFO
mustwillza 0:3d4bd1fdeb2e 323 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
mustwillza 0:3d4bd1fdeb2e 324
mustwillza 0:3d4bd1fdeb2e 325 /**
mustwillza 0:3d4bd1fdeb2e 326 * MFRC522 constructor
mustwillza 0:3d4bd1fdeb2e 327 *
mustwillza 0:3d4bd1fdeb2e 328 * @param mosi SPI MOSI pin
mustwillza 0:3d4bd1fdeb2e 329 * @param miso SPI MISO pin
mustwillza 0:3d4bd1fdeb2e 330 * @param sclk SPI SCLK pin
mustwillza 0:3d4bd1fdeb2e 331 * @param cs SPI CS pin
mustwillza 0:3d4bd1fdeb2e 332 * @param reset Reset pin
mustwillza 0:3d4bd1fdeb2e 333 */
mustwillza 0:3d4bd1fdeb2e 334 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
mustwillza 0:3d4bd1fdeb2e 335
mustwillza 0:3d4bd1fdeb2e 336 /**
mustwillza 0:3d4bd1fdeb2e 337 * MFRC522 destructor
mustwillza 0:3d4bd1fdeb2e 338 */
mustwillza 0:3d4bd1fdeb2e 339 ~MFRC522();
mustwillza 0:3d4bd1fdeb2e 340
mustwillza 0:3d4bd1fdeb2e 341
mustwillza 0:3d4bd1fdeb2e 342 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 343 //! @name Functions for manipulating the MFRC522
mustwillza 0:3d4bd1fdeb2e 344 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 345 //@{
mustwillza 0:3d4bd1fdeb2e 346
mustwillza 0:3d4bd1fdeb2e 347 /**
mustwillza 0:3d4bd1fdeb2e 348 * Initializes the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 349 */
mustwillza 0:3d4bd1fdeb2e 350 void PCD_Init (void);
mustwillza 0:3d4bd1fdeb2e 351
mustwillza 0:3d4bd1fdeb2e 352 /**
mustwillza 0:3d4bd1fdeb2e 353 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
mustwillza 0:3d4bd1fdeb2e 354 */
mustwillza 0:3d4bd1fdeb2e 355 void PCD_Reset (void);
mustwillza 0:3d4bd1fdeb2e 356
mustwillza 0:3d4bd1fdeb2e 357 /**
mustwillza 0:3d4bd1fdeb2e 358 * Turns the antenna on by enabling pins TX1 and TX2.
mustwillza 0:3d4bd1fdeb2e 359 * After a reset these pins disabled.
mustwillza 0:3d4bd1fdeb2e 360 */
mustwillza 0:3d4bd1fdeb2e 361 void PCD_AntennaOn (void);
mustwillza 0:3d4bd1fdeb2e 362
mustwillza 0:3d4bd1fdeb2e 363 /**
mustwillza 0:3d4bd1fdeb2e 364 * Writes a byte to the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 365 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 366 *
mustwillza 0:3d4bd1fdeb2e 367 * @param reg The register to write to. One of the PCD_Register enums.
mustwillza 0:3d4bd1fdeb2e 368 * @param value The value to write.
mustwillza 0:3d4bd1fdeb2e 369 */
mustwillza 0:3d4bd1fdeb2e 370 void PCD_WriteRegister (uint8_t reg, uint8_t value);
mustwillza 0:3d4bd1fdeb2e 371
mustwillza 0:3d4bd1fdeb2e 372 /**
mustwillza 0:3d4bd1fdeb2e 373 * Writes a number of bytes to the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 374 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 375 *
mustwillza 0:3d4bd1fdeb2e 376 * @param reg The register to write to. One of the PCD_Register enums.
mustwillza 0:3d4bd1fdeb2e 377 * @param count The number of bytes to write to the register
mustwillza 0:3d4bd1fdeb2e 378 * @param values The values to write. Byte array.
mustwillza 0:3d4bd1fdeb2e 379 */
mustwillza 0:3d4bd1fdeb2e 380 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
mustwillza 0:3d4bd1fdeb2e 381
mustwillza 0:3d4bd1fdeb2e 382 /**
mustwillza 0:3d4bd1fdeb2e 383 * Reads a byte from the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 384 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 385 *
mustwillza 0:3d4bd1fdeb2e 386 * @param reg The register to read from. One of the PCD_Register enums.
mustwillza 0:3d4bd1fdeb2e 387 * @returns Register value
mustwillza 0:3d4bd1fdeb2e 388 */
mustwillza 0:3d4bd1fdeb2e 389 uint8_t PCD_ReadRegister (uint8_t reg);
mustwillza 0:3d4bd1fdeb2e 390
mustwillza 0:3d4bd1fdeb2e 391 /**
mustwillza 0:3d4bd1fdeb2e 392 * Reads a number of bytes from the specified register in the MFRC522 chip.
mustwillza 0:3d4bd1fdeb2e 393 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:3d4bd1fdeb2e 394 *
mustwillza 0:3d4bd1fdeb2e 395 * @param reg The register to read from. One of the PCD_Register enums.
mustwillza 0:3d4bd1fdeb2e 396 * @param count The number of bytes to read.
mustwillza 0:3d4bd1fdeb2e 397 * @param values Byte array to store the values in.
mustwillza 0:3d4bd1fdeb2e 398 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
mustwillza 0:3d4bd1fdeb2e 399 */
mustwillza 0:3d4bd1fdeb2e 400 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
mustwillza 0:3d4bd1fdeb2e 401
mustwillza 0:3d4bd1fdeb2e 402 /**
mustwillza 0:3d4bd1fdeb2e 403 * Sets the bits given in mask in register reg.
mustwillza 0:3d4bd1fdeb2e 404 *
mustwillza 0:3d4bd1fdeb2e 405 * @param reg The register to update. One of the PCD_Register enums.
mustwillza 0:3d4bd1fdeb2e 406 * @param mask The bits to set.
mustwillza 0:3d4bd1fdeb2e 407 */
mustwillza 0:3d4bd1fdeb2e 408 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
mustwillza 0:3d4bd1fdeb2e 409
mustwillza 0:3d4bd1fdeb2e 410 /**
mustwillza 0:3d4bd1fdeb2e 411 * Clears the bits given in mask from register reg.
mustwillza 0:3d4bd1fdeb2e 412 *
mustwillza 0:3d4bd1fdeb2e 413 * @param reg The register to update. One of the PCD_Register enums.
mustwillza 0:3d4bd1fdeb2e 414 * @param mask The bits to clear.
mustwillza 0:3d4bd1fdeb2e 415 */
mustwillza 0:3d4bd1fdeb2e 416 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
mustwillza 0:3d4bd1fdeb2e 417
mustwillza 0:3d4bd1fdeb2e 418 /**
mustwillza 0:3d4bd1fdeb2e 419 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
mustwillza 0:3d4bd1fdeb2e 420 *
mustwillza 0:3d4bd1fdeb2e 421 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
mustwillza 0:3d4bd1fdeb2e 422 * @param length The number of bytes to transfer.
mustwillza 0:3d4bd1fdeb2e 423 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
mustwillza 0:3d4bd1fdeb2e 424 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 425 */
mustwillza 0:3d4bd1fdeb2e 426 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
mustwillza 0:3d4bd1fdeb2e 427
mustwillza 0:3d4bd1fdeb2e 428 /**
mustwillza 0:3d4bd1fdeb2e 429 * Executes the Transceive command.
mustwillza 0:3d4bd1fdeb2e 430 * CRC validation can only be done if backData and backLen are specified.
mustwillza 0:3d4bd1fdeb2e 431 *
mustwillza 0:3d4bd1fdeb2e 432 * @param sendData Pointer to the data to transfer to the FIFO.
mustwillza 0:3d4bd1fdeb2e 433 * @param sendLen Number of bytes to transfer to the FIFO.
mustwillza 0:3d4bd1fdeb2e 434 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
mustwillza 0:3d4bd1fdeb2e 435 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
mustwillza 0:3d4bd1fdeb2e 436 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
mustwillza 0:3d4bd1fdeb2e 437 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
mustwillza 0:3d4bd1fdeb2e 438 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
mustwillza 0:3d4bd1fdeb2e 439 *
mustwillza 0:3d4bd1fdeb2e 440 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 441 */
mustwillza 0:3d4bd1fdeb2e 442 uint8_t PCD_TransceiveData (uint8_t *sendData,
mustwillza 0:3d4bd1fdeb2e 443 uint8_t sendLen,
mustwillza 0:3d4bd1fdeb2e 444 uint8_t *backData,
mustwillza 0:3d4bd1fdeb2e 445 uint8_t *backLen,
mustwillza 0:3d4bd1fdeb2e 446 uint8_t *validBits = NULL,
mustwillza 0:3d4bd1fdeb2e 447 uint8_t rxAlign = 0,
mustwillza 0:3d4bd1fdeb2e 448 bool checkCRC = false);
mustwillza 0:3d4bd1fdeb2e 449
mustwillza 0:3d4bd1fdeb2e 450
mustwillza 0:3d4bd1fdeb2e 451 /**
mustwillza 0:3d4bd1fdeb2e 452 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
mustwillza 0:3d4bd1fdeb2e 453 * CRC validation can only be done if backData and backLen are specified.
mustwillza 0:3d4bd1fdeb2e 454 *
mustwillza 0:3d4bd1fdeb2e 455 * @param command The command to execute. One of the PCD_Command enums.
mustwillza 0:3d4bd1fdeb2e 456 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
mustwillza 0:3d4bd1fdeb2e 457 * @param sendData Pointer to the data to transfer to the FIFO.
mustwillza 0:3d4bd1fdeb2e 458 * @param sendLen Number of bytes to transfer to the FIFO.
mustwillza 0:3d4bd1fdeb2e 459 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
mustwillza 0:3d4bd1fdeb2e 460 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
mustwillza 0:3d4bd1fdeb2e 461 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
mustwillza 0:3d4bd1fdeb2e 462 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
mustwillza 0:3d4bd1fdeb2e 463 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
mustwillza 0:3d4bd1fdeb2e 464 *
mustwillza 0:3d4bd1fdeb2e 465 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 466 */
mustwillza 0:3d4bd1fdeb2e 467 uint8_t PCD_CommunicateWithPICC(uint8_t command,
mustwillza 0:3d4bd1fdeb2e 468 uint8_t waitIRq,
mustwillza 0:3d4bd1fdeb2e 469 uint8_t *sendData,
mustwillza 0:3d4bd1fdeb2e 470 uint8_t sendLen,
mustwillza 0:3d4bd1fdeb2e 471 uint8_t *backData = NULL,
mustwillza 0:3d4bd1fdeb2e 472 uint8_t *backLen = NULL,
mustwillza 0:3d4bd1fdeb2e 473 uint8_t *validBits = NULL,
mustwillza 0:3d4bd1fdeb2e 474 uint8_t rxAlign = 0,
mustwillza 0:3d4bd1fdeb2e 475 bool checkCRC = false);
mustwillza 0:3d4bd1fdeb2e 476
mustwillza 0:3d4bd1fdeb2e 477 /**
mustwillza 0:3d4bd1fdeb2e 478 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:3d4bd1fdeb2e 479 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:3d4bd1fdeb2e 480 *
mustwillza 0:3d4bd1fdeb2e 481 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mustwillza 0:3d4bd1fdeb2e 482 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:3d4bd1fdeb2e 483 *
mustwillza 0:3d4bd1fdeb2e 484 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 485 */
mustwillza 0:3d4bd1fdeb2e 486 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
mustwillza 0:3d4bd1fdeb2e 487
mustwillza 0:3d4bd1fdeb2e 488 /**
mustwillza 0:3d4bd1fdeb2e 489 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:3d4bd1fdeb2e 490 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:3d4bd1fdeb2e 491 *
mustwillza 0:3d4bd1fdeb2e 492 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mustwillza 0:3d4bd1fdeb2e 493 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:3d4bd1fdeb2e 494 *
mustwillza 0:3d4bd1fdeb2e 495 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 496 */
mustwillza 0:3d4bd1fdeb2e 497 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
mustwillza 0:3d4bd1fdeb2e 498
mustwillza 0:3d4bd1fdeb2e 499 /**
mustwillza 0:3d4bd1fdeb2e 500 * Transmits REQA or WUPA commands.
mustwillza 0:3d4bd1fdeb2e 501 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:3d4bd1fdeb2e 502 *
mustwillza 0:3d4bd1fdeb2e 503 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
mustwillza 0:3d4bd1fdeb2e 504 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mustwillza 0:3d4bd1fdeb2e 505 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:3d4bd1fdeb2e 506 *
mustwillza 0:3d4bd1fdeb2e 507 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 508 */
mustwillza 0:3d4bd1fdeb2e 509 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
mustwillza 0:3d4bd1fdeb2e 510
mustwillza 0:3d4bd1fdeb2e 511 /**
mustwillza 0:3d4bd1fdeb2e 512 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
mustwillza 0:3d4bd1fdeb2e 513 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
mustwillza 0:3d4bd1fdeb2e 514 * On success:
mustwillza 0:3d4bd1fdeb2e 515 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
mustwillza 0:3d4bd1fdeb2e 516 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
mustwillza 0:3d4bd1fdeb2e 517 *
mustwillza 0:3d4bd1fdeb2e 518 * A PICC UID consists of 4, 7 or 10 bytes.
mustwillza 0:3d4bd1fdeb2e 519 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
mustwillza 0:3d4bd1fdeb2e 520 *
mustwillza 0:3d4bd1fdeb2e 521 * UID size Number of UID bytes Cascade levels Example of PICC
mustwillza 0:3d4bd1fdeb2e 522 * ======== =================== ============== ===============
mustwillza 0:3d4bd1fdeb2e 523 * single 4 1 MIFARE Classic
mustwillza 0:3d4bd1fdeb2e 524 * double 7 2 MIFARE Ultralight
mustwillza 0:3d4bd1fdeb2e 525 * triple 10 3 Not currently in use?
mustwillza 0:3d4bd1fdeb2e 526 *
mustwillza 0:3d4bd1fdeb2e 527 *
mustwillza 0:3d4bd1fdeb2e 528 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
mustwillza 0:3d4bd1fdeb2e 529 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
mustwillza 0:3d4bd1fdeb2e 530 *
mustwillza 0:3d4bd1fdeb2e 531 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 532 */
mustwillza 0:3d4bd1fdeb2e 533 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
mustwillza 0:3d4bd1fdeb2e 534
mustwillza 0:3d4bd1fdeb2e 535 /**
mustwillza 0:3d4bd1fdeb2e 536 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
mustwillza 0:3d4bd1fdeb2e 537 *
mustwillza 0:3d4bd1fdeb2e 538 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 539 */
mustwillza 0:3d4bd1fdeb2e 540 uint8_t PICC_HaltA (void);
mustwillza 0:3d4bd1fdeb2e 541
mustwillza 0:3d4bd1fdeb2e 542 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 543 //@}
mustwillza 0:3d4bd1fdeb2e 544
mustwillza 0:3d4bd1fdeb2e 545
mustwillza 0:3d4bd1fdeb2e 546 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 547 //! @name Functions for communicating with MIFARE PICCs
mustwillza 0:3d4bd1fdeb2e 548 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 549 //@{
mustwillza 0:3d4bd1fdeb2e 550
mustwillza 0:3d4bd1fdeb2e 551 /**
mustwillza 0:3d4bd1fdeb2e 552 * Executes the MFRC522 MFAuthent command.
mustwillza 0:3d4bd1fdeb2e 553 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
mustwillza 0:3d4bd1fdeb2e 554 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
mustwillza 0:3d4bd1fdeb2e 555 * For use with MIFARE Classic PICCs.
mustwillza 0:3d4bd1fdeb2e 556 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
mustwillza 0:3d4bd1fdeb2e 557 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
mustwillza 0:3d4bd1fdeb2e 558 *
mustwillza 0:3d4bd1fdeb2e 559 * All keys are set to FFFFFFFFFFFFh at chip delivery.
mustwillza 0:3d4bd1fdeb2e 560 *
mustwillza 0:3d4bd1fdeb2e 561 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
mustwillza 0:3d4bd1fdeb2e 562 * @param blockAddr The block number. See numbering in the comments in the .h file.
mustwillza 0:3d4bd1fdeb2e 563 * @param key Pointer to the Crypteo1 key to use (6 bytes)
mustwillza 0:3d4bd1fdeb2e 564 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
mustwillza 0:3d4bd1fdeb2e 565 *
mustwillza 0:3d4bd1fdeb2e 566 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
mustwillza 0:3d4bd1fdeb2e 567 */
mustwillza 0:3d4bd1fdeb2e 568 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
mustwillza 0:3d4bd1fdeb2e 569
mustwillza 0:3d4bd1fdeb2e 570 /**
mustwillza 0:3d4bd1fdeb2e 571 * Used to exit the PCD from its authenticated state.
mustwillza 0:3d4bd1fdeb2e 572 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
mustwillza 0:3d4bd1fdeb2e 573 */
mustwillza 0:3d4bd1fdeb2e 574 void PCD_StopCrypto1 (void);
mustwillza 0:3d4bd1fdeb2e 575
mustwillza 0:3d4bd1fdeb2e 576 /**
mustwillza 0:3d4bd1fdeb2e 577 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
mustwillza 0:3d4bd1fdeb2e 578 *
mustwillza 0:3d4bd1fdeb2e 579 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
mustwillza 0:3d4bd1fdeb2e 580 *
mustwillza 0:3d4bd1fdeb2e 581 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
mustwillza 0:3d4bd1fdeb2e 582 * The MF0ICU1 returns a NAK for higher addresses.
mustwillza 0:3d4bd1fdeb2e 583 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
mustwillza 0:3d4bd1fdeb2e 584 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
mustwillza 0:3d4bd1fdeb2e 585 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
mustwillza 0:3d4bd1fdeb2e 586 *
mustwillza 0:3d4bd1fdeb2e 587 * The buffer must be at least 18 bytes because a CRC_A is also returned.
mustwillza 0:3d4bd1fdeb2e 588 * Checks the CRC_A before returning STATUS_OK.
mustwillza 0:3d4bd1fdeb2e 589 *
mustwillza 0:3d4bd1fdeb2e 590 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
mustwillza 0:3d4bd1fdeb2e 591 * @param buffer The buffer to store the data in
mustwillza 0:3d4bd1fdeb2e 592 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:3d4bd1fdeb2e 593 *
mustwillza 0:3d4bd1fdeb2e 594 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 595 */
mustwillza 0:3d4bd1fdeb2e 596 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
mustwillza 0:3d4bd1fdeb2e 597
mustwillza 0:3d4bd1fdeb2e 598 /**
mustwillza 0:3d4bd1fdeb2e 599 * Writes 16 bytes to the active PICC.
mustwillza 0:3d4bd1fdeb2e 600 *
mustwillza 0:3d4bd1fdeb2e 601 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
mustwillza 0:3d4bd1fdeb2e 602 *
mustwillza 0:3d4bd1fdeb2e 603 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
mustwillza 0:3d4bd1fdeb2e 604 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
mustwillza 0:3d4bd1fdeb2e 605 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
mustwillza 0:3d4bd1fdeb2e 606 *
mustwillza 0:3d4bd1fdeb2e 607 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
mustwillza 0:3d4bd1fdeb2e 608 * @param buffer The 16 bytes to write to the PICC
mustwillza 0:3d4bd1fdeb2e 609 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
mustwillza 0:3d4bd1fdeb2e 610 *
mustwillza 0:3d4bd1fdeb2e 611 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 612 */
mustwillza 0:3d4bd1fdeb2e 613 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
mustwillza 0:3d4bd1fdeb2e 614
mustwillza 0:3d4bd1fdeb2e 615 /**
mustwillza 0:3d4bd1fdeb2e 616 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
mustwillza 0:3d4bd1fdeb2e 617 *
mustwillza 0:3d4bd1fdeb2e 618 * @param page The page (2-15) to write to.
mustwillza 0:3d4bd1fdeb2e 619 * @param buffer The 4 bytes to write to the PICC
mustwillza 0:3d4bd1fdeb2e 620 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
mustwillza 0:3d4bd1fdeb2e 621 *
mustwillza 0:3d4bd1fdeb2e 622 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 623 */
mustwillza 0:3d4bd1fdeb2e 624 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
mustwillza 0:3d4bd1fdeb2e 625
mustwillza 0:3d4bd1fdeb2e 626 /**
mustwillza 0:3d4bd1fdeb2e 627 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
mustwillza 0:3d4bd1fdeb2e 628 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:3d4bd1fdeb2e 629 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:3d4bd1fdeb2e 630 * Use MIFARE_Transfer() to store the result in a block.
mustwillza 0:3d4bd1fdeb2e 631 *
mustwillza 0:3d4bd1fdeb2e 632 * @param blockAddr The block (0-0xff) number.
mustwillza 0:3d4bd1fdeb2e 633 * @param delta This number is subtracted from the value of block blockAddr.
mustwillza 0:3d4bd1fdeb2e 634 *
mustwillza 0:3d4bd1fdeb2e 635 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 636 */
mustwillza 0:3d4bd1fdeb2e 637 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
mustwillza 0:3d4bd1fdeb2e 638
mustwillza 0:3d4bd1fdeb2e 639 /**
mustwillza 0:3d4bd1fdeb2e 640 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
mustwillza 0:3d4bd1fdeb2e 641 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:3d4bd1fdeb2e 642 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:3d4bd1fdeb2e 643 * Use MIFARE_Transfer() to store the result in a block.
mustwillza 0:3d4bd1fdeb2e 644 *
mustwillza 0:3d4bd1fdeb2e 645 * @param blockAddr The block (0-0xff) number.
mustwillza 0:3d4bd1fdeb2e 646 * @param delta This number is added to the value of block blockAddr.
mustwillza 0:3d4bd1fdeb2e 647 *
mustwillza 0:3d4bd1fdeb2e 648 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 649 */
mustwillza 0:3d4bd1fdeb2e 650 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
mustwillza 0:3d4bd1fdeb2e 651
mustwillza 0:3d4bd1fdeb2e 652 /**
mustwillza 0:3d4bd1fdeb2e 653 * MIFARE Restore copies the value of the addressed block into a volatile memory.
mustwillza 0:3d4bd1fdeb2e 654 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:3d4bd1fdeb2e 655 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:3d4bd1fdeb2e 656 * Use MIFARE_Transfer() to store the result in a block.
mustwillza 0:3d4bd1fdeb2e 657 *
mustwillza 0:3d4bd1fdeb2e 658 * @param blockAddr The block (0-0xff) number.
mustwillza 0:3d4bd1fdeb2e 659 *
mustwillza 0:3d4bd1fdeb2e 660 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 661 */
mustwillza 0:3d4bd1fdeb2e 662 uint8_t MIFARE_Restore (uint8_t blockAddr);
mustwillza 0:3d4bd1fdeb2e 663
mustwillza 0:3d4bd1fdeb2e 664 /**
mustwillza 0:3d4bd1fdeb2e 665 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
mustwillza 0:3d4bd1fdeb2e 666 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:3d4bd1fdeb2e 667 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:3d4bd1fdeb2e 668 *
mustwillza 0:3d4bd1fdeb2e 669 * @param blockAddr The block (0-0xff) number.
mustwillza 0:3d4bd1fdeb2e 670 *
mustwillza 0:3d4bd1fdeb2e 671 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 672 */
mustwillza 0:3d4bd1fdeb2e 673 uint8_t MIFARE_Transfer (uint8_t blockAddr);
mustwillza 0:3d4bd1fdeb2e 674
mustwillza 0:3d4bd1fdeb2e 675 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 676 //@}
mustwillza 0:3d4bd1fdeb2e 677
mustwillza 0:3d4bd1fdeb2e 678
mustwillza 0:3d4bd1fdeb2e 679 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 680 //! @name Support functions
mustwillza 0:3d4bd1fdeb2e 681 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 682 //@{
mustwillza 0:3d4bd1fdeb2e 683
mustwillza 0:3d4bd1fdeb2e 684 /**
mustwillza 0:3d4bd1fdeb2e 685 * Wrapper for MIFARE protocol communication.
mustwillza 0:3d4bd1fdeb2e 686 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
mustwillza 0:3d4bd1fdeb2e 687 *
mustwillza 0:3d4bd1fdeb2e 688 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
mustwillza 0:3d4bd1fdeb2e 689 * @param sendLen Number of bytes in sendData.
mustwillza 0:3d4bd1fdeb2e 690 * @param acceptTimeout True => A timeout is also success
mustwillza 0:3d4bd1fdeb2e 691 *
mustwillza 0:3d4bd1fdeb2e 692 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 693 */
mustwillza 0:3d4bd1fdeb2e 694 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
mustwillza 0:3d4bd1fdeb2e 695
mustwillza 0:3d4bd1fdeb2e 696 /**
mustwillza 0:3d4bd1fdeb2e 697 * Translates the SAK (Select Acknowledge) to a PICC type.
mustwillza 0:3d4bd1fdeb2e 698 *
mustwillza 0:3d4bd1fdeb2e 699 * @param sak The SAK byte returned from PICC_Select().
mustwillza 0:3d4bd1fdeb2e 700 *
mustwillza 0:3d4bd1fdeb2e 701 * @return PICC_Type
mustwillza 0:3d4bd1fdeb2e 702 */
mustwillza 0:3d4bd1fdeb2e 703 uint8_t PICC_GetType (uint8_t sak);
mustwillza 0:3d4bd1fdeb2e 704
mustwillza 0:3d4bd1fdeb2e 705 /**
mustwillza 0:3d4bd1fdeb2e 706 * Returns a string pointer to the PICC type name.
mustwillza 0:3d4bd1fdeb2e 707 *
mustwillza 0:3d4bd1fdeb2e 708 * @param type One of the PICC_Type enums.
mustwillza 0:3d4bd1fdeb2e 709 *
mustwillza 0:3d4bd1fdeb2e 710 * @return A string pointer to the PICC type name.
mustwillza 0:3d4bd1fdeb2e 711 */
mustwillza 0:3d4bd1fdeb2e 712 char* PICC_GetTypeName (uint8_t type);
mustwillza 0:3d4bd1fdeb2e 713
mustwillza 0:3d4bd1fdeb2e 714 /**
mustwillza 0:3d4bd1fdeb2e 715 * Returns a string pointer to a status code name.
mustwillza 0:3d4bd1fdeb2e 716 *
mustwillza 0:3d4bd1fdeb2e 717 * @param code One of the StatusCode enums.
mustwillza 0:3d4bd1fdeb2e 718 *
mustwillza 0:3d4bd1fdeb2e 719 * @return A string pointer to a status code name.
mustwillza 0:3d4bd1fdeb2e 720 */
mustwillza 0:3d4bd1fdeb2e 721 char* GetStatusCodeName (uint8_t code);
mustwillza 0:3d4bd1fdeb2e 722
mustwillza 0:3d4bd1fdeb2e 723 /**
mustwillza 0:3d4bd1fdeb2e 724 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
mustwillza 0:3d4bd1fdeb2e 725 *
mustwillza 0:3d4bd1fdeb2e 726 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
mustwillza 0:3d4bd1fdeb2e 727 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
mustwillza 0:3d4bd1fdeb2e 728 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
mustwillza 0:3d4bd1fdeb2e 729 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
mustwillza 0:3d4bd1fdeb2e 730 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
mustwillza 0:3d4bd1fdeb2e 731 */
mustwillza 0:3d4bd1fdeb2e 732 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
mustwillza 0:3d4bd1fdeb2e 733 uint8_t g0,
mustwillza 0:3d4bd1fdeb2e 734 uint8_t g1,
mustwillza 0:3d4bd1fdeb2e 735 uint8_t g2,
mustwillza 0:3d4bd1fdeb2e 736 uint8_t g3);
mustwillza 0:3d4bd1fdeb2e 737
mustwillza 0:3d4bd1fdeb2e 738 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 739 //@}
mustwillza 0:3d4bd1fdeb2e 740
mustwillza 0:3d4bd1fdeb2e 741
mustwillza 0:3d4bd1fdeb2e 742 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 743 //! @name Convenience functions - does not add extra functionality
mustwillza 0:3d4bd1fdeb2e 744 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 745 //@{
mustwillza 0:3d4bd1fdeb2e 746
mustwillza 0:3d4bd1fdeb2e 747 /**
mustwillza 0:3d4bd1fdeb2e 748 * Returns true if a PICC responds to PICC_CMD_REQA.
mustwillza 0:3d4bd1fdeb2e 749 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
mustwillza 0:3d4bd1fdeb2e 750 *
mustwillza 0:3d4bd1fdeb2e 751 * @return bool
mustwillza 0:3d4bd1fdeb2e 752 */
mustwillza 0:3d4bd1fdeb2e 753 bool PICC_IsNewCardPresent(void);
mustwillza 0:3d4bd1fdeb2e 754
mustwillza 0:3d4bd1fdeb2e 755 /**
mustwillza 0:3d4bd1fdeb2e 756 * Simple wrapper around PICC_Select.
mustwillza 0:3d4bd1fdeb2e 757 * Returns true if a UID could be read.
mustwillza 0:3d4bd1fdeb2e 758 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
mustwillza 0:3d4bd1fdeb2e 759 * The read UID is available in the class variable uid.
mustwillza 0:3d4bd1fdeb2e 760 *
mustwillza 0:3d4bd1fdeb2e 761 * @return bool
mustwillza 0:3d4bd1fdeb2e 762 */
mustwillza 0:3d4bd1fdeb2e 763 bool PICC_ReadCardSerial (void);
mustwillza 0:3d4bd1fdeb2e 764
mustwillza 0:3d4bd1fdeb2e 765 // ************************************************************************************
mustwillza 0:3d4bd1fdeb2e 766 //@}
kantapon501 1:486ccde79dc6 767
mustwillza 0:3d4bd1fdeb2e 768
mustwillza 0:3d4bd1fdeb2e 769 private:
mustwillza 0:3d4bd1fdeb2e 770 SPI m_SPI;
mustwillza 0:3d4bd1fdeb2e 771 DigitalOut m_CS;
mustwillza 0:3d4bd1fdeb2e 772 DigitalOut m_RESET;
mustwillza 0:3d4bd1fdeb2e 773
mustwillza 0:3d4bd1fdeb2e 774 /**
mustwillza 0:3d4bd1fdeb2e 775 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
mustwillza 0:3d4bd1fdeb2e 776 *
mustwillza 0:3d4bd1fdeb2e 777 * @param command The command to use
mustwillza 0:3d4bd1fdeb2e 778 * @param blockAddr The block (0-0xff) number.
mustwillza 0:3d4bd1fdeb2e 779 * @param data The data to transfer in step 2
mustwillza 0:3d4bd1fdeb2e 780 *
mustwillza 0:3d4bd1fdeb2e 781 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:3d4bd1fdeb2e 782 */
mustwillza 0:3d4bd1fdeb2e 783 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
mustwillza 0:3d4bd1fdeb2e 784 };
mustwillza 0:3d4bd1fdeb2e 785
mustwillza 0:3d4bd1fdeb2e 786 #endif